64#include "llvm/ADT/APFloat.h"
65#include "llvm/ADT/APInt.h"
66#include "llvm/ADT/APSInt.h"
67#include "llvm/ADT/ArrayRef.h"
68#include "llvm/ADT/DenseMap.h"
69#include "llvm/ADT/FoldingSet.h"
70#include "llvm/ADT/STLExtras.h"
71#include "llvm/ADT/SmallBitVector.h"
72#include "llvm/ADT/SmallPtrSet.h"
73#include "llvm/ADT/SmallString.h"
74#include "llvm/ADT/SmallVector.h"
75#include "llvm/ADT/StringExtras.h"
76#include "llvm/ADT/StringRef.h"
77#include "llvm/ADT/StringSet.h"
78#include "llvm/ADT/StringSwitch.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/Casting.h"
81#include "llvm/Support/Compiler.h"
82#include "llvm/Support/ConvertUTF.h"
83#include "llvm/Support/ErrorHandling.h"
84#include "llvm/Support/Format.h"
85#include "llvm/Support/Locale.h"
86#include "llvm/Support/MathExtras.h"
87#include "llvm/Support/SaveAndRestore.h"
88#include "llvm/Support/raw_ostream.h"
89#include "llvm/TargetParser/RISCVTargetParser.h"
90#include "llvm/TargetParser/Triple.h"
104using namespace clang;
108 unsigned ByteNo)
const {
122 unsigned MinArgCount) {
123 unsigned ArgCount = Call->getNumArgs();
124 if (ArgCount >= MinArgCount)
127 return S.
Diag(Call->getEndLoc(), diag::err_typecheck_call_too_few_args)
128 << 0 << MinArgCount << ArgCount
129 << Call->getSourceRange();
136 unsigned ArgCount = Call->getNumArgs();
137 if (ArgCount <= MaxArgCount)
139 return S.
Diag(Call->getEndLoc(),
140 diag::err_typecheck_call_too_many_args_at_most)
141 << 0 << MaxArgCount << ArgCount
142 << Call->getSourceRange();
149 unsigned MaxArgCount) {
157 unsigned ArgCount = Call->getNumArgs();
158 if (ArgCount == DesiredArgCount)
163 assert(ArgCount > DesiredArgCount &&
"should have diagnosed this");
166 SourceRange Range(Call->getArg(DesiredArgCount)->getBeginLoc(),
167 Call->getArg(ArgCount - 1)->getEndLoc());
169 return S.
Diag(Range.getBegin(), diag::err_typecheck_call_too_many_args)
170 << 0 << DesiredArgCount << ArgCount
171 << Call->getArg(1)->getSourceRange();
175 if (
Value->isTypeDependent())
206 if (!Literal || !Literal->isOrdinary()) {
219 S.
Diag(TheCall->
getEndLoc(), diag::err_typecheck_call_too_few_args_at_least)
227 auto *Literal = dyn_cast<StringLiteral>(Arg->IgnoreParenCasts());
228 if (!Literal || !Literal->isWide()) {
229 S.
Diag(Arg->getBeginLoc(), diag::err_msvc_annotation_wide_str)
230 << Arg->getSourceRange();
264 const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(
295 bool IsBooleanAlignBuiltin = ID == Builtin::BI__builtin_is_aligned;
297 auto IsValidIntegerType = [](
QualType Ty) {
298 return Ty->isIntegerType() && !Ty->isEnumeralType() && !Ty->isBooleanType();
305 if ((!SrcTy->
isPointerType() && !IsValidIntegerType(SrcTy)) ||
309 S.
Diag(Source->
getExprLoc(), diag::err_typecheck_expect_scalar_operand)
315 if (!IsValidIntegerType(AlignOp->
getType())) {
326 llvm::APSInt AlignValue = AlignResult.
Val.
getInt();
327 llvm::APSInt MaxValue(
328 llvm::APInt::getOneBitSet(MaxAlignmentBits + 1, MaxAlignmentBits));
329 if (AlignValue < 1) {
330 S.
Diag(AlignOp->
getExprLoc(), diag::err_alignment_too_small) << 1;
333 if (llvm::APSInt::compareValues(AlignValue, MaxValue) > 0) {
338 if (!AlignValue.isPowerOf2()) {
339 S.
Diag(AlignOp->
getExprLoc(), diag::err_alignment_not_power_of_two);
342 if (AlignValue == 1) {
343 S.
Diag(AlignOp->
getExprLoc(), diag::warn_alignment_builtin_useless)
344 << IsBooleanAlignBuiltin;
369 unsigned BuiltinID) {
374 for (
unsigned I = 0; I < 2; ++I) {
398 !PtrTy->getPointeeType()->isIntegerType() ||
399 PtrTy->getPointeeType().isConstQualified()) {
401 diag::err_overflow_builtin_must_be_ptr_int)
409 if (BuiltinID == Builtin::BI__builtin_mul_overflow) {
410 for (
unsigned I = 0; I < 3; ++I) {
411 const auto Arg = TheCall->
getArg(I);
414 if (Ty->isBitIntType() && Ty->isSignedIntegerType() &&
416 return S.
Diag(Arg->getBeginLoc(),
417 diag::err_overflow_builtin_bit_int_max_size)
426struct BuiltinDumpStructGenerator {
435 : S(S), TheCall(TheCall), ErrorTracker(S.getDiagnostics()),
436 Policy(S.Context.getPrintingPolicy()) {
440 Expr *makeOpaqueValueExpr(
Expr *Inner) {
443 Inner->getObjectKind(), Inner);
444 Actions.push_back(OVE);
448 Expr *getStringLiteral(llvm::StringRef Str) {
454 bool callPrintFunction(llvm::StringRef Format,
458 Args.reserve((TheCall->
getNumArgs() - 2) + 1 + Exprs.size());
460 Args.push_back(getStringLiteral(Format));
461 Args.insert(Args.end(), Exprs.begin(), Exprs.end());
477 Actions.push_back(RealCall.
get());
483 Expr *getIndentString(
unsigned Depth) {
489 return getStringLiteral(Indent);
497 llvm::raw_svector_ostream OS(Str);
502 switch (BT->getKind()) {
503 case BuiltinType::Bool:
506 case BuiltinType::Char_U:
507 case BuiltinType::UChar:
510 case BuiltinType::Char_S:
511 case BuiltinType::SChar:
523 analyze_printf::PrintfConversionSpecifier::sArg) {
549 bool dumpUnnamedRecord(
const RecordDecl *RD,
Expr *E,
unsigned Depth) {
550 Expr *IndentLit = getIndentString(Depth);
552 if (IndentLit ? callPrintFunction(
"%s%s", {IndentLit, TypeLit})
553 : callPrintFunction(
"%s", {TypeLit}))
556 return dumpRecordValue(RD, E, IndentLit, Depth);
569 Expr *RecordArg = makeOpaqueValueExpr(E);
572 if (callPrintFunction(
" {\n"))
576 if (
const auto *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
577 for (
const auto &
Base : CXXRD->bases()) {
585 dumpUnnamedRecord(
Base.getType()->getAsRecordDecl(), BasePtr.
get(),
591 Expr *FieldIndentArg = getIndentString(Depth + 1);
594 for (
auto *D : RD->
decls()) {
595 auto *IFD = dyn_cast<IndirectFieldDecl>(D);
596 auto *FD = IFD ? IFD->getAnonField() : dyn_cast<FieldDecl>(D);
597 if (!FD || FD->isUnnamedBitfield() || FD->isAnonymousStructOrUnion())
603 getStringLiteral(FD->getName())};
605 if (FD->isBitField()) {
609 FD->getBitWidthValue(S.
Context));
623 if (
Field.isInvalid())
626 auto *InnerRD = FD->getType()->getAsRecordDecl();
627 auto *InnerCXXRD = dyn_cast_or_null<CXXRecordDecl>(InnerRD);
628 if (InnerRD && (!InnerCXXRD || InnerCXXRD->isAggregate())) {
630 if (callPrintFunction(Format, Args) ||
631 dumpRecordValue(InnerRD,
Field.get(), FieldIndentArg, Depth + 1))
635 if (appendFormatSpecifier(FD->getType(), Format)) {
637 Args.push_back(
Field.get());
647 Args.push_back(FieldAddr.
get());
650 if (callPrintFunction(Format, Args))
655 return RecordIndent ? callPrintFunction(
"%s}\n", RecordIndent)
656 : callPrintFunction(
"}\n");
659 Expr *buildWrapper() {
662 TheCall->
setType(Wrapper->getType());
683 diag::err_expected_struct_pointer_argument)
696 switch (BT ? BT->getKind() : BuiltinType::Void) {
697 case BuiltinType::Dependent:
698 case BuiltinType::Overload:
699 case BuiltinType::BoundMember:
700 case BuiltinType::PseudoObject:
701 case BuiltinType::UnknownAny:
702 case BuiltinType::BuiltinFn:
708 diag::err_expected_callable_argument)
714 BuiltinDumpStructGenerator Generator(S, TheCall);
720 Expr *PtrArg = PtrArgResult.
get();
724 if (Generator.dumpUnnamedRecord(RD, PtrArg, 0))
727 return Generator.buildWrapper();
739 if (Call->getStmtClass() != Stmt::CallExprClass) {
740 S.
Diag(BuiltinLoc, diag::err_first_argument_to_cwsc_not_call)
741 << Call->getSourceRange();
745 auto CE = cast<CallExpr>(Call);
746 if (CE->getCallee()->getType()->isBlockPointerType()) {
747 S.
Diag(BuiltinLoc, diag::err_first_argument_to_cwsc_block_call)
748 << Call->getSourceRange();
752 const Decl *TargetDecl = CE->getCalleeDecl();
753 if (
const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(TargetDecl))
754 if (FD->getBuiltinID()) {
755 S.
Diag(BuiltinLoc, diag::err_first_argument_to_cwsc_builtin_call)
756 << Call->getSourceRange();
760 if (isa<CXXPseudoDestructorExpr>(CE->getCallee()->IgnoreParens())) {
761 S.
Diag(BuiltinLoc, diag::err_first_argument_to_cwsc_pdtor_call)
762 << Call->getSourceRange();
770 S.
Diag(BuiltinLoc, diag::err_second_argument_to_cwsc_not_pointer)
784 BuiltinCall->
setType(CE->getType());
788 BuiltinCall->
setArg(1, ChainResult.
get());
795class ScanfDiagnosticFormatHandler
799 using ComputeSizeFunction =
800 llvm::function_ref<std::optional<llvm::APSInt>(
unsigned)>;
804 using DiagnoseFunction =
805 llvm::function_ref<void(
unsigned,
unsigned,
unsigned)>;
807 ComputeSizeFunction ComputeSizeArgument;
808 DiagnoseFunction Diagnose;
811 ScanfDiagnosticFormatHandler(ComputeSizeFunction ComputeSizeArgument,
812 DiagnoseFunction Diagnose)
813 : ComputeSizeArgument(ComputeSizeArgument), Diagnose(Diagnose) {}
816 const char *StartSpecifier,
817 unsigned specifierLen)
override {
818 if (!FS.consumesDataArgument())
821 unsigned NulByte = 0;
822 switch ((FS.getConversionSpecifier().getKind())) {
835 analyze_format_string::OptionalAmount::HowSpecified::Constant)
840 std::optional<llvm::APSInt> DestSizeAPS =
841 ComputeSizeArgument(FS.getArgIndex());
845 unsigned DestSize = DestSizeAPS->getZExtValue();
847 if (DestSize < SourceSize)
848 Diagnose(FS.getArgIndex(), DestSize, SourceSize);
854class EstimateSizeFormatHandler
859 EstimateSizeFormatHandler(StringRef Format)
860 :
Size(
std::
min(Format.find(0), Format.size()) +
864 const char *,
unsigned SpecifierLen,
867 const size_t FieldWidth = computeFieldWidth(FS);
868 const size_t Precision = computePrecision(FS);
871 switch (FS.getConversionSpecifier().getKind()) {
875 Size += std::max(FieldWidth, (
size_t)1);
887 Size += std::max(FieldWidth, Precision);
903 Size += std::max(FieldWidth, 1 +
904 (Precision ? 1 + Precision
914 (Precision ? 1 + Precision : 0) +
924 (Precision ? 1 + Precision : 0) +
936 Size += std::max(FieldWidth, 2 + Precision);
948 Size += FS.hasPlusPrefix() || FS.hasSpacePrefix();
950 if (FS.hasAlternativeForm()) {
951 switch (FS.getConversionSpecifier().getKind()) {
980 Size += (Precision ? 0 : 1);
987 assert(SpecifierLen <= Size &&
"no underflow");
988 Size -= SpecifierLen;
992 size_t getSizeLowerBound()
const {
return Size; }
997 size_t FieldWidth = 0;
1005 size_t Precision = 0;
1010 switch (FS.getConversionSpecifier().getKind()) {
1052 StringRef &FormatStrRef,
size_t &StrLen,
1054 if (
const auto *Format = dyn_cast<StringLiteral>(FormatExpr);
1055 Format && (Format->isOrdinary() || Format->isUTF8())) {
1056 FormatStrRef = Format->getString();
1059 assert(T &&
"String literal not of constant array type!");
1060 size_t TypeSize = T->
getSize().getZExtValue();
1062 StrLen = std::min(std::max(TypeSize,
size_t(1)) - 1, FormatStrRef.find(0));
1068void Sema::checkFortifiedBuiltinMemoryFunction(
FunctionDecl *FD,
1074 bool UseDABAttr =
false;
1077 const auto *DABAttr = FD->
getAttr<DiagnoseAsBuiltinAttr>();
1079 UseDecl = DABAttr->getFunction();
1080 assert(UseDecl &&
"Missing FunctionDecl in DiagnoseAsBuiltin attribute!");
1092 auto TranslateIndex = [&](
unsigned Index) -> std::optional<unsigned> {
1099 unsigned DABIndices = DABAttr->argIndices_size();
1100 unsigned NewIndex = Index < DABIndices
1101 ? DABAttr->argIndices_begin()[Index]
1104 return std::nullopt;
1108 auto ComputeExplicitObjectSizeArgument =
1109 [&](
unsigned Index) -> std::optional<llvm::APSInt> {
1110 std::optional<unsigned> IndexOptional = TranslateIndex(Index);
1112 return std::nullopt;
1113 unsigned NewIndex = *IndexOptional;
1117 return std::nullopt;
1123 auto ComputeSizeArgument =
1124 [&](
unsigned Index) -> std::optional<llvm::APSInt> {
1130 if (Index < FD->getNumParams()) {
1131 if (
const auto *POS =
1133 BOSType = POS->getType();
1136 std::optional<unsigned> IndexOptional = TranslateIndex(Index);
1138 return std::nullopt;
1139 unsigned NewIndex = *IndexOptional;
1142 return std::nullopt;
1144 const Expr *ObjArg = TheCall->
getArg(NewIndex);
1147 return std::nullopt;
1150 return llvm::APSInt::getUnsigned(
Result).extOrTrunc(SizeTypeWidth);
1153 auto ComputeStrLenArgument =
1154 [&](
unsigned Index) -> std::optional<llvm::APSInt> {
1155 std::optional<unsigned> IndexOptional = TranslateIndex(Index);
1157 return std::nullopt;
1158 unsigned NewIndex = *IndexOptional;
1160 const Expr *ObjArg = TheCall->
getArg(NewIndex);
1163 return std::nullopt;
1165 return llvm::APSInt::getUnsigned(
Result + 1).extOrTrunc(SizeTypeWidth);
1168 std::optional<llvm::APSInt> SourceSize;
1169 std::optional<llvm::APSInt> DestinationSize;
1170 unsigned DiagID = 0;
1171 bool IsChkVariant =
false;
1173 auto GetFunctionName = [&]() {
1179 FunctionName = FunctionName.drop_front(std::strlen(
"__builtin___"));
1180 FunctionName = FunctionName.drop_back(std::strlen(
"_chk"));
1181 }
else if (FunctionName.startswith(
"__builtin_")) {
1182 FunctionName = FunctionName.drop_front(std::strlen(
"__builtin_"));
1184 return FunctionName;
1187 switch (BuiltinID) {
1190 case Builtin::BI__builtin_strcpy:
1191 case Builtin::BIstrcpy: {
1192 DiagID = diag::warn_fortify_strlen_overflow;
1193 SourceSize = ComputeStrLenArgument(1);
1194 DestinationSize = ComputeSizeArgument(0);
1198 case Builtin::BI__builtin___strcpy_chk: {
1199 DiagID = diag::warn_fortify_strlen_overflow;
1200 SourceSize = ComputeStrLenArgument(1);
1201 DestinationSize = ComputeExplicitObjectSizeArgument(2);
1202 IsChkVariant =
true;
1206 case Builtin::BIscanf:
1207 case Builtin::BIfscanf:
1208 case Builtin::BIsscanf: {
1209 unsigned FormatIndex = 1;
1210 unsigned DataIndex = 2;
1211 if (BuiltinID == Builtin::BIscanf) {
1216 const auto *FormatExpr =
1219 StringRef FormatStrRef;
1224 auto Diagnose = [&](
unsigned ArgIndex,
unsigned DestSize,
1225 unsigned SourceSize) {
1226 DiagID = diag::warn_fortify_scanf_overflow;
1227 unsigned Index = ArgIndex + DataIndex;
1228 StringRef FunctionName = GetFunctionName();
1230 PDiag(DiagID) << FunctionName << (Index + 1)
1231 << DestSize << SourceSize);
1234 auto ShiftedComputeSizeArgument = [&](
unsigned Index) {
1235 return ComputeSizeArgument(Index + DataIndex);
1237 ScanfDiagnosticFormatHandler H(ShiftedComputeSizeArgument,
Diagnose);
1238 const char *FormatBytes = FormatStrRef.data();
1249 case Builtin::BIsprintf:
1250 case Builtin::BI__builtin___sprintf_chk: {
1251 size_t FormatIndex = BuiltinID == Builtin::BIsprintf ? 1 : 3;
1254 StringRef FormatStrRef;
1257 EstimateSizeFormatHandler H(FormatStrRef);
1258 const char *FormatBytes = FormatStrRef.data();
1260 H, FormatBytes, FormatBytes + StrLen,
getLangOpts(),
1262 DiagID = diag::warn_fortify_source_format_overflow;
1263 SourceSize = llvm::APSInt::getUnsigned(H.getSizeLowerBound())
1264 .extOrTrunc(SizeTypeWidth);
1265 if (BuiltinID == Builtin::BI__builtin___sprintf_chk) {
1266 DestinationSize = ComputeExplicitObjectSizeArgument(2);
1267 IsChkVariant =
true;
1269 DestinationSize = ComputeSizeArgument(0);
1276 case Builtin::BI__builtin___memcpy_chk:
1277 case Builtin::BI__builtin___memmove_chk:
1278 case Builtin::BI__builtin___memset_chk:
1279 case Builtin::BI__builtin___strlcat_chk:
1280 case Builtin::BI__builtin___strlcpy_chk:
1281 case Builtin::BI__builtin___strncat_chk:
1282 case Builtin::BI__builtin___strncpy_chk:
1283 case Builtin::BI__builtin___stpncpy_chk:
1284 case Builtin::BI__builtin___memccpy_chk:
1285 case Builtin::BI__builtin___mempcpy_chk: {
1286 DiagID = diag::warn_builtin_chk_overflow;
1287 SourceSize = ComputeExplicitObjectSizeArgument(TheCall->
getNumArgs() - 2);
1289 ComputeExplicitObjectSizeArgument(TheCall->
getNumArgs() - 1);
1290 IsChkVariant =
true;
1294 case Builtin::BI__builtin___snprintf_chk:
1295 case Builtin::BI__builtin___vsnprintf_chk: {
1296 DiagID = diag::warn_builtin_chk_overflow;
1297 SourceSize = ComputeExplicitObjectSizeArgument(1);
1298 DestinationSize = ComputeExplicitObjectSizeArgument(3);
1299 IsChkVariant =
true;
1303 case Builtin::BIstrncat:
1304 case Builtin::BI__builtin_strncat:
1305 case Builtin::BIstrncpy:
1306 case Builtin::BI__builtin_strncpy:
1307 case Builtin::BIstpncpy:
1308 case Builtin::BI__builtin_stpncpy: {
1314 DiagID = diag::warn_fortify_source_size_mismatch;
1315 SourceSize = ComputeExplicitObjectSizeArgument(TheCall->
getNumArgs() - 1);
1316 DestinationSize = ComputeSizeArgument(0);
1320 case Builtin::BImemcpy:
1321 case Builtin::BI__builtin_memcpy:
1322 case Builtin::BImemmove:
1323 case Builtin::BI__builtin_memmove:
1324 case Builtin::BImemset:
1325 case Builtin::BI__builtin_memset:
1326 case Builtin::BImempcpy:
1327 case Builtin::BI__builtin_mempcpy: {
1328 DiagID = diag::warn_fortify_source_overflow;
1329 SourceSize = ComputeExplicitObjectSizeArgument(TheCall->
getNumArgs() - 1);
1330 DestinationSize = ComputeSizeArgument(0);
1333 case Builtin::BIsnprintf:
1334 case Builtin::BI__builtin_snprintf:
1335 case Builtin::BIvsnprintf:
1336 case Builtin::BI__builtin_vsnprintf: {
1337 DiagID = diag::warn_fortify_source_size_mismatch;
1338 SourceSize = ComputeExplicitObjectSizeArgument(1);
1340 StringRef FormatStrRef;
1344 EstimateSizeFormatHandler H(FormatStrRef);
1345 const char *FormatBytes = FormatStrRef.data();
1347 H, FormatBytes, FormatBytes + StrLen,
getLangOpts(),
1349 llvm::APSInt FormatSize =
1350 llvm::APSInt::getUnsigned(H.getSizeLowerBound())
1351 .extOrTrunc(SizeTypeWidth);
1352 if (FormatSize > *SourceSize && *SourceSize != 0) {
1353 DiagID = diag::warn_fortify_source_format_truncation;
1354 DestinationSize = SourceSize;
1355 SourceSize = FormatSize;
1360 DestinationSize = ComputeSizeArgument(0);
1364 if (!SourceSize || !DestinationSize ||
1365 llvm::APSInt::compareValues(*SourceSize, *DestinationSize) <= 0)
1368 StringRef FunctionName = GetFunctionName();
1372 DestinationSize->toString(DestinationStr, 10);
1373 SourceSize->toString(SourceStr, 10);
1376 << FunctionName << DestinationStr << SourceStr);
1389 while (S && !S->isSEHExceptScope())
1391 if (!S || !(S->getFlags() & NeededScopeFlags)) {
1394 << DRE->getDecl()->getIdentifier();
1412 unsigned ArgCounter = 0;
1413 bool IllegalParams =
false;
1417 I != E; ++I, ++ArgCounter) {
1418 if (!(*I)->isPointerType() || !(*I)->getPointeeType()->isVoidType() ||
1419 (*I)->getPointeeType().getQualifiers().getAddressSpace() !=
1425 if (isa<BlockExpr>(BlockArg)) {
1426 BlockDecl *BD = cast<BlockExpr>(BlockArg)->getBlockDecl();
1428 }
else if (isa<DeclRefExpr>(BlockArg)) {
1429 ErrorLoc = cast<DeclRefExpr>(BlockArg)->getBeginLoc();
1432 diag::err_opencl_enqueue_kernel_blocks_non_local_void_args);
1433 IllegalParams =
true;
1437 return IllegalParams;
1447 S.
Diag(Call->getBeginLoc(), diag::err_opencl_requires_extension)
1448 << 1 << Call->getDirectCallee()
1449 <<
"cl_khr_subgroups or __opencl_c_subgroups";
1465 S.
Diag(NDRangeArg->
getBeginLoc(), diag::err_opencl_builtin_expected_type)
1472 S.
Diag(BlockArg->
getBeginLoc(), diag::err_opencl_builtin_expected_type)
1488 S.
Diag(BlockArg->
getBeginLoc(), diag::err_opencl_builtin_expected_type)
1500 unsigned Start,
unsigned End) {
1501 bool IllegalParams =
false;
1502 for (
unsigned I = Start; I <= End; ++I)
1505 return IllegalParams;
1512 unsigned NumNonVarArgs) {
1515 unsigned NumBlockParams =
1517 unsigned TotalNumArgs = TheCall->
getNumArgs();
1521 if (TotalNumArgs != NumBlockParams + NumNonVarArgs) {
1523 diag::err_opencl_enqueue_kernel_local_size_args);
1563 diag::err_typecheck_call_too_few_args_at_least)
1564 << 0 << 4 << NumArgs;
1576 diag::err_opencl_builtin_expected_type)
1584 diag::err_opencl_builtin_expected_type)
1585 << TheCall->
getDirectCallee() <<
"'kernel_enqueue_flags_t' (i.e. uint)";
1592 diag::err_opencl_builtin_expected_type)
1611 diag::err_opencl_enqueue_kernel_blocks_no_args);
1635 diag::err_opencl_builtin_expected_type)
1648 diag::err_opencl_builtin_expected_type)
1660 diag::err_opencl_builtin_expected_type)
1674 diag::err_opencl_enqueue_kernel_incorrect_args);
1680 return D->
getAttr<OpenCLAccessAttr>();
1685 const Expr *Arg0 = Call->getArg(0);
1688 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_first_arg)
1692 OpenCLAccessAttr *AccessQual =
1698 switch (Call->getDirectCallee()->getBuiltinID()) {
1699 case Builtin::BIread_pipe:
1700 case Builtin::BIreserve_read_pipe:
1701 case Builtin::BIcommit_read_pipe:
1702 case Builtin::BIwork_group_reserve_read_pipe:
1703 case Builtin::BIsub_group_reserve_read_pipe:
1704 case Builtin::BIwork_group_commit_read_pipe:
1705 case Builtin::BIsub_group_commit_read_pipe:
1706 if (!(!AccessQual || AccessQual->isReadOnly())) {
1708 diag::err_opencl_builtin_pipe_invalid_access_modifier)
1713 case Builtin::BIwrite_pipe:
1714 case Builtin::BIreserve_write_pipe:
1715 case Builtin::BIcommit_write_pipe:
1716 case Builtin::BIwork_group_reserve_write_pipe:
1717 case Builtin::BIsub_group_reserve_write_pipe:
1718 case Builtin::BIwork_group_commit_write_pipe:
1719 case Builtin::BIsub_group_commit_write_pipe:
1720 if (!(AccessQual && AccessQual->isWriteOnly())) {
1722 diag::err_opencl_builtin_pipe_invalid_access_modifier)
1735 const Expr *Arg0 = Call->getArg(0);
1736 const Expr *ArgIdx = Call->getArg(Idx);
1745 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_invalid_arg)
1760 switch (Call->getNumArgs()) {
1777 if (!Call->getArg(1)->getType()->isReserveIDT()) {
1778 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_invalid_arg)
1780 << Call->getArg(1)->getType() << Call->getArg(1)->getSourceRange();
1785 const Expr *Arg2 = Call->getArg(2);
1788 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_invalid_arg)
1799 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_arg_num)
1800 << Call->getDirectCallee() << Call->getSourceRange();
1820 if (!Call->getArg(1)->getType()->isIntegerType() &&
1821 !Call->getArg(1)->getType()->isUnsignedIntegerType()) {
1822 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_invalid_arg)
1824 << Call->getArg(1)->getType() << Call->getArg(1)->getSourceRange();
1849 if (!Call->getArg(1)->getType()->isReserveIDT()) {
1850 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_invalid_arg)
1852 << Call->getArg(1)->getType() << Call->getArg(1)->getSourceRange();
1868 if (!Call->getArg(0)->getType()->isPipeType()) {
1869 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_pipe_first_arg)
1870 << Call->getDirectCallee() << Call->getArg(0)->getSourceRange();
1888 auto RT = Call->getArg(0)->getType();
1889 if (!RT->isPointerType() || RT->getPointeeType()
1891 S.
Diag(Call->getBeginLoc(), diag::err_opencl_builtin_to_addr_invalid_arg)
1892 << Call->getArg(0) << Call->getDirectCallee() << Call->getSourceRange();
1897 S.
Diag(Call->getArg(0)->getBeginLoc(),
1898 diag::warn_opencl_generic_address_space_arg)
1899 << Call->getDirectCallee()->getNameInfo().getAsString()
1900 << Call->getArg(0)->getSourceRange();
1903 RT = RT->getPointeeType();
1904 auto Qual = RT.getQualifiers();
1905 switch (BuiltinID) {
1906 case Builtin::BIto_global:
1909 case Builtin::BIto_local:
1912 case Builtin::BIto_private:
1916 llvm_unreachable(
"Invalid builtin function");
1919 RT.getUnqualifiedType(), Qual)));
1945 auto DiagSelect = [&]() -> std::optional<unsigned> {
1952 return std::optional<unsigned>{};
1967 diag::err_incomplete_type))
1971 "Unhandled non-object pointer case");
1989 llvm::Triple::ObjectFormatType CurObjFormat =
1991 if (llvm::is_contained(UnsupportedObjectFormatTypes, CurObjFormat)) {
2004 llvm::Triple::ArchType CurArch =
2006 if (llvm::is_contained(SupportedArchs, CurArch))
2016bool Sema::CheckTSBuiltinFunctionCall(
const TargetInfo &TI,
unsigned BuiltinID,
2023 case llvm::Triple::arm:
2024 case llvm::Triple::armeb:
2025 case llvm::Triple::thumb:
2026 case llvm::Triple::thumbeb:
2027 return CheckARMBuiltinFunctionCall(TI, BuiltinID, TheCall);
2028 case llvm::Triple::aarch64:
2029 case llvm::Triple::aarch64_32:
2030 case llvm::Triple::aarch64_be:
2031 return CheckAArch64BuiltinFunctionCall(TI, BuiltinID, TheCall);
2032 case llvm::Triple::bpfeb:
2033 case llvm::Triple::bpfel:
2034 return CheckBPFBuiltinFunctionCall(BuiltinID, TheCall);
2035 case llvm::Triple::hexagon:
2036 return CheckHexagonBuiltinFunctionCall(BuiltinID, TheCall);
2037 case llvm::Triple::mips:
2038 case llvm::Triple::mipsel:
2039 case llvm::Triple::mips64:
2040 case llvm::Triple::mips64el:
2041 return CheckMipsBuiltinFunctionCall(TI, BuiltinID, TheCall);
2042 case llvm::Triple::systemz:
2043 return CheckSystemZBuiltinFunctionCall(BuiltinID, TheCall);
2044 case llvm::Triple::x86:
2045 case llvm::Triple::x86_64:
2046 return CheckX86BuiltinFunctionCall(TI, BuiltinID, TheCall);
2047 case llvm::Triple::ppc:
2048 case llvm::Triple::ppcle:
2049 case llvm::Triple::ppc64:
2050 case llvm::Triple::ppc64le:
2051 return CheckPPCBuiltinFunctionCall(TI, BuiltinID, TheCall);
2052 case llvm::Triple::amdgcn:
2053 return CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall);
2054 case llvm::Triple::riscv32:
2055 case llvm::Triple::riscv64:
2056 return CheckRISCVBuiltinFunctionCall(TI, BuiltinID, TheCall);
2057 case llvm::Triple::loongarch32:
2058 case llvm::Triple::loongarch64:
2059 return CheckLoongArchBuiltinFunctionCall(TI, BuiltinID, TheCall);
2060 case llvm::Triple::wasm32:
2061 case llvm::Triple::wasm64:
2062 return CheckWebAssemblyBuiltinFunctionCall(TI, BuiltinID, TheCall);
2063 case llvm::Triple::nvptx:
2064 case llvm::Triple::nvptx64:
2065 return CheckNVPTXBuiltinFunctionCall(TI, BuiltinID, TheCall);
2075 return S.
Diag(Loc, diag::err_builtin_invalid_arg_type)
2086 EltTy = VecTy->getElementType();
2089 return S.
Diag(Loc, diag::err_builtin_invalid_arg_type)
2090 << ArgIndex << 5 << ArgTy;
2097Sema::CheckBuiltinFunctionCall(
FunctionDecl *FDecl,
unsigned BuiltinID,
2102 unsigned ICEArguments = 0;
2109 for (
unsigned ArgNo = 0; ICEArguments != 0; ++ArgNo) {
2111 if ((ICEArguments & (1 << ArgNo)) == 0)
continue;
2116 if (ArgNo < TheCall->getNumArgs() &&
2117 SemaBuiltinConstantArg(TheCall, ArgNo,
Result))
2119 ICEArguments &= ~(1 << ArgNo);
2122 switch (BuiltinID) {
2123 case Builtin::BI__builtin___CFStringMakeConstantString:
2127 *
this, BuiltinID, TheCall,
2128 {llvm::Triple::GOFF, llvm::Triple::XCOFF}))
2131 "Wrong # arguments to builtin CFStringMakeConstantString");
2132 if (CheckObjCString(TheCall->
getArg(0)))
2135 case Builtin::BI__builtin_ms_va_start:
2136 case Builtin::BI__builtin_stdarg_start:
2137 case Builtin::BI__builtin_va_start:
2138 if (SemaBuiltinVAStart(BuiltinID, TheCall))
2141 case Builtin::BI__va_start: {
2143 case llvm::Triple::aarch64:
2144 case llvm::Triple::arm:
2145 case llvm::Triple::thumb:
2146 if (SemaBuiltinVAStartARMMicrosoft(TheCall))
2150 if (SemaBuiltinVAStart(BuiltinID, TheCall))
2158 case Builtin::BI_interlockedbittestandset_acq:
2159 case Builtin::BI_interlockedbittestandset_rel:
2160 case Builtin::BI_interlockedbittestandset_nf:
2161 case Builtin::BI_interlockedbittestandreset_acq:
2162 case Builtin::BI_interlockedbittestandreset_rel:
2163 case Builtin::BI_interlockedbittestandreset_nf:
2165 *
this, BuiltinID, TheCall,
2166 {llvm::Triple::arm, llvm::Triple::thumb, llvm::Triple::aarch64}))
2171 case Builtin::BI_bittest64:
2172 case Builtin::BI_bittestandcomplement64:
2173 case Builtin::BI_bittestandreset64:
2174 case Builtin::BI_bittestandset64:
2175 case Builtin::BI_interlockedbittestandreset64:
2176 case Builtin::BI_interlockedbittestandset64:
2178 {llvm::Triple::x86_64, llvm::Triple::arm,
2179 llvm::Triple::thumb,
2180 llvm::Triple::aarch64}))
2184 case Builtin::BI__builtin_set_flt_rounds:
2186 {llvm::Triple::x86, llvm::Triple::x86_64,
2187 llvm::Triple::arm, llvm::Triple::thumb,
2188 llvm::Triple::aarch64}))
2192 case Builtin::BI__builtin_isgreater:
2193 case Builtin::BI__builtin_isgreaterequal:
2194 case Builtin::BI__builtin_isless:
2195 case Builtin::BI__builtin_islessequal:
2196 case Builtin::BI__builtin_islessgreater:
2197 case Builtin::BI__builtin_isunordered:
2198 if (SemaBuiltinUnorderedCompare(TheCall))
2201 case Builtin::BI__builtin_fpclassify:
2202 if (SemaBuiltinFPClassification(TheCall, 6))
2205 case Builtin::BI__builtin_isfpclass:
2206 if (SemaBuiltinFPClassification(TheCall, 2))
2209 case Builtin::BI__builtin_isfinite:
2210 case Builtin::BI__builtin_isinf:
2211 case Builtin::BI__builtin_isinf_sign:
2212 case Builtin::BI__builtin_isnan:
2213 case Builtin::BI__builtin_isnormal:
2214 case Builtin::BI__builtin_signbit:
2215 case Builtin::BI__builtin_signbitf:
2216 case Builtin::BI__builtin_signbitl:
2217 if (SemaBuiltinFPClassification(TheCall, 1))
2220 case Builtin::BI__builtin_shufflevector:
2224 case Builtin::BI__builtin_prefetch:
2225 if (SemaBuiltinPrefetch(TheCall))
2228 case Builtin::BI__builtin_alloca_with_align:
2229 case Builtin::BI__builtin_alloca_with_align_uninitialized:
2230 if (SemaBuiltinAllocaWithAlign(TheCall))
2233 case Builtin::BI__builtin_alloca:
2234 case Builtin::BI__builtin_alloca_uninitialized:
2238 case Builtin::BI__arithmetic_fence:
2239 if (SemaBuiltinArithmeticFence(TheCall))
2242 case Builtin::BI__assume:
2243 case Builtin::BI__builtin_assume:
2244 if (SemaBuiltinAssume(TheCall))
2247 case Builtin::BI__builtin_assume_aligned:
2248 if (SemaBuiltinAssumeAligned(TheCall))
2251 case Builtin::BI__builtin_dynamic_object_size:
2252 case Builtin::BI__builtin_object_size:
2253 if (SemaBuiltinConstantArgRange(TheCall, 1, 0, 3))
2256 case Builtin::BI__builtin_longjmp:
2257 if (SemaBuiltinLongjmp(TheCall))
2260 case Builtin::BI__builtin_setjmp:
2261 if (SemaBuiltinSetjmp(TheCall))
2264 case Builtin::BI__builtin_classify_type:
2268 case Builtin::BI__builtin_complex:
2269 if (SemaBuiltinComplex(TheCall))
2272 case Builtin::BI__builtin_constant_p: {
2280 case Builtin::BI__builtin_launder:
2282 case Builtin::BI__sync_fetch_and_add:
2283 case Builtin::BI__sync_fetch_and_add_1:
2284 case Builtin::BI__sync_fetch_and_add_2:
2285 case Builtin::BI__sync_fetch_and_add_4:
2286 case Builtin::BI__sync_fetch_and_add_8:
2287 case Builtin::BI__sync_fetch_and_add_16:
2288 case Builtin::BI__sync_fetch_and_sub:
2289 case Builtin::BI__sync_fetch_and_sub_1:
2290 case Builtin::BI__sync_fetch_and_sub_2:
2291 case Builtin::BI__sync_fetch_and_sub_4:
2292 case Builtin::BI__sync_fetch_and_sub_8:
2293 case Builtin::BI__sync_fetch_and_sub_16:
2294 case Builtin::BI__sync_fetch_and_or:
2295 case Builtin::BI__sync_fetch_and_or_1:
2296 case Builtin::BI__sync_fetch_and_or_2:
2297 case Builtin::BI__sync_fetch_and_or_4:
2298 case Builtin::BI__sync_fetch_and_or_8:
2299 case Builtin::BI__sync_fetch_and_or_16:
2300 case Builtin::BI__sync_fetch_and_and:
2301 case Builtin::BI__sync_fetch_and_and_1:
2302 case Builtin::BI__sync_fetch_and_and_2:
2303 case Builtin::BI__sync_fetch_and_and_4:
2304 case Builtin::BI__sync_fetch_and_and_8:
2305 case Builtin::BI__sync_fetch_and_and_16:
2306 case Builtin::BI__sync_fetch_and_xor:
2307 case Builtin::BI__sync_fetch_and_xor_1:
2308 case Builtin::BI__sync_fetch_and_xor_2:
2309 case Builtin::BI__sync_fetch_and_xor_4:
2310 case Builtin::BI__sync_fetch_and_xor_8:
2311 case Builtin::BI__sync_fetch_and_xor_16:
2312 case Builtin::BI__sync_fetch_and_nand:
2313 case Builtin::BI__sync_fetch_and_nand_1:
2314 case Builtin::BI__sync_fetch_and_nand_2:
2315 case Builtin::BI__sync_fetch_and_nand_4:
2316 case Builtin::BI__sync_fetch_and_nand_8:
2317 case Builtin::BI__sync_fetch_and_nand_16:
2318 case Builtin::BI__sync_add_and_fetch:
2319 case Builtin::BI__sync_add_and_fetch_1:
2320 case Builtin::BI__sync_add_and_fetch_2:
2321 case Builtin::BI__sync_add_and_fetch_4:
2322 case Builtin::BI__sync_add_and_fetch_8:
2323 case Builtin::BI__sync_add_and_fetch_16:
2324 case Builtin::BI__sync_sub_and_fetch:
2325 case Builtin::BI__sync_sub_and_fetch_1:
2326 case Builtin::BI__sync_sub_and_fetch_2:
2327 case Builtin::BI__sync_sub_and_fetch_4:
2328 case Builtin::BI__sync_sub_and_fetch_8:
2329 case Builtin::BI__sync_sub_and_fetch_16:
2330 case Builtin::BI__sync_and_and_fetch:
2331 case Builtin::BI__sync_and_and_fetch_1:
2332 case Builtin::BI__sync_and_and_fetch_2:
2333 case Builtin::BI__sync_and_and_fetch_4:
2334 case Builtin::BI__sync_and_and_fetch_8:
2335 case Builtin::BI__sync_and_and_fetch_16:
2336 case Builtin::BI__sync_or_and_fetch:
2337 case Builtin::BI__sync_or_and_fetch_1:
2338 case Builtin::BI__sync_or_and_fetch_2:
2339 case Builtin::BI__sync_or_and_fetch_4:
2340 case Builtin::BI__sync_or_and_fetch_8:
2341 case Builtin::BI__sync_or_and_fetch_16:
2342 case Builtin::BI__sync_xor_and_fetch:
2343 case Builtin::BI__sync_xor_and_fetch_1:
2344 case Builtin::BI__sync_xor_and_fetch_2:
2345 case Builtin::BI__sync_xor_and_fetch_4:
2346 case Builtin::BI__sync_xor_and_fetch_8:
2347 case Builtin::BI__sync_xor_and_fetch_16:
2348 case Builtin::BI__sync_nand_and_fetch:
2349 case Builtin::BI__sync_nand_and_fetch_1:
2350 case Builtin::BI__sync_nand_and_fetch_2:
2351 case Builtin::BI__sync_nand_and_fetch_4:
2352 case Builtin::BI__sync_nand_and_fetch_8:
2353 case Builtin::BI__sync_nand_and_fetch_16:
2354 case Builtin::BI__sync_val_compare_and_swap:
2355 case Builtin::BI__sync_val_compare_and_swap_1:
2356 case Builtin::BI__sync_val_compare_and_swap_2:
2357 case Builtin::BI__sync_val_compare_and_swap_4:
2358 case Builtin::BI__sync_val_compare_and_swap_8:
2359 case Builtin::BI__sync_val_compare_and_swap_16:
2360 case Builtin::BI__sync_bool_compare_and_swap:
2361 case Builtin::BI__sync_bool_compare_and_swap_1:
2362 case Builtin::BI__sync_bool_compare_and_swap_2:
2363 case Builtin::BI__sync_bool_compare_and_swap_4:
2364 case Builtin::BI__sync_bool_compare_and_swap_8:
2365 case Builtin::BI__sync_bool_compare_and_swap_16:
2366 case Builtin::BI__sync_lock_test_and_set:
2367 case Builtin::BI__sync_lock_test_and_set_1:
2368 case Builtin::BI__sync_lock_test_and_set_2:
2369 case Builtin::BI__sync_lock_test_and_set_4:
2370 case Builtin::BI__sync_lock_test_and_set_8:
2371 case Builtin::BI__sync_lock_test_and_set_16:
2372 case Builtin::BI__sync_lock_release:
2373 case Builtin::BI__sync_lock_release_1:
2374 case Builtin::BI__sync_lock_release_2:
2375 case Builtin::BI__sync_lock_release_4:
2376 case Builtin::BI__sync_lock_release_8:
2377 case Builtin::BI__sync_lock_release_16:
2378 case Builtin::BI__sync_swap:
2379 case Builtin::BI__sync_swap_1:
2380 case Builtin::BI__sync_swap_2:
2381 case Builtin::BI__sync_swap_4:
2382 case Builtin::BI__sync_swap_8:
2383 case Builtin::BI__sync_swap_16:
2384 return SemaBuiltinAtomicOverloaded(TheCallResult);
2385 case Builtin::BI__sync_synchronize:
2389 case Builtin::BI__builtin_nontemporal_load:
2390 case Builtin::BI__builtin_nontemporal_store:
2391 return SemaBuiltinNontemporalOverloaded(TheCallResult);
2392 case Builtin::BI__builtin_memcpy_inline: {
2405 case Builtin::BI__builtin_memset_inline: {
2416#define BUILTIN(ID, TYPE, ATTRS)
2417#define ATOMIC_BUILTIN(ID, TYPE, ATTRS) \
2418 case Builtin::BI##ID: \
2419 return SemaAtomicOpsOverloaded(TheCallResult, AtomicExpr::AO##ID);
2420#include "clang/Basic/Builtins.def"
2421 case Builtin::BI__annotation:
2425 case Builtin::BI__builtin_annotation:
2429 case Builtin::BI__builtin_addressof:
2433 case Builtin::BI__builtin_function_start:
2437 case Builtin::BI__builtin_is_aligned:
2438 case Builtin::BI__builtin_align_up:
2439 case Builtin::BI__builtin_align_down:
2443 case Builtin::BI__builtin_add_overflow:
2444 case Builtin::BI__builtin_sub_overflow:
2445 case Builtin::BI__builtin_mul_overflow:
2449 case Builtin::BI__builtin_operator_new:
2450 case Builtin::BI__builtin_operator_delete: {
2451 bool IsDelete = BuiltinID == Builtin::BI__builtin_operator_delete;
2453 SemaBuiltinOperatorNewDeleteOverloaded(TheCallResult, IsDelete);
2458 case Builtin::BI__builtin_dump_struct:
2460 case Builtin::BI__builtin_expect_with_probability: {
2471 Diag(ProbArg->
getBeginLoc(), diag::err_probability_not_constant_float)
2478 bool LoseInfo =
false;
2479 Probability.convert(llvm::APFloat::IEEEdouble(),
2480 llvm::RoundingMode::Dynamic, &LoseInfo);
2481 if (!(Probability >= llvm::APFloat(0.0) &&
2482 Probability <= llvm::APFloat(1.0))) {
2489 case Builtin::BI__builtin_preserve_access_index:
2493 case Builtin::BI__builtin_call_with_static_chain:
2497 case Builtin::BI__exception_code:
2498 case Builtin::BI_exception_code:
2500 diag::err_seh___except_block))
2503 case Builtin::BI__exception_info:
2504 case Builtin::BI_exception_info:
2506 diag::err_seh___except_filter))
2509 case Builtin::BI__GetExceptionInfo:
2521 case Builtin::BIaddressof:
2522 case Builtin::BI__addressof:
2523 case Builtin::BIforward:
2524 case Builtin::BIforward_like:
2525 case Builtin::BImove:
2526 case Builtin::BImove_if_noexcept:
2527 case Builtin::BIas_const: {
2535 bool ReturnsPointer = BuiltinID == Builtin::BIaddressof ||
2536 BuiltinID == Builtin::BI__addressof;
2538 (ReturnsPointer ?
Result->isAnyPointerType()
2539 :
Result->isReferenceType()) &&
2541 Result->getPointeeType()))) {
2542 Diag(TheCall->
getBeginLoc(), diag::err_builtin_move_forward_unsupported)
2549 case Builtin::BIread_pipe:
2550 case Builtin::BIwrite_pipe:
2556 case Builtin::BIreserve_read_pipe:
2557 case Builtin::BIreserve_write_pipe:
2558 case Builtin::BIwork_group_reserve_read_pipe:
2559 case Builtin::BIwork_group_reserve_write_pipe:
2563 case Builtin::BIsub_group_reserve_read_pipe:
2564 case Builtin::BIsub_group_reserve_write_pipe:
2569 case Builtin::BIcommit_read_pipe:
2570 case Builtin::BIcommit_write_pipe:
2571 case Builtin::BIwork_group_commit_read_pipe:
2572 case Builtin::BIwork_group_commit_write_pipe:
2576 case Builtin::BIsub_group_commit_read_pipe:
2577 case Builtin::BIsub_group_commit_write_pipe:
2582 case Builtin::BIget_pipe_num_packets:
2583 case Builtin::BIget_pipe_max_packets:
2587 case Builtin::BIto_global:
2588 case Builtin::BIto_local:
2589 case Builtin::BIto_private:
2594 case Builtin::BIenqueue_kernel:
2598 case Builtin::BIget_kernel_work_group_size:
2599 case Builtin::BIget_kernel_preferred_work_group_size_multiple:
2603 case Builtin::BIget_kernel_max_sub_group_size_for_ndrange:
2604 case Builtin::BIget_kernel_sub_group_count_for_ndrange:
2608 case Builtin::BI__builtin_os_log_format:
2611 case Builtin::BI__builtin_os_log_format_buffer_size:
2612 if (SemaBuiltinOSLogFormat(TheCall))
2615 case Builtin::BI__builtin_frame_address:
2616 case Builtin::BI__builtin_return_address: {
2617 if (SemaBuiltinConstantArgRange(TheCall, 0, 0, 0xFFFF))
2625 Result.Val.getInt() != 0)
2627 << ((BuiltinID == Builtin::BI__builtin_return_address)
2628 ?
"__builtin_return_address"
2629 :
"__builtin_frame_address")
2634 case Builtin::BI__builtin_nondeterministic_value: {
2635 if (SemaBuiltinNonDeterministicValue(TheCall))
2642 case Builtin::BI__builtin_elementwise_abs: {
2643 if (PrepareBuiltinElementwiseMathOneArgCall(TheCall))
2650 EltTy = VecTy->getElementType();
2653 diag::err_builtin_invalid_arg_type)
2662 case Builtin::BI__builtin_elementwise_ceil:
2663 case Builtin::BI__builtin_elementwise_cos:
2664 case Builtin::BI__builtin_elementwise_exp:
2665 case Builtin::BI__builtin_elementwise_exp2:
2666 case Builtin::BI__builtin_elementwise_floor:
2667 case Builtin::BI__builtin_elementwise_log:
2668 case Builtin::BI__builtin_elementwise_log2:
2669 case Builtin::BI__builtin_elementwise_log10:
2670 case Builtin::BI__builtin_elementwise_roundeven:
2671 case Builtin::BI__builtin_elementwise_round:
2672 case Builtin::BI__builtin_elementwise_rint:
2673 case Builtin::BI__builtin_elementwise_nearbyint:
2674 case Builtin::BI__builtin_elementwise_sin:
2675 case Builtin::BI__builtin_elementwise_sqrt:
2676 case Builtin::BI__builtin_elementwise_trunc:
2677 case Builtin::BI__builtin_elementwise_canonicalize: {
2678 if (PrepareBuiltinElementwiseMathOneArgCall(TheCall))
2687 case Builtin::BI__builtin_elementwise_fma: {
2688 if (SemaBuiltinElementwiseTernaryMath(TheCall))
2695 case Builtin::BI__builtin_elementwise_pow: {
2696 if (SemaBuiltinElementwiseMath(TheCall))
2710 case Builtin::BI__builtin_elementwise_add_sat:
2711 case Builtin::BI__builtin_elementwise_sub_sat: {
2712 if (SemaBuiltinElementwiseMath(TheCall))
2720 EltTy = VecTy->getElementType();
2730 case Builtin::BI__builtin_elementwise_min:
2731 case Builtin::BI__builtin_elementwise_max:
2732 if (SemaBuiltinElementwiseMath(TheCall))
2736 case Builtin::BI__builtin_elementwise_bitreverse: {
2737 if (PrepareBuiltinElementwiseMathOneArgCall(TheCall))
2745 EltTy = VecTy->getElementType();
2755 case Builtin::BI__builtin_elementwise_copysign: {
2775 diag::err_typecheck_call_different_arg_types)
2776 << MagnitudeTy << SignTy;
2784 case Builtin::BI__builtin_reduce_max:
2785 case Builtin::BI__builtin_reduce_min: {
2786 if (PrepareBuiltinReduceMathOneArgCall(TheCall))
2797 TheCall->
setType(TyA->getElementType());
2803 case Builtin::BI__builtin_reduce_add:
2804 case Builtin::BI__builtin_reduce_mul:
2805 case Builtin::BI__builtin_reduce_xor:
2806 case Builtin::BI__builtin_reduce_or:
2807 case Builtin::BI__builtin_reduce_and: {
2808 if (PrepareBuiltinReduceMathOneArgCall(TheCall))
2813 if (!TyA || !TyA->getElementType()->isIntegerType()) {
2818 TheCall->
setType(TyA->getElementType());
2822 case Builtin::BI__builtin_matrix_transpose:
2823 return SemaBuiltinMatrixTranspose(TheCall, TheCallResult);
2825 case Builtin::BI__builtin_matrix_column_major_load:
2826 return SemaBuiltinMatrixColumnMajorLoad(TheCall, TheCallResult);
2828 case Builtin::BI__builtin_matrix_column_major_store:
2829 return SemaBuiltinMatrixColumnMajorStore(TheCall, TheCallResult);
2831 case Builtin::BI__builtin_get_device_side_mangled_name: {
2832 auto Check = [](
CallExpr *TheCall) {
2838 auto *D = DRE->getDecl();
2839 if (!isa<FunctionDecl>(D) && !isa<VarDecl>(D))
2841 return D->hasAttr<CUDAGlobalAttr>() || D->hasAttr<CUDADeviceAttr>() ||
2842 D->hasAttr<CUDAConstantAttr>() || D->hasAttr<HIPManagedAttr>();
2844 if (!Check(TheCall)) {
2846 diag::err_hip_invalid_args_builtin_mangled_name);
2857 "Aux Target Builtin, but not an aux target?");
2859 if (CheckTSBuiltinFunctionCall(
2870 return TheCallResult;
2874static unsigned RFT(
unsigned t,
bool shift =
false,
bool ForceQuad =
false) {
2876 int IsQuad = ForceQuad ?
true :
Type.isQuad();
2877 switch (
Type.getEltType()) {
2880 return shift ? 7 : (8 << IsQuad) - 1;
2883 return shift ? 15 : (4 << IsQuad) - 1;
2885 return shift ? 31 : (2 << IsQuad) - 1;
2888 return shift ? 63 : (1 << IsQuad) - 1;
2890 return shift ? 127 : (1 << IsQuad) - 1;
2892 assert(!shift &&
"cannot shift float types!");
2893 return (4 << IsQuad) - 1;
2895 assert(!shift &&
"cannot shift float types!");
2896 return (2 << IsQuad) - 1;
2898 assert(!shift &&
"cannot shift float types!");
2899 return (1 << IsQuad) - 1;
2901 assert(!shift &&
"cannot shift float types!");
2902 return (4 << IsQuad) - 1;
2904 llvm_unreachable(
"Invalid NeonTypeFlag!");
2911 bool IsPolyUnsigned,
bool IsInt64Long) {
2945 llvm_unreachable(
"Invalid NeonTypeFlag!");
2948bool Sema::CheckSVEBuiltinFunctionCall(
unsigned BuiltinID,
CallExpr *TheCall) {
2952 switch (BuiltinID) {
2955#define GET_SVE_IMMEDIATE_CHECK
2956#include "clang/Basic/arm_sve_sema_rangechecks.inc"
2957#undef GET_SVE_IMMEDIATE_CHECK
2958#define GET_SME_IMMEDIATE_CHECK
2959#include "clang/Basic/arm_sme_sema_rangechecks.inc"
2960#undef GET_SME_IMMEDIATE_CHECK
2964 bool HasError =
false;
2965 for (
auto &I : ImmChecks) {
2966 int ArgNum, CheckTy, ElementSizeInBits;
2967 std::tie(ArgNum, CheckTy, ElementSizeInBits) = I;
2973 auto CheckImmediateInSet = [&](OptionSetCheckFnTy CheckImm,
2974 int ErrDiag) ->
bool {
2982 if (SemaBuiltinConstantArg(TheCall, ArgNum, Imm))
2985 if (!CheckImm(Imm.getSExtValue()))
2991 case SVETypeFlags::ImmCheck0_31:
2992 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 31))
2995 case SVETypeFlags::ImmCheck0_13:
2996 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 13))
2999 case SVETypeFlags::ImmCheck1_16:
3000 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 16))
3003 case SVETypeFlags::ImmCheck0_7:
3004 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 7))
3007 case SVETypeFlags::ImmCheckExtract:
3008 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0,
3009 (2048 / ElementSizeInBits) - 1))
3012 case SVETypeFlags::ImmCheckShiftRight:
3013 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, ElementSizeInBits))
3016 case SVETypeFlags::ImmCheckShiftRightNarrow:
3017 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1,
3018 ElementSizeInBits / 2))
3021 case SVETypeFlags::ImmCheckShiftLeft:
3022 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0,
3023 ElementSizeInBits - 1))
3026 case SVETypeFlags::ImmCheckLaneIndex:
3027 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0,
3028 (128 / (1 * ElementSizeInBits)) - 1))
3031 case SVETypeFlags::ImmCheckLaneIndexCompRotate:
3032 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0,
3033 (128 / (2 * ElementSizeInBits)) - 1))
3036 case SVETypeFlags::ImmCheckLaneIndexDot:
3037 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0,
3038 (128 / (4 * ElementSizeInBits)) - 1))
3041 case SVETypeFlags::ImmCheckComplexRot90_270:
3042 if (CheckImmediateInSet([](int64_t
V) {
return V == 90 ||
V == 270; },
3043 diag::err_rotation_argument_to_cadd))
3046 case SVETypeFlags::ImmCheckComplexRotAll90:
3047 if (CheckImmediateInSet(
3049 return V == 0 ||
V == 90 ||
V == 180 ||
V == 270;
3051 diag::err_rotation_argument_to_cmla))
3054 case SVETypeFlags::ImmCheck0_1:
3055 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 1))
3058 case SVETypeFlags::ImmCheck0_2:
3059 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 2))
3062 case SVETypeFlags::ImmCheck0_3:
3063 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 3))
3066 case SVETypeFlags::ImmCheck0_0:
3067 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 0))
3070 case SVETypeFlags::ImmCheck0_15:
3071 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
3074 case SVETypeFlags::ImmCheck0_255:
3075 if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
3084bool Sema::CheckNeonBuiltinFunctionCall(
const TargetInfo &TI,
3085 unsigned BuiltinID,
CallExpr *TheCall) {
3090 bool HasConstPtr =
false;
3091 switch (BuiltinID) {
3092#define GET_NEON_OVERLOAD_CHECK
3093#include "clang/Basic/arm_neon.inc"
3094#include "clang/Basic/arm_fp16.inc"
3095#undef GET_NEON_OVERLOAD_CHECK
3102 if (SemaBuiltinConstantArg(TheCall, ImmArg,
Result))
3105 TV =
Result.getLimitedValue(64);
3106 if ((TV > 63) || (mask & (1ULL << TV)) == 0)
3111 if (PtrArgNum >= 0) {
3115 Arg = ICE->getSubExpr();
3119 llvm::Triple::ArchType Arch = TI.
getTriple().getArch();
3120 bool IsPolyUnsigned = Arch == llvm::Triple::aarch64 ||
3121 Arch == llvm::Triple::aarch64_32 ||
3122 Arch == llvm::Triple::aarch64_be;
3140 unsigned i = 0, l = 0, u = 0;
3141 switch (BuiltinID) {
3144 #define GET_NEON_IMMEDIATE_CHECK
3145 #include "clang/Basic/arm_neon.inc"
3146 #include "clang/Basic/arm_fp16.inc"
3147 #undef GET_NEON_IMMEDIATE_CHECK
3150 return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
3153bool Sema::CheckMVEBuiltinFunctionCall(
unsigned BuiltinID,
CallExpr *TheCall) {
3154 switch (BuiltinID) {
3157 #include "clang/Basic/arm_mve_builtin_sema.inc"
3161bool Sema::CheckCDEBuiltinFunctionCall(
const TargetInfo &TI,
unsigned BuiltinID,
3164 switch (BuiltinID) {
3167#include "clang/Basic/arm_cde_builtin_sema.inc"
3173 return CheckARMCoprocessorImmediate(TI, TheCall->
getArg(0),
true);
3176bool Sema::CheckARMCoprocessorImmediate(
const TargetInfo &TI,
3177 const Expr *CoprocArg,
bool WantCDE) {
3186 int64_t CoprocNo = CoprocNoAP.getExtValue();
3187 assert(CoprocNo >= 0 &&
"Coprocessor immediate must be non-negative");
3190 bool IsCDECoproc = CoprocNo <= 7 && (CDECoprocMask & (1 << CoprocNo));
3192 if (IsCDECoproc != WantCDE)
3199bool Sema::CheckARMBuiltinExclusiveCall(
unsigned BuiltinID,
CallExpr *TheCall,
3200 unsigned MaxWidth) {
3201 assert((BuiltinID == ARM::BI__builtin_arm_ldrex ||
3202 BuiltinID == ARM::BI__builtin_arm_ldaex ||
3203 BuiltinID == ARM::BI__builtin_arm_strex ||
3204 BuiltinID == ARM::BI__builtin_arm_stlex ||
3205 BuiltinID == AArch64::BI__builtin_arm_ldrex ||
3206 BuiltinID == AArch64::BI__builtin_arm_ldaex ||
3207 BuiltinID == AArch64::BI__builtin_arm_strex ||
3208 BuiltinID == AArch64::BI__builtin_arm_stlex) &&
3209 "unexpected ARM builtin");
3210 bool IsLdrex = BuiltinID == ARM::BI__builtin_arm_ldrex ||
3211 BuiltinID == ARM::BI__builtin_arm_ldaex ||
3212 BuiltinID == AArch64::BI__builtin_arm_ldrex ||
3213 BuiltinID == AArch64::BI__builtin_arm_ldaex;
3225 Expr *PointerArg = TheCall->
getArg(IsLdrex ? 0 : 1);
3229 PointerArg = PointerArgRes.
get();
3249 CastNeeded = CK_BitCast;
3250 Diag(DRE->
getBeginLoc(), diag::ext_typecheck_convert_discards_qualifiers)
3260 PointerArg = PointerArgRes.
get();
3262 TheCall->
setArg(IsLdrex ? 0 : 1, PointerArg);
3267 Diag(DRE->
getBeginLoc(), diag::err_atomic_builtin_must_be_pointer_intfltptr)
3274 assert(MaxWidth == 64 &&
"Diagnostic unexpectedly inaccurate");
3275 Diag(DRE->
getBeginLoc(), diag::err_atomic_exclusive_builtin_pointer_size)
3314bool Sema::CheckARMBuiltinFunctionCall(
const TargetInfo &TI,
unsigned BuiltinID,
3316 if (BuiltinID == ARM::BI__builtin_arm_ldrex ||
3317 BuiltinID == ARM::BI__builtin_arm_ldaex ||
3318 BuiltinID == ARM::BI__builtin_arm_strex ||
3319 BuiltinID == ARM::BI__builtin_arm_stlex) {
3320 return CheckARMBuiltinExclusiveCall(BuiltinID, TheCall, 64);
3323 if (BuiltinID == ARM::BI__builtin_arm_prefetch) {
3324 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) ||
3325 SemaBuiltinConstantArgRange(TheCall, 2, 0, 1);
3328 if (BuiltinID == ARM::BI__builtin_arm_rsr64 ||
3329 BuiltinID == ARM::BI__builtin_arm_wsr64)
3330 return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 3,
false);
3332 if (BuiltinID == ARM::BI__builtin_arm_rsr ||
3333 BuiltinID == ARM::BI__builtin_arm_rsrp ||
3334 BuiltinID == ARM::BI__builtin_arm_wsr ||
3335 BuiltinID == ARM::BI__builtin_arm_wsrp)
3336 return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5,
true);
3338 if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall))
3340 if (CheckMVEBuiltinFunctionCall(BuiltinID, TheCall))
3342 if (CheckCDEBuiltinFunctionCall(TI, BuiltinID, TheCall))
3348 switch (BuiltinID) {
3349 default:
return false;
3350 case ARM::BI__builtin_arm_ssat:
3351 return SemaBuiltinConstantArgRange(TheCall, 1, 1, 32);
3352 case ARM::BI__builtin_arm_usat:
3353 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
3354 case ARM::BI__builtin_arm_ssat16:
3355 return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
3356 case ARM::BI__builtin_arm_usat16:
3357 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15);
3358 case ARM::BI__builtin_arm_vcvtr_f:
3359 case ARM::BI__builtin_arm_vcvtr_d:
3360 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
3361 case ARM::BI__builtin_arm_dmb:
3362 case ARM::BI__builtin_arm_dsb:
3363 case ARM::BI__builtin_arm_isb:
3364 case ARM::BI__builtin_arm_dbg:
3365 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 15);
3366 case ARM::BI__builtin_arm_cdp:
3367 case ARM::BI__builtin_arm_cdp2:
3368 case ARM::BI__builtin_arm_mcr:
3369 case ARM::BI__builtin_arm_mcr2:
3370 case ARM::BI__builtin_arm_mrc:
3371 case ARM::BI__builtin_arm_mrc2:
3372 case ARM::BI__builtin_arm_mcrr:
3373 case ARM::BI__builtin_arm_mcrr2:
3374 case ARM::BI__builtin_arm_mrrc:
3375 case ARM::BI__builtin_arm_mrrc2:
3376 case ARM::BI__builtin_arm_ldc:
3377 case ARM::BI__builtin_arm_ldcl:
3378 case ARM::BI__builtin_arm_ldc2:
3379 case ARM::BI__builtin_arm_ldc2l:
3380 case ARM::BI__builtin_arm_stc:
3381 case ARM::BI__builtin_arm_stcl:
3382 case ARM::BI__builtin_arm_stc2:
3383 case ARM::BI__builtin_arm_stc2l:
3384 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 15) ||
3385 CheckARMCoprocessorImmediate(TI, TheCall->
getArg(0),
3390bool Sema::CheckAArch64BuiltinFunctionCall(
const TargetInfo &TI,
3393 if (BuiltinID == AArch64::BI__builtin_arm_ldrex ||
3394 BuiltinID == AArch64::BI__builtin_arm_ldaex ||
3395 BuiltinID == AArch64::BI__builtin_arm_strex ||
3396 BuiltinID == AArch64::BI__builtin_arm_stlex) {
3397 return CheckARMBuiltinExclusiveCall(BuiltinID, TheCall, 128);
3400 if (BuiltinID == AArch64::BI__builtin_arm_prefetch) {
3401 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) ||
3402 SemaBuiltinConstantArgRange(TheCall, 2, 0, 3) ||
3403 SemaBuiltinConstantArgRange(TheCall, 3, 0, 1) ||
3404 SemaBuiltinConstantArgRange(TheCall, 4, 0, 1);
3407 if (BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
3408 BuiltinID == AArch64::BI__builtin_arm_wsr64 ||
3409 BuiltinID == AArch64::BI__builtin_arm_rsr128 ||
3410 BuiltinID == AArch64::BI__builtin_arm_wsr128)
3411 return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5,
true);
3414 if (BuiltinID == AArch64::BI__builtin_arm_irg ||
3415 BuiltinID == AArch64::BI__builtin_arm_addg ||
3416 BuiltinID == AArch64::BI__builtin_arm_gmi ||
3417 BuiltinID == AArch64::BI__builtin_arm_ldg ||
3418 BuiltinID == AArch64::BI__builtin_arm_stg ||
3419 BuiltinID == AArch64::BI__builtin_arm_subp) {
3420 return SemaBuiltinARMMemoryTaggingCall(BuiltinID, TheCall);
3423 if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
3424 BuiltinID == AArch64::BI__builtin_arm_rsrp ||
3425 BuiltinID == AArch64::BI__builtin_arm_wsr ||
3426 BuiltinID == AArch64::BI__builtin_arm_wsrp)
3427 return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5,
true);
3432 if (BuiltinID == AArch64::BI_ReadStatusReg ||
3433 BuiltinID == AArch64::BI_WriteStatusReg)
3434 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0x7fff);
3436 if (BuiltinID == AArch64::BI__getReg)
3437 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
3439 if (BuiltinID == AArch64::BI__break)
3440 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0xffff);
3442 if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall))
3445 if (CheckSVEBuiltinFunctionCall(BuiltinID, TheCall))
3450 unsigned i = 0, l = 0, u = 0;
3451 switch (BuiltinID) {
3452 default:
return false;
3453 case AArch64::BI__builtin_arm_dmb:
3454 case AArch64::BI__builtin_arm_dsb:
3455 case AArch64::BI__builtin_arm_isb: l = 0; u = 15;
break;
3456 case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535;
break;
3459 return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
3496 if (!RT->getDecl()->getDeclName().isEmpty())
3499 if (!ET->getDecl()->getDeclName().isEmpty())
3515 const auto *UO = dyn_cast<UnaryOperator>(Arg->
IgnoreParens());
3519 const auto *CE = dyn_cast<CStyleCastExpr>(UO->getSubExpr());
3522 if (CE->getCastKind() != CK_IntegralToPointer &&
3523 CE->getCastKind() != CK_NullToPointer)
3527 const auto *DR = dyn_cast<DeclRefExpr>(CE->getSubExpr());
3532 dyn_cast<EnumConstantDecl>(DR->getDecl());
3543 return llvm::is_contained(ET->getDecl()->enumerators(), Enumerator);
3546bool Sema::CheckBPFBuiltinFunctionCall(
unsigned BuiltinID,
3548 assert((BuiltinID == BPF::BI__builtin_preserve_field_info ||
3549 BuiltinID == BPF::BI__builtin_btf_type_id ||
3550 BuiltinID == BPF::BI__builtin_preserve_type_info ||
3551 BuiltinID == BPF::BI__builtin_preserve_enum_value) &&
3552 "unexpected BPF builtin");
3562 if (BuiltinID == BPF::BI__builtin_preserve_field_info)
3563 kind = diag::err_preserve_field_info_not_const;
3564 else if (BuiltinID == BPF::BI__builtin_btf_type_id)
3565 kind = diag::err_btf_type_id_not_const;
3566 else if (BuiltinID == BPF::BI__builtin_preserve_type_info)
3567 kind = diag::err_preserve_type_info_not_const;
3569 kind = diag::err_preserve_enum_value_not_const;
3575 Arg = TheCall->
getArg(0);
3576 bool InvalidArg =
false;
3577 bool ReturnUnsignedInt =
true;
3578 if (BuiltinID == BPF::BI__builtin_preserve_field_info) {
3581 kind = diag::err_preserve_field_info_not_field;
3583 }
else if (BuiltinID == BPF::BI__builtin_preserve_type_info) {
3586 kind = diag::err_preserve_type_info_invalid;
3588 }
else if (BuiltinID == BPF::BI__builtin_preserve_enum_value) {
3591 kind = diag::err_preserve_enum_value_invalid;
3593 ReturnUnsignedInt =
false;
3594 }
else if (BuiltinID == BPF::BI__builtin_btf_type_id) {
3595 ReturnUnsignedInt =
false;
3603 if (ReturnUnsignedInt)
3610bool Sema::CheckHexagonBuiltinArgument(
unsigned BuiltinID,
CallExpr *TheCall) {
3623 { Hexagon::BI__builtin_circ_ldd, {{ 3,
true, 4, 3 }} },
3624 { Hexagon::BI__builtin_circ_ldw, {{ 3,
true, 4, 2 }} },
3625 { Hexagon::BI__builtin_circ_ldh, {{ 3,
true, 4, 1 }} },
3626 { Hexagon::BI__builtin_circ_lduh, {{ 3,
true, 4, 1 }} },
3627 { Hexagon::BI__builtin_circ_ldb, {{ 3,
true, 4, 0 }} },
3628 { Hexagon::BI__builtin_circ_ldub, {{ 3,
true, 4, 0 }} },
3629 { Hexagon::BI__builtin_circ_std, {{ 3,
true, 4, 3 }} },
3630 { Hexagon::BI__builtin_circ_stw, {{ 3,
true, 4, 2 }} },
3631 { Hexagon::BI__builtin_circ_sth, {{ 3,
true, 4, 1 }} },
3632 { Hexagon::BI__builtin_circ_sthhi, {{ 3,
true, 4, 1 }} },
3633 { Hexagon::BI__builtin_circ_stb, {{ 3,
true, 4, 0 }} },
3635 { Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{ 1,
true, 4, 0 }} },
3636 { Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{ 1,
true, 4, 0 }} },
3637 { Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{ 1,
true, 4, 1 }} },
3638 { Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{ 1,
true, 4, 1 }} },
3639 { Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{ 1,
true, 4, 2 }} },
3640 { Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{ 1,
true, 4, 3 }} },
3641 { Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{ 1,
true, 4, 0 }} },
3642 { Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{ 1,
true, 4, 1 }} },
3643 { Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{ 1,
true, 4, 1 }} },
3644 { Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{ 1,
true, 4, 2 }} },
3645 { Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{ 1,
true, 4, 3 }} },
3647 { Hexagon::BI__builtin_HEXAGON_A2_combineii, {{ 1,
true, 8, 0 }} },
3648 { Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{ 1,
false, 16, 0 }} },
3649 { Hexagon::BI__builtin_HEXAGON_A2_tfril, {{ 1,
false, 16, 0 }} },
3650 { Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{ 0,
true, 8, 0 }} },
3651 { Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{ 1,
false, 5, 0 }} },
3652 { Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{ 1,
false, 8, 0 }} },
3653 { Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{ 1,
true, 8, 0 }} },
3654 { Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{ 1,
false, 5, 0 }} },
3655 { Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{ 1,
false, 5, 0 }} },
3656 { Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{ 1,
false, 5, 0 }} },
3657 { Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{ 1,
false, 8, 0 }} },
3658 { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{ 1,
true, 8, 0 }} },
3659 { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{ 1,
false, 7, 0 }} },
3660 { Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{ 1,
true, 8, 0 }} },
3661 { Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{ 1,
true, 8, 0 }} },
3662 { Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{ 1,
false, 7, 0 }} },
3663 { Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{ 1,
true, 8, 0 }} },
3664 { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{ 1,
true, 8, 0 }} },
3665 { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{ 1,
false, 7, 0 }} },
3666 { Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{ 1,
false, 6, 0 }} },
3667 { Hexagon::BI__builtin_HEXAGON_C2_muxii, {{ 2,
true, 8, 0 }} },
3668 { Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{ 1,
false, 6, 0 }} },
3669 { Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{ 1,
false, 5, 0 }} },
3670 { Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{ 0,
false, 10, 0 }} },
3671 { Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{ 0,
false, 10, 0 }} },
3672 { Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{ 1,
false, 5, 0 }} },
3673 { Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{ 0,
false, 10, 0 }} },
3674 { Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{ 0,
false, 10, 0 }} },
3675 { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{ 2,
false, 6, 0 }} },
3676 { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{ 1,
false, 6, 2 }} },
3677 { Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{ 2,
false, 3, 0 }} },
3678 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{ 2,
false, 6, 0 }} },
3679 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{ 2,
false, 6, 0 }} },
3680 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{ 1,
false, 6, 0 }} },
3681 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{ 2,
false, 6, 0 }} },
3682 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{ 2,
false, 6, 0 }} },
3683 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{ 2,
false, 6, 0 }} },
3684 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{ 2,
false, 5, 0 }} },
3685 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{ 2,
false, 5, 0 }} },
3686 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{ 1,
false, 5, 0 }} },
3687 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{ 2,
false, 5, 0 }} },
3688 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{ 2,
false, 5, 0 }} },
3689 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{ 1,
false, 5, 0 }} },
3690 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{ 2,
false, 5, 0 }} },
3691 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{ 1,
false, 4, 0 }} },
3692 { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{ 1,
false, 5, 0 }} },
3693 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{ 2,
false, 6, 0 }} },
3694 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{ 2,
false, 6, 0 }} },
3695 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{ 1,
false, 6, 0 }} },
3696 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{ 2,
false, 6, 0 }} },
3697 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{ 2,
false, 6, 0 }} },
3698 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax,
3699 {{ 1,
false, 6, 0 }} },
3700 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{ 1,
false, 6, 0 }} },
3701 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{ 2,
false, 5, 0 }} },
3702 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{ 2,
false, 5, 0 }} },
3703 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{ 1,
false, 5, 0 }} },
3704 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{ 2,
false, 5, 0 }} },
3705 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{ 2,
false, 5, 0 }} },
3706 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax,
3707 {{ 1,
false, 5, 0 }} },
3708 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{ 1,
false, 5, 0 }} },
3709 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{ 1,
false, 5, 0 }} },
3710 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{ 1,
false, 4, 0 }} },
3711 { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{ 1,
false, 5, 0 }} },
3712 { Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{ 1,
false, 5, 0 }} },
3713 { Hexagon::BI__builtin_HEXAGON_S2_extractu, {{ 1,
false, 5, 0 },
3714 { 2,
false, 5, 0 }} },
3715 { Hexagon::BI__builtin_HEXAGON_S2_extractup, {{ 1,
false, 6, 0 },
3716 { 2,
false, 6, 0 }} },
3717 { Hexagon::BI__builtin_HEXAGON_S2_insert, {{ 2,
false, 5, 0 },
3718 { 3,
false, 5, 0 }} },
3719 { Hexagon::BI__builtin_HEXAGON_S2_insertp, {{ 2,
false, 6, 0 },
3720 { 3,
false, 6, 0 }} },
3721 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{ 2,
false, 6, 0 }} },
3722 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{ 2,
false, 6, 0 }} },
3723 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{ 1,
false, 6, 0 }} },
3724 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{ 2,
false, 6, 0 }} },
3725 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{ 2,
false, 6, 0 }} },
3726 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{ 2,
false, 6, 0 }} },
3727 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{ 2,
false, 5, 0 }} },
3728 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{ 2,
false, 5, 0 }} },
3729 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{ 1,
false, 5, 0 }} },
3730 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{ 2,
false, 5, 0 }} },
3731 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{ 2,
false, 5, 0 }} },
3732 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{ 2,
false, 5, 0 }} },
3733 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{ 1,
false, 4, 0 }} },
3734 { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{ 1,
false, 5, 0 }} },
3735 { Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{ 1,
false, 5, 0 }} },
3736 { Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax,
3737 {{ 2,
false, 4, 0 },
3738 { 3,
false, 5, 0 }} },
3739 { Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax,
3740 {{ 2,
false, 4, 0 },
3741 { 3,
false, 5, 0 }} },
3742 { Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax,
3743 {{ 2,
false, 4, 0 },
3744 { 3,
false, 5, 0 }} },
3745 { Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax,
3746 {{ 2,
false, 4, 0 },
3747 { 3,
false, 5, 0 }} },
3748 { Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{ 1,
false, 5, 0 }} },
3749 { Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{ 1,
false, 5, 0 }} },
3750 { Hexagon::BI__builtin_HEXAGON_S2_valignib, {{ 2,
false, 3, 0 }} },
3751 { Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{ 2,
false, 3, 0 }} },
3752 { Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{ 2,
false, 5, 0 }} },
3753 { Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{ 2,
false, 5, 0 }} },
3754 { Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{ 2,
false, 5, 0 }} },
3755 { Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{ 2,
false, 5, 0 }} },
3756 { Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{ 1,
true , 6, 0 }} },
3757 { Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{ 1,
true, 6, 0 }} },
3758 { Hexagon::BI__builtin_HEXAGON_S4_extract, {{ 1,
false, 5, 0 },
3759 { 2,
false, 5, 0 }} },
3760 { Hexagon::BI__builtin_HEXAGON_S4_extractp, {{ 1,
false, 6, 0 },
3761 { 2,
false, 6, 0 }} },
3762 { Hexagon::BI__builtin_HEXAGON_S4_lsli, {{ 0,
true, 6, 0 }} },
3763 { Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{ 1,
false, 5, 0 }} },
3764 { Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{ 2,
false, 5, 0 }} },
3765 { Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{ 2,
false, 5, 0 }} },
3766 { Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{ 2,
false, 5, 0 }} },
3767 { Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{ 2,
false, 5, 0 }} },
3768 { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{ 3,
false, 2, 0 }} },
3769 { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{ 2,
false, 2, 0 }} },
3770 { Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax,
3771 {{ 1,
false, 4, 0 }} },
3772 { Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{ 1,
false, 4, 0 }} },
3773 { Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax,
3774 {{ 1,
false, 4, 0 }} },
3775 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{ 1,
false, 6, 0 }} },
3776 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{ 2,
false, 6, 0 }} },
3777 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{ 2,
false, 6, 0 }} },
3778 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{ 2,
false, 6, 0 }} },
3779 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{ 2,
false, 6, 0 }} },
3780 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{ 2,
false, 6, 0 }} },
3781 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{ 1,
false, 5, 0 }} },
3782 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{ 2,
false, 5, 0 }} },
3783 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{ 2,
false, 5, 0 }} },
3784 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{ 2,
false, 5, 0 }} },
3785 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{ 2,
false, 5, 0 }} },
3786 { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{ 2,
false, 5, 0 }} },
3787 { Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{ 2,
false, 3, 0 }} },
3788 { Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{ 2,
false, 3, 0 }} },
3789 { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{ 2,
false, 3, 0 }} },
3790 { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{ 2,
false, 3, 0 }} },
3791 { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{ 2,
false, 1, 0 }} },
3792 { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{ 2,
false, 1, 0 }} },
3793 { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{ 3,
false, 1, 0 }} },
3794 { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B,
3795 {{ 3,
false, 1, 0 }} },
3796 { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{ 2,
false, 1, 0 }} },
3797 { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{ 2,
false, 1, 0 }} },
3798 { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{ 3,
false, 1, 0 }} },
3799 { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B,
3800 {{ 3,
false, 1, 0 }} },
3801 { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{ 2,
false, 1, 0 }} },
3802 { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{ 2,
false, 1, 0 }} },
3803 { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{ 3,
false, 1, 0 }} },
3804 { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B,
3805 {{ 3,
false, 1, 0 }} },
3807 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{ 2,
false, 2, 0 }} },
3808 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B,
3809 {{ 2,
false, 2, 0 }} },
3810 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx,
3811 {{ 3,
false, 2, 0 }} },
3812 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B,
3813 {{ 3,
false, 2, 0 }} },
3814 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{ 2,
false, 2, 0 }} },
3815 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B,
3816 {{ 2,
false, 2, 0 }} },
3817 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx,
3818 {{ 3,
false, 2, 0 }} },
3819 { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B,
3820 {{ 3,
false, 2, 0 }} },
3821 { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{ 2,
false, 3, 0 }} },
3822 { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{ 2,
false, 3, 0 }} },
3823 { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{ 3,
false, 3, 0 }} },
3824 { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B,
3825 {{ 3,
false, 3, 0 }} },
3826 { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{ 2,
false, 3, 0 }} },
3827 { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{ 2,
false, 3, 0 }} },
3828 { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{ 3,
false, 3, 0 }} },
3829 { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B,
3830 {{ 3,
false, 3, 0 }} },
3835 static const bool SortOnce =
3838 return LHS.BuiltinID < RHS.BuiltinID;
3844 Infos, [=](
const BuiltinInfo &BI) {
return BI.BuiltinID < BuiltinID; });
3845 if (F == std::end(Infos) || F->BuiltinID != BuiltinID)
3850 for (
const ArgInfo &A : F->Infos) {
3852 if (A.BitWidth == 0)
3855 int32_t Min = A.IsSigned ? -(1 << (A.BitWidth - 1)) : 0;
3856 int32_t Max = (1 << (A.IsSigned ? A.BitWidth - 1 : A.BitWidth)) - 1;
3858 Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max);
3860 unsigned M = 1 << A.Align;
3863 Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max);
3864 Error |= SemaBuiltinConstantArgMultiple(TheCall, A.OpNum, M);
3870bool Sema::CheckHexagonBuiltinFunctionCall(
unsigned BuiltinID,
3872 return CheckHexagonBuiltinArgument(BuiltinID, TheCall);
3875bool Sema::CheckLoongArchBuiltinFunctionCall(
const TargetInfo &TI,
3878 switch (BuiltinID) {
3881 case LoongArch::BI__builtin_loongarch_cacop_d:
3882 case LoongArch::BI__builtin_loongarch_cacop_w: {
3883 SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(5));
3884 SemaBuiltinConstantArgRange(TheCall, 2, llvm::minIntN(12),
3888 case LoongArch::BI__builtin_loongarch_break:
3889 case LoongArch::BI__builtin_loongarch_dbar:
3890 case LoongArch::BI__builtin_loongarch_ibar:
3891 case LoongArch::BI__builtin_loongarch_syscall:
3893 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
3894 case LoongArch::BI__builtin_loongarch_csrrd_w:
3895 case LoongArch::BI__builtin_loongarch_csrrd_d:
3896 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 16383);
3897 case LoongArch::BI__builtin_loongarch_csrwr_w:
3898 case LoongArch::BI__builtin_loongarch_csrwr_d:
3899 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 16383);
3900 case LoongArch::BI__builtin_loongarch_csrxchg_w:
3901 case LoongArch::BI__builtin_loongarch_csrxchg_d:
3902 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 16383);
3903 case LoongArch::BI__builtin_loongarch_lddir_d:
3904 case LoongArch::BI__builtin_loongarch_ldpte_d:
3905 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
3906 case LoongArch::BI__builtin_loongarch_movfcsr2gr:
3907 case LoongArch::BI__builtin_loongarch_movgr2fcsr:
3908 return SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(2));
3914bool Sema::CheckMipsBuiltinFunctionCall(
const TargetInfo &TI,
3915 unsigned BuiltinID,
CallExpr *TheCall) {
3916 return CheckMipsBuiltinCpu(TI, BuiltinID, TheCall) ||
3917 CheckMipsBuiltinArgument(BuiltinID, TheCall);
3920bool Sema::CheckMipsBuiltinCpu(
const TargetInfo &TI,
unsigned BuiltinID,
3923 if (Mips::BI__builtin_mips_addu_qb <= BuiltinID &&
3924 BuiltinID <= Mips::BI__builtin_mips_lwx) {
3926 return Diag(TheCall->
getBeginLoc(), diag::err_mips_builtin_requires_dsp);
3929 if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID &&
3930 BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) {
3933 diag::err_mips_builtin_requires_dspr2);
3936 if (Mips::BI__builtin_msa_add_a_b <= BuiltinID &&
3937 BuiltinID <= Mips::BI__builtin_msa_xori_b) {
3939 return Diag(TheCall->
getBeginLoc(), diag::err_mips_builtin_requires_msa);
3954bool Sema::CheckMipsBuiltinArgument(
unsigned BuiltinID,
CallExpr *TheCall) {
3955 unsigned i = 0, l = 0, u = 0, m = 0;
3956 switch (BuiltinID) {
3957 default:
return false;
3958 case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63;
break;
3959 case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63;
break;
3960 case Mips::BI__builtin_mips_append: i = 2; l = 0; u = 31;
break;
3961 case Mips::BI__builtin_mips_balign: i = 2; l = 0; u = 3;
break;
3962 case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31;
break;
3963 case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31;
break;
3964 case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31;
break;
3968 case Mips::BI__builtin_msa_bclri_b:
3969 case Mips::BI__builtin_msa_bnegi_b:
3970 case Mips::BI__builtin_msa_bseti_b:
3971 case Mips::BI__builtin_msa_sat_s_b:
3972 case Mips::BI__builtin_msa_sat_u_b:
3973 case Mips::BI__builtin_msa_slli_b:
3974 case Mips::BI__builtin_msa_srai_b:
3975 case Mips::BI__builtin_msa_srari_b:
3976 case Mips::BI__builtin_msa_srli_b:
3977 case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7;
break;
3978 case Mips::BI__builtin_msa_binsli_b:
3979 case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7;
break;
3981 case Mips::BI__builtin_msa_bclri_h:
3982 case Mips::BI__builtin_msa_bnegi_h:
3983 case Mips::BI__builtin_msa_bseti_h:
3984 case Mips::BI__builtin_msa_sat_s_h:
3985 case Mips::BI__builtin_msa_sat_u_h:
3986 case Mips::BI__builtin_msa_slli_h:
3987 case Mips::BI__builtin_msa_srai_h:
3988 case Mips::BI__builtin_msa_srari_h:
3989 case Mips::BI__builtin_msa_srli_h:
3990 case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15;
break;
3991 case Mips::BI__builtin_msa_binsli_h:
3992 case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15;
break;
3996 case Mips::BI__builtin_msa_cfcmsa:
3997 case Mips::BI__builtin_msa_ctcmsa: i = 0; l = 0; u = 31;
break;
3998 case Mips::BI__builtin_msa_clei_u_b:
3999 case Mips::BI__builtin_msa_clei_u_h:
4000 case Mips::BI__builtin_msa_clei_u_w:
4001 case Mips::BI__builtin_msa_clei_u_d:
4002 case Mips::BI__builtin_msa_clti_u_b:
4003 case Mips::BI__builtin_msa_clti_u_h:
4004 case Mips::BI__builtin_msa_clti_u_w:
4005 case Mips::BI__builtin_msa_clti_u_d:
4006 case Mips::BI__builtin_msa_maxi_u_b:
4007 case Mips::BI__builtin_msa_maxi_u_h:
4008 case Mips::BI__builtin_msa_maxi_u_w:
4009 case Mips::BI__builtin_msa_maxi_u_d:
4010 case Mips::BI__builtin_msa_mini_u_b:
4011 case Mips::BI__builtin_msa_mini_u_h:
4012 case Mips::BI__builtin_msa_mini_u_w:
4013 case Mips::BI__builtin_msa_mini_u_d:
4014 case Mips::BI__builtin_msa_addvi_b:
4015 case Mips::BI__builtin_msa_addvi_h:
4016 case Mips::BI__builtin_msa_addvi_w:
4017 case Mips::BI__builtin_msa_addvi_d:
4018 case Mips::BI__builtin_msa_bclri_w:
4019 case Mips::BI__builtin_msa_bnegi_w:
4020 case Mips::BI__builtin_msa_bseti_w:
4021 case Mips::BI__builtin_msa_sat_s_w:
4022 case Mips::BI__builtin_msa_sat_u_w:
4023 case Mips::BI__builtin_msa_slli_w:
4024 case Mips::BI__builtin_msa_srai_w:
4025 case Mips::BI__builtin_msa_srari_w:
4026 case Mips::BI__builtin_msa_srli_w:
4027 case Mips::BI__builtin_msa_srlri_w:
4028 case Mips::BI__builtin_msa_subvi_b:
4029 case Mips::BI__builtin_msa_subvi_h:
4030 case Mips::BI__builtin_msa_subvi_w:
4031 case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31;
break;
4032 case Mips::BI__builtin_msa_binsli_w:
4033 case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31;
break;
4035 case Mips::BI__builtin_msa_bclri_d:
4036 case Mips::BI__builtin_msa_bnegi_d:
4037 case Mips::BI__builtin_msa_bseti_d:
4038 case Mips::BI__builtin_msa_sat_s_d:
4039 case Mips::BI__builtin_msa_sat_u_d:
4040 case Mips::BI__builtin_msa_slli_d:
4041 case Mips::BI__builtin_msa_srai_d:
4042 case Mips::BI__builtin_msa_srari_d:
4043 case Mips::BI__builtin_msa_srli_d:
4044 case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63;
break;
4045 case Mips::BI__builtin_msa_binsli_d:
4046 case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63;
break;
4048 case Mips::BI__builtin_msa_ceqi_b:
4049 case Mips::BI__builtin_msa_ceqi_h:
4050 case Mips::BI__builtin_msa_ceqi_w:
4051 case Mips::BI__builtin_msa_ceqi_d:
4052 case Mips::BI__builtin_msa_clti_s_b:
4053 case Mips::BI__builtin_msa_clti_s_h:
4054 case Mips::BI__builtin_msa_clti_s_w:
4055 case Mips::BI__builtin_msa_clti_s_d:
4056 case Mips::BI__builtin_msa_clei_s_b:
4057 case Mips::BI__builtin_msa_clei_s_h:
4058 case Mips::BI__builtin_msa_clei_s_w:
4059 case Mips::BI__builtin_msa_clei_s_d:
4060 case Mips::BI__builtin_msa_maxi_s_b:
4061 case Mips::BI__builtin_msa_maxi_s_h:
4062 case Mips::BI__builtin_msa_maxi_s_w:
4063 case Mips::BI__builtin_msa_maxi_s_d:
4064 case Mips::BI__builtin_msa_mini_s_b:
4065 case Mips::BI__builtin_msa_mini_s_h:
4066 case Mips::BI__builtin_msa_mini_s_w:
4067 case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15;
break;
4069 case Mips::BI__builtin_msa_andi_b:
4070 case Mips::BI__builtin_msa_nori_b:
4071 case Mips::BI__builtin_msa_ori_b:
4072 case Mips::BI__builtin_msa_shf_b:
4073 case Mips::BI__builtin_msa_shf_h:
4074 case Mips::BI__builtin_msa_shf_w:
4075 case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255;
break;
4076 case Mips::BI__builtin_msa_bseli_b:
4077 case Mips::BI__builtin_msa_bmnzi_b:
4078 case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255;
break;
4081 case Mips::BI__builtin_msa_copy_s_b:
4082 case Mips::BI__builtin_msa_copy_u_b:
4083 case Mips::BI__builtin_msa_insve_b:
4084 case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15;
break;
4085 case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15;
break;
4087 case Mips::BI__builtin_msa_copy_s_h:
4088 case Mips::BI__builtin_msa_copy_u_h:
4089 case Mips::BI__builtin_msa_insve_h:
4090 case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7;
break;
4091 case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7;
break;
4093 case Mips::BI__builtin_msa_copy_s_w:
4094 case Mips::BI__builtin_msa_copy_u_w:
4095 case Mips::BI__builtin_msa_insve_w:
4096 case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3;
break;
4097 case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3;
break;
4099 case Mips::BI__builtin_msa_copy_s_d:
4100 case Mips::BI__builtin_msa_copy_u_d:
4101 case Mips::BI__builtin_msa_insve_d:
4102 case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1;
break;
4103 case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1;
break;
4106 case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255;
break;
4107 case Mips::BI__builtin_msa_ldi_h:
4108 case Mips::BI__builtin_msa_ldi_w:
4109 case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511;
break;
4110 case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1;
break;
4111 case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2;
break;
4112 case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4;
break;
4113 case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8;
break;
4114 case Mips::BI__builtin_msa_ldr_d: i = 1; l = -4096; u = 4088; m = 8;
break;
4115 case Mips::BI__builtin_msa_ldr_w: i = 1; l = -2048; u = 2044; m = 4;
break;
4116 case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1;
break;
4117 case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2;
break;
4118 case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4;
break;
4119 case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8;
break;
4120 case Mips::BI__builtin_msa_str_d: i = 2; l = -4096; u = 4088; m = 8;
break;
4121 case Mips::BI__builtin_msa_str_w: i = 2; l = -2048; u = 2044; m = 4;
break;
4125 return SemaBuiltinConstantArgRange(TheCall, i, l, u);
4127 return SemaBuiltinConstantArgRange(TheCall, i, l, u) ||
4128 SemaBuiltinConstantArgMultiple(TheCall, i, m);
4139 bool RequireICE =
false;
4147 unsigned size = strtoul(Str, &End, 10);
4148 assert(End != Str &&
"Missing constant parameter constraint");
4151 return Context.
IntTy;
4155 unsigned size = strtoul(Str, &End, 10);
4156 assert(End != Str &&
"Missing PowerPC MMA type size");
4160 #define PPC_VECTOR_TYPE(typeName, Id, size) \
4161 case size: Type = Context.Id##Ty; break;
4162 #include "clang/Basic/PPCTypes.def"
4163 default: llvm_unreachable(
"Invalid PowerPC MMA vector type");
4165 bool CheckVectorArgs =
false;
4166 while (!CheckVectorArgs) {
4175 CheckVectorArgs =
true;
4189 switch (BuiltinID) {
4190 case PPC::BI__builtin_divde:
4191 case PPC::BI__builtin_divdeu:
4192 case PPC::BI__builtin_bpermd:
4193 case PPC::BI__builtin_pdepd:
4194 case PPC::BI__builtin_pextd:
4195 case PPC::BI__builtin_ppc_ldarx:
4196 case PPC::BI__builtin_ppc_stdcx:
4197 case PPC::BI__builtin_ppc_tdw:
4198 case PPC::BI__builtin_ppc_trapd:
4199 case PPC::BI__builtin_ppc_cmpeqb:
4200 case PPC::BI__builtin_ppc_setb:
4201 case PPC::BI__builtin_ppc_mulhd:
4202 case PPC::BI__builtin_ppc_mulhdu:
4203 case PPC::BI__builtin_ppc_maddhd:
4204 case PPC::BI__builtin_ppc_maddhdu:
4205 case PPC::BI__builtin_ppc_maddld:
4206 case PPC::BI__builtin_ppc_load8r:
4207 case PPC::BI__builtin_ppc_store8r:
4208 case PPC::BI__builtin_ppc_insert_exp:
4209 case PPC::BI__builtin_ppc_extract_sig:
4210 case PPC::BI__builtin_ppc_addex:
4211 case PPC::BI__builtin_darn:
4212 case PPC::BI__builtin_darn_raw:
4213 case PPC::BI__builtin_ppc_compare_and_swaplp:
4214 case PPC::BI__builtin_ppc_fetch_and_addlp:
4215 case PPC::BI__builtin_ppc_fetch_and_andlp:
4216 case PPC::BI__builtin_ppc_fetch_and_orlp:
4217 case PPC::BI__builtin_ppc_fetch_and_swaplp:
4227bool Sema::SemaValueIsRunOfOnes(
CallExpr *TheCall,
unsigned ArgNum) {
4235 if (SemaBuiltinConstantArg(TheCall, ArgNum,
Result))
4239 if (
Result.isShiftedMask() || (~
Result).isShiftedMask())
4243 diag::err_argument_not_contiguous_bit_field)
4247bool Sema::CheckPPCBuiltinFunctionCall(
const TargetInfo &TI,
unsigned BuiltinID,
4249 unsigned i = 0, l = 0, u = 0;
4254 return Diag(TheCall->
getBeginLoc(), diag::err_64_bit_builtin_32_bit_tgt)
4257 switch (BuiltinID) {
4258 default:
return false;
4259 case PPC::BI__builtin_altivec_crypto_vshasigmaw:
4260 case PPC::BI__builtin_altivec_crypto_vshasigmad:
4261 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) ||
4262 SemaBuiltinConstantArgRange(TheCall, 2, 0, 15);
4263 case PPC::BI__builtin_altivec_dss:
4264 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3);
4265 case PPC::BI__builtin_tbegin:
4266 case PPC::BI__builtin_tend:
4267 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
4268 case PPC::BI__builtin_tsr:
4269 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7);
4270 case PPC::BI__builtin_tabortwc:
4271 case PPC::BI__builtin_tabortdc:
4272 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
4273 case PPC::BI__builtin_tabortwci:
4274 case PPC::BI__builtin_tabortdci:
4275 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) ||
4276 SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
4280 case PPC::BI__builtin_unpack_longdouble:
4281 if (SemaBuiltinConstantArgRange(TheCall, 1, 0, 1))
4284 case PPC::BI__builtin_pack_longdouble:
4286 return Diag(TheCall->
getBeginLoc(), diag::err_ppc_builtin_requires_abi)
4289 case PPC::BI__builtin_altivec_dst:
4290 case PPC::BI__builtin_altivec_dstt:
4291 case PPC::BI__builtin_altivec_dstst:
4292 case PPC::BI__builtin_altivec_dststt:
4293 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
4294 case PPC::BI__builtin_vsx_xxpermdi:
4295 case PPC::BI__builtin_vsx_xxsldwi:
4296 return SemaBuiltinVSX(TheCall);
4297 case PPC::BI__builtin_unpack_vector_int128:
4298 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
4299 case PPC::BI__builtin_altivec_vgnb:
4300 return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
4301 case PPC::BI__builtin_vsx_xxeval:
4302 return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
4303 case PPC::BI__builtin_altivec_vsldbi:
4304 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
4305 case PPC::BI__builtin_altivec_vsrdbi:
4306 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
4307 case PPC::BI__builtin_vsx_xxpermx:
4308 return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
4309 case PPC::BI__builtin_ppc_tw:
4310 case PPC::BI__builtin_ppc_tdw:
4311 return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
4312 case PPC::BI__builtin_ppc_cmprb:
4313 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
4316 case PPC::BI__builtin_ppc_rlwnm:
4317 return SemaValueIsRunOfOnes(TheCall, 2);
4318 case PPC::BI__builtin_ppc_rlwimi:
4319 case PPC::BI__builtin_ppc_rldimi:
4320 return SemaBuiltinConstantArg(TheCall, 2,
Result) ||
4321 SemaValueIsRunOfOnes(TheCall, 3);
4322 case PPC::BI__builtin_ppc_addex: {
4323 if (SemaBuiltinConstantArgRange(TheCall, 2, 0, 3))
4333 case PPC::BI__builtin_ppc_mtfsb0:
4334 case PPC::BI__builtin_ppc_mtfsb1:
4335 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
4336 case PPC::BI__builtin_ppc_mtfsf:
4337 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 255);
4338 case PPC::BI__builtin_ppc_mtfsfi:
4339 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) ||
4340 SemaBuiltinConstantArgRange(TheCall, 1, 0, 15);
4341 case PPC::BI__builtin_ppc_alignx:
4342 return SemaBuiltinConstantArgPower2(TheCall, 0);
4343 case PPC::BI__builtin_ppc_rdlam:
4344 return SemaValueIsRunOfOnes(TheCall, 2);
4345 case PPC::BI__builtin_vsx_ldrmb:
4346 case PPC::BI__builtin_vsx_strmb:
4347 return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
4348 case PPC::BI__builtin_altivec_vcntmbb:
4349 case PPC::BI__builtin_altivec_vcntmbh:
4350 case PPC::BI__builtin_altivec_vcntmbw:
4351 case PPC::BI__builtin_altivec_vcntmbd:
4352 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
4353 case PPC::BI__builtin_vsx_xxgenpcvbm:
4354 case PPC::BI__builtin_vsx_xxgenpcvhm:
4355 case PPC::BI__builtin_vsx_xxgenpcvwm:
4356 case PPC::BI__builtin_vsx_xxgenpcvdm:
4357 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
4358 case PPC::BI__builtin_ppc_test_data_class: {
4366 diag::err_ppc_invalid_test_data_class_type);
4367 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 127);
4369 case PPC::BI__builtin_ppc_maxfe:
4370 case PPC::BI__builtin_ppc_minfe:
4371 case PPC::BI__builtin_ppc_maxfl:
4372 case PPC::BI__builtin_ppc_minfl:
4373 case PPC::BI__builtin_ppc_maxfs:
4374 case PPC::BI__builtin_ppc_minfs: {
4376 (BuiltinID == PPC::BI__builtin_ppc_maxfe ||
4377 BuiltinID == PPC::BI__builtin_ppc_minfe))
4378 return Diag(TheCall->
getBeginLoc(), diag::err_target_unsupported_type)
4383 if (BuiltinID == PPC::BI__builtin_ppc_maxfl ||
4384 BuiltinID == PPC::BI__builtin_ppc_minfl)
4386 else if (BuiltinID == PPC::BI__builtin_ppc_maxfs ||
4387 BuiltinID == PPC::BI__builtin_ppc_minfs)
4389 for (
unsigned I = 0, E = TheCall->
getNumArgs(); I < E; ++I)
4392 diag::err_typecheck_convert_incompatible)
4396#define CUSTOM_BUILTIN(Name, Intr, Types, Acc, Feature) \
4397 case PPC::BI__builtin_##Name: \
4398 return SemaBuiltinPPCMMACall(TheCall, BuiltinID, Types);
4399#include "clang/Basic/BuiltinsPPC.def"
4401 return SemaBuiltinConstantArgRange(TheCall, i, l, u);
4410 QualType CoreType =
Type.getCanonicalType().getUnqualifiedType();
4411#define PPC_VECTOR_TYPE(Name, Id, Size) || CoreType == Context.Id##Ty
4413#include
"clang/Basic/PPCTypes.def"
4415 Diag(
TypeLoc, diag::err_ppc_invalid_use_mma_type);
4421bool Sema::CheckAMDGCNBuiltinFunctionCall(
unsigned BuiltinID,
4424 unsigned OrderIndex, ScopeIndex;
4425 switch (BuiltinID) {
4426 case AMDGPU::BI__builtin_amdgcn_atomic_inc32:
4427 case AMDGPU::BI__builtin_amdgcn_atomic_inc64:
4428 case AMDGPU::BI__builtin_amdgcn_atomic_dec32:
4429 case AMDGPU::BI__builtin_amdgcn_atomic_dec64:
4433 case AMDGPU::BI__builtin_amdgcn_fence:
4442 auto ArgExpr = Arg.
get();
4445 if (!ArgExpr->EvaluateAsInt(ArgResult,
Context))
4446 return Diag(ArgExpr->getExprLoc(), diag::err_typecheck_expect_int)
4447 << ArgExpr->getType();
4448 auto Ord = ArgResult.
Val.
getInt().getZExtValue();
4452 if (!llvm::isValidAtomicOrderingCABI(Ord))
4453 return Diag(ArgExpr->getBeginLoc(),
4454 diag::warn_atomic_op_has_invalid_memory_order)
4455 << ArgExpr->getSourceRange();
4456 switch (
static_cast<llvm::AtomicOrderingCABI
>(Ord)) {
4457 case llvm::AtomicOrderingCABI::relaxed:
4458 case llvm::AtomicOrderingCABI::consume:
4459 if (BuiltinID == AMDGPU::BI__builtin_amdgcn_fence)
4460 return Diag(ArgExpr->getBeginLoc(),
4461 diag::warn_atomic_op_has_invalid_memory_order)
4462 << ArgExpr->getSourceRange();
4464 case llvm::AtomicOrderingCABI::acquire:
4465 case llvm::AtomicOrderingCABI::release:
4466 case llvm::AtomicOrderingCABI::acq_rel:
4467 case llvm::AtomicOrderingCABI::seq_cst:
4471 Arg = TheCall->
getArg(ScopeIndex);
4472 ArgExpr = Arg.
get();
4475 if (!ArgExpr->EvaluateAsConstantExpr(ArgResult1,
Context))
4476 return Diag(ArgExpr->getExprLoc(), diag::err_expr_not_string_literal)
4477 << ArgExpr->getType();
4482bool Sema::CheckRISCVLMUL(
CallExpr *TheCall,
unsigned ArgNum) {
4491 if (SemaBuiltinConstantArg(TheCall, ArgNum,
Result))
4495 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7))
4498 return Diag(TheCall->
getBeginLoc(), diag::err_riscv_builtin_invalid_lmul)
4504 assert((EGW == 128 || EGW == 256) &&
"EGW can only be 128 or 256 bits");
4514 unsigned EGS = EGW / ElemSize;
4517 if (EGS <= MinElemCount)
4521 assert(EGS % MinElemCount == 0);
4522 unsigned VScaleFactor = EGS / MinElemCount;
4524 unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
4525 std::string RequiredExt =
"zvl" + std::to_string(MinRequiredVLEN) +
"b";
4528 diag::err_riscv_type_requires_extension) <<
Type << RequiredExt;
4533bool Sema::CheckRISCVBuiltinFunctionCall(
const TargetInfo &TI,
4538 bool FeatureMissing =
false;
4541 Features.split(ReqFeatures,
',', -1,
false);
4544 for (StringRef F : ReqFeatures) {
4546 F.split(ReqOpFeatures,
'|');
4548 if (llvm::none_of(ReqOpFeatures,
4549 [&TI](StringRef OF) {
return TI.
hasFeature(OF); })) {
4550 std::string FeatureStrs;
4551 bool IsExtension =
true;
4552 for (StringRef OF : ReqOpFeatures) {
4555 if (OF ==
"64bit") {
4556 assert(ReqOpFeatures.size() == 1 &&
"Expected '64bit' to be alone");
4558 IsExtension =
false;
4560 if (OF ==
"32bit") {
4561 assert(ReqOpFeatures.size() == 1 &&
"Expected '32bit' to be alone");
4563 IsExtension =
false;
4567 OF.consume_front(
"experimental-");
4568 std::string FeatureStr = OF.str();
4569 FeatureStr[0] = std::toupper(FeatureStr[0]);
4571 FeatureStrs += FeatureStrs.empty() ?
"" :
", ";
4573 FeatureStrs += FeatureStr;
4577 FeatureMissing =
true;
4578 Diag(TheCall->
getBeginLoc(), diag::err_riscv_builtin_requires_extension)
4589 switch (BuiltinID) {
4592 case RISCVVector::BI__builtin_rvv_vmulhsu_vv:
4593 case RISCVVector::BI__builtin_rvv_vmulhsu_vx:
4594 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tu:
4595 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tu:
4596 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_m:
4597 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_m:
4598 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_mu:
4599 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_mu:
4600 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tum:
4601 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tum:
4602 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tumu:
4603 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tumu:
4604 case RISCVVector::BI__builtin_rvv_vmulhu_vv:
4605 case RISCVVector::BI__builtin_rvv_vmulhu_vx:
4606 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tu:
4607 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tu:
4608 case RISCVVector::BI__builtin_rvv_vmulhu_vv_m:
4609 case RISCVVector::BI__builtin_rvv_vmulhu_vx_m:
4610 case RISCVVector::BI__builtin_rvv_vmulhu_vv_mu:
4611 case RISCVVector::BI__builtin_rvv_vmulhu_vx_mu:
4612 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tum:
4613 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tum:
4614 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tumu:
4615 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tumu:
4616 case RISCVVector::BI__builtin_rvv_vmulh_vv:
4617 case RISCVVector::BI__builtin_rvv_vmulh_vx:
4618 case RISCVVector::BI__builtin_rvv_vmulh_vv_tu:
4619 case RISCVVector::BI__builtin_rvv_vmulh_vx_tu:
4620 case RISCVVector::BI__builtin_rvv_vmulh_vv_m:
4621 case RISCVVector::BI__builtin_rvv_vmulh_vx_m:
4622 case RISCVVector::BI__builtin_rvv_vmulh_vv_mu:
4623 case RISCVVector::BI__builtin_rvv_vmulh_vx_mu:
4624 case RISCVVector::BI__builtin_rvv_vmulh_vv_tum:
4625 case RISCVVector::BI__builtin_rvv_vmulh_vx_tum:
4626 case RISCVVector::BI__builtin_rvv_vmulh_vv_tumu:
4627 case RISCVVector::BI__builtin_rvv_vmulh_vx_tumu:
4628 case RISCVVector::BI__builtin_rvv_vsmul_vv:
4629 case RISCVVector::BI__builtin_rvv_vsmul_vx:
4630 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:
4631 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:
4632 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:
4633 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:
4634 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:
4635 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:
4636 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:
4637 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:
4638 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:
4639 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {
4640 bool RequireV =
false;
4641 for (
unsigned ArgNum = 0; ArgNum < TheCall->
getNumArgs(); ++ArgNum)
4647 diag::err_riscv_builtin_requires_extension)
4654 switch (BuiltinID) {
4655 case RISCVVector::BI__builtin_rvv_vsetvli:
4656 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) ||
4657 CheckRISCVLMUL(TheCall, 2);
4658 case RISCVVector::BI__builtin_rvv_vsetvlimax:
4659 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4660 CheckRISCVLMUL(TheCall, 1);
4661 case RISCVVector::BI__builtin_rvv_vget_v: {
4672 MaxIndex = (VecInfo.
EC.getKnownMinValue() * VecInfo.
NumVectors) /
4673 (ResVecInfo.
EC.getKnownMinValue() * ResVecInfo.
NumVectors);
4674 return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);
4676 case RISCVVector::BI__builtin_rvv_vset_v: {
4687 MaxIndex = (ResVecInfo.
EC.getKnownMinValue() * ResVecInfo.
NumVectors) /
4689 return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);
4692 case RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu:
4693 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:
4694 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:
4695 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {
4700 SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
4702 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:
4703 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {
4706 SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
4708 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:
4709 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {
4712 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
4714 case RISCVVector::BI__builtin_rvv_vaesdf_vv:
4715 case RISCVVector::BI__builtin_rvv_vaesdf_vs:
4716 case RISCVVector::BI__builtin_rvv_vaesdm_vv:
4717 case RISCVVector::BI__builtin_rvv_vaesdm_vs:
4718 case RISCVVector::BI__builtin_rvv_vaesef_vv:
4719 case RISCVVector::BI__builtin_rvv_vaesef_vs:
4720 case RISCVVector::BI__builtin_rvv_vaesem_vv:
4721 case RISCVVector::BI__builtin_rvv_vaesem_vs:
4722 case RISCVVector::BI__builtin_rvv_vaesz_vs:
4723 case RISCVVector::BI__builtin_rvv_vsm4r_vv:
4724 case RISCVVector::BI__builtin_rvv_vsm4r_vs:
4725 case RISCVVector::BI__builtin_rvv_vaesdf_vv_tu:
4726 case RISCVVector::BI__builtin_rvv_vaesdf_vs_tu:
4727 case RISCVVector::BI__builtin_rvv_vaesdm_vv_tu:
4728 case RISCVVector::BI__builtin_rvv_vaesdm_vs_tu:
4729 case RISCVVector::BI__builtin_rvv_vaesef_vv_tu:
4730 case RISCVVector::BI__builtin_rvv_vaesef_vs_tu:
4731 case RISCVVector::BI__builtin_rvv_vaesem_vv_tu:
4732 case RISCVVector::BI__builtin_rvv_vaesem_vs_tu:
4733 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:
4734 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:
4735 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {
4741 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:
4742 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:
4743 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:
4744 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:
4745 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:
4746 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {
4751 if (ElemSize == 64 && !TI.
hasFeature(
"experimental-zvknhb"))
4754 << Op1Type <<
"experimental-zvknhb";
4761 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8:
4762 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf4:
4763 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf2:
4764 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m1:
4765 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m2:
4766 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m4:
4767 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m8:
4768 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf4:
4769 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf2:
4770 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m1:
4771 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m2:
4772 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m4:
4773 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m8:
4774 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32mf2:
4775 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m1:
4776 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m2:
4777 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m4:
4778 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m8:
4779 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m1:
4780 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m2:
4781 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m4:
4782 case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m8:
4784 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4785 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
4786 SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) ||
4787 SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
4788 case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:
4790 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4791 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
4792 SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
4793 case RISCVVector::BI__builtin_rvv_sf_vc_v_i:
4794 case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:
4796 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4797 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
4798 SemaBuiltinConstantArgRange(TheCall, 2, -16, 15);
4799 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv:
4800 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:
4802 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4803 SemaBuiltinConstantArgRange(TheCall, 2, -16, 15);
4804 case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:
4805 case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:
4806 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:
4807 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:
4808 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:
4809 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:
4811 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4812 SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
4813 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf8:
4814 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf4:
4815 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf2:
4816 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m1:
4817 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m2:
4818 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m4:
4819 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m8:
4820 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf4:
4821 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf2:
4822 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m1:
4823 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m2:
4824 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m4:
4825 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m8:
4826 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32mf2:
4827 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m1:
4828 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m2:
4829 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m4:
4830 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m8:
4831 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m1:
4832 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m2:
4833 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m4:
4834 case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m8:
4836 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4837 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
4838 SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
4839 case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:
4840 case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:
4842 case RISCVVector::BI__builtin_rvv_sf_vc_v_x:
4843 case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:
4845 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
4846 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
4847 case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:
4848 case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:
4849 case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:
4850 case RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:
4852 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv:
4853 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv:
4854 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:
4855 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:
4857 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:
4858 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:
4859 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:
4860 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:
4861 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:
4862 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:
4863 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:
4864 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:
4866 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3);
4867 case RISCVVector::BI__builtin_rvv_sf_vc_fv_se:
4869 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1) ||
4870 SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
4871 case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:
4872 case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:
4873 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:
4874 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:
4875 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:
4876 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:
4878 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv:
4879 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:
4881 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
4883 case RISCV::BI__builtin_riscv_aes32dsi:
4884 case RISCV::BI__builtin_riscv_aes32dsmi:
4885 case RISCV::BI__builtin_riscv_aes32esi:
4886 case RISCV::BI__builtin_riscv_aes32esmi:
4887 case RISCV::BI__builtin_riscv_sm4ks:
4888 case RISCV::BI__builtin_riscv_sm4ed:
4889 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
4891 case RISCV::BI__builtin_riscv_aes64ks1i:
4892 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 10);
4894 case RISCVVector::BI__builtin_rvv_vaaddu_vv:
4895 case RISCVVector::BI__builtin_rvv_vaaddu_vx:
4896 case RISCVVector::BI__builtin_rvv_vaadd_vv:
4897 case RISCVVector::BI__builtin_rvv_vaadd_vx:
4898 case RISCVVector::BI__builtin_rvv_vasubu_vv:
4899 case RISCVVector::BI__builtin_rvv_vasubu_vx:
4900 case RISCVVector::BI__builtin_rvv_vasub_vv:
4901 case RISCVVector::BI__builtin_rvv_vasub_vx:
4902 case RISCVVector::BI__builtin_rvv_vsmul_vv:
4903 case RISCVVector::BI__builtin_rvv_vsmul_vx:
4904 case RISCVVector::BI__builtin_rvv_vssra_vv:
4905 case RISCVVector::BI__builtin_rvv_vssra_vx:
4906 case RISCVVector::BI__builtin_rvv_vssrl_vv:
4907 case RISCVVector::BI__builtin_rvv_vssrl_vx:
4908 case RISCVVector::BI__builtin_rvv_vnclip_wv:
4909 case RISCVVector::BI__builtin_rvv_vnclip_wx:
4910 case RISCVVector::BI__builtin_rvv_vnclipu_wv:
4911 case RISCVVector::BI__builtin_rvv_vnclipu_wx:
4912 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
4913 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu:
4914 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu:
4915 case RISCVVector::BI__builtin_rvv_vaadd_vv_tu:
4916 case RISCVVector::BI__builtin_rvv_vaadd_vx_tu:
4917 case RISCVVector::BI__builtin_rvv_vasubu_vv_tu:
4918 case RISCVVector::BI__builtin_rvv_vasubu_vx_tu:
4919 case RISCVVector::BI__builtin_rvv_vasub_vv_tu:
4920 case RISCVVector::BI__builtin_rvv_vasub_vx_tu:
4921 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:
4922 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:
4923 case RISCVVector::BI__builtin_rvv_vssra_vv_tu:
4924 case RISCVVector::BI__builtin_rvv_vssra_vx_tu:
4925 case RISCVVector::BI__builtin_rvv_vssrl_vv_tu:
4926 case RISCVVector::BI__builtin_rvv_vssrl_vx_tu:
4927 case RISCVVector::BI__builtin_rvv_vnclip_wv_tu:
4928 case RISCVVector::BI__builtin_rvv_vnclip_wx_tu:
4929 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:
4930 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:
4931 case RISCVVector::BI__builtin_rvv_vaaddu_vv_m:
4932 case RISCVVector::BI__builtin_rvv_vaaddu_vx_m:
4933 case RISCVVector::BI__builtin_rvv_vaadd_vv_m:
4934 case RISCVVector::BI__builtin_rvv_vaadd_vx_m:
4935 case RISCVVector::BI__builtin_rvv_vasubu_vv_m:
4936 case RISCVVector::BI__builtin_rvv_vasubu_vx_m:
4937 case RISCVVector::BI__builtin_rvv_vasub_vv_m:
4938 case RISCVVector::BI__builtin_rvv_vasub_vx_m:
4939 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:
4940 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:
4941 case RISCVVector::BI__builtin_rvv_vssra_vv_m:
4942 case RISCVVector::BI__builtin_rvv_vssra_vx_m:
4943 case RISCVVector::BI__builtin_rvv_vssrl_vv_m:
4944 case RISCVVector::BI__builtin_rvv_vssrl_vx_m:
4945 case RISCVVector::BI__builtin_rvv_vnclip_wv_m:
4946 case RISCVVector::BI__builtin_rvv_vnclip_wx_m:
4947 case RISCVVector::BI__builtin_rvv_vnclipu_wv_m:
4948 case RISCVVector::BI__builtin_rvv_vnclipu_wx_m:
4949 return SemaBuiltinConstantArgRange(TheCall, 3, 0, 3);
4950 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:
4951 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:
4952 case RISCVVector::BI__builtin_rvv_vaaddu_vv_mu:
4953 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tum:
4954 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tumu:
4955 case RISCVVector::BI__builtin_rvv_vaaddu_vx_mu:
4956 case RISCVVector::BI__builtin_rvv_vaadd_vv_tum:
4957 case RISCVVector::BI__builtin_rvv_vaadd_vv_tumu:
4958 case RISCVVector::BI__builtin_rvv_vaadd_vv_mu:
4959 case RISCVVector::BI__builtin_rvv_vaadd_vx_tum:
4960 case RISCVVector::BI__builtin_rvv_vaadd_vx_tumu:
4961 case RISCVVector::BI__builtin_rvv_vaadd_vx_mu:
4962 case RISCVVector::BI__builtin_rvv_vasubu_vv_tum:
4963 case RISCVVector::BI__builtin_rvv_vasubu_vv_tumu:
4964 case RISCVVector::BI__builtin_rvv_vasubu_vv_mu:
4965 case RISCVVector::BI__builtin_rvv_vasubu_vx_tum:
4966 case RISCVVector::BI__builtin_rvv_vasubu_vx_tumu:
4967 case RISCVVector::BI__builtin_rvv_vasubu_vx_mu:
4968 case RISCVVector::BI__builtin_rvv_vasub_vv_tum:
4969 case RISCVVector::BI__builtin_rvv_vasub_vv_tumu:
4970 case RISCVVector::BI__builtin_rvv_vasub_vv_mu:
4971 case RISCVVector::BI__builtin_rvv_vasub_vx_tum:
4972 case RISCVVector::BI__builtin_rvv_vasub_vx_tumu:
4973 case RISCVVector::BI__builtin_rvv_vasub_vx_mu:
4974 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:
4975 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:
4976 case RISCVVector::BI__builtin_rvv_vssra_vv_mu:
4977 case RISCVVector::BI__builtin_rvv_vssra_vx_mu:
4978 case RISCVVector::BI__builtin_rvv_vssrl_vv_mu:
4979 case RISCVVector::BI__builtin_rvv_vssrl_vx_mu:
4980 case RISCVVector::BI__builtin_rvv_vnclip_wv_mu:
4981 case RISCVVector::BI__builtin_rvv_vnclip_wx_mu:
4982 case RISCVVector::BI__builtin_rvv_vnclipu_wv_mu:
4983 case RISCVVector::BI__builtin_rvv_vnclipu_wx_mu:
4984 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:
4985 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:
4986 case RISCVVector::BI__builtin_rvv_vssra_vv_tum:
4987 case RISCVVector::BI__builtin_rvv_vssra_vx_tum:
4988 case RISCVVector::BI__builtin_rvv_vssrl_vv_tum:
4989 case RISCVVector::BI__builtin_rvv_vssrl_vx_tum:
4990 case RISCVVector::BI__builtin_rvv_vnclip_wv_tum:
4991 case RISCVVector::BI__builtin_rvv_vnclip_wx_tum:
4992 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tum:
4993 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tum:
4994 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:
4995 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu:
4996 case RISCVVector::BI__builtin_rvv_vssra_vv_tumu:
4997 case RISCVVector::BI__builtin_rvv_vssra_vx_tumu:
4998 case RISCVVector::BI__builtin_rvv_vssrl_vv_tumu:
4999 case RISCVVector::BI__builtin_rvv_vssrl_vx_tumu:
5000 case RISCVVector::BI__builtin_rvv_vnclip_wv_tumu:
5001 case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu:
5002 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu:
5003 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu:
5004 return SemaBuiltinConstantArgRange(TheCall, 4, 0, 3);
5005 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm:
5006 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm:
5007 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm:
5008 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm:
5009 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm:
5010 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm:
5011 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm:
5012 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm:
5013 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm:
5014 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm:
5015 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:
5016 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:
5017 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:
5018 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 4);
5019 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:
5020 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:
5021 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm:
5022 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm:
5023 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:
5024 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm:
5025 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm:
5026 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm:
5027 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm:
5028 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm:
5029 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm:
5030 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm:
5031 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm:
5032 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm:
5033 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm:
5034 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm:
5035 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm:
5036 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:
5037 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:
5038 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:
5039 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:
5040 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:
5041 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:
5042 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:
5043 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:
5044 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:
5045 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:
5046 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tu:
5047 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tu:
5048 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tu:
5049 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tu:
5050 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tu:
5051 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tu:
5052 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tu:
5053 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:
5054 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:
5055 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:
5056 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:
5057 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:
5058 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:
5059 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_m:
5060 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_m:
5061 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_m:
5062 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_m:
5063 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_m:
5064 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_m:
5065 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_m:
5066 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:
5067 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:
5068 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:
5069 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 4);
5070 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:
5071 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
5072 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:
5073 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:
5074 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:
5075 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tu:
5076 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tu:
5077 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tu:
5078 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tu:
5079 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tu:
5080 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tu:
5081 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tu:
5082 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:
5083 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:
5084 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:
5085 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:
5086 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:
5087 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:
5088 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:
5089 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:
5090 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:
5091 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:
5092 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:
5093 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:
5094 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:
5095 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:
5096 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:
5097 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:
5098 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:
5099 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:
5100 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:
5101 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:
5102 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:
5103 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:
5104 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:
5105 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:
5106 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:
5107 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:
5108 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:
5109 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:
5110 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm:
5111 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm:
5112 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm:
5113 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm:
5114 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm:
5115 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:
5116 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:
5117 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:
5118 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:
5119 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:
5120 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:
5121 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:
5122 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:
5123 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:
5124 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:
5125 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:
5126 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:
5127 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:
5128 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:
5129 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:
5130 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:
5131 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:
5132 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:
5133 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:
5134 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tu:
5135 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tu:
5136 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tu:
5137 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tu:
5138 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tu:
5139 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:
5140 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:
5141 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:
5142 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:
5143 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:
5144 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:
5145 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_m:
5146 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_m:
5147 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_m:
5148 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_m:
5149 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_m:
5150 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_m:
5151 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_m:
5152 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_m:
5153 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_m:
5154 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_m:
5155 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_m:
5156 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_m:
5157 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_m:
5158 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_m:
5159 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_m:
5160 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_m:
5161 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_m:
5162 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_m:
5163 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_m:
5164 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_m:
5165 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_m:
5166 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:
5167 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:
5168 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:
5169 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tum:
5170 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tum:
5171 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tum:
5172 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tum:
5173 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tum:
5174 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tum:
5175 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tum:
5176 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:
5177 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:
5178 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:
5179 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:
5180 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:
5181 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:
5182 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tumu:
5183 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tumu:
5184 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tumu:
5185 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tumu:
5186 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tumu:
5187 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tumu:
5188 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tumu:
5189 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:
5190 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:
5191 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:
5192 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:
5193 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:
5194 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:
5195 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_mu:
5196 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_mu:
5197 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_mu:
5198 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_mu:
5199 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_mu:
5200 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_mu:
5201 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_mu:
5202 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:
5203 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:
5204 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:
5205 return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4);
5206 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:
5207 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:
5208 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m:
5209 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_m:
5210 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_m:
5211 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_m:
5212 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_m:
5213 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_m:
5214 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_m:
5215 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_m:
5216 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_m:
5217 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_m:
5218 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_m:
5219 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_m:
5220 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_m:
5221 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_m:
5222 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_m:
5223 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_m:
5224 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_m:
5225 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_m:
5226 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_m:
5227 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:
5228 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:
5229 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:
5230 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
5231 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
5232 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
5233 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:
5234 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:
5235 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:
5236 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:
5237 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:
5238 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:
5239 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:
5240 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:
5241 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:
5242 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:
5243 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:
5244 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:
5245 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:
5246 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:
5247 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:
5248 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:
5249 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:
5250 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:
5251 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:
5252 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:
5253 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:
5254 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:
5255 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:
5256 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:
5257 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:
5258 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:
5259 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:
5260 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:
5261 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:
5262 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:
5263 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:
5264 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:
5265 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:
5266 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tum:
5267 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tum:
5268 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tum:
5269 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tum:
5270 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tum:
5271 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:
5272 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:
5273 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:
5274 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:
5275 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:
5276 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:
5277 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:
5278 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:
5279 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:
5280 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:
5281 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:
5282 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:
5283 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:
5284 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:
5285 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:
5286 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:
5287 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:
5288 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:
5289 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:
5290 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:
5291 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:
5292 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:
5293 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:
5294 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:
5295 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:
5296 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:
5297 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:
5298 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:
5299 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:
5300 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:
5301 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:
5302 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:
5303 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:
5304 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:
5305 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:
5306 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:
5307 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:
5308 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:
5309 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:
5310 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:
5311 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:
5312 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:
5313 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:
5314 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tumu:
5315 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tumu:
5316 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tumu:
5317 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tumu:
5318 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tumu:
5319 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:
5320 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:
5321 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:
5322 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
5323 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
5324 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
5325 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:
5326 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:
5327 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:
5328 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:
5329 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:
5330 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:
5331 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:
5332 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:
5333 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:
5334 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:
5335 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:
5336 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:
5337 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:
5338 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:
5339 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:
5340 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:
5341 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:
5342 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:
5343 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:
5344 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:
5345 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:
5346 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:
5347 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:
5348 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:
5349 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:
5350 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:
5351 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:
5352 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:
5353 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:
5354 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:
5355 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:
5356 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:
5357 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:
5358 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_mu:
5359 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_mu:
5360 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_mu:
5361 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_mu:
5362 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_mu:
5363 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:
5364 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:
5365 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
5366 return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4);
5367 case RISCV::BI__builtin_riscv_ntl_load:
5368 case RISCV::BI__builtin_riscv_ntl_store:
5371 assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||
5372 BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&
5373 "Unexpected RISC-V nontemporal load/store builtin!");
5374 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;
5375 unsigned NumArgs = IsStore ? 3 : 2;
5386 SemaBuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5))
5393 if (PointerArgResult.