clang 24.0.0git
riscv_packed_simd.h File Reference
#include <stdint.h>

Go to the source code of this file.

Macros

#define __DEFAULT_FN_ATTRS   __attribute__((__always_inline__, __nodebug__))
#define __packed_splat2(ty, x)
#define __packed_splat4(ty, x)
#define __packed_splat8(ty, x)
#define __packed_splat(name, ty, scalar_ty, splat)
#define __packed_scalar_binary_op(name, ty, scalar_ty, op, splat)
#define __packed_binary_op(name, ty, op)
#define __packed_unary_op(name, ty, op)
#define __packed_extract(name, rty, ty, max_idx)
#define __packed_subvector_extract8(name, rty, ty)
#define __packed_subvector_extract4(name, rty, ty)
#define __packed_store(name, ty, elt_ty)
#define __packed_binary_builtin(name, ty, builtin)
#define __packed_binary_builtin_mixed(name, rty, ty1, ty2, builtin)
#define __packed_ternary_builtin(name, ty, builtin)
#define __packed_ternary_builtin_mixed(name, rty, ty1, ty2, builtin)
#define __packed_sh1add(name, ty)
#define __packed_sh1sadd(name, ty)
#define __packed_cmp(name, ty, rty, op)
#define __packed_pabs(name, ty, rty)
#define __packed_binary_builtin_cast(name, ty, rty, builtin)
#define __packed_reduction(name, rty, ty, builtin)
#define __packed_merge_builtin(name, ty, mask_ty, builtin)
#define __packed_unary_builtin(name, ty, builtin)
#define __packed_cls(name, ty, builtin)
#define __packed_slx(name, ty)
#define __packed_srx(name, ty)
#define __packed_slideupx(name, ty, bits_ty, log2_elt_bits)
#define __packed_slidedownx(name, ty, bits_ty, log2_elt_bits)
#define __packed_widen_convert(name, rty, ty)
#define __packed_widen_binary_op(name, rty, ty, op)
#define __packed_widen_binary_acc_op(name, rty, ty, op)
#define __packed_widen_sub_acc_op(name, rty, ty)
#define __packed_widen_mul(name, rty, ty)
#define __packed_widen_mulsu(name, rty, ty1, ty2, uty)
#define __packed_widen_high2(name, rty, ty)
#define __packed_widen_high4(name, rty, ty)
#define __packed_narrow_even2(name, rty, ty, sty)
#define __packed_narrow_even4(name, rty, ty, sty)
#define __packed_narrow_odd2(name, rty, ty, sty, uty)
#define __packed_narrow_odd4(name, rty, ty, sty, uty)
#define __packed_reverse2(name, ty)
#define __packed_reverse4(name, ty)
#define __packed_reverse8(name, ty)
#define __packed_zip2(name, rty, ty)
#define __packed_zip4(name, rty, ty)
#define __packed_unzipe2(name, rty, ty)
#define __packed_unzipe4(name, rty, ty)
#define __packed_unzipo2(name, rty, ty)
#define __packed_unzipo4(name, rty, ty)
#define __packed_concat2(name, rty, ty)
#define __packed_concat4(name, rty, ty)
#define __packed_slide1(name, ty, elt_ty, ...)
#define __packed_pair_ee2(name, ty)
#define __packed_pair_eo2(name, ty)
#define __packed_pair_oe2(name, ty)
#define __packed_pair_oo2(name, ty)
#define __packed_pair_ee4(name, ty)
#define __packed_pair_eo4(name, ty)
#define __packed_pair_oe4(name, ty)
#define __packed_pair_oo4(name, ty)
#define __packed_pair_ee8(name, ty)
#define __packed_pair_eo8(name, ty)
#define __packed_pair_oe8(name, ty)
#define __packed_pair_oo8(name, ty)
#define __packed_nzip2(name, rty, ty)
#define __packed_nzip4(name, rty, ty)
#define __packed_nziph2(name, rty, ty)
#define __packed_nziph4(name, rty, ty)
#define __packed_wunzip_ext(name, rty, ty, ext)
#define __packed_wunzip_shift(name, rty, ty, op, shamt)
#define __packed_wunzip_odd_hi(name, rty, ty, zip)
#define __packed_abdsum(name, rty, ty, builtin)
#define __packed_ternary_builtin_cast(name, rty, ty, builtin)
#define __packed_reinterpret(name, rty, ty)
#define __packed_insert(name, ty, elt_ty, max_idx)
#define __packed_join2(name, ty, elt_ty)
#define __packed_join4(name, ty, elt_ty)
#define __packed_load(name, ty, elt_ty)
#define __riscv_sati_i32(rs1, width)
#define __riscv_usati_u32(rs1, width)
#define __packed_mulh_builtin(name, res_ty, ty1, ty2)
#define __riscv_pusati_u16x2(rs1, width)
#define __riscv_psati_i16x2(rs1, width)
#define __riscv_pusati_u16x4(rs1, width)
#define __riscv_pusati_u32x2(rs1, width)
#define __riscv_psati_i16x4(rs1, width)
#define __riscv_psati_i32x2(rs1, width)

Typedefs

typedef int8_t int8x4_t __attribute__((__vector_size__(4)))

Functions

 __packed_cls (cls_32, int32_t, __builtin_clrsb) __packed_unary_builtin(rev_32
__builtin_bitreverse32 __packed_slx (slx_32, uint32_t) __packed_srx(srx_32
__builtin_bitreverse32 uint32_t __packed_binary_builtin (aadd_i32, int32_t, __builtin_riscv_aadd_i32) __packed_binary_builtin(aaddu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __packed_binary_builtin (asub_i32, int32_t, __builtin_riscv_asub_i32) __packed_binary_builtin(asubu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __packed_binary_builtin (sadd_i32, int32_t, __builtin_elementwise_add_sat) __packed_binary_builtin(saddu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __packed_binary_builtin (ssub_i32, int32_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(ssubu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_pabs (abs_u32, int32_t, uint32_t) __packed_mulh_builtin(mulh_i32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t __packed_mulh_builtin (mulhr_i32, int32_t, int32_t, int32_t) __packed_mulh_builtin(mulhu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t __packed_mulh_builtin (mulhru_u32, uint32_t, uint32_t, uint32_t) __packed_mulh_builtin(mulhsu_i32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __packed_mulh_builtin (mulhrsu_i32, int32_t, int32_t, uint32_t) __packed_ternary_builtin(mhacc_i32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __packed_ternary_builtin (mhracc_i32, int32_t, __builtin_riscv_mhracc_i32) __packed_ternary_builtin(mhaccu_u32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __packed_ternary_builtin (mhraccu_u32, uint32_t, __builtin_riscv_mhraccu_u32) __packed_ternary_builtin_mixed(mhaccsu_i32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __packed_ternary_builtin_mixed (mhraccsu_i32, int32_t, int32_t, uint32_t, __builtin_riscv_mhraccsu_i32) __packed_binary_builtin(mulq_i32
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __packed_binary_builtin (mulqr_i32, int32_t, __builtin_riscv_mulqr_i32) __packed_ternary_builtin_mixed(mqwacc_i64
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_ternary_builtin_mixed (mqrwacc_i64, int64_t, int32_t, int32_t, __builtin_riscv_mqrwacc_i64) __packed_splat(pmv_s_u8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat (pmv_s_i8x4, int8x4_t, int8_t, __packed_splat4) __packed_splat(pmv_s_u16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat (pmv_s_i16x2, int16x2_t, int16_t, __packed_splat2) __packed_splat(pmv_s_u8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat (pmv_s_i8x8, int8x8_t, int8_t, __packed_splat8) __packed_splat(pmv_s_u16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat (pmv_s_i16x4, int16x4_t, int16_t, __packed_splat4) __packed_splat(pmv_s_u32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat (pmv_s_i32x2, int32x2_t, int32_t, __packed_splat2) __packed_binary_op(padd_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (padd_u8x4, uint8x4_t,+) __packed_binary_op(padd_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (padd_u16x2, uint16x2_t,+) __packed_binary_op(psub_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (psub_u8x4, uint8x4_t, -) __packed_binary_op(psub_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (psub_u16x2, uint16x2_t, -) __packed_unary_op(pneg_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_unary_op (pneg_i16x2, int16x2_t, -) __packed_binary_op(padd_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (padd_u8x8, uint8x8_t,+) __packed_binary_op(padd_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (padd_u16x4, uint16x4_t,+) __packed_binary_op(padd_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (padd_u32x2, uint32x2_t,+) __packed_binary_op(psub_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (psub_u8x8, uint8x8_t, -) __packed_binary_op(psub_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (psub_u16x4, uint16x4_t, -) __packed_binary_op(psub_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op (psub_u32x2, uint32x2_t, -) __packed_unary_op(pneg_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_unary_op (pneg_i16x4, int16x4_t, -) __packed_unary_op(pneg_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_scalar_binary_op (padd_s_u8x4, uint8x4_t, uint8_t,+, __packed_splat4) __packed_scalar_binary_op(padd_s_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_scalar_binary_op (padd_s_u16x2, uint16x2_t, uint16_t,+, __packed_splat2) __packed_scalar_binary_op(padd_s_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_scalar_binary_op (padd_s_u8x8, uint8x8_t, uint8_t,+, __packed_splat8) __packed_scalar_binary_op(padd_s_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_scalar_binary_op (padd_s_u16x4, uint16x4_t, uint16_t,+, __packed_splat4) __packed_scalar_binary_op(padd_s_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_scalar_binary_op (padd_s_u32x2, uint32x2_t, uint32_t,+, __packed_splat2) __packed_scalar_binary_op(padd_s_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_builtin (psadd_i8x4, int8x4_t, __builtin_elementwise_add_sat) __packed_binary_builtin(psadd_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __packed_binary_builtin (psaddu_u8x4, uint8x4_t, __builtin_elementwise_add_sat) __packed_binary_builtin(psaddu_u16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin (pssub_i8x4, int8x4_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(pssub_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_binary_builtin (pssubu_u8x4, uint8x4_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(pssubu_u16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_binary_builtin (psadd_i8x8, int8x8_t, __builtin_elementwise_add_sat) __packed_binary_builtin(psadd_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __packed_binary_builtin (psadd_i32x2, int32x2_t, __builtin_elementwise_add_sat) __packed_binary_builtin(psaddu_u8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin (psaddu_u16x4, uint16x4_t, __builtin_elementwise_add_sat) __packed_binary_builtin(psaddu_u32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin (pssub_i8x8, int8x8_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(pssub_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_binary_builtin (pssub_i32x2, int32x2_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(pssubu_u8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_binary_builtin (pssubu_u16x4, uint16x4_t, __builtin_elementwise_sub_sat) __packed_binary_builtin(pssubu_u32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_sh1add (psh1add_i16x2, int16x2_t) __packed_sh1add(psh1add_u16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t __packed_sh1sadd (pssh1sadd_i16x2, int16x2_t) __packed_sh1add(psh1add_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t __packed_sh1add (psh1add_u16x4, uint16x4_t) __packed_sh1add(psh1add_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t __packed_sh1add (psh1add_u32x2, uint32x2_t) __packed_sh1sadd(pssh1sadd_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __packed_sh1sadd (pssh1sadd_i32x2, int32x2_t) __packed_binary_builtin(pas_x_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __packed_binary_builtin (psa_x_i16x2, int16x2_t, __builtin_riscv_psa_x_i16x2) __packed_binary_builtin(psas_x_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __packed_binary_builtin (pssa_x_i16x2, int16x2_t, __builtin_riscv_pssa_x_i16x2) __packed_binary_builtin(paas_x_i16x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __packed_binary_builtin (pasa_x_i16x2, int16x2_t, __builtin_riscv_pasa_x_i16x2) __packed_binary_builtin(pas_x_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __packed_binary_builtin (psa_x_i16x4, int16x4_t, __builtin_riscv_psa_x_i16x4) __packed_binary_builtin(psas_x_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __packed_binary_builtin (pssa_x_i16x4, int16x4_t, __builtin_riscv_pssa_x_i16x4) __packed_binary_builtin(paas_x_i16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __packed_binary_builtin (pasa_x_i16x4, int16x4_t, __builtin_riscv_pasa_x_i16x4) __packed_binary_builtin(pas_x_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __packed_binary_builtin (psa_x_i32x2, int32x2_t, __builtin_riscv_psa_x_i32x2) __packed_binary_builtin(psas_x_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __packed_binary_builtin (pssa_x_i32x2, int32x2_t, __builtin_riscv_pssa_x_i32x2) __packed_binary_builtin(paas_x_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __packed_binary_builtin (pasa_x_i32x2, int32x2_t, __builtin_riscv_pasa_x_i32x2) __packed_binary_builtin(pmin_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __packed_binary_builtin (pmin_i16x2, int16x2_t, __builtin_elementwise_min) __packed_binary_builtin(pminu_u8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin (pminu_u16x2, uint16x2_t, __builtin_elementwise_min) __packed_binary_builtin(pmax_i8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __packed_binary_builtin (pmax_i16x2, int16x2_t, __builtin_elementwise_max) __packed_binary_builtin(pmaxu_u8x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin (pmaxu_u16x2, uint16x2_t, __builtin_elementwise_max) __packed_binary_builtin(pmin_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __packed_binary_builtin (pmin_i16x4, int16x4_t, __builtin_elementwise_min) __packed_binary_builtin(pmin_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin (pminu_u8x8, uint8x8_t, __builtin_elementwise_min) __packed_binary_builtin(pminu_u16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin (pminu_u32x2, uint32x2_t, __builtin_elementwise_min) __packed_binary_builtin(pmax_i8x8
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __packed_binary_builtin (pmax_i16x4, int16x4_t, __builtin_elementwise_max) __packed_binary_builtin(pmax_i32x2
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin (pmaxu_u8x8, uint8x8_t, __builtin_elementwise_max) __packed_binary_builtin(pmaxu_u16x4
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin (pmaxu_u32x2, uint32x2_t, __builtin_elementwise_max) __packed_cmp(pmseq_i8x4_u8x4

Variables

 uint32_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 int64_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 uint8x4_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 uint8_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 uint16x2_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 uint16_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 uint8x8_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 uint16x4_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 uint32x2_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int8x4_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int16x2_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int8x8_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int16x4_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int32x2_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 int8_t
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 int16_t

Macro Definition Documentation

◆ __DEFAULT_FN_ATTRS

#define __DEFAULT_FN_ATTRS   __attribute__((__always_inline__, __nodebug__))

Definition at line 33 of file riscv_packed_simd.h.

◆ __packed_abdsum

#define __packed_abdsum ( name,
rty,
ty,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return builtin(__rs1, __rs2); \
}
#define __DEFAULT_FN_ATTRS

Definition at line 405 of file riscv_packed_simd.h.

◆ __packed_binary_builtin

◆ __packed_binary_builtin_cast

#define __packed_binary_builtin_cast ( name,
ty,
rty,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return (rty)builtin(__rs1, __rs2); \
}

Definition at line 142 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_binary_builtin_mixed

#define __packed_binary_builtin_mixed ( name,
rty,
ty1,
ty2,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty1 __rs1, \
ty2 __rs2) { \
return builtin(__rs1, __rs2); \
}

Definition at line 98 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_binary_op

#define __packed_binary_op ( name,
ty,
op )

◆ __packed_cls

#define __packed_cls ( name,
ty,
builtin )
Value:
static __inline__ unsigned __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return builtin(__rs1); \
}

Definition at line 165 of file riscv_packed_simd.h.

◆ __packed_cmp

#define __packed_cmp ( name,
ty,
rty,
op )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return (rty)(__rs1 op __rs2); \
}

Definition at line 131 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_concat2

#define __packed_concat2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __lo, ty __hi) { \
return __builtin_shufflevector(__lo, __hi, 0, 1, 2, 3); \
}

Definition at line 303 of file riscv_packed_simd.h.

◆ __packed_concat4

#define __packed_concat4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __lo, ty __hi) { \
return __builtin_shufflevector(__lo, __hi, 0, 1, 2, 3, 4, 5, 6, 7); \
}

Definition at line 307 of file riscv_packed_simd.h.

◆ __packed_extract

#define __packed_extract ( name,
rty,
ty,
max_idx )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __v, \
unsigned __idx) \
__attribute__((__enable_if__( \
__idx <= (max_idx), \
"index must be a constant integer from 0 to " #max_idx))) { \
return __v[__idx]; \
}
return __v
Definition arm_acle.h:88

Definition at line 60 of file riscv_packed_simd.h.

◆ __packed_insert

#define __packed_insert ( name,
ty,
elt_ty,
max_idx )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __v, elt_ty __e, \
unsigned __idx) \
__attribute__((__enable_if__( \
__idx <= (max_idx), \
"index must be a constant integer from 0 to " #max_idx))) { \
__v[__idx] = __e; \
return __v; \
}

Definition at line 423 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_join2

#define __packed_join2 ( name,
ty,
elt_ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(elt_ty __e0, \
elt_ty __e1) { \
return (ty){__e0, __e1}; \
}

Definition at line 433 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_join4

#define __packed_join4 ( name,
ty,
elt_ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name( \
elt_ty __e0, elt_ty __e1, elt_ty __e2, elt_ty __e3) { \
return (ty){__e0, __e1, __e2, __e3}; \
}

Definition at line 439 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_load

#define __packed_load ( name,
ty,
elt_ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(elt_ty *__p) { \
typedef ty __attribute__((__aligned__(1))) ua_ty; \
return *(ua_ty *)__p; \
}
_Float16 __2f16 __attribute__((ext_vector_type(2)))
Zeroes the upper 128 bits (bits 255:128) of all YMM registers.
static __inline__ uint32_t volatile uint32_t * __p
Definition arm_acle.h:57
return(__x > > __y)|(__x<<(32 - __y))

Definition at line 445 of file riscv_packed_simd.h.

◆ __packed_merge_builtin

#define __packed_merge_builtin ( name,
ty,
mask_ty,
builtin )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2, \
mask_ty __rd) { \
return (ty)builtin(__rs1, __rs2, __rd); \
}

Definition at line 154 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_mulh_builtin

#define __packed_mulh_builtin ( name,
res_ty,
ty1,
ty2 )
Value:
static __inline__ res_ty __DEFAULT_FN_ATTRS __riscv_##name(ty1 __rs1, \
ty2 __rs2) { \
return __builtin_riscv_##name(__rs1, __rs2); \
}

Referenced by __packed_mulh_builtin(), __packed_mulh_builtin(), and __packed_mulh_builtin().

◆ __packed_narrow_even2

#define __packed_narrow_even2 ( name,
rty,
ty,
sty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_convertvector(__rs1, rty); \
}

Definition at line 244 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_narrow_even4

#define __packed_narrow_even4 ( name,
rty,
ty,
sty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_convertvector(__rs1, rty); \
}

Definition at line 248 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_narrow_odd2

#define __packed_narrow_odd2 ( name,
rty,
ty,
sty,
uty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector((sty)__rs1, (sty)__rs1, 1, 3); \
}

Definition at line 252 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_narrow_odd4

#define __packed_narrow_odd4 ( name,
rty,
ty,
sty,
uty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector((sty)__rs1, (sty)__rs1, 1, 3, 5, 7); \
}

Definition at line 256 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_nzip2

#define __packed_nzip2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 4, 2, 6); \
}

Definition at line 367 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_nzip4

#define __packed_nzip4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 8, 2, 10, 4, 12, \
6, 14); \
}

Definition at line 372 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_nziph2

#define __packed_nziph2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 5, 3, 7); \
}

Definition at line 378 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_nziph4

#define __packed_nziph4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 9, 3, 11, 5, 13, \
7, 15); \
}

Definition at line 383 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pabs

#define __packed_pabs ( name,
ty,
rty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return (rty)__builtin_elementwise_abs(__rs1); \
}

Definition at line 137 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin(), and __packed_pabs().

◆ __packed_pair_ee2

#define __packed_pair_ee2 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 2); \
}

Definition at line 318 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_ee4

#define __packed_pair_ee4 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 4, 2, 6); \
}

Definition at line 334 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_ee8

#define __packed_pair_ee8 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 8, 2, 10, 4, 12, 6, 14); \
}

Definition at line 350 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_eo2

#define __packed_pair_eo2 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 3); \
}

Definition at line 322 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_eo4

#define __packed_pair_eo4 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 5, 2, 7); \
}

Definition at line 338 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_eo8

#define __packed_pair_eo8 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 9, 2, 11, 4, 13, 6, 15); \
}

Definition at line 354 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oe2

#define __packed_pair_oe2 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 2); \
}

Definition at line 326 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oe4

#define __packed_pair_oe4 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 4, 3, 6); \
}

Definition at line 342 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oe8

#define __packed_pair_oe8 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 8, 3, 10, 5, 12, 7, 14); \
}

Definition at line 358 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oo2

#define __packed_pair_oo2 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 3); \
}

Definition at line 330 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oo4

#define __packed_pair_oo4 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 5, 3, 7); \
}

Definition at line 346 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_pair_oo8

#define __packed_pair_oo8 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 1, 9, 3, 11, 5, 13, 7, 15); \
}

Definition at line 362 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_reduction

#define __packed_reduction ( name,
rty,
ty,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
rty __rs2) { \
return builtin(__rs1, __rs2); \
}

Definition at line 148 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_reinterpret

#define __packed_reinterpret ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_preinterpret_##name( \
ty __x) { \
return __builtin_bit_cast(rty, __x); \
}

Definition at line 417 of file riscv_packed_simd.h.

◆ __packed_reverse2

#define __packed_reverse2 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 1, 0); \
}

Definition at line 263 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_reverse4

#define __packed_reverse4 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 3, 2, 1, 0); \
}

Definition at line 267 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_reverse8

#define __packed_reverse8 ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 7, 6, 5, 4, 3, 2, 1, 0); \
}

Definition at line 271 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_scalar_binary_op

#define __packed_scalar_binary_op ( name,
ty,
scalar_ty,
op,
splat )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
scalar_ty __rs2) { \
return __rs1 op splat(ty, __rs2); \
}

Definition at line 44 of file riscv_packed_simd.h.

Referenced by __packed_scalar_binary_op(), __packed_scalar_binary_op(), __packed_scalar_binary_op(), __packed_scalar_binary_op(), and __packed_scalar_binary_op().

◆ __packed_sh1add

#define __packed_sh1add ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return (__rs1 << 1) + __rs2; \
}

Definition at line 116 of file riscv_packed_simd.h.

Referenced by __packed_sh1add(), __packed_sh1add(), __packed_sh1add(), and __packed_sh1sadd().

◆ __packed_sh1sadd

#define __packed_sh1sadd ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
return __builtin_elementwise_add_sat( \
__builtin_elementwise_add_sat(__rs1, __rs1), __rs2); \
}

Definition at line 125 of file riscv_packed_simd.h.

Referenced by __packed_sh1add(), __packed_sh1sadd(), and __packed_sh1sadd().

◆ __packed_slide1

#define __packed_slide1 ( name,
ty,
elt_ty,
... )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, \
elt_ty __rs1) { \
return __builtin_shufflevector(__rd, (ty){__rs1}, __VA_ARGS__); \
}

Definition at line 312 of file riscv_packed_simd.h.

◆ __packed_slidedownx

#define __packed_slidedownx ( name,
ty,
bits_ty,
log2_elt_bits )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
unsigned __rs2) { \
bits_ty __bits = __builtin_elementwise_fshr( \
__builtin_bit_cast(bits_ty, __rs1), __builtin_bit_cast(bits_ty, __rd), \
(bits_ty)__rs2 << (log2_elt_bits)); \
return __builtin_bit_cast(ty, __bits); \
}

Definition at line 191 of file riscv_packed_simd.h.

◆ __packed_slideupx

#define __packed_slideupx ( name,
ty,
bits_ty,
log2_elt_bits )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
unsigned __rs2) { \
bits_ty __bits = __builtin_elementwise_fshl( \
__builtin_bit_cast(bits_ty, __rd), __builtin_bit_cast(bits_ty, __rs1), \
(bits_ty)__rs2 << (log2_elt_bits)); \
return __builtin_bit_cast(ty, __bits); \
}

Definition at line 182 of file riscv_packed_simd.h.

◆ __packed_slx

#define __packed_slx ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
unsigned __shamt) { \
return __builtin_elementwise_fshl(__rd, __rs1, (ty)__shamt); \
}

Definition at line 170 of file riscv_packed_simd.h.

Referenced by __packed_slx().

◆ __packed_splat

#define __packed_splat ( name,
ty,
scalar_ty,
splat )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(scalar_ty __x) { \
return splat(ty, __x); \
}

Definition at line 39 of file riscv_packed_simd.h.

Referenced by __packed_splat(), __packed_splat(), __packed_splat(), __packed_splat(), and __packed_splat().

◆ __packed_splat2

#define __packed_splat2 ( ty,
x )
Value:
((ty){(x), (x)})

Definition at line 35 of file riscv_packed_simd.h.

Referenced by __packed_scalar_binary_op(), __packed_scalar_binary_op(), __packed_splat(), and __packed_splat().

◆ __packed_splat4

#define __packed_splat4 ( ty,
x )
Value:
((ty){(x), (x), (x), (x)})

Definition at line 36 of file riscv_packed_simd.h.

Referenced by __packed_scalar_binary_op(), __packed_scalar_binary_op(), __packed_splat(), and __packed_splat().

◆ __packed_splat8

#define __packed_splat8 ( ty,
x )
Value:
((ty){(x), (x), (x), (x), (x), (x), (x), (x)})

Definition at line 37 of file riscv_packed_simd.h.

Referenced by __packed_scalar_binary_op(), and __packed_splat().

◆ __packed_srx

#define __packed_srx ( name,
ty )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
unsigned __shamt) { \
return __builtin_elementwise_fshr(__rs1, __rd, (ty)__shamt); \
}

Definition at line 176 of file riscv_packed_simd.h.

Referenced by __packed_slx().

◆ __packed_store

#define __packed_store ( name,
ty,
elt_ty )
Value:
static __inline__ void __DEFAULT_FN_ATTRS __riscv_##name(elt_ty *__p, \
ty __v) { \
typedef ty __attribute__((__aligned__(1))) ua_ty; \
*(ua_ty *)__p = __v; \
}

Definition at line 86 of file riscv_packed_simd.h.

◆ __packed_subvector_extract4

#define __packed_subvector_extract4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __v, \
unsigned __idx) \
__attribute__((__enable_if__( \
__idx <= 1, "index must be a constant integer from 0 to 1"))) { \
return __idx ? __builtin_shufflevector(__v, __v, 2, 3) \
: __builtin_shufflevector(__v, __v, 0, 1); \
}

Definition at line 77 of file riscv_packed_simd.h.

◆ __packed_subvector_extract8

#define __packed_subvector_extract8 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __v, \
unsigned __idx) \
__attribute__((__enable_if__( \
__idx <= 1, "index must be a constant integer from 0 to 1"))) { \
return __idx ? __builtin_shufflevector(__v, __v, 4, 5, 6, 7) \
: __builtin_shufflevector(__v, __v, 0, 1, 2, 3); \
}

Definition at line 69 of file riscv_packed_simd.h.

◆ __packed_ternary_builtin

#define __packed_ternary_builtin ( name,
ty,
builtin )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \
ty __rs2) { \
return builtin(__rd, __rs1, __rs2); \
}

Definition at line 104 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin(), __packed_ternary_builtin(), and __packed_ternary_builtin().

◆ __packed_ternary_builtin_cast

#define __packed_ternary_builtin_cast ( name,
rty,
ty,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty __rs1, \
ty __rs2) { \
return builtin(__rd, __rs1, __rs2); \
}

Definition at line 411 of file riscv_packed_simd.h.

◆ __packed_ternary_builtin_mixed

#define __packed_ternary_builtin_mixed ( name,
rty,
ty1,
ty2,
builtin )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty1 __rs1, \
ty2 __rs2) { \
return builtin(__rd, __rs1, __rs2); \
}

Definition at line 110 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin(), __packed_ternary_builtin(), __packed_ternary_builtin_mixed(), and __packed_ternary_builtin_mixed().

◆ __packed_unary_builtin

#define __packed_unary_builtin ( name,
ty,
builtin )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return builtin(__rs1); \
}

Definition at line 160 of file riscv_packed_simd.h.

◆ __packed_unary_op

#define __packed_unary_op ( name,
ty,
op )
Value:
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return op __rs1; \
}

Definition at line 55 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin(), __packed_binary_op(), __packed_binary_op(), __packed_unary_op(), and __packed_unary_op().

◆ __packed_unzipe2

#define __packed_unzipe2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 0, 2); \
}

Definition at line 286 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_unzipe4

#define __packed_unzipe4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 0, 2, 4, 6); \
}

Definition at line 290 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_unzipo2

#define __packed_unzipo2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 1, 3); \
}

Definition at line 294 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_unzipo4

#define __packed_unzipo4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_shufflevector(__rs1, __rs1, 1, 3, 5, 7); \
}

Definition at line 298 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_binary_acc_op

#define __packed_widen_binary_acc_op ( name,
rty,
ty,
op )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty __rs1, \
ty __rs2) { \
return __rd op __builtin_convertvector(__rs1, rty) \
op __builtin_convertvector(__rs2, rty); \
}

Definition at line 210 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_binary_op

#define __packed_widen_binary_op ( name,
rty,
ty,
op )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_convertvector(__rs1, rty) \
op __builtin_convertvector(__rs2, rty); \
}

Definition at line 204 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_convert

#define __packed_widen_convert ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return __builtin_convertvector(__rs1, rty); \
}

Definition at line 200 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_high2

#define __packed_widen_high2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return (rty)__builtin_shufflevector((ty){0}, __rs1, 0, 2, 1, 3); \
}

Definition at line 234 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_high4

#define __packed_widen_high4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return (rty)__builtin_shufflevector((ty){0}, __rs1, 0, 4, 1, 5, 2, 6, 3, \
7); \
}

Definition at line 238 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_mul

#define __packed_widen_mul ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_convertvector(__rs1, rty) * \
__builtin_convertvector(__rs2, rty); \
}

Definition at line 222 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_mulsu

#define __packed_widen_mulsu ( name,
rty,
ty1,
ty2,
uty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty1 __rs1, \
ty2 __rs2) { \
return __builtin_convertvector(__rs1, rty) * \
(rty) __builtin_convertvector(__rs2, uty); \
}

Definition at line 228 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_widen_sub_acc_op

#define __packed_widen_sub_acc_op ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty __rs1, \
ty __rs2) { \
return __rd + __builtin_convertvector(__rs1, rty) - \
__builtin_convertvector(__rs2, rty); \
}

Definition at line 216 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_wunzip_ext

#define __packed_wunzip_ext ( name,
rty,
ty,
ext )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return ext(__rs1); \
}

Definition at line 390 of file riscv_packed_simd.h.

◆ __packed_wunzip_odd_hi

#define __packed_wunzip_odd_hi ( name,
rty,
ty,
zip )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return (rty)zip((rty){0}, (rty)__rs1); \
}

Definition at line 400 of file riscv_packed_simd.h.

◆ __packed_wunzip_shift

#define __packed_wunzip_shift ( name,
rty,
ty,
op,
shamt )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
return (rty)__rs1 op shamt; \
}

Definition at line 395 of file riscv_packed_simd.h.

◆ __packed_zip2

#define __packed_zip2 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 2, 1, 3); \
}

Definition at line 276 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __packed_zip4

#define __packed_zip4 ( name,
rty,
ty )
Value:
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
return __builtin_shufflevector(__rs1, __rs2, 0, 4, 1, 5, 2, 6, 3, 7); \
}

Definition at line 281 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin().

◆ __riscv_psati_i16x2

#define __riscv_psati_i16x2 ( rs1,
width )
Value:
__builtin_riscv_psati_i16x2(rs1, width)

◆ __riscv_psati_i16x4

#define __riscv_psati_i16x4 ( rs1,
width )
Value:
__builtin_riscv_psati_i16x4(rs1, width)

◆ __riscv_psati_i32x2

#define __riscv_psati_i32x2 ( rs1,
width )
Value:
__builtin_riscv_psati_i32x2(rs1, width)

◆ __riscv_pusati_u16x2

#define __riscv_pusati_u16x2 ( rs1,
width )
Value:
__builtin_riscv_pusati_u16x2(rs1, width)

◆ __riscv_pusati_u16x4

#define __riscv_pusati_u16x4 ( rs1,
width )
Value:
__builtin_riscv_pusati_u16x4(rs1, width)

◆ __riscv_pusati_u32x2

#define __riscv_pusati_u32x2 ( rs1,
width )
Value:
__builtin_riscv_pusati_u32x2(rs1, width)

◆ __riscv_sati_i32

#define __riscv_sati_i32 ( rs1,
width )
Value:
__builtin_riscv_sati_i32(rs1, width)

◆ __riscv_usati_u32

#define __riscv_usati_u32 ( rs1,
width )
Value:
__builtin_riscv_usati_u32(rs1, width)

Typedef Documentation

◆ __attribute__

typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)))

Definition at line 21 of file riscv_packed_simd.h.

Function Documentation

◆ __packed_binary_builtin() [1/34]

__builtin_bitreverse32 uint32_t __packed_binary_builtin ( aadd_i32 ,
int32_t ,
__builtin_riscv_aadd_i32  )

References int32_t, and uint32_t.

◆ __packed_binary_builtin() [2/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __packed_binary_builtin ( asub_i32 ,
int32_t ,
__builtin_riscv_asub_i32  )

◆ __packed_binary_builtin() [3/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __packed_binary_builtin ( mulqr_i32 ,
int32_t ,
__builtin_riscv_mulqr_i32  )

References __packed_binary_builtin, and int32_t.

◆ __packed_binary_builtin() [4/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __packed_binary_builtin ( pasa_x_i16x2 ,
int16x2_t ,
__builtin_riscv_pasa_x_i16x2  )

◆ __packed_binary_builtin() [5/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __packed_binary_builtin ( pasa_x_i16x4 ,
int16x4_t ,
__builtin_riscv_pasa_x_i16x4  )

◆ __packed_binary_builtin() [6/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __packed_binary_builtin ( pasa_x_i32x2 ,
int32x2_t ,
__builtin_riscv_pasa_x_i32x2  )

◆ __packed_binary_builtin() [7/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __packed_binary_builtin ( pmax_i16x2 ,
int16x2_t ,
__builtin_elementwise_max  )

◆ __packed_binary_builtin() [8/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __packed_binary_builtin ( pmax_i16x4 ,
int16x4_t ,
__builtin_elementwise_max  )

◆ __packed_binary_builtin() [9/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin ( pmaxu_u16x2 ,
uint16x2_t ,
__builtin_elementwise_max  )

◆ __packed_binary_builtin() [10/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin ( pmaxu_u32x2 ,
uint32x2_t ,
__builtin_elementwise_max  )

◆ __packed_binary_builtin() [11/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __packed_binary_builtin ( pmaxu_u8x8 ,
uint8x8_t ,
__builtin_elementwise_max  )

◆ __packed_binary_builtin() [12/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __packed_binary_builtin ( pmin_i16x2 ,
int16x2_t ,
__builtin_elementwise_min  )

◆ __packed_binary_builtin() [13/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __packed_binary_builtin ( pmin_i16x4 ,
int16x4_t ,
__builtin_elementwise_min  )

◆ __packed_binary_builtin() [14/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin ( pminu_u16x2 ,
uint16x2_t ,
__builtin_elementwise_min  )

◆ __packed_binary_builtin() [15/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin ( pminu_u32x2 ,
uint32x2_t ,
__builtin_elementwise_min  )

◆ __packed_binary_builtin() [16/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __packed_binary_builtin ( pminu_u8x8 ,
uint8x8_t ,
__builtin_elementwise_min  )

◆ __packed_binary_builtin() [17/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __packed_binary_builtin ( psa_x_i16x2 ,
int16x2_t ,
__builtin_riscv_psa_x_i16x2  )

◆ __packed_binary_builtin() [18/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __packed_binary_builtin ( psa_x_i16x4 ,
int16x4_t ,
__builtin_riscv_psa_x_i16x4  )

◆ __packed_binary_builtin() [19/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __packed_binary_builtin ( psa_x_i32x2 ,
int32x2_t ,
__builtin_riscv_psa_x_i32x2  )

◆ __packed_binary_builtin() [20/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __packed_binary_builtin ( psadd_i32x2 ,
int32x2_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [21/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_builtin ( psadd_i8x4 ,
int8x4_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [22/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_binary_builtin ( psadd_i8x8 ,
int8x8_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [23/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin ( psaddu_u16x4 ,
uint16x4_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [24/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __packed_binary_builtin ( psaddu_u8x4 ,
uint8x4_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [25/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __packed_binary_builtin ( pssa_x_i16x2 ,
int16x2_t ,
__builtin_riscv_pssa_x_i16x2  )

◆ __packed_binary_builtin() [26/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __packed_binary_builtin ( pssa_x_i16x4 ,
int16x4_t ,
__builtin_riscv_pssa_x_i16x4  )

◆ __packed_binary_builtin() [27/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __packed_binary_builtin ( pssa_x_i32x2 ,
int32x2_t ,
__builtin_riscv_pssa_x_i32x2  )

◆ __packed_binary_builtin() [28/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_binary_builtin ( pssub_i32x2 ,
int32x2_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_builtin() [29/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin ( pssub_i8x4 ,
int8x4_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_builtin() [30/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __packed_binary_builtin ( pssub_i8x8 ,
int8x8_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_builtin() [31/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_binary_builtin ( pssubu_u16x4 ,
uint16x4_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_builtin() [32/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_binary_builtin ( pssubu_u8x4 ,
uint8x4_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_builtin() [33/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __packed_binary_builtin ( sadd_i32 ,
int32_t ,
__builtin_elementwise_add_sat  )

◆ __packed_binary_builtin() [34/34]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __packed_binary_builtin ( ssub_i32 ,
int32_t ,
__builtin_elementwise_sub_sat  )

◆ __packed_binary_op() [1/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( padd_u16x2 ,
uint16x2_t ,
+  )

◆ __packed_binary_op() [2/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( padd_u16x4 ,
uint16x4_t ,
+  )

References __packed_binary_op, and uint16x4_t.

◆ __packed_binary_op() [3/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( padd_u32x2 ,
uint32x2_t ,
+  )

◆ __packed_binary_op() [4/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( padd_u8x4 ,
uint8x4_t ,
+  )

References __packed_binary_op, and uint8x4_t.

◆ __packed_binary_op() [5/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( padd_u8x8 ,
uint8x8_t ,
+  )

References __packed_binary_op, and uint8x8_t.

◆ __packed_binary_op() [6/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( psub_u16x2 ,
uint16x2_t ,
-  )

◆ __packed_binary_op() [7/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( psub_u16x4 ,
uint16x4_t ,
-  )

◆ __packed_binary_op() [8/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( psub_u32x2 ,
uint32x2_t ,
-  )

◆ __packed_binary_op() [9/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( psub_u8x4 ,
uint8x4_t ,
-  )

◆ __packed_binary_op() [10/10]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_binary_op ( psub_u8x8 ,
uint8x8_t ,
-  )

◆ __packed_cls()

__packed_cls ( cls_32 ,
int32_t ,
__builtin_clrsb  )

References int32_t.

◆ __packed_mulh_builtin() [1/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t __packed_mulh_builtin ( mulhr_i32 ,
int32_t ,
int32_t ,
int32_t  )

◆ __packed_mulh_builtin() [2/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __packed_mulh_builtin ( mulhrsu_i32 ,
int32_t ,
int32_t ,
uint32_t  )

◆ __packed_mulh_builtin() [3/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t __packed_mulh_builtin ( mulhru_u32 ,
uint32_t ,
uint32_t ,
uint32_t  )

◆ __packed_pabs()

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __packed_pabs ( abs_u32 ,
int32_t ,
uint32_t  )

References __packed_pabs, int32_t, int64_t, and uint32_t.

◆ __packed_scalar_binary_op() [1/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_scalar_binary_op ( padd_s_u16x2 ,
uint16x2_t ,
uint16_t ,
+ ,
__packed_splat2  )

◆ __packed_scalar_binary_op() [2/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_scalar_binary_op ( padd_s_u16x4 ,
uint16x4_t ,
uint16_t ,
+ ,
__packed_splat4  )

◆ __packed_scalar_binary_op() [3/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_scalar_binary_op ( padd_s_u32x2 ,
uint32x2_t ,
uint32_t ,
+ ,
__packed_splat2  )

◆ __packed_scalar_binary_op() [4/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_scalar_binary_op ( padd_s_u8x4 ,
uint8x4_t ,
uint8_t ,
+ ,
__packed_splat4  )

◆ __packed_scalar_binary_op() [5/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_scalar_binary_op ( padd_s_u8x8 ,
uint8x8_t ,
uint8_t ,
+ ,
__packed_splat8  )

◆ __packed_sh1add() [1/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __packed_sh1add ( psh1add_i16x2 ,
int16x2_t  )

◆ __packed_sh1add() [2/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t __packed_sh1add ( psh1add_u16x4 ,
uint16x4_t  )

◆ __packed_sh1add() [3/3]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t __packed_sh1add ( psh1add_u32x2 ,
uint32x2_t  )

◆ __packed_sh1sadd() [1/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t __packed_sh1sadd ( pssh1sadd_i16x2 ,
int16x2_t  )

◆ __packed_sh1sadd() [2/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __packed_sh1sadd ( pssh1sadd_i32x2 ,
int32x2_t  )

◆ __packed_slx()

__builtin_bitreverse32 __packed_slx ( slx_32 ,
uint32_t  )

◆ __packed_splat() [1/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat ( pmv_s_i16x2 ,
int16x2_t ,
int16_t ,
__packed_splat2  )

◆ __packed_splat() [2/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat ( pmv_s_i16x4 ,
int16x4_t ,
int16_t ,
__packed_splat4  )

◆ __packed_splat() [3/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat ( pmv_s_i32x2 ,
int32x2_t ,
int32_t ,
__packed_splat2  )

◆ __packed_splat() [4/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat ( pmv_s_i8x4 ,
int8x4_t ,
int8_t ,
__packed_splat4  )

◆ __packed_splat() [5/5]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat ( pmv_s_i8x8 ,
int8x8_t ,
int8_t ,
__packed_splat8  )

◆ __packed_ternary_builtin() [1/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __packed_ternary_builtin ( mhracc_i32 ,
int32_t ,
__builtin_riscv_mhracc_i32  )

◆ __packed_ternary_builtin() [2/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __packed_ternary_builtin ( mhraccu_u32 ,
uint32_t ,
__builtin_riscv_mhraccu_u32  )

◆ __packed_ternary_builtin_mixed() [1/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __packed_ternary_builtin_mixed ( mhraccsu_i32 ,
int32_t ,
int32_t ,
uint32_t ,
__builtin_riscv_mhraccsu_i32  )

◆ __packed_ternary_builtin_mixed() [2/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_ternary_builtin_mixed ( mqrwacc_i64 ,
int64_t ,
int32_t ,
int32_t ,
__builtin_riscv_mqrwacc_i64  )

◆ __packed_unary_op() [1/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_unary_op ( pneg_i16x2 ,
int16x2_t ,
-  )

References __packed_unary_op, and int16x2_t.

◆ __packed_unary_op() [2/2]

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_unary_op ( pneg_i16x4 ,
int16x4_t ,
-  )

Variable Documentation

◆ int16_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 int16_t

◆ int16x2_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 int16x2_t

◆ int16x4_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 int16x4_t

◆ int32_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 int32_t

◆ int32x2_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max int32x2_t

◆ int64_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 int64_t
Examples
/work/as-worker-4/publish-doxygen-docs/llvm-project/clang/lib/StaticAnalyzer/Core/RegionStore.cpp.

Definition at line 520 of file riscv_packed_simd.h.

Referenced by __packed_binary_builtin(), __packed_pabs(), __packed_slx(), __packed_ternary_builtin_mixed(), amo_ldat_sadd(), amo_ldat_smax(), amo_ldat_smin(), amo_ldat_sswap(), amo_stdat_sadd(), amo_stdat_smax(), amo_stdat_smin(), calculateOffset(), clang::SemaARM::CheckARMCoprocessorImmediate(), checkBuiltinTemplateIdType(), CheckC23ConstexprInitStringLiteral(), clang::checkFPMScaleIfConstant(), CheckGatherBuiltin(), CollectArgsForIntegratedAssembler(), clang::threadSafety::til::Literal::compare(), constructAggregate(), ConvertAPValueToString(), convertOffsetsFromSvalToUnsigneds(), convertSizedByBoundToElementCount(), convertToDenseElementsAttrImpl(), clang::CIRGen::CIRGenBuilderTy::createMaskedLoad(), createNewGlobalView(), determineEndOffset(), diagnoseXorMisusedAsPow(), clang::CIRGen::CIRGenFunction::emitAlignmentAssumption(), clang::CIRGen::CIRGenFunction::emitAlignmentAssumption(), emitAtomicOp(), emitAtomicOp(), clang::markup::EmitInteger(), emitNeonRShiftImm(), emitNeonShiftVector(), emitNeonSplat(), emitPshufWord(), escapeByStartIndexAndCount(), evalOMPAdjustArgsBound(), EvaluateBuiltinStrLen(), clang::ento::ExplodedNode::ExplodedNode(), flattenAPValue(), cir::CIRBaseBuilderTy::getAlignmentAttr(), clang::Diagnostic::getArgSInt(), clang::StringLiteral::getCodeUnitS(), cir::CIRBaseBuilderTy::getConstantInt(), cir::CIRBaseBuilderTy::getConstPtrAttr(), GetFieldOffset(), GetFieldOffset(), getFieldOffsetInBits(), cir::CIRBaseBuilderTy::getGlobalViewAttr(), clang::ento::ExplodedNode::getID(), clang::StackFrame::getID(), getIntValueFromConstOp(), clang::ento::RegionOffset::getOffset(), getOffsetDifferenceInBits(), getRecordedIntegerWidth(), clang::CIRGen::CIRGenFunction::getSExtIntValueFromConstOp(), clang::ConstantArrayType::getSExtSize(), cir::CIRBaseBuilderTy::getSignedInt(), getSubobjectOffset(), getSubobjectOffset(), getSubobjectSizeInBits(), clang::CIRGen::CIRGenFunction::getZExtIntValueFromConstOp(), HandleIntegerHumanModifier(), HandleLValueArrayAdjustment(), handleVectorShuffle(), clang::isASCII(), isValidOrderingForOp(), cir::lowerDataMemberCast(), clang::ItaniumMangleContext::mangleCXXCtorVTable(), parseSwitchFlatOpCases(), performTypeAdjustment(), performTypeAdjustment(), clang::threadSafety::til::PrettyPrinter< Self, StreamType >::printLiteral(), PrintOffset(), clang::ento::RegionOffset::RegionOffset(), sourceLocationRecordToJSON(), clang::StackFrame::StackFrame(), clang::StackFrame::StackFrameManager, structHasUniqueObjectRepresentations(), structSubobjectsHaveUniqueObjectRepresentations(), TryPrintAsStringLiteral(), tryToInvalidateFReadBufferByElements(), wasm_i64x2_const(), wasm_i64x2_const_splat(), wasm_i64x2_extract_lane(), wasm_i64x2_make(), wasm_i64x2_replace_lane(), wasm_i64x2_shl(), wasm_i64x2_shr(), wasm_i64x2_splat(), wasm_u64x2_shr(), wasm_v128_load64_lane(), wasm_v128_load64_zero(), and wasm_v128_store64_lane().

◆ int8_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 int8_t

◆ int8x4_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_max int8x4_t

◆ int8x8_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min int8x8_t

◆ uint16_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 uint16_t

◆ uint16x2_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat uint16x2_t

◆ uint16x4_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max uint16x4_t

◆ uint32_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 uint32_t
Examples
/work/as-worker-4/publish-doxygen-docs/llvm-project/clang/lib/StaticAnalyzer/Core/RegionStore.cpp.

Definition at line 456 of file riscv_packed_simd.h.

Referenced by __attribute__(), __attribute__(), __attribute__(), __DO_LANE_OPS(), __DO_LANE_OPS(), __DO_LANE_OPS(), __DO_LANE_OPS(), __DO_LANE_OPS(), __DO_LANE_OPS(), __gpu_ballot(), __gpu_ballot(), __gpu_block_id(), __gpu_block_id_x(), __gpu_block_id_x(), __gpu_block_id_x(), __gpu_block_id_y(), __gpu_block_id_y(), __gpu_block_id_y(), __gpu_block_id_z(), __gpu_block_id_z(), __gpu_block_id_z(), __gpu_lane_id(), __gpu_lane_id(), __gpu_lane_id(), __gpu_lane_mask(), __gpu_match_all_u32(), __gpu_match_any_u32(), __gpu_num_blocks(), __gpu_num_blocks_x(), __gpu_num_blocks_x(), __gpu_num_blocks_x(), __gpu_num_blocks_y(), __gpu_num_blocks_y(), __gpu_num_blocks_y(), __gpu_num_blocks_z(), __gpu_num_blocks_z(), __gpu_num_blocks_z(), __gpu_num_lanes(), __gpu_num_lanes(), __gpu_num_lanes(), __gpu_num_threads(), __gpu_num_threads_x(), __gpu_num_threads_x(), __gpu_num_threads_x(), __gpu_num_threads_y(), __gpu_num_threads_y(), __gpu_num_threads_y(), __gpu_num_threads_z(), __gpu_num_threads_z(), __gpu_num_threads_z(), __gpu_read_first_lane_f32(), __gpu_read_first_lane_u32(), __gpu_read_first_lane_u32(), __gpu_read_first_lane_u32(), __gpu_read_first_lane_u64(), __gpu_shuffle_idx_f32(), __gpu_shuffle_idx_f64(), __gpu_shuffle_idx_u32(), __gpu_shuffle_idx_u32(), __gpu_shuffle_idx_u32(), __gpu_shuffle_idx_u64(), __gpu_sync_lane(), __gpu_thread_id(), __gpu_thread_id_x(), __gpu_thread_id_x(), __gpu_thread_id_x(), __gpu_thread_id_y(), __gpu_thread_id_y(), __gpu_thread_id_y(), __gpu_thread_id_z(), __gpu_thread_id_z(), __gpu_thread_id_z(), __packed_binary_builtin(), __packed_binary_builtin(), __packed_binary_builtin(), __packed_binary_builtin(), __packed_binary_builtin(), __packed_mulh_builtin(), __packed_mulh_builtin(), __packed_mulh_builtin(), __packed_pabs(), __packed_scalar_binary_op(), __packed_slx(), __packed_ternary_builtin(), __packed_ternary_builtin(), __packed_ternary_builtin_mixed(), clang::serialization::MultiOnDiskHashTable< ReaderInfo >::add(), clang::BitsPacker::addBits(), AddClassMessageCompletions(), clang::api_notes::APINotesWriter::addContext(), addImplicitBindingAttrToDecl(), clang::api_notes::APINotesWriter::addObjCMethod(), clang::BitsUnpacker::advance(), amo_lwat_add(), amo_lwat_and(), amo_lwat_ior(), amo_lwat_swap(), amo_lwat_umax(), amo_lwat_umin(), amo_lwat_xor(), amo_stwat_add(), amo_stwat_and(), amo_stwat_ior(), amo_stwat_umax(), amo_stwat_umin(), amo_stwat_xor(), clang::ento::APSIntType::APSIntType(), ARMMVEConstantSplat(), clang::serialization::TypeIdx::asTypeID(), clang::BitsUnpacker::BitsUnpacker(), clang::interp::IntegralAP< false >::bitWidth(), clang::CodeGen::BlockFlags::BlockFlags(), clang::interp::FixedPoint::bytesToSerialize(), clang::interp::IntegralAP< false >::bytesToSerialize(), clang::BitsUnpacker::canGetNextNBits(), clang::BitsPacker::canWriteNextNBits(), clang::checkAMDGPUFlatWorkGroupSizeArguments(), clang::checkAMDGPUMaxNumWorkGroupsArguments(), clang::checkAMDGPUWavesPerEUArguments(), clang::SemaARM::CheckARMCoprocessorImmediate(), CheckC23ConstexprInitStringLiteral(), CheckCodepointValidInIdentifier(), checkPositiveIntArgument(), clang::checkSwiftAsyncErrorBlock(), clang::Sema::checkUInt32Argument(), clang::SarifResult::clang::SarifDocumentWriter, clang::CodeGen::CGHLSLOffsetInfo::compareOffsets(), computeFullLaneShuffleMask(), clang::api_notes::ContextTableKey::ContextTableKey(), clang::api_notes::ContextTableKey::ContextTableKey(), clang::api_notes::ContextTableKey::ContextTableKey(), ConvertAPValueToString(), convertToBlockPointer(), clang::SarifResult::create(), clang::CIRGen::CIRGenBuilderTy::createIsFPClass(), createSemanticSignatureElement(), clang::Type::VectorTypeBitfields::DependentVectorType, clang::interp::FixedPoint::deserialize(), clang::interp::IntegralAP< false >::deserialize(), clang::interp::IntegralAP< false >::deserializeSize(), diagnoseMathematicalNotationInIdentifier(), clang::serialization::MultiOnDiskHashTableGenerator< ReaderInfo, WriterInfo >::emit(), emitMappingInformation(), emitPshufWord(), EncodeUCNEscape(), clang::ExternalASTSource::ExternalSemaSource, clang::interp::SourceMap::findSourceForOffset(), clang::FunctionEffect::fromOpaqueInt32(), clang::PointerAuthQualifier::fromOpaqueValue(), clang::api_notes::FunctionTableKey::FunctionTableKey(), clang::api_notes::FunctionTableKey::FunctionTableKey(), clang::api_notes::FunctionTableKey::FunctionTableKey(), clang::api_notes::FunctionTableKey::FunctionTableKey(), clang::OffloadArch::getAMDGPU(), clang::TargetInfo::getARMCDECoprocMask(), clang::PointerAuthQualifier::getAsOpaqueValue(), clang::CodeGen::BlockFieldFlags::getBitMask(), clang::CodeGen::BlockFlags::getBitMask(), clang::ento::APSIntType::getBitWidth(), getBitWidth(), clang::StringLiteral::getCodeUnit(), clang::Preprocessor::getCounterValue(), getDeclAlignIfRequired(), GetDISourceLanguageName(), getEnumInfo(), GetFieldOffset(), clang::api_notes::getFunctionKeyImpl(), clang::api_notes::getFunctionKeyImpl(), clang::ExternalASTSource::getGeneration(), getInlineSpirvConstant(), clang::OffloadArch::getIntelGPU(), clang::serialization::TypeIdx::getModuleFileIndex(), clang::BitsUnpacker::getNextBits(), clang::SemaHLSL::getNextImplicitBindingOrderID(), clang::OffloadArch::getNVPTX(), clang::serialization::PPEntityOffset::getOffset(), clang::Sema::AlignPackInfo::getRawEncoding(), clang::hlsl::getResourceDimensions(), clang::hlsl::getStageFromEnvironment(), clang::ExternalSubmoduleSource::getSubmodule(), cir::direct::LLVMBlockAddressInfo::getTagIndex(), getTypeAlignIfRequired(), getTypeAlignIfRequired(), clang::CIRGen::CIRGenBuilderTy::getUInt32(), GFNIAffine(), cir::GlobalCtorDtorEntry::GlobalCtorDtorEntry(), clang::SemaAMDGPU::handleAMDGPUNumSGPRAttr(), clang::SemaAMDGPU::handleAMDGPUNumVGPRAttr(), clang::SemaSwift::handleAsyncError(), handleCallbackAttr(), handleDiagnoseAsBuiltinAttr(), handleFormatAttr(), handleInitPriorityAttr(), handleLayoutVersion(), handleMinVectorWidthAttr(), handlePassObjectSizeAttr(), handlePatchableFunctionEntryAttr(), clang::SemaOpenCL::handleSubGroupSize(), handleVTablePointerAuthentication(), InitializeStandardPredefinedMacros(), isAllowedIDChar(), isAllowedInitiallyIDChar(), clang::isASCII(), isMathematicalExtensionID(), isUnicodeWhitespace(), clang::launchExecutor(), clang::MicrosoftMangleContext::mangleCXXCatchableType(), clang::MicrosoftMangleContext::mangleCXXCatchableTypeArray(), clang::MicrosoftMangleContext::mangleCXXRTTIBaseClassDescriptor(), clang::MicrosoftMangleContext::mangleCXXThrowInfo(), mangleThunkThisAdjustment(), maybeDiagnoseIDCharCompat(), maybeDiagnoseUTF8Homoglyph(), MeasureUCNEscape(), MVEImmediateShr(), nan(), clang::DeclContext::ObjCContainerDeclBitfields::ObjCContainerDecl, clang::CodeGen::CGHLSLOffsetInfo::operator[](), clang::outOfProcessJITBuilder(), clang::ParsedAttributeArgumentsProperties::ParsedAttributeArgumentsProperties(), parseToleranceOption(), clang::serialization::PPEntityOffset::PPEntityOffset(), printArg< IntegralAP< false > >(), printArg< IntegralAP< true > >(), ProcessNamedUCNEscape(), ProcessNumericUCNEscape(), ProcessUCNEscape(), profileIntValue(), clang::interp::SourceMap::push(), clang::ASTReader::ReadAlignPackInfo(), clang::serialization::DataStreamBasicReader< Impl >::readAPInt(), clang::serialization::DataStreamBasicReader< Impl >::readArray(), clang::ASTReaderListener::ReadCounter(), clang::serialization::DataStreamBasicReader< Impl >::readExtParameterInfo(), clang::serialization::DataStreamBasicReader< Impl >::readFunctionEffect(), clang::serialization::DataStreamBasicReader< Impl >::readNestedNameSpecifier(), clang::ASTRecordReader::readUInt32(), clang::CodeGen::CodeGenModule::Release(), clang::BitsPacker::reset(), clang::hlsl::RootSignatureToken::RootSignatureToken(), clang::hlsl::RootSignatureToken::RootSignatureToken(), scaleBranchWeight(), clang::interp::FixedPoint::serialize(), clang::interp::IntegralAP< false >::serialize(), clang::Qualifiers::setAddressSpace(), clang::Preprocessor::setCounterValue(), clang::detail::SarifArtifactLocation::setIndex(), clang::SarifResult::setIndex(), clang::detail::SarifArtifact::setOffset(), clang::CodeGen::CodeGenPGO::setValueProfilingFlag(), sharedGetConstructorDestructorAttrExpr(), clang::api_notes::SingleDeclTableKey::SingleDeclTableKey(), clang::api_notes::SingleDeclTableKey::SingleDeclTableKey(), clang::FunctionEffect::toOpaqueInt32(), clang::serialization::TypeIdx::TypeIdx(), clang::BitsUnpacker::updateValue(), clang::Preprocessor::VariadicMacroScopeGuard, wasm_i16x8_bitmask(), wasm_i16x8_shl(), wasm_i16x8_shr(), wasm_i32x4_bitmask(), wasm_i32x4_shl(), wasm_i32x4_shr(), wasm_i64x2_bitmask(), wasm_i64x2_shl(), wasm_i64x2_shr(), wasm_i8x16_bitmask(), wasm_i8x16_shl(), wasm_i8x16_shr(), wasm_u16x8_shr(), wasm_u32x4_const(), wasm_u32x4_const_splat(), wasm_u32x4_make(), wasm_u32x4_replace_lane(), wasm_u32x4_shr(), wasm_u32x4_splat(), wasm_u64x2_shr(), wasm_u8x16_shr(), wasm_v128_load32_splat(), WriteCharValueForDiagnostic(), clang::serialization::DataStreamBasicWriter< Impl >::writeEnum(), clang::serialization::DataStreamBasicWriter< Impl >::writeExceptionSpecInfo(), clang::serialization::DataStreamBasicWriter< Impl >::writeExtParameterInfo(), and clang::ASTRecordWriter::writeUInt32().

◆ uint32x2_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint32x2_t

◆ uint8_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 uint8_t

◆ uint8x4_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat uint16x2_t int16x4_t int32x2_t int16x4_t __builtin_riscv_pas_x_i16x2 __builtin_riscv_psas_x_i16x2 __builtin_riscv_paas_x_i16x2 __builtin_riscv_pas_x_i16x4 __builtin_riscv_psas_x_i16x4 __builtin_riscv_paas_x_i16x4 __builtin_riscv_pas_x_i32x2 __builtin_riscv_psas_x_i32x2 __builtin_riscv_paas_x_i32x2 __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_min __builtin_elementwise_max __builtin_elementwise_max __builtin_elementwise_max uint8x4_t

◆ uint8x8_t

__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __packed_splat4 __packed_splat2 __packed_splat8 __packed_splat4 __packed_splat2 __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat __builtin_elementwise_sub_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_add_sat __builtin_elementwise_sub_sat uint8x8_t