clang 18.0.0git
X86.cpp
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1//===- X86.cpp ------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ABIInfoImpl.h"
10#include "TargetInfo.h"
12#include "llvm/ADT/SmallBitVector.h"
13
14using namespace clang;
15using namespace clang::CodeGen;
16
17namespace {
18
19/// IsX86_MMXType - Return true if this is an MMX type.
20bool IsX86_MMXType(llvm::Type *IRType) {
21 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
22 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
23 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
24 IRType->getScalarSizeInBits() != 64;
25}
26
27static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
28 StringRef Constraint,
29 llvm::Type* Ty) {
30 bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
31 .Cases("y", "&y", "^Ym", true)
32 .Default(false);
33 if (IsMMXCons && Ty->isVectorTy()) {
34 if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() !=
35 64) {
36 // Invalid MMX constraint
37 return nullptr;
38 }
39
40 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
41 }
42
43 // No operation needed
44 return Ty;
45}
46
47/// Returns true if this type can be passed in SSE registers with the
48/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
49static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
50 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
51 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
52 if (BT->getKind() == BuiltinType::LongDouble) {
53 if (&Context.getTargetInfo().getLongDoubleFormat() ==
54 &llvm::APFloat::x87DoubleExtended())
55 return false;
56 }
57 return true;
58 }
59 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
60 // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
61 // registers specially.
62 unsigned VecSize = Context.getTypeSize(VT);
63 if (VecSize == 128 || VecSize == 256 || VecSize == 512)
64 return true;
65 }
66 return false;
67}
68
69/// Returns true if this aggregate is small enough to be passed in SSE registers
70/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
71static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
72 return NumMembers <= 4;
73}
74
75/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
76static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
77 auto AI = ABIArgInfo::getDirect(T);
78 AI.setInReg(true);
79 AI.setCanBeFlattened(false);
80 return AI;
81}
82
83//===----------------------------------------------------------------------===//
84// X86-32 ABI Implementation
85//===----------------------------------------------------------------------===//
86
87/// Similar to llvm::CCState, but for Clang.
88struct CCState {
89 CCState(CGFunctionInfo &FI)
90 : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()),
91 Required(FI.getRequiredArgs()), IsDelegateCall(FI.isDelegateCall()) {}
92
93 llvm::SmallBitVector IsPreassigned;
94 unsigned CC = CallingConv::CC_C;
95 unsigned FreeRegs = 0;
96 unsigned FreeSSERegs = 0;
98 bool IsDelegateCall = false;
99};
100
101/// X86_32ABIInfo - The X86-32 ABI information.
102class X86_32ABIInfo : public ABIInfo {
103 enum Class {
104 Integer,
105 Float
106 };
107
108 static const unsigned MinABIStackAlignInBytes = 4;
109
110 bool IsDarwinVectorABI;
111 bool IsRetSmallStructInRegABI;
112 bool IsWin32StructABI;
113 bool IsSoftFloatABI;
114 bool IsMCUABI;
115 bool IsLinuxABI;
116 unsigned DefaultNumRegisterParameters;
117
118 static bool isRegisterSize(unsigned Size) {
119 return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
120 }
121
122 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
123 // FIXME: Assumes vectorcall is in use.
124 return isX86VectorTypeForVectorCall(getContext(), Ty);
125 }
126
128 uint64_t NumMembers) const override {
129 // FIXME: Assumes vectorcall is in use.
130 return isX86VectorCallAggregateSmallEnough(NumMembers);
131 }
132
133 bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
134
135 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
136 /// such that the argument will be passed in memory.
137 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
138
139 ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
140
141 /// Return the alignment to use for the given type on the stack.
142 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
143
144 Class classify(QualType Ty) const;
145 ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
146 ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State,
147 unsigned ArgIndex) const;
148
149 /// Updates the number of available free registers, returns
150 /// true if any registers were allocated.
151 bool updateFreeRegs(QualType Ty, CCState &State) const;
152
153 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
154 bool &NeedsPadding) const;
155 bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
156
157 bool canExpandIndirectArgument(QualType Ty) const;
158
159 /// Rewrite the function info so that all memory arguments use
160 /// inalloca.
161 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
162
163 void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
164 CharUnits &StackOffset, ABIArgInfo &Info,
165 QualType Type) const;
166 void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
167
168public:
169
170 void computeInfo(CGFunctionInfo &FI) const override;
171 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
172 QualType Ty) const override;
173
174 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
175 bool RetSmallStructInRegABI, bool Win32StructABI,
176 unsigned NumRegisterParameters, bool SoftFloatABI)
177 : ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
178 IsRetSmallStructInRegABI(RetSmallStructInRegABI),
179 IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI),
180 IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
181 IsLinuxABI(CGT.getTarget().getTriple().isOSLinux() ||
182 CGT.getTarget().getTriple().isOSCygMing()),
183 DefaultNumRegisterParameters(NumRegisterParameters) {}
184};
185
186class X86_32SwiftABIInfo : public SwiftABIInfo {
187public:
188 explicit X86_32SwiftABIInfo(CodeGenTypes &CGT)
189 : SwiftABIInfo(CGT, /*SwiftErrorInRegister=*/false) {}
190
192 bool AsReturnValue) const override {
193 // LLVM's x86-32 lowering currently only assigns up to three
194 // integer registers and three fp registers. Oddly, it'll use up to
195 // four vector registers for vectors, but those can overlap with the
196 // scalar registers.
197 return occupiesMoreThan(ComponentTys, /*total=*/3);
198 }
199};
200
201class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
202public:
203 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
204 bool RetSmallStructInRegABI, bool Win32StructABI,
205 unsigned NumRegisterParameters, bool SoftFloatABI)
206 : TargetCodeGenInfo(std::make_unique<X86_32ABIInfo>(
207 CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
208 NumRegisterParameters, SoftFloatABI)) {
209 SwiftInfo = std::make_unique<X86_32SwiftABIInfo>(CGT);
210 }
211
212 static bool isStructReturnInRegABI(
213 const llvm::Triple &Triple, const CodeGenOptions &Opts);
214
215 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
216 CodeGen::CodeGenModule &CGM) const override;
217
218 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
219 // Darwin uses different dwarf register numbers for EH.
220 if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
221 return 4;
222 }
223
225 llvm::Value *Address) const override;
226
228 StringRef Constraint,
229 llvm::Type* Ty) const override {
230 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
231 }
232
233 void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
234 std::string &Constraints,
235 std::vector<llvm::Type *> &ResultRegTypes,
236 std::vector<llvm::Type *> &ResultTruncRegTypes,
237 std::vector<LValue> &ResultRegDests,
238 std::string &AsmString,
239 unsigned NumOutputs) const override;
240
241 StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
242 return "movl\t%ebp, %ebp"
243 "\t\t// marker for objc_retainAutoreleaseReturnValue";
244 }
245};
246
247}
248
249/// Rewrite input constraint references after adding some output constraints.
250/// In the case where there is one output and one input and we add one output,
251/// we need to replace all operand references greater than or equal to 1:
252/// mov $0, $1
253/// mov eax, $1
254/// The result will be:
255/// mov $0, $2
256/// mov eax, $2
257static void rewriteInputConstraintReferences(unsigned FirstIn,
258 unsigned NumNewOuts,
259 std::string &AsmString) {
260 std::string Buf;
261 llvm::raw_string_ostream OS(Buf);
262 size_t Pos = 0;
263 while (Pos < AsmString.size()) {
264 size_t DollarStart = AsmString.find('$', Pos);
265 if (DollarStart == std::string::npos)
266 DollarStart = AsmString.size();
267 size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
268 if (DollarEnd == std::string::npos)
269 DollarEnd = AsmString.size();
270 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
271 Pos = DollarEnd;
272 size_t NumDollars = DollarEnd - DollarStart;
273 if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
274 // We have an operand reference.
275 size_t DigitStart = Pos;
276 if (AsmString[DigitStart] == '{') {
277 OS << '{';
278 ++DigitStart;
279 }
280 size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
281 if (DigitEnd == std::string::npos)
282 DigitEnd = AsmString.size();
283 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
284 unsigned OperandIndex;
285 if (!OperandStr.getAsInteger(10, OperandIndex)) {
286 if (OperandIndex >= FirstIn)
287 OperandIndex += NumNewOuts;
288 OS << OperandIndex;
289 } else {
290 OS << OperandStr;
291 }
292 Pos = DigitEnd;
293 }
294 }
295 AsmString = std::move(OS.str());
296}
297
298/// Add output constraints for EAX:EDX because they are return registers.
299void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
300 CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
301 std::vector<llvm::Type *> &ResultRegTypes,
302 std::vector<llvm::Type *> &ResultTruncRegTypes,
303 std::vector<LValue> &ResultRegDests, std::string &AsmString,
304 unsigned NumOutputs) const {
305 uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
306
307 // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
308 // larger.
309 if (!Constraints.empty())
310 Constraints += ',';
311 if (RetWidth <= 32) {
312 Constraints += "={eax}";
313 ResultRegTypes.push_back(CGF.Int32Ty);
314 } else {
315 // Use the 'A' constraint for EAX:EDX.
316 Constraints += "=A";
317 ResultRegTypes.push_back(CGF.Int64Ty);
318 }
319
320 // Truncate EAX or EAX:EDX to an integer of the appropriate size.
321 llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
322 ResultTruncRegTypes.push_back(CoerceTy);
323
324 // Coerce the integer by bitcasting the return slot pointer.
325 ReturnSlot.setAddress(ReturnSlot.getAddress(CGF).withElementType(CoerceTy));
326 ResultRegDests.push_back(ReturnSlot);
327
328 rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
329}
330
331/// shouldReturnTypeInRegister - Determine if the given type should be
332/// returned in a register (for the Darwin and MCU ABI).
333bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
334 ASTContext &Context) const {
335 uint64_t Size = Context.getTypeSize(Ty);
336
337 // For i386, type must be register sized.
338 // For the MCU ABI, it only needs to be <= 8-byte
339 if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
340 return false;
341
342 if (Ty->isVectorType()) {
343 // 64- and 128- bit vectors inside structures are not returned in
344 // registers.
345 if (Size == 64 || Size == 128)
346 return false;
347
348 return true;
349 }
350
351 // If this is a builtin, pointer, enum, complex type, member pointer, or
352 // member function pointer it is ok.
353 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
354 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
356 return true;
357
358 // Arrays are treated like records.
359 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
360 return shouldReturnTypeInRegister(AT->getElementType(), Context);
361
362 // Otherwise, it must be a record type.
363 const RecordType *RT = Ty->getAs<RecordType>();
364 if (!RT) return false;
365
366 // FIXME: Traverse bases here too.
367
368 // Structure types are passed in register if all fields would be
369 // passed in a register.
370 for (const auto *FD : RT->getDecl()->fields()) {
371 // Empty fields are ignored.
372 if (isEmptyField(Context, FD, true))
373 continue;
374
375 // Check fields recursively.
376 if (!shouldReturnTypeInRegister(FD->getType(), Context))
377 return false;
378 }
379 return true;
380}
381
382static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
383 // Treat complex types as the element type.
384 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
385 Ty = CTy->getElementType();
386
387 // Check for a type which we know has a simple scalar argument-passing
388 // convention without any padding. (We're specifically looking for 32
389 // and 64-bit integer and integer-equivalents, float, and double.)
390 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
391 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
392 return false;
393
394 uint64_t Size = Context.getTypeSize(Ty);
395 return Size == 32 || Size == 64;
396}
397
398static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
399 uint64_t &Size) {
400 for (const auto *FD : RD->fields()) {
401 // Scalar arguments on the stack get 4 byte alignment on x86. If the
402 // argument is smaller than 32-bits, expanding the struct will create
403 // alignment padding.
404 if (!is32Or64BitBasicType(FD->getType(), Context))
405 return false;
406
407 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
408 // how to expand them yet, and the predicate for telling if a bitfield still
409 // counts as "basic" is more complicated than what we were doing previously.
410 if (FD->isBitField())
411 return false;
412
413 Size += Context.getTypeSize(FD->getType());
414 }
415 return true;
416}
417
418static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
419 uint64_t &Size) {
420 // Don't do this if there are any non-empty bases.
421 for (const CXXBaseSpecifier &Base : RD->bases()) {
422 if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
423 Size))
424 return false;
425 }
426 if (!addFieldSizes(Context, RD, Size))
427 return false;
428 return true;
429}
430
431/// Test whether an argument type which is to be passed indirectly (on the
432/// stack) would have the equivalent layout if it was expanded into separate
433/// arguments. If so, we prefer to do the latter to avoid inhibiting
434/// optimizations.
435bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
436 // We can only expand structure types.
437 const RecordType *RT = Ty->getAs<RecordType>();
438 if (!RT)
439 return false;
440 const RecordDecl *RD = RT->getDecl();
441 uint64_t Size = 0;
442 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
443 if (!IsWin32StructABI) {
444 // On non-Windows, we have to conservatively match our old bitcode
445 // prototypes in order to be ABI-compatible at the bitcode level.
446 if (!CXXRD->isCLike())
447 return false;
448 } else {
449 // Don't do this for dynamic classes.
450 if (CXXRD->isDynamicClass())
451 return false;
452 }
453 if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
454 return false;
455 } else {
456 if (!addFieldSizes(getContext(), RD, Size))
457 return false;
458 }
459
460 // We can do this if there was no alignment padding.
461 return Size == getContext().getTypeSize(Ty);
462}
463
464ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
465 // If the return value is indirect, then the hidden argument is consuming one
466 // integer register.
467 if (State.FreeRegs) {
468 --State.FreeRegs;
469 if (!IsMCUABI)
470 return getNaturalAlignIndirectInReg(RetTy);
471 }
472 return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
473}
474
475ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
476 CCState &State) const {
477 if (RetTy->isVoidType())
478 return ABIArgInfo::getIgnore();
479
480 const Type *Base = nullptr;
481 uint64_t NumElts = 0;
482 if ((State.CC == llvm::CallingConv::X86_VectorCall ||
483 State.CC == llvm::CallingConv::X86_RegCall) &&
484 isHomogeneousAggregate(RetTy, Base, NumElts)) {
485 // The LLVM struct type for such an aggregate should lower properly.
486 return ABIArgInfo::getDirect();
487 }
488
489 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
490 // On Darwin, some vectors are returned in registers.
491 if (IsDarwinVectorABI) {
492 uint64_t Size = getContext().getTypeSize(RetTy);
493
494 // 128-bit vectors are a special case; they are returned in
495 // registers and we need to make sure to pick a type the LLVM
496 // backend will like.
497 if (Size == 128)
498 return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
499 llvm::Type::getInt64Ty(getVMContext()), 2));
500
501 // Always return in register if it fits in a general purpose
502 // register, or if it is 64 bits and has a single element.
503 if ((Size == 8 || Size == 16 || Size == 32) ||
504 (Size == 64 && VT->getNumElements() == 1))
505 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
506 Size));
507
508 return getIndirectReturnResult(RetTy, State);
509 }
510
511 return ABIArgInfo::getDirect();
512 }
513
514 if (isAggregateTypeForABI(RetTy)) {
515 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
516 // Structures with flexible arrays are always indirect.
517 if (RT->getDecl()->hasFlexibleArrayMember())
518 return getIndirectReturnResult(RetTy, State);
519 }
520
521 // If specified, structs and unions are always indirect.
522 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
523 return getIndirectReturnResult(RetTy, State);
524
525 // Ignore empty structs/unions.
526 if (isEmptyRecord(getContext(), RetTy, true))
527 return ABIArgInfo::getIgnore();
528
529 // Return complex of _Float16 as <2 x half> so the backend will use xmm0.
530 if (const ComplexType *CT = RetTy->getAs<ComplexType>()) {
531 QualType ET = getContext().getCanonicalType(CT->getElementType());
532 if (ET->isFloat16Type())
533 return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
534 llvm::Type::getHalfTy(getVMContext()), 2));
535 }
536
537 // Small structures which are register sized are generally returned
538 // in a register.
539 if (shouldReturnTypeInRegister(RetTy, getContext())) {
540 uint64_t Size = getContext().getTypeSize(RetTy);
541
542 // As a special-case, if the struct is a "single-element" struct, and
543 // the field is of type "float" or "double", return it in a
544 // floating-point register. (MSVC does not apply this special case.)
545 // We apply a similar transformation for pointer types to improve the
546 // quality of the generated IR.
547 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
548 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
549 || SeltTy->hasPointerRepresentation())
550 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
551
552 // FIXME: We should be able to narrow this integer in cases with dead
553 // padding.
554 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
555 }
556
557 return getIndirectReturnResult(RetTy, State);
558 }
559
560 // Treat an enum type as its underlying type.
561 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
562 RetTy = EnumTy->getDecl()->getIntegerType();
563
564 if (const auto *EIT = RetTy->getAs<BitIntType>())
565 if (EIT->getNumBits() > 64)
566 return getIndirectReturnResult(RetTy, State);
567
568 return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
570}
571
572unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
573 unsigned Align) const {
574 // Otherwise, if the alignment is less than or equal to the minimum ABI
575 // alignment, just use the default; the backend will handle this.
576 if (Align <= MinABIStackAlignInBytes)
577 return 0; // Use default alignment.
578
579 if (IsLinuxABI) {
580 // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't
581 // want to spend any effort dealing with the ramifications of ABI breaks.
582 //
583 // If the vector type is __m128/__m256/__m512, return the default alignment.
584 if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64))
585 return Align;
586 }
587 // On non-Darwin, the stack type alignment is always 4.
588 if (!IsDarwinVectorABI) {
589 // Set explicit alignment, since we may need to realign the top.
590 return MinABIStackAlignInBytes;
591 }
592
593 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
594 if (Align >= 16 && (isSIMDVectorType(getContext(), Ty) ||
595 isRecordWithSIMDVectorType(getContext(), Ty)))
596 return 16;
597
598 return MinABIStackAlignInBytes;
599}
600
601ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
602 CCState &State) const {
603 if (!ByVal) {
604 if (State.FreeRegs) {
605 --State.FreeRegs; // Non-byval indirects just use one pointer.
606 if (!IsMCUABI)
607 return getNaturalAlignIndirectInReg(Ty);
608 }
609 return getNaturalAlignIndirect(Ty, false);
610 }
611
612 // Compute the byval alignment.
613 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
614 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
615 if (StackAlign == 0)
616 return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
617
618 // If the stack alignment is less than the type alignment, realign the
619 // argument.
620 bool Realign = TypeAlign > StackAlign;
622 /*ByVal=*/true, Realign);
623}
624
625X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
626 const Type *T = isSingleElementStruct(Ty, getContext());
627 if (!T)
628 T = Ty.getTypePtr();
629
630 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
631 BuiltinType::Kind K = BT->getKind();
632 if (K == BuiltinType::Float || K == BuiltinType::Double)
633 return Float;
634 }
635 return Integer;
636}
637
638bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
639 if (!IsSoftFloatABI) {
640 Class C = classify(Ty);
641 if (C == Float)
642 return false;
643 }
644
645 unsigned Size = getContext().getTypeSize(Ty);
646 unsigned SizeInRegs = (Size + 31) / 32;
647
648 if (SizeInRegs == 0)
649 return false;
650
651 if (!IsMCUABI) {
652 if (SizeInRegs > State.FreeRegs) {
653 State.FreeRegs = 0;
654 return false;
655 }
656 } else {
657 // The MCU psABI allows passing parameters in-reg even if there are
658 // earlier parameters that are passed on the stack. Also,
659 // it does not allow passing >8-byte structs in-register,
660 // even if there are 3 free registers available.
661 if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
662 return false;
663 }
664
665 State.FreeRegs -= SizeInRegs;
666 return true;
667}
668
669bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
670 bool &InReg,
671 bool &NeedsPadding) const {
672 // On Windows, aggregates other than HFAs are never passed in registers, and
673 // they do not consume register slots. Homogenous floating-point aggregates
674 // (HFAs) have already been dealt with at this point.
675 if (IsWin32StructABI && isAggregateTypeForABI(Ty))
676 return false;
677
678 NeedsPadding = false;
679 InReg = !IsMCUABI;
680
681 if (!updateFreeRegs(Ty, State))
682 return false;
683
684 if (IsMCUABI)
685 return true;
686
687 if (State.CC == llvm::CallingConv::X86_FastCall ||
688 State.CC == llvm::CallingConv::X86_VectorCall ||
689 State.CC == llvm::CallingConv::X86_RegCall) {
690 if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
691 NeedsPadding = true;
692
693 return false;
694 }
695
696 return true;
697}
698
699bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
700 bool IsPtrOrInt = (getContext().getTypeSize(Ty) <= 32) &&
702 Ty->isReferenceType());
703
704 if (!IsPtrOrInt && (State.CC == llvm::CallingConv::X86_FastCall ||
705 State.CC == llvm::CallingConv::X86_VectorCall))
706 return false;
707
708 if (!updateFreeRegs(Ty, State))
709 return false;
710
711 if (!IsPtrOrInt && State.CC == llvm::CallingConv::X86_RegCall)
712 return false;
713
714 // Return true to apply inreg to all legal parameters except for MCU targets.
715 return !IsMCUABI;
716}
717
718void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
719 // Vectorcall x86 works subtly different than in x64, so the format is
720 // a bit different than the x64 version. First, all vector types (not HVAs)
721 // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
722 // This differs from the x64 implementation, where the first 6 by INDEX get
723 // registers.
724 // In the second pass over the arguments, HVAs are passed in the remaining
725 // vector registers if possible, or indirectly by address. The address will be
726 // passed in ECX/EDX if available. Any other arguments are passed according to
727 // the usual fastcall rules.
729 for (int I = 0, E = Args.size(); I < E; ++I) {
730 const Type *Base = nullptr;
731 uint64_t NumElts = 0;
732 const QualType &Ty = Args[I].type;
733 if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
734 isHomogeneousAggregate(Ty, Base, NumElts)) {
735 if (State.FreeSSERegs >= NumElts) {
736 State.FreeSSERegs -= NumElts;
737 Args[I].info = ABIArgInfo::getDirectInReg();
738 State.IsPreassigned.set(I);
739 }
740 }
741 }
742}
743
744ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, CCState &State,
745 unsigned ArgIndex) const {
746 // FIXME: Set alignment on indirect arguments.
747 bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
748 bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
749 bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
750
752 TypeInfo TI = getContext().getTypeInfo(Ty);
753
754 // Check with the C++ ABI first.
755 const RecordType *RT = Ty->getAs<RecordType>();
756 if (RT) {
757 CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
758 if (RAA == CGCXXABI::RAA_Indirect) {
759 return getIndirectResult(Ty, false, State);
760 } else if (State.IsDelegateCall) {
761 // Avoid having different alignments on delegate call args by always
762 // setting the alignment to 4, which is what we do for inallocas.
763 ABIArgInfo Res = getIndirectResult(Ty, false, State);
765 return Res;
766 } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
767 // The field index doesn't matter, we'll fix it up later.
768 return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
769 }
770 }
771
772 // Regcall uses the concept of a homogenous vector aggregate, similar
773 // to other targets.
774 const Type *Base = nullptr;
775 uint64_t NumElts = 0;
776 if ((IsRegCall || IsVectorCall) &&
777 isHomogeneousAggregate(Ty, Base, NumElts)) {
778 if (State.FreeSSERegs >= NumElts) {
779 State.FreeSSERegs -= NumElts;
780
781 // Vectorcall passes HVAs directly and does not flatten them, but regcall
782 // does.
783 if (IsVectorCall)
784 return getDirectX86Hva();
785
786 if (Ty->isBuiltinType() || Ty->isVectorType())
787 return ABIArgInfo::getDirect();
788 return ABIArgInfo::getExpand();
789 }
790 return getIndirectResult(Ty, /*ByVal=*/false, State);
791 }
792
793 if (isAggregateTypeForABI(Ty)) {
794 // Structures with flexible arrays are always indirect.
795 // FIXME: This should not be byval!
796 if (RT && RT->getDecl()->hasFlexibleArrayMember())
797 return getIndirectResult(Ty, true, State);
798
799 // Ignore empty structs/unions on non-Windows.
800 if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
801 return ABIArgInfo::getIgnore();
802
803 llvm::LLVMContext &LLVMContext = getVMContext();
804 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
805 bool NeedsPadding = false;
806 bool InReg;
807 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
808 unsigned SizeInRegs = (TI.Width + 31) / 32;
809 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
810 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
811 if (InReg)
812 return ABIArgInfo::getDirectInReg(Result);
813 else
814 return ABIArgInfo::getDirect(Result);
815 }
816 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
817
818 // Pass over-aligned aggregates to non-variadic functions on Windows
819 // indirectly. This behavior was added in MSVC 2015. Use the required
820 // alignment from the record layout, since that may be less than the
821 // regular type alignment, and types with required alignment of less than 4
822 // bytes are not passed indirectly.
823 if (IsWin32StructABI && State.Required.isRequiredArg(ArgIndex)) {
824 unsigned AlignInBits = 0;
825 if (RT) {
826 const ASTRecordLayout &Layout =
827 getContext().getASTRecordLayout(RT->getDecl());
828 AlignInBits = getContext().toBits(Layout.getRequiredAlignment());
829 } else if (TI.isAlignRequired()) {
830 AlignInBits = TI.Align;
831 }
832 if (AlignInBits > 32)
833 return getIndirectResult(Ty, /*ByVal=*/false, State);
834 }
835
836 // Expand small (<= 128-bit) record types when we know that the stack layout
837 // of those arguments will match the struct. This is important because the
838 // LLVM backend isn't smart enough to remove byval, which inhibits many
839 // optimizations.
840 // Don't do this for the MCU if there are still free integer registers
841 // (see X86_64 ABI for full explanation).
842 if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) &&
843 canExpandIndirectArgument(Ty))
845 IsFastCall || IsVectorCall || IsRegCall, PaddingType);
846
847 return getIndirectResult(Ty, true, State);
848 }
849
850 if (const VectorType *VT = Ty->getAs<VectorType>()) {
851 // On Windows, vectors are passed directly if registers are available, or
852 // indirectly if not. This avoids the need to align argument memory. Pass
853 // user-defined vector types larger than 512 bits indirectly for simplicity.
854 if (IsWin32StructABI) {
855 if (TI.Width <= 512 && State.FreeSSERegs > 0) {
856 --State.FreeSSERegs;
858 }
859 return getIndirectResult(Ty, /*ByVal=*/false, State);
860 }
861
862 // On Darwin, some vectors are passed in memory, we handle this by passing
863 // it as an i8/i16/i32/i64.
864 if (IsDarwinVectorABI) {
865 if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
866 (TI.Width == 64 && VT->getNumElements() == 1))
868 llvm::IntegerType::get(getVMContext(), TI.Width));
869 }
870
871 if (IsX86_MMXType(CGT.ConvertType(Ty)))
872 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
873
874 return ABIArgInfo::getDirect();
875 }
876
877
878 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
879 Ty = EnumTy->getDecl()->getIntegerType();
880
881 bool InReg = shouldPrimitiveUseInReg(Ty, State);
882
883 if (isPromotableIntegerTypeForABI(Ty)) {
884 if (InReg)
886 return ABIArgInfo::getExtend(Ty);
887 }
888
889 if (const auto *EIT = Ty->getAs<BitIntType>()) {
890 if (EIT->getNumBits() <= 64) {
891 if (InReg)
893 return ABIArgInfo::getDirect();
894 }
895 return getIndirectResult(Ty, /*ByVal=*/false, State);
896 }
897
898 if (InReg)
900 return ABIArgInfo::getDirect();
901}
902
903void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
904 CCState State(FI);
905 if (IsMCUABI)
906 State.FreeRegs = 3;
907 else if (State.CC == llvm::CallingConv::X86_FastCall) {
908 State.FreeRegs = 2;
909 State.FreeSSERegs = 3;
910 } else if (State.CC == llvm::CallingConv::X86_VectorCall) {
911 State.FreeRegs = 2;
912 State.FreeSSERegs = 6;
913 } else if (FI.getHasRegParm())
914 State.FreeRegs = FI.getRegParm();
915 else if (State.CC == llvm::CallingConv::X86_RegCall) {
916 State.FreeRegs = 5;
917 State.FreeSSERegs = 8;
918 } else if (IsWin32StructABI) {
919 // Since MSVC 2015, the first three SSE vectors have been passed in
920 // registers. The rest are passed indirectly.
921 State.FreeRegs = DefaultNumRegisterParameters;
922 State.FreeSSERegs = 3;
923 } else
924 State.FreeRegs = DefaultNumRegisterParameters;
925
926 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
928 } else if (FI.getReturnInfo().isIndirect()) {
929 // The C++ ABI is not aware of register usage, so we have to check if the
930 // return value was sret and put it in a register ourselves if appropriate.
931 if (State.FreeRegs) {
932 --State.FreeRegs; // The sret parameter consumes a register.
933 if (!IsMCUABI)
934 FI.getReturnInfo().setInReg(true);
935 }
936 }
937
938 // The chain argument effectively gives us another free register.
939 if (FI.isChainCall())
940 ++State.FreeRegs;
941
942 // For vectorcall, do a first pass over the arguments, assigning FP and vector
943 // arguments to XMM registers as available.
944 if (State.CC == llvm::CallingConv::X86_VectorCall)
945 runVectorCallFirstPass(FI, State);
946
947 bool UsedInAlloca = false;
949 for (unsigned I = 0, E = Args.size(); I < E; ++I) {
950 // Skip arguments that have already been assigned.
951 if (State.IsPreassigned.test(I))
952 continue;
953
954 Args[I].info =
955 classifyArgumentType(Args[I].type, State, I);
956 UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
957 }
958
959 // If we needed to use inalloca for any argument, do a second pass and rewrite
960 // all the memory arguments to use inalloca.
961 if (UsedInAlloca)
962 rewriteWithInAlloca(FI);
963}
964
965void
966X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
967 CharUnits &StackOffset, ABIArgInfo &Info,
968 QualType Type) const {
969 // Arguments are always 4-byte-aligned.
971 assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct");
972
973 // sret pointers and indirect things will require an extra pointer
974 // indirection, unless they are byval. Most things are byval, and will not
975 // require this indirection.
976 bool IsIndirect = false;
977 if (Info.isIndirect() && !Info.getIndirectByVal())
978 IsIndirect = true;
979 Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
980 llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
981 if (IsIndirect)
982 LLTy = llvm::PointerType::getUnqual(getVMContext());
983 FrameFields.push_back(LLTy);
984 StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type);
985
986 // Insert padding bytes to respect alignment.
987 CharUnits FieldEnd = StackOffset;
988 StackOffset = FieldEnd.alignTo(WordSize);
989 if (StackOffset != FieldEnd) {
990 CharUnits NumBytes = StackOffset - FieldEnd;
991 llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
992 Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
993 FrameFields.push_back(Ty);
994 }
995}
996
997static bool isArgInAlloca(const ABIArgInfo &Info) {
998 // Leave ignored and inreg arguments alone.
999 switch (Info.getKind()) {
1001 return true;
1002 case ABIArgInfo::Ignore:
1004 return false;
1006 case ABIArgInfo::Direct:
1007 case ABIArgInfo::Extend:
1008 return !Info.getInReg();
1009 case ABIArgInfo::Expand:
1011 // These are aggregate types which are never passed in registers when
1012 // inalloca is involved.
1013 return true;
1014 }
1015 llvm_unreachable("invalid enum");
1016}
1017
1018void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1019 assert(IsWin32StructABI && "inalloca only supported on win32");
1020
1021 // Build a packed struct type for all of the arguments in memory.
1022 SmallVector<llvm::Type *, 6> FrameFields;
1023
1024 // The stack alignment is always 4.
1025 CharUnits StackAlign = CharUnits::fromQuantity(4);
1026
1027 CharUnits StackOffset;
1029
1030 // Put 'this' into the struct before 'sret', if necessary.
1031 bool IsThisCall =
1032 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1034 if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1035 isArgInAlloca(I->info)) {
1036 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1037 ++I;
1038 }
1039
1040 // Put the sret parameter into the inalloca struct if it's in memory.
1041 if (Ret.isIndirect() && !Ret.getInReg()) {
1042 addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
1043 // On Windows, the hidden sret parameter is always returned in eax.
1044 Ret.setInAllocaSRet(IsWin32StructABI);
1045 }
1046
1047 // Skip the 'this' parameter in ecx.
1048 if (IsThisCall)
1049 ++I;
1050
1051 // Put arguments passed in memory into the struct.
1052 for (; I != E; ++I) {
1053 if (isArgInAlloca(I->info))
1054 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1055 }
1056
1057 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1058 /*isPacked=*/true),
1059 StackAlign);
1060}
1061
1062Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1063 Address VAListAddr, QualType Ty) const {
1064
1065 auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1066
1067 // x86-32 changes the alignment of certain arguments on the stack.
1068 //
1069 // Just messing with TypeInfo like this works because we never pass
1070 // anything indirectly.
1072 getTypeStackAlignInBytes(Ty, TypeInfo.Align.getQuantity()));
1073
1074 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1076 /*AllowHigherAlign*/ true);
1077}
1078
1079bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1080 const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1081 assert(Triple.getArch() == llvm::Triple::x86);
1082
1083 switch (Opts.getStructReturnConvention()) {
1085 break;
1086 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1087 return false;
1088 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1089 return true;
1090 }
1091
1092 if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1093 return true;
1094
1095 switch (Triple.getOS()) {
1096 case llvm::Triple::DragonFly:
1097 case llvm::Triple::FreeBSD:
1098 case llvm::Triple::OpenBSD:
1099 case llvm::Triple::Win32:
1100 return true;
1101 default:
1102 return false;
1103 }
1104}
1105
1106static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV,
1108 if (!FD->hasAttr<AnyX86InterruptAttr>())
1109 return;
1110
1111 llvm::Function *Fn = cast<llvm::Function>(GV);
1112 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1113 if (FD->getNumParams() == 0)
1114 return;
1115
1116 auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
1117 llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
1118 llvm::Attribute NewAttr = llvm::Attribute::getWithByValType(
1119 Fn->getContext(), ByValTy);
1120 Fn->addParamAttr(0, NewAttr);
1121}
1122
1123void X86_32TargetCodeGenInfo::setTargetAttributes(
1124 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1125 if (GV->isDeclaration())
1126 return;
1127 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1128 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1129 llvm::Function *Fn = cast<llvm::Function>(GV);
1130 Fn->addFnAttr("stackrealign");
1131 }
1132
1133 addX86InterruptAttrs(FD, GV, CGM);
1134 }
1135}
1136
1137bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1139 llvm::Value *Address) const {
1140 CodeGen::CGBuilderTy &Builder = CGF.Builder;
1141
1142 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1143
1144 // 0-7 are the eight integer registers; the order is different
1145 // on Darwin (for EH), but the range is the same.
1146 // 8 is %eip.
1147 AssignToArrayRange(Builder, Address, Four8, 0, 8);
1148
1149 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1150 // 12-16 are st(0..4). Not sure why we stop at 4.
1151 // These have size 16, which is sizeof(long double) on
1152 // platforms with 8-byte alignment for that type.
1153 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1154 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1155
1156 } else {
1157 // 9 is %eflags, which doesn't get a size on Darwin for some
1158 // reason.
1159 Builder.CreateAlignedStore(
1160 Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1161 CharUnits::One());
1162
1163 // 11-16 are st(0..5). Not sure why we stop at 5.
1164 // These have size 12, which is sizeof(long double) on
1165 // platforms with 4-byte alignment for that type.
1166 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1167 AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1168 }
1169
1170 return false;
1171}
1172
1173//===----------------------------------------------------------------------===//
1174// X86-64 ABI Implementation
1175//===----------------------------------------------------------------------===//
1176
1177
1178namespace {
1179
1180/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1181static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1182 switch (AVXLevel) {
1183 case X86AVXABILevel::AVX512:
1184 return 512;
1185 case X86AVXABILevel::AVX:
1186 return 256;
1187 case X86AVXABILevel::None:
1188 return 128;
1189 }
1190 llvm_unreachable("Unknown AVXLevel");
1191}
1192
1193/// X86_64ABIInfo - The X86_64 ABI information.
1194class X86_64ABIInfo : public ABIInfo {
1195 enum Class {
1196 Integer = 0,
1197 SSE,
1198 SSEUp,
1199 X87,
1200 X87Up,
1201 ComplexX87,
1202 NoClass,
1203 Memory
1204 };
1205
1206 /// merge - Implement the X86_64 ABI merging algorithm.
1207 ///
1208 /// Merge an accumulating classification \arg Accum with a field
1209 /// classification \arg Field.
1210 ///
1211 /// \param Accum - The accumulating classification. This should
1212 /// always be either NoClass or the result of a previous merge
1213 /// call. In addition, this should never be Memory (the caller
1214 /// should just return Memory for the aggregate).
1215 static Class merge(Class Accum, Class Field);
1216
1217 /// postMerge - Implement the X86_64 ABI post merging algorithm.
1218 ///
1219 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1220 /// final MEMORY or SSE classes when necessary.
1221 ///
1222 /// \param AggregateSize - The size of the current aggregate in
1223 /// the classification process.
1224 ///
1225 /// \param Lo - The classification for the parts of the type
1226 /// residing in the low word of the containing object.
1227 ///
1228 /// \param Hi - The classification for the parts of the type
1229 /// residing in the higher words of the containing object.
1230 ///
1231 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1232
1233 /// classify - Determine the x86_64 register classes in which the
1234 /// given type T should be passed.
1235 ///
1236 /// \param Lo - The classification for the parts of the type
1237 /// residing in the low word of the containing object.
1238 ///
1239 /// \param Hi - The classification for the parts of the type
1240 /// residing in the high word of the containing object.
1241 ///
1242 /// \param OffsetBase - The bit offset of this type in the
1243 /// containing object. Some parameters are classified different
1244 /// depending on whether they straddle an eightbyte boundary.
1245 ///
1246 /// \param isNamedArg - Whether the argument in question is a "named"
1247 /// argument, as used in AMD64-ABI 3.5.7.
1248 ///
1249 /// \param IsRegCall - Whether the calling conversion is regcall.
1250 ///
1251 /// If a word is unused its result will be NoClass; if a type should
1252 /// be passed in Memory then at least the classification of \arg Lo
1253 /// will be Memory.
1254 ///
1255 /// The \arg Lo class will be NoClass iff the argument is ignored.
1256 ///
1257 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1258 /// also be ComplexX87.
1259 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1260 bool isNamedArg, bool IsRegCall = false) const;
1261
1262 llvm::Type *GetByteVectorType(QualType Ty) const;
1263 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
1264 unsigned IROffset, QualType SourceTy,
1265 unsigned SourceOffset) const;
1266 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
1267 unsigned IROffset, QualType SourceTy,
1268 unsigned SourceOffset) const;
1269
1270 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1271 /// such that the argument will be returned in memory.
1272 ABIArgInfo getIndirectReturnResult(QualType Ty) const;
1273
1274 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1275 /// such that the argument will be passed in memory.
1276 ///
1277 /// \param freeIntRegs - The number of free integer registers remaining
1278 /// available.
1279 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
1280
1282
1283 ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
1284 unsigned &neededInt, unsigned &neededSSE,
1285 bool isNamedArg,
1286 bool IsRegCall = false) const;
1287
1288 ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
1289 unsigned &NeededSSE,
1290 unsigned &MaxVectorWidth) const;
1291
1292 ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
1293 unsigned &NeededSSE,
1294 unsigned &MaxVectorWidth) const;
1295
1296 bool IsIllegalVectorType(QualType Ty) const;
1297
1298 /// The 0.98 ABI revision clarified a lot of ambiguities,
1299 /// unfortunately in ways that were not always consistent with
1300 /// certain previous compilers. In particular, platforms which
1301 /// required strict binary compatibility with older versions of GCC
1302 /// may need to exempt themselves.
1303 bool honorsRevision0_98() const {
1304 return !getTarget().getTriple().isOSDarwin();
1305 }
1306
1307 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
1308 /// classify it as INTEGER (for compatibility with older clang compilers).
1309 bool classifyIntegerMMXAsSSE() const {
1310 // Clang <= 3.8 did not do this.
1311 if (getContext().getLangOpts().getClangABICompat() <=
1312 LangOptions::ClangABI::Ver3_8)
1313 return false;
1314
1315 const llvm::Triple &Triple = getTarget().getTriple();
1316 if (Triple.isOSDarwin() || Triple.isPS() || Triple.isOSFreeBSD())
1317 return false;
1318 return true;
1319 }
1320
1321 // GCC classifies vectors of __int128 as memory.
1322 bool passInt128VectorsInMem() const {
1323 // Clang <= 9.0 did not do this.
1324 if (getContext().getLangOpts().getClangABICompat() <=
1325 LangOptions::ClangABI::Ver9)
1326 return false;
1327
1328 const llvm::Triple &T = getTarget().getTriple();
1329 return T.isOSLinux() || T.isOSNetBSD();
1330 }
1331
1332 X86AVXABILevel AVXLevel;
1333 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
1334 // 64-bit hardware.
1335 bool Has64BitPointers;
1336
1337public:
1338 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
1339 : ABIInfo(CGT), AVXLevel(AVXLevel),
1340 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {}
1341
1342 bool isPassedUsingAVXType(QualType type) const {
1343 unsigned neededInt, neededSSE;
1344 // The freeIntRegs argument doesn't matter here.
1345 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
1346 /*isNamedArg*/true);
1347 if (info.isDirect()) {
1348 llvm::Type *ty = info.getCoerceToType();
1349 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
1350 return vectorTy->getPrimitiveSizeInBits().getFixedValue() > 128;
1351 }
1352 return false;
1353 }
1354
1355 void computeInfo(CGFunctionInfo &FI) const override;
1356
1357 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1358 QualType Ty) const override;
1359 Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
1360 QualType Ty) const override;
1361
1362 bool has64BitPointers() const {
1363 return Has64BitPointers;
1364 }
1365};
1366
1367/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1368class WinX86_64ABIInfo : public ABIInfo {
1369public:
1370 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
1371 : ABIInfo(CGT), AVXLevel(AVXLevel),
1372 IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
1373
1374 void computeInfo(CGFunctionInfo &FI) const override;
1375
1376 Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1377 QualType Ty) const override;
1378
1379 bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1380 // FIXME: Assumes vectorcall is in use.
1381 return isX86VectorTypeForVectorCall(getContext(), Ty);
1382 }
1383
1385 uint64_t NumMembers) const override {
1386 // FIXME: Assumes vectorcall is in use.
1387 return isX86VectorCallAggregateSmallEnough(NumMembers);
1388 }
1389
1390private:
1391 ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
1392 bool IsVectorCall, bool IsRegCall) const;
1393 ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
1394 const ABIArgInfo &current) const;
1395
1396 X86AVXABILevel AVXLevel;
1397
1398 bool IsMingw64;
1399};
1400
1401class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1402public:
1403 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
1404 : TargetCodeGenInfo(std::make_unique<X86_64ABIInfo>(CGT, AVXLevel)) {
1405 SwiftInfo =
1406 std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/true);
1407 }
1408
1409 /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
1410 /// autoreleaseRV/retainRV and autoreleaseRV/unsafeClaimRV optimizations.
1411 bool markARCOptimizedReturnCallsAsNoTail() const override { return true; }
1412
1413 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1414 return 7;
1415 }
1416
1418 llvm::Value *Address) const override {
1419 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1420
1421 // 0-15 are the 16 integer registers.
1422 // 16 is %rip.
1423 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1424 return false;
1425 }
1426
1428 StringRef Constraint,
1429 llvm::Type* Ty) const override {
1430 return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1431 }
1432
1433 bool isNoProtoCallVariadic(const CallArgList &args,
1434 const FunctionNoProtoType *fnType) const override {
1435 // The default CC on x86-64 sets %al to the number of SSA
1436 // registers used, and GCC sets this when calling an unprototyped
1437 // function, so we override the default behavior. However, don't do
1438 // that when AVX types are involved: the ABI explicitly states it is
1439 // undefined, and it doesn't work in practice because of how the ABI
1440 // defines varargs anyway.
1441 if (fnType->getCallConv() == CC_C) {
1442 bool HasAVXType = false;
1443 for (CallArgList::const_iterator
1444 it = args.begin(), ie = args.end(); it != ie; ++it) {
1445 if (getABIInfo<X86_64ABIInfo>().isPassedUsingAVXType(it->Ty)) {
1446 HasAVXType = true;
1447 break;
1448 }
1449 }
1450
1451 if (!HasAVXType)
1452 return true;
1453 }
1454
1455 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
1456 }
1457
1458 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1459 CodeGen::CodeGenModule &CGM) const override {
1460 if (GV->isDeclaration())
1461 return;
1462 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1463 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1464 llvm::Function *Fn = cast<llvm::Function>(GV);
1465 Fn->addFnAttr("stackrealign");
1466 }
1467
1468 addX86InterruptAttrs(FD, GV, CGM);
1469 }
1470 }
1471
1473 const FunctionDecl *Caller,
1474 const FunctionDecl *Callee,
1475 const CallArgList &Args) const override;
1476};
1477} // namespace
1478
1479static void initFeatureMaps(const ASTContext &Ctx,
1480 llvm::StringMap<bool> &CallerMap,
1481 const FunctionDecl *Caller,
1482 llvm::StringMap<bool> &CalleeMap,
1483 const FunctionDecl *Callee) {
1484 if (CalleeMap.empty() && CallerMap.empty()) {
1485 // The caller is potentially nullptr in the case where the call isn't in a
1486 // function. In this case, the getFunctionFeatureMap ensures we just get
1487 // the TU level setting (since it cannot be modified by 'target'..
1488 Ctx.getFunctionFeatureMap(CallerMap, Caller);
1489 Ctx.getFunctionFeatureMap(CalleeMap, Callee);
1490 }
1491}
1492
1494 SourceLocation CallLoc,
1495 const llvm::StringMap<bool> &CallerMap,
1496 const llvm::StringMap<bool> &CalleeMap,
1497 QualType Ty, StringRef Feature,
1498 bool IsArgument) {
1499 bool CallerHasFeat = CallerMap.lookup(Feature);
1500 bool CalleeHasFeat = CalleeMap.lookup(Feature);
1501 if (!CallerHasFeat && !CalleeHasFeat)
1502 return Diag.Report(CallLoc, diag::warn_avx_calling_convention)
1503 << IsArgument << Ty << Feature;
1504
1505 // Mixing calling conventions here is very clearly an error.
1506 if (!CallerHasFeat || !CalleeHasFeat)
1507 return Diag.Report(CallLoc, diag::err_avx_calling_convention)
1508 << IsArgument << Ty << Feature;
1509
1510 // Else, both caller and callee have the required feature, so there is no need
1511 // to diagnose.
1512 return false;
1513}
1514
1516 SourceLocation CallLoc,
1517 const llvm::StringMap<bool> &CallerMap,
1518 const llvm::StringMap<bool> &CalleeMap,
1519 QualType Ty, bool IsArgument) {
1520 bool Caller256 = CallerMap.lookup("avx512f") && !CallerMap.lookup("evex512");
1521 bool Callee256 = CalleeMap.lookup("avx512f") && !CalleeMap.lookup("evex512");
1522
1523 // Forbid 512-bit or larger vector pass or return when we disabled ZMM
1524 // instructions.
1525 if (Caller256 || Callee256)
1526 return Diag.Report(CallLoc, diag::err_avx_calling_convention)
1527 << IsArgument << Ty << "evex512";
1528
1529 return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty,
1530 "avx512f", IsArgument);
1531}
1532
1534 SourceLocation CallLoc,
1535 const llvm::StringMap<bool> &CallerMap,
1536 const llvm::StringMap<bool> &CalleeMap, QualType Ty,
1537 bool IsArgument) {
1538 uint64_t Size = Ctx.getTypeSize(Ty);
1539 if (Size > 256)
1540 return checkAVX512ParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty,
1541 IsArgument);
1542
1543 if (Size > 128)
1544 return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx",
1545 IsArgument);
1546
1547 return false;
1548}
1549
1550void X86_64TargetCodeGenInfo::checkFunctionCallABI(
1551 CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
1552 const FunctionDecl *Callee, const CallArgList &Args) const {
1553 llvm::StringMap<bool> CallerMap;
1554 llvm::StringMap<bool> CalleeMap;
1555 unsigned ArgIndex = 0;
1556
1557 // We need to loop through the actual call arguments rather than the
1558 // function's parameters, in case this variadic.
1559 for (const CallArg &Arg : Args) {
1560 // The "avx" feature changes how vectors >128 in size are passed. "avx512f"
1561 // additionally changes how vectors >256 in size are passed. Like GCC, we
1562 // warn when a function is called with an argument where this will change.
1563 // Unlike GCC, we also error when it is an obvious ABI mismatch, that is,
1564 // the caller and callee features are mismatched.
1565 // Unfortunately, we cannot do this diagnostic in SEMA, since the callee can
1566 // change its ABI with attribute-target after this call.
1567 if (Arg.getType()->isVectorType() &&
1568 CGM.getContext().getTypeSize(Arg.getType()) > 128) {
1569 initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
1570 QualType Ty = Arg.getType();
1571 // The CallArg seems to have desugared the type already, so for clearer
1572 // diagnostics, replace it with the type in the FunctionDecl if possible.
1573 if (ArgIndex < Callee->getNumParams())
1574 Ty = Callee->getParamDecl(ArgIndex)->getType();
1575
1576 if (checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
1577 CalleeMap, Ty, /*IsArgument*/ true))
1578 return;
1579 }
1580 ++ArgIndex;
1581 }
1582
1583 // Check return always, as we don't have a good way of knowing in codegen
1584 // whether this value is used, tail-called, etc.
1585 if (Callee->getReturnType()->isVectorType() &&
1586 CGM.getContext().getTypeSize(Callee->getReturnType()) > 128) {
1587 initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
1588 checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
1589 CalleeMap, Callee->getReturnType(),
1590 /*IsArgument*/ false);
1591 }
1592}
1593
1595 // If the argument does not end in .lib, automatically add the suffix.
1596 // If the argument contains a space, enclose it in quotes.
1597 // This matches the behavior of MSVC.
1598 bool Quote = Lib.contains(' ');
1599 std::string ArgStr = Quote ? "\"" : "";
1600 ArgStr += Lib;
1601 if (!Lib.ends_with_insensitive(".lib") && !Lib.ends_with_insensitive(".a"))
1602 ArgStr += ".lib";
1603 ArgStr += Quote ? "\"" : "";
1604 return ArgStr;
1605}
1606
1607namespace {
1608class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
1609public:
1610 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
1611 bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
1612 unsigned NumRegisterParameters)
1613 : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
1614 Win32StructABI, NumRegisterParameters, false) {}
1615
1616 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1617 CodeGen::CodeGenModule &CGM) const override;
1618
1619 void getDependentLibraryOption(llvm::StringRef Lib,
1620 llvm::SmallString<24> &Opt) const override {
1621 Opt = "/DEFAULTLIB:";
1622 Opt += qualifyWindowsLibrary(Lib);
1623 }
1624
1625 void getDetectMismatchOption(llvm::StringRef Name,
1626 llvm::StringRef Value,
1627 llvm::SmallString<32> &Opt) const override {
1628 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1629 }
1630};
1631} // namespace
1632
1633void WinX86_32TargetCodeGenInfo::setTargetAttributes(
1634 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1635 X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
1636 if (GV->isDeclaration())
1637 return;
1638 addStackProbeTargetAttributes(D, GV, CGM);
1639}
1640
1641namespace {
1642class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
1643public:
1644 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
1645 X86AVXABILevel AVXLevel)
1646 : TargetCodeGenInfo(std::make_unique<WinX86_64ABIInfo>(CGT, AVXLevel)) {
1647 SwiftInfo =
1648 std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/true);
1649 }
1650
1651 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1652 CodeGen::CodeGenModule &CGM) const override;
1653
1654 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1655 return 7;
1656 }
1657
1658 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1659 llvm::Value *Address) const override {
1660 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
1661
1662 // 0-15 are the 16 integer registers.
1663 // 16 is %rip.
1664 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
1665 return false;
1666 }
1667
1668 void getDependentLibraryOption(llvm::StringRef Lib,
1669 llvm::SmallString<24> &Opt) const override {
1670 Opt = "/DEFAULTLIB:";
1671 Opt += qualifyWindowsLibrary(Lib);
1672 }
1673
1674 void getDetectMismatchOption(llvm::StringRef Name,
1675 llvm::StringRef Value,
1676 llvm::SmallString<32> &Opt) const override {
1677 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
1678 }
1679};
1680} // namespace
1681
1682void WinX86_64TargetCodeGenInfo::setTargetAttributes(
1683 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1685 if (GV->isDeclaration())
1686 return;
1687 if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1688 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1689 llvm::Function *Fn = cast<llvm::Function>(GV);
1690 Fn->addFnAttr("stackrealign");
1691 }
1692
1693 addX86InterruptAttrs(FD, GV, CGM);
1694 }
1695
1696 addStackProbeTargetAttributes(D, GV, CGM);
1697}
1698
1699void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
1700 Class &Hi) const {
1701 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
1702 //
1703 // (a) If one of the classes is Memory, the whole argument is passed in
1704 // memory.
1705 //
1706 // (b) If X87UP is not preceded by X87, the whole argument is passed in
1707 // memory.
1708 //
1709 // (c) If the size of the aggregate exceeds two eightbytes and the first
1710 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1711 // argument is passed in memory. NOTE: This is necessary to keep the
1712 // ABI working for processors that don't support the __m256 type.
1713 //
1714 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1715 //
1716 // Some of these are enforced by the merging logic. Others can arise
1717 // only with unions; for example:
1718 // union { _Complex double; unsigned; }
1719 //
1720 // Note that clauses (b) and (c) were added in 0.98.
1721 //
1722 if (Hi == Memory)
1723 Lo = Memory;
1724 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
1725 Lo = Memory;
1726 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1727 Lo = Memory;
1728 if (Hi == SSEUp && Lo != SSE)
1729 Hi = SSE;
1730}
1731
1732X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
1733 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
1734 // classified recursively so that always two fields are
1735 // considered. The resulting class is calculated according to
1736 // the classes of the fields in the eightbyte:
1737 //
1738 // (a) If both classes are equal, this is the resulting class.
1739 //
1740 // (b) If one of the classes is NO_CLASS, the resulting class is
1741 // the other class.
1742 //
1743 // (c) If one of the classes is MEMORY, the result is the MEMORY
1744 // class.
1745 //
1746 // (d) If one of the classes is INTEGER, the result is the
1747 // INTEGER.
1748 //
1749 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
1750 // MEMORY is used as class.
1751 //
1752 // (f) Otherwise class SSE is used.
1753
1754 // Accum should never be memory (we should have returned) or
1755 // ComplexX87 (because this cannot be passed in a structure).
1756 assert((Accum != Memory && Accum != ComplexX87) &&
1757 "Invalid accumulated classification during merge.");
1758 if (Accum == Field || Field == NoClass)
1759 return Accum;
1760 if (Field == Memory)
1761 return Memory;
1762 if (Accum == NoClass)
1763 return Field;
1764 if (Accum == Integer || Field == Integer)
1765 return Integer;
1766 if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
1767 Accum == X87 || Accum == X87Up)
1768 return Memory;
1769 return SSE;
1770}
1771
1772void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, Class &Lo,
1773 Class &Hi, bool isNamedArg, bool IsRegCall) const {
1774 // FIXME: This code can be simplified by introducing a simple value class for
1775 // Class pairs with appropriate constructor methods for the various
1776 // situations.
1777
1778 // FIXME: Some of the split computations are wrong; unaligned vectors
1779 // shouldn't be passed in registers for example, so there is no chance they
1780 // can straddle an eightbyte. Verify & simplify.
1781
1782 Lo = Hi = NoClass;
1783
1784 Class &Current = OffsetBase < 64 ? Lo : Hi;
1785 Current = Memory;
1786
1787 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1788 BuiltinType::Kind k = BT->getKind();
1789
1790 if (k == BuiltinType::Void) {
1791 Current = NoClass;
1792 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
1793 Lo = Integer;
1794 Hi = Integer;
1795 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
1796 Current = Integer;
1797 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
1798 k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
1799 Current = SSE;
1800 } else if (k == BuiltinType::LongDouble) {
1801 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
1802 if (LDF == &llvm::APFloat::IEEEquad()) {
1803 Lo = SSE;
1804 Hi = SSEUp;
1805 } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
1806 Lo = X87;
1807 Hi = X87Up;
1808 } else if (LDF == &llvm::APFloat::IEEEdouble()) {
1809 Current = SSE;
1810 } else
1811 llvm_unreachable("unexpected long double representation!");
1812 }
1813 // FIXME: _Decimal32 and _Decimal64 are SSE.
1814 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1815 return;
1816 }
1817
1818 if (const EnumType *ET = Ty->getAs<EnumType>()) {
1819 // Classify the underlying integer type.
1820 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
1821 return;
1822 }
1823
1824 if (Ty->hasPointerRepresentation()) {
1825 Current = Integer;
1826 return;
1827 }
1828
1829 if (Ty->isMemberPointerType()) {
1830 if (Ty->isMemberFunctionPointerType()) {
1831 if (Has64BitPointers) {
1832 // If Has64BitPointers, this is an {i64, i64}, so classify both
1833 // Lo and Hi now.
1834 Lo = Hi = Integer;
1835 } else {
1836 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
1837 // straddles an eightbyte boundary, Hi should be classified as well.
1838 uint64_t EB_FuncPtr = (OffsetBase) / 64;
1839 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
1840 if (EB_FuncPtr != EB_ThisAdj) {
1841 Lo = Hi = Integer;
1842 } else {
1843 Current = Integer;
1844 }
1845 }
1846 } else {
1847 Current = Integer;
1848 }
1849 return;
1850 }
1851
1852 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1853 uint64_t Size = getContext().getTypeSize(VT);
1854 if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
1855 // gcc passes the following as integer:
1856 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
1857 // 2 bytes - <2 x char>, <1 x short>
1858 // 1 byte - <1 x char>
1859 Current = Integer;
1860
1861 // If this type crosses an eightbyte boundary, it should be
1862 // split.
1863 uint64_t EB_Lo = (OffsetBase) / 64;
1864 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
1865 if (EB_Lo != EB_Hi)
1866 Hi = Lo;
1867 } else if (Size == 64) {
1868 QualType ElementType = VT->getElementType();
1869
1870 // gcc passes <1 x double> in memory. :(
1871 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
1872 return;
1873
1874 // gcc passes <1 x long long> as SSE but clang used to unconditionally
1875 // pass them as integer. For platforms where clang is the de facto
1876 // platform compiler, we must continue to use integer.
1877 if (!classifyIntegerMMXAsSSE() &&
1878 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
1879 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
1880 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
1881 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
1882 Current = Integer;
1883 else
1884 Current = SSE;
1885
1886 // If this type crosses an eightbyte boundary, it should be
1887 // split.
1888 if (OffsetBase && OffsetBase != 64)
1889 Hi = Lo;
1890 } else if (Size == 128 ||
1891 (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
1892 QualType ElementType = VT->getElementType();
1893
1894 // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :(
1895 if (passInt128VectorsInMem() && Size != 128 &&
1896 (ElementType->isSpecificBuiltinType(BuiltinType::Int128) ||
1897 ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
1898 return;
1899
1900 // Arguments of 256-bits are split into four eightbyte chunks. The
1901 // least significant one belongs to class SSE and all the others to class
1902 // SSEUP. The original Lo and Hi design considers that types can't be
1903 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
1904 // This design isn't correct for 256-bits, but since there're no cases
1905 // where the upper parts would need to be inspected, avoid adding
1906 // complexity and just consider Hi to match the 64-256 part.
1907 //
1908 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
1909 // registers if they are "named", i.e. not part of the "..." of a
1910 // variadic function.
1911 //
1912 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
1913 // split into eight eightbyte chunks, one SSE and seven SSEUP.
1914 Lo = SSE;
1915 Hi = SSEUp;
1916 }
1917 return;
1918 }
1919
1920 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
1921 QualType ET = getContext().getCanonicalType(CT->getElementType());
1922
1923 uint64_t Size = getContext().getTypeSize(Ty);
1924 if (ET->isIntegralOrEnumerationType()) {
1925 if (Size <= 64)
1926 Current = Integer;
1927 else if (Size <= 128)
1928 Lo = Hi = Integer;
1929 } else if (ET->isFloat16Type() || ET == getContext().FloatTy ||
1930 ET->isBFloat16Type()) {
1931 Current = SSE;
1932 } else if (ET == getContext().DoubleTy) {
1933 Lo = Hi = SSE;
1934 } else if (ET == getContext().LongDoubleTy) {
1935 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
1936 if (LDF == &llvm::APFloat::IEEEquad())
1937 Current = Memory;
1938 else if (LDF == &llvm::APFloat::x87DoubleExtended())
1939 Current = ComplexX87;
1940 else if (LDF == &llvm::APFloat::IEEEdouble())
1941 Lo = Hi = SSE;
1942 else
1943 llvm_unreachable("unexpected long double representation!");
1944 }
1945
1946 // If this complex type crosses an eightbyte boundary then it
1947 // should be split.
1948 uint64_t EB_Real = (OffsetBase) / 64;
1949 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
1950 if (Hi == NoClass && EB_Real != EB_Imag)
1951 Hi = Lo;
1952
1953 return;
1954 }
1955
1956 if (const auto *EITy = Ty->getAs<BitIntType>()) {
1957 if (EITy->getNumBits() <= 64)
1958 Current = Integer;
1959 else if (EITy->getNumBits() <= 128)
1960 Lo = Hi = Integer;
1961 // Larger values need to get passed in memory.
1962 return;
1963 }
1964
1965 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
1966 // Arrays are treated like structures.
1967
1968 uint64_t Size = getContext().getTypeSize(Ty);
1969
1970 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
1971 // than eight eightbytes, ..., it has class MEMORY.
1972 // regcall ABI doesn't have limitation to an object. The only limitation
1973 // is the free registers, which will be checked in computeInfo.
1974 if (!IsRegCall && Size > 512)
1975 return;
1976
1977 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
1978 // fields, it has class MEMORY.
1979 //
1980 // Only need to check alignment of array base.
1981 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
1982 return;
1983
1984 // Otherwise implement simplified merge. We could be smarter about
1985 // this, but it isn't worth it and would be harder to verify.
1986 Current = NoClass;
1987 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
1988 uint64_t ArraySize = AT->getSize().getZExtValue();
1989
1990 // The only case a 256-bit wide vector could be used is when the array
1991 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
1992 // to work for sizes wider than 128, early check and fallback to memory.
1993 //
1994 if (Size > 128 &&
1995 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
1996 return;
1997
1998 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
1999 Class FieldLo, FieldHi;
2000 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2001 Lo = merge(Lo, FieldLo);
2002 Hi = merge(Hi, FieldHi);
2003 if (Lo == Memory || Hi == Memory)
2004 break;
2005 }
2006
2007 postMerge(Size, Lo, Hi);
2008 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2009 return;
2010 }
2011
2012 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2013 uint64_t Size = getContext().getTypeSize(Ty);
2014
2015 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2016 // than eight eightbytes, ..., it has class MEMORY.
2017 if (Size > 512)
2018 return;
2019
2020 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2021 // copy constructor or a non-trivial destructor, it is passed by invisible
2022 // reference.
2023 if (getRecordArgABI(RT, getCXXABI()))
2024 return;
2025
2026 const RecordDecl *RD = RT->getDecl();
2027
2028 // Assume variable sized types are passed in memory.
2029 if (RD->hasFlexibleArrayMember())
2030 return;
2031
2032 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2033
2034 // Reset Lo class, this will be recomputed.
2035 Current = NoClass;
2036
2037 // If this is a C++ record, classify the bases first.
2038 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2039 for (const auto &I : CXXRD->bases()) {
2040 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2041 "Unexpected base class!");
2042 const auto *Base =
2043 cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
2044
2045 // Classify this field.
2046 //
2047 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2048 // single eightbyte, each is classified separately. Each eightbyte gets
2049 // initialized to class NO_CLASS.
2050 Class FieldLo, FieldHi;
2051 uint64_t Offset =
2052 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2053 classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2054 Lo = merge(Lo, FieldLo);
2055 Hi = merge(Hi, FieldHi);
2056 if (Lo == Memory || Hi == Memory) {
2057 postMerge(Size, Lo, Hi);
2058 return;
2059 }
2060 }
2061 }
2062
2063 // Classify the fields one at a time, merging the results.
2064 unsigned idx = 0;
2065 bool UseClang11Compat = getContext().getLangOpts().getClangABICompat() <=
2067 getContext().getTargetInfo().getTriple().isPS();
2068 bool IsUnion = RT->isUnionType() && !UseClang11Compat;
2069
2070 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2071 i != e; ++i, ++idx) {
2072 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2073 bool BitField = i->isBitField();
2074
2075 // Ignore padding bit-fields.
2076 if (BitField && i->isUnnamedBitfield())
2077 continue;
2078
2079 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2080 // eight eightbytes, or it contains unaligned fields, it has class MEMORY.
2081 //
2082 // The only case a 256-bit or a 512-bit wide vector could be used is when
2083 // the struct contains a single 256-bit or 512-bit element. Early check
2084 // and fallback to memory.
2085 //
2086 // FIXME: Extended the Lo and Hi logic properly to work for size wider
2087 // than 128.
2088 if (Size > 128 &&
2089 ((!IsUnion && Size != getContext().getTypeSize(i->getType())) ||
2090 Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2091 Lo = Memory;
2092 postMerge(Size, Lo, Hi);
2093 return;
2094 }
2095 // Note, skip this test for bit-fields, see below.
2096 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2097 Lo = Memory;
2098 postMerge(Size, Lo, Hi);
2099 return;
2100 }
2101
2102 // Classify this field.
2103 //
2104 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2105 // exceeds a single eightbyte, each is classified
2106 // separately. Each eightbyte gets initialized to class
2107 // NO_CLASS.
2108 Class FieldLo, FieldHi;
2109
2110 // Bit-fields require special handling, they do not force the
2111 // structure to be passed in memory even if unaligned, and
2112 // therefore they can straddle an eightbyte.
2113 if (BitField) {
2114 assert(!i->isUnnamedBitfield());
2115 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2116 uint64_t Size = i->getBitWidthValue(getContext());
2117
2118 uint64_t EB_Lo = Offset / 64;
2119 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2120
2121 if (EB_Lo) {
2122 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2123 FieldLo = NoClass;
2124 FieldHi = Integer;
2125 } else {
2126 FieldLo = Integer;
2127 FieldHi = EB_Hi ? Integer : NoClass;
2128 }
2129 } else
2130 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2131 Lo = merge(Lo, FieldLo);
2132 Hi = merge(Hi, FieldHi);
2133 if (Lo == Memory || Hi == Memory)
2134 break;
2135 }
2136
2137 postMerge(Size, Lo, Hi);
2138 }
2139}
2140
2141ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2142 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2143 // place naturally.
2144 if (!isAggregateTypeForABI(Ty)) {
2145 // Treat an enum type as its underlying type.
2146 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2147 Ty = EnumTy->getDecl()->getIntegerType();
2148
2149 if (Ty->isBitIntType())
2150 return getNaturalAlignIndirect(Ty);
2151
2152 return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
2154 }
2155
2156 return getNaturalAlignIndirect(Ty);
2157}
2158
2159bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2160 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2161 uint64_t Size = getContext().getTypeSize(VecTy);
2162 unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2163 if (Size <= 64 || Size > LargestVector)
2164 return true;
2165 QualType EltTy = VecTy->getElementType();
2166 if (passInt128VectorsInMem() &&
2167 (EltTy->isSpecificBuiltinType(BuiltinType::Int128) ||
2168 EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
2169 return true;
2170 }
2171
2172 return false;
2173}
2174
2175ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2176 unsigned freeIntRegs) const {
2177 // If this is a scalar LLVM value then assume LLVM will pass it in the right
2178 // place naturally.
2179 //
2180 // This assumption is optimistic, as there could be free registers available
2181 // when we need to pass this argument in memory, and LLVM could try to pass
2182 // the argument in the free register. This does not seem to happen currently,
2183 // but this code would be much safer if we could mark the argument with
2184 // 'onstack'. See PR12193.
2185 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty) &&
2186 !Ty->isBitIntType()) {
2187 // Treat an enum type as its underlying type.
2188 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2189 Ty = EnumTy->getDecl()->getIntegerType();
2190
2191 return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
2193 }
2194
2195 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2196 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2197
2198 // Compute the byval alignment. We specify the alignment of the byval in all
2199 // cases so that the mid-level optimizer knows the alignment of the byval.
2200 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2201
2202 // Attempt to avoid passing indirect results using byval when possible. This
2203 // is important for good codegen.
2204 //
2205 // We do this by coercing the value into a scalar type which the backend can
2206 // handle naturally (i.e., without using byval).
2207 //
2208 // For simplicity, we currently only do this when we have exhausted all of the
2209 // free integer registers. Doing this when there are free integer registers
2210 // would require more care, as we would have to ensure that the coerced value
2211 // did not claim the unused register. That would require either reording the
2212 // arguments to the function (so that any subsequent inreg values came first),
2213 // or only doing this optimization when there were no following arguments that
2214 // might be inreg.
2215 //
2216 // We currently expect it to be rare (particularly in well written code) for
2217 // arguments to be passed on the stack when there are still free integer
2218 // registers available (this would typically imply large structs being passed
2219 // by value), so this seems like a fair tradeoff for now.
2220 //
2221 // We can revisit this if the backend grows support for 'onstack' parameter
2222 // attributes. See PR12193.
2223 if (freeIntRegs == 0) {
2224 uint64_t Size = getContext().getTypeSize(Ty);
2225
2226 // If this type fits in an eightbyte, coerce it into the matching integral
2227 // type, which will end up on the stack (with alignment 8).
2228 if (Align == 8 && Size <= 64)
2229 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2230 Size));
2231 }
2232
2234}
2235
2236/// The ABI specifies that a value should be passed in a full vector XMM/YMM
2237/// register. Pick an LLVM IR type that will be passed as a vector register.
2238llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2239 // Wrapper structs/arrays that only contain vectors are passed just like
2240 // vectors; strip them off if present.
2241 if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2242 Ty = QualType(InnerTy, 0);
2243
2244 llvm::Type *IRType = CGT.ConvertType(Ty);
2245 if (isa<llvm::VectorType>(IRType)) {
2246 // Don't pass vXi128 vectors in their native type, the backend can't
2247 // legalize them.
2248 if (passInt128VectorsInMem() &&
2249 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy(128)) {
2250 // Use a vXi64 vector.
2251 uint64_t Size = getContext().getTypeSize(Ty);
2252 return llvm::FixedVectorType::get(llvm::Type::getInt64Ty(getVMContext()),
2253 Size / 64);
2254 }
2255
2256 return IRType;
2257 }
2258
2259 if (IRType->getTypeID() == llvm::Type::FP128TyID)
2260 return IRType;
2261
2262 // We couldn't find the preferred IR vector type for 'Ty'.
2263 uint64_t Size = getContext().getTypeSize(Ty);
2264 assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2265
2266
2267 // Return a LLVM IR vector type based on the size of 'Ty'.
2268 return llvm::FixedVectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2269 Size / 64);
2270}
2271
2272/// BitsContainNoUserData - Return true if the specified [start,end) bit range
2273/// is known to either be off the end of the specified type or being in
2274/// alignment padding. The user type specified is known to be at most 128 bits
2275/// in size, and have passed through X86_64ABIInfo::classify with a successful
2276/// classification that put one of the two halves in the INTEGER class.
2277///
2278/// It is conservatively correct to return false.
2279static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2280 unsigned EndBit, ASTContext &Context) {
2281 // If the bytes being queried are off the end of the type, there is no user
2282 // data hiding here. This handles analysis of builtins, vectors and other
2283 // types that don't contain interesting padding.
2284 unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2285 if (TySize <= StartBit)
2286 return true;
2287
2288 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2289 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2290 unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2291
2292 // Check each element to see if the element overlaps with the queried range.
2293 for (unsigned i = 0; i != NumElts; ++i) {
2294 // If the element is after the span we care about, then we're done..
2295 unsigned EltOffset = i*EltSize;
2296 if (EltOffset >= EndBit) break;
2297
2298 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2299 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2300 EndBit-EltOffset, Context))
2301 return false;
2302 }
2303 // If it overlaps no elements, then it is safe to process as padding.
2304 return true;
2305 }
2306
2307 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2308 const RecordDecl *RD = RT->getDecl();
2309 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2310
2311 // If this is a C++ record, check the bases first.
2312 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2313 for (const auto &I : CXXRD->bases()) {
2314 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2315 "Unexpected base class!");
2316 const auto *Base =
2317 cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
2318
2319 // If the base is after the span we care about, ignore it.
2320 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2321 if (BaseOffset >= EndBit) continue;
2322
2323 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2324 if (!BitsContainNoUserData(I.getType(), BaseStart,
2325 EndBit-BaseOffset, Context))
2326 return false;
2327 }
2328 }
2329
2330 // Verify that no field has data that overlaps the region of interest. Yes
2331 // this could be sped up a lot by being smarter about queried fields,
2332 // however we're only looking at structs up to 16 bytes, so we don't care
2333 // much.
2334 unsigned idx = 0;
2335 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2336 i != e; ++i, ++idx) {
2337 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2338
2339 // If we found a field after the region we care about, then we're done.
2340 if (FieldOffset >= EndBit) break;
2341
2342 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2343 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2344 Context))
2345 return false;
2346 }
2347
2348 // If nothing in this record overlapped the area of interest, then we're
2349 // clean.
2350 return true;
2351 }
2352
2353 return false;
2354}
2355
2356/// getFPTypeAtOffset - Return a floating point type at the specified offset.
2357static llvm::Type *getFPTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2358 const llvm::DataLayout &TD) {
2359 if (IROffset == 0 && IRType->isFloatingPointTy())
2360 return IRType;
2361
2362 // If this is a struct, recurse into the field at the specified offset.
2363 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2364 if (!STy->getNumContainedTypes())
2365 return nullptr;
2366
2367 const llvm::StructLayout *SL = TD.getStructLayout(STy);
2368 unsigned Elt = SL->getElementContainingOffset(IROffset);
2369 IROffset -= SL->getElementOffset(Elt);
2370 return getFPTypeAtOffset(STy->getElementType(Elt), IROffset, TD);
2371 }
2372
2373 // If this is an array, recurse into the field at the specified offset.
2374 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2375 llvm::Type *EltTy = ATy->getElementType();
2376 unsigned EltSize = TD.getTypeAllocSize(EltTy);
2377 IROffset -= IROffset / EltSize * EltSize;
2378 return getFPTypeAtOffset(EltTy, IROffset, TD);
2379 }
2380
2381 return nullptr;
2382}
2383
2384/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2385/// low 8 bytes of an XMM register, corresponding to the SSE class.
2386llvm::Type *X86_64ABIInfo::
2387GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2388 QualType SourceTy, unsigned SourceOffset) const {
2389 const llvm::DataLayout &TD = getDataLayout();
2390 unsigned SourceSize =
2391 (unsigned)getContext().getTypeSize(SourceTy) / 8 - SourceOffset;
2392 llvm::Type *T0 = getFPTypeAtOffset(IRType, IROffset, TD);
2393 if (!T0 || T0->isDoubleTy())
2394 return llvm::Type::getDoubleTy(getVMContext());
2395
2396 // Get the adjacent FP type.
2397 llvm::Type *T1 = nullptr;
2398 unsigned T0Size = TD.getTypeAllocSize(T0);
2399 if (SourceSize > T0Size)
2400 T1 = getFPTypeAtOffset(IRType, IROffset + T0Size, TD);
2401 if (T1 == nullptr) {
2402 // Check if IRType is a half/bfloat + float. float type will be in IROffset+4 due
2403 // to its alignment.
2404 if (T0->is16bitFPTy() && SourceSize > 4)
2405 T1 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
2406 // If we can't get a second FP type, return a simple half or float.
2407 // avx512fp16-abi.c:pr51813_2 shows it works to return float for
2408 // {float, i8} too.
2409 if (T1 == nullptr)
2410 return T0;
2411 }
2412
2413 if (T0->isFloatTy() && T1->isFloatTy())
2414 return llvm::FixedVectorType::get(T0, 2);
2415
2416 if (T0->is16bitFPTy() && T1->is16bitFPTy()) {
2417 llvm::Type *T2 = nullptr;
2418 if (SourceSize > 4)
2419 T2 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
2420 if (T2 == nullptr)
2421 return llvm::FixedVectorType::get(T0, 2);
2422 return llvm::FixedVectorType::get(T0, 4);
2423 }
2424
2425 if (T0->is16bitFPTy() || T1->is16bitFPTy())
2426 return llvm::FixedVectorType::get(llvm::Type::getHalfTy(getVMContext()), 4);
2427
2428 return llvm::Type::getDoubleTy(getVMContext());
2429}
2430
2431
2432/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2433/// an 8-byte GPR. This means that we either have a scalar or we are talking
2434/// about the high or low part of an up-to-16-byte struct. This routine picks
2435/// the best LLVM IR type to represent this, which may be i64 or may be anything
2436/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
2437/// etc).
2438///
2439/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
2440/// the source type. IROffset is an offset in bytes into the LLVM IR type that
2441/// the 8-byte value references. PrefType may be null.
2442///
2443/// SourceTy is the source-level type for the entire argument. SourceOffset is
2444/// an offset into this that we're processing (which is always either 0 or 8).
2445///
2446llvm::Type *X86_64ABIInfo::
2447GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2448 QualType SourceTy, unsigned SourceOffset) const {
2449 // If we're dealing with an un-offset LLVM IR type, then it means that we're
2450 // returning an 8-byte unit starting with it. See if we can safely use it.
2451 if (IROffset == 0) {
2452 // Pointers and int64's always fill the 8-byte unit.
2453 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
2454 IRType->isIntegerTy(64))
2455 return IRType;
2456
2457 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2458 // goodness in the source type is just tail padding. This is allowed to
2459 // kick in for struct {double,int} on the int, but not on
2460 // struct{double,int,int} because we wouldn't return the second int. We
2461 // have to do this analysis on the source type because we can't depend on
2462 // unions being lowered a specific way etc.
2463 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2464 IRType->isIntegerTy(32) ||
2465 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
2466 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
2467 cast<llvm::IntegerType>(IRType)->getBitWidth();
2468
2469 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
2470 SourceOffset*8+64, getContext()))
2471 return IRType;
2472 }
2473 }
2474
2475 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2476 // If this is a struct, recurse into the field at the specified offset.
2477 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
2478 if (IROffset < SL->getSizeInBytes()) {
2479 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2480 IROffset -= SL->getElementOffset(FieldIdx);
2481
2482 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2483 SourceTy, SourceOffset);
2484 }
2485 }
2486
2487 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2488 llvm::Type *EltTy = ATy->getElementType();
2489 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
2490 unsigned EltOffset = IROffset/EltSize*EltSize;
2491 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2492 SourceOffset);
2493 }
2494
2495 // Okay, we don't have any better idea of what to pass, so we pass this in an
2496 // integer register that isn't too big to fit the rest of the struct.
2497 unsigned TySizeInBytes =
2498 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
2499
2500 assert(TySizeInBytes != SourceOffset && "Empty field?");
2501
2502 // It is always safe to classify this as an integer type up to i64 that
2503 // isn't larger than the structure.
2504 return llvm::IntegerType::get(getVMContext(),
2505 std::min(TySizeInBytes-SourceOffset, 8U)*8);
2506}
2507
2508
2509/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2510/// be used as elements of a two register pair to pass or return, return a
2511/// first class aggregate to represent them. For example, if the low part of
2512/// a by-value argument should be passed as i32* and the high part as float,
2513/// return {i32*, float}.
2514static llvm::Type *
2515GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
2516 const llvm::DataLayout &TD) {
2517 // In order to correctly satisfy the ABI, we need to the high part to start
2518 // at offset 8. If the high and low parts we inferred are both 4-byte types
2519 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
2520 // the second element at offset 8. Check for this:
2521 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
2522 llvm::Align HiAlign = TD.getABITypeAlign(Hi);
2523 unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
2524 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2525
2526 // To handle this, we have to increase the size of the low part so that the
2527 // second element will start at an 8 byte offset. We can't increase the size
2528 // of the second element because it might make us access off the end of the
2529 // struct.
2530 if (HiStart != 8) {
2531 // There are usually two sorts of types the ABI generation code can produce
2532 // for the low part of a pair that aren't 8 bytes in size: half, float or
2533 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
2534 // NaCl).
2535 // Promote these to a larger type.
2536 if (Lo->isHalfTy() || Lo->isFloatTy())
2537 Lo = llvm::Type::getDoubleTy(Lo->getContext());
2538 else {
2539 assert((Lo->isIntegerTy() || Lo->isPointerTy())
2540 && "Invalid/unknown lo type");
2541 Lo = llvm::Type::getInt64Ty(Lo->getContext());
2542 }
2543 }
2544
2545 llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
2546
2547 // Verify that the second element is at an 8-byte offset.
2548 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2549 "Invalid x86-64 argument pair!");
2550 return Result;
2551}
2552
2553ABIArgInfo X86_64ABIInfo::
2554classifyReturnType(QualType RetTy) const {
2555 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2556 // classification algorithm.
2557 X86_64ABIInfo::Class Lo, Hi;
2558 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2559
2560 // Check some invariants.
2561 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2562 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2563
2564 llvm::Type *ResType = nullptr;
2565 switch (Lo) {
2566 case NoClass:
2567 if (Hi == NoClass)
2568 return ABIArgInfo::getIgnore();
2569 // If the low part is just padding, it takes no register, leave ResType
2570 // null.
2571 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2572 "Unknown missing lo part");
2573 break;
2574
2575 case SSEUp:
2576 case X87Up:
2577 llvm_unreachable("Invalid classification for lo word.");
2578
2579 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
2580 // hidden argument.
2581 case Memory:
2582 return getIndirectReturnResult(RetTy);
2583
2584 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
2585 // available register of the sequence %rax, %rdx is used.
2586 case Integer:
2587 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2588
2589 // If we have a sign or zero extended integer, make sure to return Extend
2590 // so that the parameter gets the right LLVM IR attributes.
2591 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2592 // Treat an enum type as its underlying type.
2593 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
2594 RetTy = EnumTy->getDecl()->getIntegerType();
2595
2596 if (RetTy->isIntegralOrEnumerationType() &&
2597 isPromotableIntegerTypeForABI(RetTy))
2598 return ABIArgInfo::getExtend(RetTy);
2599 }
2600 break;
2601
2602 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2603 // available SSE register of the sequence %xmm0, %xmm1 is used.
2604 case SSE:
2605 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
2606 break;
2607
2608 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
2609 // returned on the X87 stack in %st0 as 80-bit x87 number.
2610 case X87:
2611 ResType = llvm::Type::getX86_FP80Ty(getVMContext());
2612 break;
2613
2614 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
2615 // part of the value is returned in %st0 and the imaginary part in
2616 // %st1.
2617 case ComplexX87:
2618 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
2619 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
2620 llvm::Type::getX86_FP80Ty(getVMContext()));
2621 break;
2622 }
2623
2624 llvm::Type *HighPart = nullptr;
2625 switch (Hi) {
2626 // Memory was handled previously and X87 should
2627 // never occur as a hi class.
2628 case Memory:
2629 case X87:
2630 llvm_unreachable("Invalid classification for hi word.");
2631
2632 case ComplexX87: // Previously handled.
2633 case NoClass:
2634 break;
2635
2636 case Integer:
2637 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2638 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2639 return ABIArgInfo::getDirect(HighPart, 8);
2640 break;
2641 case SSE:
2642 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2643 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2644 return ABIArgInfo::getDirect(HighPart, 8);
2645 break;
2646
2647 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
2648 // is passed in the next available eightbyte chunk if the last used
2649 // vector register.
2650 //
2651 // SSEUP should always be preceded by SSE, just widen.
2652 case SSEUp:
2653 assert(Lo == SSE && "Unexpected SSEUp classification.");
2654 ResType = GetByteVectorType(RetTy);
2655 break;
2656
2657 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
2658 // returned together with the previous X87 value in %st0.
2659 case X87Up:
2660 // If X87Up is preceded by X87, we don't need to do
2661 // anything. However, in some cases with unions it may not be
2662 // preceded by X87. In such situations we follow gcc and pass the
2663 // extra bits in an SSE reg.
2664 if (Lo != X87) {
2665 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
2666 if (Lo == NoClass) // Return HighPart at offset 8 in memory.
2667 return ABIArgInfo::getDirect(HighPart, 8);
2668 }
2669 break;
2670 }
2671
2672 // If a high part was specified, merge it together with the low part. It is
2673 // known to pass in the high eightbyte of the result. We do this by forming a
2674 // first class struct aggregate with the high and low part: {low, high}
2675 if (HighPart)
2676 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2677
2678 return ABIArgInfo::getDirect(ResType);
2679}
2680
2682X86_64ABIInfo::classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2683 unsigned &neededInt, unsigned &neededSSE,
2684 bool isNamedArg, bool IsRegCall) const {
2686
2687 X86_64ABIInfo::Class Lo, Hi;
2688 classify(Ty, 0, Lo, Hi, isNamedArg, IsRegCall);
2689
2690 // Check some invariants.
2691 // FIXME: Enforce these by construction.
2692 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2693 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2694
2695 neededInt = 0;
2696 neededSSE = 0;
2697 llvm::Type *ResType = nullptr;
2698 switch (Lo) {
2699 case NoClass:
2700 if (Hi == NoClass)
2701 return ABIArgInfo::getIgnore();
2702 // If the low part is just padding, it takes no register, leave ResType
2703 // null.
2704 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2705 "Unknown missing lo part");
2706 break;
2707
2708 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
2709 // on the stack.
2710 case Memory:
2711
2712 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
2713 // COMPLEX_X87, it is passed in memory.
2714 case X87:
2715 case ComplexX87:
2716 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
2717 ++neededInt;
2718 return getIndirectResult(Ty, freeIntRegs);
2719
2720 case SSEUp:
2721 case X87Up:
2722 llvm_unreachable("Invalid classification for lo word.");
2723
2724 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
2725 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
2726 // and %r9 is used.
2727 case Integer:
2728 ++neededInt;
2729
2730 // Pick an 8-byte type based on the preferred type.
2731 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
2732
2733 // If we have a sign or zero extended integer, make sure to return Extend
2734 // so that the parameter gets the right LLVM IR attributes.
2735 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2736 // Treat an enum type as its underlying type.
2737 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2738 Ty = EnumTy->getDecl()->getIntegerType();
2739
2740 if (Ty->isIntegralOrEnumerationType() &&
2741 isPromotableIntegerTypeForABI(Ty))
2742 return ABIArgInfo::getExtend(Ty);
2743 }
2744
2745 break;
2746
2747 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2748 // available SSE register is used, the registers are taken in the
2749 // order from %xmm0 to %xmm7.
2750 case SSE: {
2751 llvm::Type *IRType = CGT.ConvertType(Ty);
2752 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
2753 ++neededSSE;
2754 break;
2755 }
2756 }
2757
2758 llvm::Type *HighPart = nullptr;
2759 switch (Hi) {
2760 // Memory was handled previously, ComplexX87 and X87 should
2761 // never occur as hi classes, and X87Up must be preceded by X87,
2762 // which is passed in memory.
2763 case Memory:
2764 case X87:
2765 case ComplexX87:
2766 llvm_unreachable("Invalid classification for hi word.");
2767
2768 case NoClass: break;
2769
2770 case Integer:
2771 ++neededInt;
2772 // Pick an 8-byte type based on the preferred type.
2773 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2774
2775 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2776 return ABIArgInfo::getDirect(HighPart, 8);
2777 break;
2778
2779 // X87Up generally doesn't occur here (long double is passed in
2780 // memory), except in situations involving unions.
2781 case X87Up:
2782 case SSE:
2783 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
2784
2785 if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
2786 return ABIArgInfo::getDirect(HighPart, 8);
2787
2788 ++neededSSE;
2789 break;
2790
2791 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
2792 // eightbyte is passed in the upper half of the last used SSE
2793 // register. This only happens when 128-bit vectors are passed.
2794 case SSEUp:
2795 assert(Lo == SSE && "Unexpected SSEUp classification");
2796 ResType = GetByteVectorType(Ty);
2797 break;
2798 }
2799
2800 // If a high part was specified, merge it together with the low part. It is
2801 // known to pass in the high eightbyte of the result. We do this by forming a
2802 // first class struct aggregate with the high and low part: {low, high}
2803 if (HighPart)
2804 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
2805
2806 return ABIArgInfo::getDirect(ResType);
2807}
2808
2810X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2811 unsigned &NeededSSE,
2812 unsigned &MaxVectorWidth) const {
2813 auto RT = Ty->getAs<RecordType>();
2814 assert(RT && "classifyRegCallStructType only valid with struct types");
2815
2816 if (RT->getDecl()->hasFlexibleArrayMember())
2817 return getIndirectReturnResult(Ty);
2818
2819 // Sum up bases
2820 if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
2821 if (CXXRD->isDynamicClass()) {
2822 NeededInt = NeededSSE = 0;
2823 return getIndirectReturnResult(Ty);
2824 }
2825
2826 for (const auto &I : CXXRD->bases())
2827 if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE,
2828 MaxVectorWidth)
2829 .isIndirect()) {
2830 NeededInt = NeededSSE = 0;
2831 return getIndirectReturnResult(Ty);
2832 }
2833 }
2834
2835 // Sum up members
2836 for (const auto *FD : RT->getDecl()->fields()) {
2837 QualType MTy = FD->getType();
2838 if (MTy->isRecordType() && !MTy->isUnionType()) {
2839 if (classifyRegCallStructTypeImpl(MTy, NeededInt, NeededSSE,
2840 MaxVectorWidth)
2841 .isIndirect()) {
2842 NeededInt = NeededSSE = 0;
2843 return getIndirectReturnResult(Ty);
2844 }
2845 } else {
2846 unsigned LocalNeededInt, LocalNeededSSE;
2847 if (classifyArgumentType(MTy, UINT_MAX, LocalNeededInt, LocalNeededSSE,
2848 true, true)
2849 .isIndirect()) {
2850 NeededInt = NeededSSE = 0;
2851 return getIndirectReturnResult(Ty);
2852 }
2853 if (const auto *AT = getContext().getAsConstantArrayType(MTy))
2854 MTy = AT->getElementType();
2855 if (const auto *VT = MTy->getAs<VectorType>())
2856 if (getContext().getTypeSize(VT) > MaxVectorWidth)
2857 MaxVectorWidth = getContext().getTypeSize(VT);
2858 NeededInt += LocalNeededInt;
2859 NeededSSE += LocalNeededSSE;
2860 }
2861 }
2862
2863 return ABIArgInfo::getDirect();
2864}
2865
2867X86_64ABIInfo::classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2868 unsigned &NeededSSE,
2869 unsigned &MaxVectorWidth) const {
2870
2871 NeededInt = 0;
2872 NeededSSE = 0;
2873 MaxVectorWidth = 0;
2874
2875 return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE,
2876 MaxVectorWidth);
2877}
2878
2879void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
2880
2881 const unsigned CallingConv = FI.getCallingConvention();
2882 // It is possible to force Win64 calling convention on any x86_64 target by
2883 // using __attribute__((ms_abi)). In such case to correctly emit Win64
2884 // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
2885 if (CallingConv == llvm::CallingConv::Win64) {
2886 WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
2887 Win64ABIInfo.computeInfo(FI);
2888 return;
2889 }
2890
2891 bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
2892
2893 // Keep track of the number of assigned registers.
2894 unsigned FreeIntRegs = IsRegCall ? 11 : 6;
2895 unsigned FreeSSERegs = IsRegCall ? 16 : 8;
2896 unsigned NeededInt = 0, NeededSSE = 0, MaxVectorWidth = 0;
2897
2898 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
2899 if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
2900 !FI.getReturnType()->getTypePtr()->isUnionType()) {
2901 FI.getReturnInfo() = classifyRegCallStructType(
2902 FI.getReturnType(), NeededInt, NeededSSE, MaxVectorWidth);
2903 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
2904 FreeIntRegs -= NeededInt;
2905 FreeSSERegs -= NeededSSE;
2906 } else {
2907 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
2908 }
2909 } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>() &&
2910 getContext().getCanonicalType(FI.getReturnType()
2911 ->getAs<ComplexType>()
2912 ->getElementType()) ==
2913 getContext().LongDoubleTy)
2914 // Complex Long Double Type is passed in Memory when Regcall
2915 // calling convention is used.
2916 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
2917 else
2919 }
2920
2921 // If the return value is indirect, then the hidden argument is consuming one
2922 // integer register.
2923 if (FI.getReturnInfo().isIndirect())
2924 --FreeIntRegs;
2925 else if (NeededSSE && MaxVectorWidth > 0)
2926 FI.setMaxVectorWidth(MaxVectorWidth);
2927
2928 // The chain argument effectively gives us another free register.
2929 if (FI.isChainCall())
2930 ++FreeIntRegs;
2931
2932 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
2933 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
2934 // get assigned (in left-to-right order) for passing as follows...
2935 unsigned ArgNo = 0;
2936 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
2937 it != ie; ++it, ++ArgNo) {
2938 bool IsNamedArg = ArgNo < NumRequiredArgs;
2939
2940 if (IsRegCall && it->type->isStructureOrClassType())
2941 it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE,
2942 MaxVectorWidth);
2943 else
2944 it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
2945 NeededSSE, IsNamedArg);
2946
2947 // AMD64-ABI 3.2.3p3: If there are no registers available for any
2948 // eightbyte of an argument, the whole argument is passed on the
2949 // stack. If registers have already been assigned for some
2950 // eightbytes of such an argument, the assignments get reverted.
2951 if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
2952 FreeIntRegs -= NeededInt;
2953 FreeSSERegs -= NeededSSE;
2954 if (MaxVectorWidth > FI.getMaxVectorWidth())
2955 FI.setMaxVectorWidth(MaxVectorWidth);
2956 } else {
2957 it->info = getIndirectResult(it->type, FreeIntRegs);
2958 }
2959 }
2960}
2961
2963 Address VAListAddr, QualType Ty) {
2964 Address overflow_arg_area_p =
2965 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
2966 llvm::Value *overflow_arg_area =
2967 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
2968
2969 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
2970 // byte boundary if alignment needed by type exceeds 8 byte boundary.
2971 // It isn't stated explicitly in the standard, but in practice we use
2972 // alignment greater than 16 where necessary.
2973 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
2974 if (Align > CharUnits::fromQuantity(8)) {
2975 overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
2976 Align);
2977 }
2978
2979 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
2980 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
2981 llvm::Value *Res = overflow_arg_area;
2982
2983 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
2984 // l->overflow_arg_area + sizeof(type).
2985 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
2986 // an 8 byte boundary.
2987
2988 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
2989 llvm::Value *Offset =
2990 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
2991 overflow_arg_area = CGF.Builder.CreateGEP(CGF.Int8Ty, overflow_arg_area,
2992 Offset, "overflow_arg_area.next");
2993 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
2994
2995 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
2996 return Address(Res, LTy, Align);
2997}
2998
2999Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3000 QualType Ty) const {
3001 // Assume that va_list type is correct; should be pointer to LLVM type:
3002 // struct {
3003 // i32 gp_offset;
3004 // i32 fp_offset;
3005 // i8* overflow_arg_area;
3006 // i8* reg_save_area;
3007 // };
3008 unsigned neededInt, neededSSE;
3009
3010 Ty = getContext().getCanonicalType(Ty);
3011 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3012 /*isNamedArg*/false);
3013
3014 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3015 // in the registers. If not go to step 7.
3016 if (!neededInt && !neededSSE)
3017 return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3018
3019 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3020 // general purpose registers needed to pass type and num_fp to hold
3021 // the number of floating point registers needed.
3022
3023 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3024 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3025 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3026 //
3027 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3028 // register save space).
3029
3030 llvm::Value *InRegs = nullptr;
3031 Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3032 llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3033 if (neededInt) {
3034 gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
3035 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3036 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3037 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3038 }
3039
3040 if (neededSSE) {
3041 fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
3042 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3043 llvm::Value *FitsInFP =
3044 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3045 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3046 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3047 }
3048
3049 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3050 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3051 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3052 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3053
3054 // Emit code to load the value if it was passed in registers.
3055
3056 CGF.EmitBlock(InRegBlock);
3057
3058 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3059 // an offset of l->gp_offset and/or l->fp_offset. This may require
3060 // copying to a temporary location in case the parameter is passed
3061 // in different register classes or requires an alignment greater
3062 // than 8 for general purpose registers and 16 for XMM registers.
3063 //
3064 // FIXME: This really results in shameful code when we end up needing to
3065 // collect arguments from different places; often what should result in a
3066 // simple assembling of a structure from scattered addresses has many more
3067 // loads than necessary. Can we clean this up?
3068 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3069 llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3070 CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
3071
3072 Address RegAddr = Address::invalid();
3073 if (neededInt && neededSSE) {
3074 // FIXME: Cleanup.
3075 assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3076 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3077 Address Tmp = CGF.CreateMemTemp(Ty);
3078 Tmp = Tmp.withElementType(ST);
3079 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3080 llvm::Type *TyLo = ST->getElementType(0);
3081 llvm::Type *TyHi = ST->getElementType(1);
3082 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3083 "Unexpected ABI info for mixed regs");
3084 llvm::Value *GPAddr =
3085 CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset);
3086 llvm::Value *FPAddr =
3087 CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset);
3088 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3089 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3090
3091 // Copy the first element.
3092 // FIXME: Our choice of alignment here and below is probably pessimistic.
3093 llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3094 TyLo, RegLoAddr,
3095 CharUnits::fromQuantity(getDataLayout().getABITypeAlign(TyLo)));
3096 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3097
3098 // Copy the second element.
3100 TyHi, RegHiAddr,
3101 CharUnits::fromQuantity(getDataLayout().getABITypeAlign(TyHi)));
3102 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3103
3104 RegAddr = Tmp.withElementType(LTy);
3105 } else if (neededInt) {
3106 RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset),
3107 LTy, CharUnits::fromQuantity(8));
3108
3109 // Copy to a temporary if necessary to ensure the appropriate alignment.
3110 auto TInfo = getContext().getTypeInfoInChars(Ty);
3111 uint64_t TySize = TInfo.Width.getQuantity();
3112 CharUnits TyAlign = TInfo.Align;
3113
3114 // Copy into a temporary if the type is more aligned than the
3115 // register save area.
3116 if (TyAlign.getQuantity() > 8) {
3117 Address Tmp = CGF.CreateMemTemp(Ty);
3118 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3119 RegAddr = Tmp;
3120 }
3121
3122 } else if (neededSSE == 1) {
3123 RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset),
3124 LTy, CharUnits::fromQuantity(16));
3125 } else {
3126 assert(neededSSE == 2 && "Invalid number of needed registers!");
3127 // SSE registers are spaced 16 bytes apart in the register save
3128 // area, we need to collect the two eightbytes together.
3129 // The ABI isn't explicit about this, but it seems reasonable
3130 // to assume that the slots are 16-byte aligned, since the stack is
3131 // naturally 16-byte aligned and the prologue is expected to store
3132 // all the SSE registers to the RSA.
3133 Address RegAddrLo = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea,
3134 fp_offset),
3136 Address RegAddrHi =
3137 CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3139 llvm::Type *ST = AI.canHaveCoerceToType()
3140 ? AI.getCoerceToType()
3141 : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3142 llvm::Value *V;
3143 Address Tmp = CGF.CreateMemTemp(Ty);
3144 Tmp = Tmp.withElementType(ST);
3145 V = CGF.Builder.CreateLoad(
3146 RegAddrLo.withElementType(ST->getStructElementType(0)));
3147 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3148 V = CGF.Builder.CreateLoad(
3149 RegAddrHi.withElementType(ST->getStructElementType(1)));
3150 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3151
3152 RegAddr = Tmp.withElementType(LTy);
3153 }
3154
3155 // AMD64-ABI 3.5.7p5: Step 5. Set:
3156 // l->gp_offset = l->gp_offset + num_gp * 8
3157 // l->fp_offset = l->fp_offset + num_fp * 16.
3158 if (neededInt) {
3159 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3160 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3161 gp_offset_p);
3162 }
3163 if (neededSSE) {
3164 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3165 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3166 fp_offset_p);
3167 }
3168 CGF.EmitBranch(ContBlock);
3169
3170 // Emit code to load the value if it was passed in memory.
3171
3172 CGF.EmitBlock(InMemBlock);
3173 Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3174
3175 // Return the appropriate result.
3176
3177 CGF.EmitBlock(ContBlock);
3178 Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3179 "vaarg.addr");
3180 return ResAddr;
3181}
3182
3183Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3184 QualType Ty) const {
3185 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3186 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3187 uint64_t Width = getContext().getTypeSize(Ty);
3188 bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
3189
3190 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
3193 /*allowHigherAlign*/ false);
3194}
3195
3196ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
3197 QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo &current) const {
3198 const Type *Base = nullptr;
3199 uint64_t NumElts = 0;
3200
3201 if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3202 isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3203 FreeSSERegs -= NumElts;
3204 return getDirectX86Hva();
3205 }
3206 return current;
3207}
3208
3209ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3210 bool IsReturnType, bool IsVectorCall,
3211 bool IsRegCall) const {
3212
3213 if (Ty->isVoidType())
3214 return ABIArgInfo::getIgnore();
3215
3216 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3217 Ty = EnumTy->getDecl()->getIntegerType();
3218
3219 TypeInfo Info = getContext().getTypeInfo(Ty);
3220 uint64_t Width = Info.Width;
3221 CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3222
3223 const RecordType *RT = Ty->getAs<RecordType>();
3224 if (RT) {
3225 if (!IsReturnType) {
3226 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3227 return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3228 }
3229
3230 if (RT->getDecl()->hasFlexibleArrayMember())
3231 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3232
3233 }
3234
3235 const Type *Base = nullptr;
3236 uint64_t NumElts = 0;
3237 // vectorcall adds the concept of a homogenous vector aggregate, similar to
3238 // other targets.
3239 if ((IsVectorCall || IsRegCall) &&
3240 isHomogeneousAggregate(Ty, Base, NumElts)) {
3241 if (IsRegCall) {
3242 if (FreeSSERegs >= NumElts) {
3243 FreeSSERegs -= NumElts;
3244 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3245 return ABIArgInfo::getDirect();
3246 return ABIArgInfo::getExpand();
3247 }
3248 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3249 } else if (IsVectorCall) {
3250 if (FreeSSERegs >= NumElts &&
3251 (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3252 FreeSSERegs -= NumElts;
3253 return ABIArgInfo::getDirect();
3254 } else if (IsReturnType) {
3255 return ABIArgInfo::getExpand();
3256 } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3257 // HVAs are delayed and reclassified in the 2nd step.
3258 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3259 }
3260 }
3261 }
3262
3263 if (Ty->isMemberPointerType()) {
3264 // If the member pointer is represented by an LLVM int or ptr, pass it
3265 // directly.
3266 llvm::Type *LLTy = CGT.ConvertType(Ty);
3267 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3268 return ABIArgInfo::getDirect();
3269 }
3270
3271 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3272 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3273 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3274 if (Width > 64 || !llvm::isPowerOf2_64(Width))
3275 return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3276
3277 // Otherwise, coerce it to a small integer.
3278 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3279 }
3280
3281 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3282 switch (BT->getKind()) {
3283 case BuiltinType::Bool:
3284 // Bool type is always extended to the ABI, other builtin types are not
3285 // extended.
3286 return ABIArgInfo::getExtend(Ty);
3287
3288 case BuiltinType::LongDouble:
3289 // Mingw64 GCC uses the old 80 bit extended precision floating point
3290 // unit. It passes them indirectly through memory.
3291 if (IsMingw64) {
3292 const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3293 if (LDF == &llvm::APFloat::x87DoubleExtended())
3294 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3295 }
3296 break;
3297
3298 case BuiltinType::Int128:
3299 case BuiltinType::UInt128:
3300 // If it's a parameter type, the normal ABI rule is that arguments larger
3301 // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
3302 // even though it isn't particularly efficient.
3303 if (!IsReturnType)
3304 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3305
3306 // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
3307 // Clang matches them for compatibility.
3308 return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
3309 llvm::Type::getInt64Ty(getVMContext()), 2));
3310
3311 default:
3312 break;
3313 }
3314 }
3315
3316 if (Ty->isBitIntType()) {
3317 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3318 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3319 // However, non-power-of-two bit-precise integers will be passed as 1, 2, 4,
3320 // or 8 bytes anyway as long is it fits in them, so we don't have to check
3321 // the power of 2.
3322 if (Width <= 64)
3323 return ABIArgInfo::getDirect();
3324 return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3325 }
3326
3327 return ABIArgInfo::getDirect();
3328}
3329
3330void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3331 const unsigned CC = FI.getCallingConvention();
3332 bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
3333 bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
3334
3335 // If __attribute__((sysv_abi)) is in use, use the SysV argument
3336 // classification rules.
3337 if (CC == llvm::CallingConv::X86_64_SysV) {
3338 X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
3339 SysVABIInfo.computeInfo(FI);
3340 return;
3341 }
3342
3343 unsigned FreeSSERegs = 0;
3344 if (IsVectorCall) {
3345 // We can use up to 4 SSE return registers with vectorcall.
3346 FreeSSERegs = 4;
3347 } else if (IsRegCall) {
3348 // RegCall gives us 16 SSE registers.
3349 FreeSSERegs = 16;
3350 }
3351
3352 if (!getCXXABI().classifyReturnType(FI))
3353 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3354 IsVectorCall, IsRegCall);
3355
3356 if (IsVectorCall) {
3357 // We can use up to 6 SSE register parameters with vectorcall.
3358 FreeSSERegs = 6;
3359 } else if (IsRegCall) {
3360 // RegCall gives us 16 SSE registers, we can reuse the return registers.
3361 FreeSSERegs = 16;
3362 }
3363
3364 unsigned ArgNum = 0;
3365 unsigned ZeroSSERegs = 0;
3366 for (auto &I : FI.arguments()) {
3367 // Vectorcall in x64 only permits the first 6 arguments to be passed as
3368 // XMM/YMM registers. After the sixth argument, pretend no vector
3369 // registers are left.
3370 unsigned *MaybeFreeSSERegs =
3371 (IsVectorCall && ArgNum >= 6) ? &ZeroSSERegs : &FreeSSERegs;
3372 I.info =
3373 classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
3374 ++ArgNum;
3375 }
3376
3377 if (IsVectorCall) {
3378 // For vectorcall, assign aggregate HVAs to any free vector registers in a
3379 // second pass.
3380 for (auto &I : FI.arguments())
3381 I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
3382 }
3383}
3384
3385Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3386 QualType Ty) const {
3387 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3388 // not 1, 2, 4, or 8 bytes, must be passed by reference."
3389 uint64_t Width = getContext().getTypeSize(Ty);
3390 bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
3391
3392 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
3395 /*allowHigherAlign*/ false);
3396}
3397
3398std::unique_ptr<TargetCodeGenInfo> CodeGen::createX86_32TargetCodeGenInfo(
3399 CodeGenModule &CGM, bool DarwinVectorABI, bool Win32StructABI,
3400 unsigned NumRegisterParameters, bool SoftFloatABI) {
3401 bool RetSmallStructInRegABI = X86_32TargetCodeGenInfo::isStructReturnInRegABI(
3402 CGM.getTriple(), CGM.getCodeGenOpts());
3403 return std::make_unique<X86_32TargetCodeGenInfo>(
3404 CGM.getTypes(), DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
3405 NumRegisterParameters, SoftFloatABI);
3406}
3407
3408std::unique_ptr<TargetCodeGenInfo> CodeGen::createWinX86_32TargetCodeGenInfo(
3409 CodeGenModule &CGM, bool DarwinVectorABI, bool Win32StructABI,
3410 unsigned NumRegisterParameters) {
3411 bool RetSmallStructInRegABI = X86_32TargetCodeGenInfo::isStructReturnInRegABI(
3412 CGM.getTriple(), CGM.getCodeGenOpts());
3413 return std::make_unique<WinX86_32TargetCodeGenInfo>(
3414 CGM.getTypes(), DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
3415 NumRegisterParameters);
3416}
3417
3418std::unique_ptr<TargetCodeGenInfo>
3420 X86AVXABILevel AVXLevel) {
3421 return std::make_unique<X86_64TargetCodeGenInfo>(CGM.getTypes(), AVXLevel);
3422}
3423
3424std::unique_ptr<TargetCodeGenInfo>
3426 X86AVXABILevel AVXLevel) {
3427 return std::make_unique<WinX86_64TargetCodeGenInfo>(CGM.getTypes(), AVXLevel);
3428}
#define V(N, I)
Definition: ASTContext.h:3241
static bool checkAVX512ParamFeature(DiagnosticsEngine &Diag, SourceLocation CallLoc, const llvm::StringMap< bool > &CallerMap, const llvm::StringMap< bool > &CalleeMap, QualType Ty, bool IsArgument)
Definition: X86.cpp:1515
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context)
Definition: X86.cpp:382
static void rewriteInputConstraintReferences(unsigned FirstIn, unsigned NumNewOuts, std::string &AsmString)
Rewrite input constraint references after adding some output constraints.
Definition: X86.cpp:257
static void initFeatureMaps(const ASTContext &Ctx, llvm::StringMap< bool > &CallerMap, const FunctionDecl *Caller, llvm::StringMap< bool > &CalleeMap, const FunctionDecl *Callee)
Definition: X86.cpp:1479
static llvm::Type * GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, const llvm::DataLayout &TD)
GetX86_64ByValArgumentPair - Given a high and low type that can ideally be used as elements of a two ...
Definition: X86.cpp:2515
static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx, SourceLocation CallLoc, const llvm::StringMap< bool > &CallerMap, const llvm::StringMap< bool > &CalleeMap, QualType Ty, bool IsArgument)
Definition: X86.cpp:1533
static bool checkAVXParamFeature(DiagnosticsEngine &Diag, SourceLocation CallLoc, const llvm::StringMap< bool > &CallerMap, const llvm::StringMap< bool > &CalleeMap, QualType Ty, StringRef Feature, bool IsArgument)
Definition: X86.cpp:1493
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD, uint64_t &Size)
Definition: X86.cpp:418
static llvm::Type * getFPTypeAtOffset(llvm::Type *IRType, unsigned IROffset, const llvm::DataLayout &TD)
getFPTypeAtOffset - Return a floating point type at the specified offset.
Definition: X86.cpp:2357
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD, uint64_t &Size)
Definition: X86.cpp:398
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, unsigned EndBit, ASTContext &Context)
BitsContainNoUserData - Return true if the specified [start,end) bit range is known to either be off ...
Definition: X86.cpp:2279
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, Address VAListAddr, QualType Ty)
Definition: X86.cpp:2962
static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM)
Definition: X86.cpp:1106
static bool isArgInAlloca(const ABIArgInfo &Info)
Definition: X86.cpp:997
static DiagnosticBuilder Diag(DiagnosticsEngine *Diags, const LangOptions &Features, FullSourceLoc TokLoc, const char *TokBegin, const char *TokRangeBegin, const char *TokRangeEnd, unsigned DiagID)
Produce a diagnostic highlighting some portion of a literal.
Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...
Definition: ASTContext.h:182
const ConstantArrayType * getAsConstantArrayType(QualType T) const
Definition: ASTContext.h:2728
CharUnits getTypeAlignInChars(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in characters.
const ASTRecordLayout & getASTRecordLayout(const RecordDecl *D) const
Get or compute information about the layout of the specified record (struct/union/class) D,...
TypeInfoChars getTypeInfoInChars(const Type *T) const
int64_t toBits(CharUnits CharSize) const
Convert a size in characters to a size in bits.
uint64_t getTypeSize(QualType T) const
Return the size of the specified (complete) type T, in bits.
Definition: ASTContext.h:2307
const TargetInfo & getTargetInfo() const
Definition: ASTContext.h:749
void getFunctionFeatureMap(llvm::StringMap< bool > &FeatureMap, const FunctionDecl *) const
ASTRecordLayout - This class contains layout information for one RecordDecl, which is a struct/union/...
Definition: RecordLayout.h:38
uint64_t getFieldOffset(unsigned FieldNo) const
getFieldOffset - Get the offset of the given field index, in bits.
Definition: RecordLayout.h:200
CharUnits getRequiredAlignment() const
Definition: RecordLayout.h:311
CharUnits getBaseClassOffset(const CXXRecordDecl *Base) const
getBaseClassOffset - Get the offset, in chars, for the given base class.
Definition: RecordLayout.h:249
A fixed int type of a specified bitwidth.
Definition: Type.h:6664
This class is used for builtin types like 'int'.
Definition: Type.h:2738
Represents a base class of a C++ class.
Definition: DeclCXX.h:146
Represents a C++ struct/union/class.
Definition: DeclCXX.h:258
base_class_range bases()
Definition: DeclCXX.h:618
CanProxy< U > getAs() const
Retrieve a canonical type pointer with a different static type, upcasting or downcasting as needed.
const T * getTypePtr() const
Retrieve the underlying type pointer, which refers to a canonical type.
Definition: CanonicalType.h:83
CharUnits - This is an opaque type for sizes expressed in character units.
Definition: CharUnits.h:38
QuantityType getQuantity() const
getQuantity - Get the raw integer representation of this quantity.
Definition: CharUnits.h:185
static CharUnits One()
One - Construct a CharUnits quantity of one.
Definition: CharUnits.h:58
bool isMultipleOf(CharUnits N) const
Test whether this is a multiple of the other value.
Definition: CharUnits.h:143
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition: CharUnits.h:63
CharUnits alignTo(const CharUnits &Align) const
alignTo - Returns the next integer (mod 2**64) that is greater than or equal to this quantity and is ...
Definition: CharUnits.h:201
CodeGenOptions - Track various options which control how the code is optimized and passed to the back...
ABIArgInfo - Helper class to encapsulate information about how a specific C type should be passed to ...
static ABIArgInfo getInAlloca(unsigned FieldIndex, bool Indirect=false)
static ABIArgInfo getIgnore()
static ABIArgInfo getExpand()
void setIndirectAlign(CharUnits IA)
static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T=nullptr)
static ABIArgInfo getExpandWithPadding(bool PaddingInReg, llvm::Type *Padding)
static ABIArgInfo getIndirect(CharUnits Alignment, bool ByVal=true, bool Realign=false, llvm::Type *Padding=nullptr)
static ABIArgInfo getDirect(llvm::Type *T=nullptr, unsigned Offset=0, llvm::Type *Padding=nullptr, bool CanBeFlattened=true, unsigned Align=0)
@ Extend
Extend - Valid only for integer argument types.
@ Ignore
Ignore - Ignore the argument (treat as void).
@ IndirectAliased
IndirectAliased - Similar to Indirect, but the pointer may be to an object that is otherwise referenc...
@ Expand
Expand - Only valid for aggregate argument types.
@ InAlloca
InAlloca - Pass the argument directly using the LLVM inalloca attribute.
@ Indirect
Indirect - Pass the argument indirectly via a hidden pointer with the specified alignment (0 indicate...
@ CoerceAndExpand
CoerceAndExpand - Only valid for aggregate argument types.
@ Direct
Direct - Pass the argument directly using the normal converted LLVM type, or by coercing to another s...
static ABIArgInfo getExtend(QualType Ty, llvm::Type *T=nullptr)
llvm::Type * getCoerceToType() const
static ABIArgInfo getDirectInReg(llvm::Type *T=nullptr)
ABIInfo - Target specific hooks for defining how a type should be passed or returned from functions.
Definition: ABIInfo.h:44
virtual CodeGen::Address EmitMSVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const
Emit the target dependent code to load a value of.
Definition: ABIInfo.cpp:42
ASTContext & getContext() const
Definition: ABIInfo.cpp:20
virtual bool isHomogeneousAggregateBaseType(QualType Ty) const
Definition: ABIInfo.cpp:47
virtual CodeGen::Address EmitVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const =0
EmitVAArg - Emit the target dependent code to load a value of.
virtual bool isHomogeneousAggregateSmallEnough(const Type *Base, uint64_t Members) const
Definition: ABIInfo.cpp:51
const TargetInfo & getTarget() const
Definition: ABIInfo.cpp:30
virtual void computeInfo(CodeGen::CGFunctionInfo &FI) const =0
An aligned address.
Definition: Address.h:29
static Address invalid()
Definition: Address.h:46
Address withElementType(llvm::Type *ElemTy) const
Return address with different element type, but same pointer and alignment.
Definition: Address.h:100
llvm::StoreInst * CreateStore(llvm::Value *Val, Address Addr, bool IsVolatile=false)
Definition: CGBuilder.h:97
Address CreateConstInBoundsByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Given a pointer to i8, adjust it by a given constant offset.
Definition: CGBuilder.h:259
Address CreateStructGEP(Address Addr, unsigned Index, const llvm::Twine &Name="")
Definition: CGBuilder.h:172
llvm::LoadInst * CreateLoad(Address Addr, const llvm::Twine &Name="")
Definition: CGBuilder.h:71
llvm::CallInst * CreateMemCpy(Address Dest, Address Src, llvm::Value *Size, bool IsVolatile=false)
Definition: CGBuilder.h:297
llvm::LoadInst * CreateAlignedLoad(llvm::Type *Ty, llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition: CGBuilder.h:89
Address CreateGEP(Address Addr, llvm::Value *Index, const llvm::Twine &Name="")
Definition: CGBuilder.h:246
RecordArgABI
Specify how one should pass an argument of a record type.
Definition: CGCXXABI.h:154
@ RAA_Indirect
Pass it as a pointer to temporary memory.
Definition: CGCXXABI.h:165
@ RAA_DirectInMemory
Pass it on the stack using its defined layout.
Definition: CGCXXABI.h:162
CGFunctionInfo - Class to encapsulate the information about a function definition.
unsigned getCallingConvention() const
getCallingConvention - Return the user specified calling convention, which has been translated into a...
const_arg_iterator arg_begin() const
CanQualType getReturnType() const
MutableArrayRef< ArgInfo > arguments()
const_arg_iterator arg_end() const
void setArgStruct(llvm::StructType *Ty, CharUnits Align)
unsigned getMaxVectorWidth() const
Return the maximum vector width in the arguments.
unsigned getNumRequiredArgs() const
void setMaxVectorWidth(unsigned Width)
Set the maximum vector width in the arguments.
CallArgList - Type for representing both the value and type of arguments in a call.
Definition: CGCall.h:257
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
llvm::BasicBlock * createBasicBlock(const Twine &name="", llvm::Function *parent=nullptr, llvm::BasicBlock *before=nullptr)
createBasicBlock - Create an LLVM basic block.
void EmitBlock(llvm::BasicBlock *BB, bool IsFinished=false)
EmitBlock - Emit the given block.
llvm::Type * ConvertTypeForMem(QualType T)
void EmitBranch(llvm::BasicBlock *Block)
EmitBranch - Emit a branch to the specified basic block from the current insert block,...
Address CreateMemTemp(QualType T, const Twine &Name="tmp", Address *Alloca=nullptr)
CreateMemTemp - Create a temporary memory object of the given type, with appropriate alignmen and cas...
llvm::LLVMContext & getLLVMContext()
This class organizes the cross-function state that is used while generating LLVM code.
DiagnosticsEngine & getDiags() const
const TargetInfo & getTarget() const
const llvm::Triple & getTriple() const
ASTContext & getContext() const
const CodeGenOptions & getCodeGenOpts() const
This class organizes the cross-module state that is used while lowering AST types to LLVM types.
Definition: CodeGenTypes.h:54
llvm::Type * ConvertType(QualType T)
ConvertType - Convert type T into a llvm::Type.
LValue - This represents an lvalue references.
Definition: CGValue.h:171
Address getAddress(CodeGenFunction &CGF) const
Definition: CGValue.h:350
QualType getType() const
Definition: CGValue.h:279
void setAddress(Address address)
Definition: CGValue.h:354
A class for recording the number of arguments that a function signature requires.
Target specific hooks for defining how a type should be passed or returned from functions with one of...
Definition: ABIInfo.h:118
bool occupiesMoreThan(ArrayRef< llvm::Type * > scalarTypes, unsigned maxAllRegisters) const
Does the given lowering require more than the given number of registers when expanded?
Definition: ABIInfo.cpp:203
virtual bool shouldPassIndirectly(ArrayRef< llvm::Type * > ComponentTys, bool AsReturnValue) const
Returns true if an aggregate which expands to the given type sequence should be passed / returned ind...
Definition: ABIInfo.cpp:221
TargetCodeGenInfo - This class organizes various target-specific codegeneration issues,...
Definition: TargetInfo.h:46
virtual void addReturnRegisterOutputs(CodeGen::CodeGenFunction &CGF, CodeGen::LValue ReturnValue, std::string &Constraints, std::vector< llvm::Type * > &ResultRegTypes, std::vector< llvm::Type * > &ResultTruncRegTypes, std::vector< CodeGen::LValue > &ResultRegDests, std::string &AsmString, unsigned NumOutputs) const
Adds constraints and types for result registers.
Definition: TargetInfo.h:179
virtual llvm::Type * adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, StringRef Constraint, llvm::Type *Ty) const
Corrects the low-level LLVM type for a given constraint and "usual" type.
Definition: TargetInfo.h:165
virtual StringRef getARCRetainAutoreleasedReturnValueMarker() const
Retrieve the address of a function to call immediately before calling objc_retainAutoreleasedReturnVa...
Definition: TargetInfo.h:200
virtual bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const
Initializes the given DWARF EH register-size table, a char*.
Definition: TargetInfo.h:125
virtual void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const
setTargetAttributes - Provides a convenient hook to handle extra target-specific attributes for the g...
Definition: TargetInfo.h:75
static std::string qualifyWindowsLibrary(StringRef Lib)
Definition: X86.cpp:1594
virtual int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const
Determines the DWARF register number for the stack pointer, for exception-handling purposes.
Definition: TargetInfo.h:117
virtual void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller, const FunctionDecl *Callee, const CallArgList &Args) const
Any further codegen related checks that need to be done on a function call in a target specific manne...
Definition: TargetInfo.h:89
virtual bool markARCOptimizedReturnCallsAsNoTail() const
Determine whether a call to objc_retainAutoreleasedReturnValue or objc_unsafeClaimAutoreleasedReturnV...
Definition: TargetInfo.h:206
virtual bool isNoProtoCallVariadic(const CodeGen::CallArgList &args, const FunctionNoProtoType *fnType) const
Determine whether a call to an unprototyped functions under the given calling convention should use t...
Definition: TargetInfo.cpp:86
Complex values, per C99 6.2.5p11.
Definition: Type.h:2843
QualType getElementType() const
Definition: Type.h:2853
Represents the canonical version of C arrays with a specified constant size.
Definition: Type.h:3184
specific_decl_iterator - Iterates over a subrange of declarations stored in a DeclContext,...
Definition: DeclBase.h:2340
Decl - This represents one declaration (or definition), e.g.
Definition: DeclBase.h:85
bool hasAttr() const
Definition: DeclBase.h:581
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of enums.
Definition: Type.h:4997
Represents a function declaration or definition.
Definition: Decl.h:1957
const ParmVarDecl * getParamDecl(unsigned i) const
Definition: Decl.h:2664
unsigned getNumParams() const
Return the number of parameters this function must have based on its FunctionType.
Definition: Decl.cpp:3629
Represents a K&R-style 'int foo()' function, which has no information available about its arguments.
Definition: Type.h:4116
CallingConv getCallConv() const
Definition: Type.h:4089
@ Ver11
Attempt to be ABI-compatible with code generated by Clang 11.0.x (git 2e10b7a39b93).
A (possibly-)qualified type.
Definition: Type.h:736
const Type * getTypePtr() const
Retrieves a pointer to the underlying (unqualified) type.
Definition: Type.h:6781
QualType getCanonicalType() const
Definition: Type.h:6833
Represents a struct/union/class.
Definition: Decl.h:4117
bool hasFlexibleArrayMember() const
Definition: Decl.h:4150
field_iterator field_end() const
Definition: Decl.h:4326
field_range fields() const
Definition: Decl.h:4323
field_iterator field_begin() const
Definition: Decl.cpp:5006
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of structs/unions/cl...
Definition: Type.h:4971
RecordDecl * getDecl() const
Definition: Type.h:4981
Encodes a location in the source.
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1218
const llvm::fltSemantics & getLongDoubleFormat() const
Definition: TargetInfo.h:759
The base class of the type hierarchy.
Definition: Type.h:1602
bool isBlockPointerType() const
Definition: Type.h:7041
bool isVoidType() const
Definition: Type.h:7352
bool isFloat16Type() const
Definition: Type.h:7361
bool isPointerType() const
Definition: Type.h:7033
bool isReferenceType() const
Definition: Type.h:7045
bool isEnumeralType() const
Definition: Type.h:7127
bool isIntegralOrEnumerationType() const
Determine whether this type is an integral or enumeration type.
Definition: Type.h:7455
bool isBitIntType() const
Definition: Type.h:7257
bool isSpecificBuiltinType(unsigned K) const
Test for a particular builtin type.
Definition: Type.h:7321
bool isBuiltinType() const
Helper methods to distinguish type categories.
Definition: Type.h:7119
bool isAnyComplexType() const
Definition: Type.h:7131
bool isMemberPointerType() const
Definition: Type.h:7081
bool isBFloat16Type() const
Definition: Type.h:7365
bool isMemberFunctionPointerType() const
Definition: Type.h:7085
bool isVectorType() const
Definition: Type.h:7135
const T * getAs() const
Member-template getAs<specific type>'.
Definition: Type.h:7558
bool isRecordType() const
Definition: Type.h:7123
bool isUnionType() const
Definition: Type.cpp:621
bool hasPointerRepresentation() const
Whether this type is represented natively as a pointer.
Definition: Type.h:7499
QualType getType() const
Definition: Decl.h:715
Represents a GCC generic vector type.
Definition: Type.h:3507
#define UINT_MAX
Definition: limits.h:60
ABIArgInfo classifyArgumentType(CodeGenModule &CGM, CanQualType type)
Classify the rules for how to pass a particular type.
CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, CGCXXABI &CXXABI)
std::unique_ptr< TargetCodeGenInfo > createX86_64TargetCodeGenInfo(CodeGenModule &CGM, X86AVXABILevel AVXLevel)
Definition: X86.cpp:3419
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI, const ABIInfo &Info)
Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType ValueTy, bool IsIndirect, TypeInfoChars ValueInfo, CharUnits SlotSizeAndAlign, bool AllowHigherAlign, bool ForceRightAdjust=false)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
std::unique_ptr< TargetCodeGenInfo > createWinX86_32TargetCodeGenInfo(CodeGenModule &CGM, bool DarwinVectorABI, bool Win32StructABI, unsigned NumRegisterParameters)
Definition: X86.cpp:3408
bool isRecordWithSIMDVectorType(ASTContext &Context, QualType Ty)
Address emitMergePHI(CodeGenFunction &CGF, Address Addr1, llvm::BasicBlock *Block1, Address Addr2, llvm::BasicBlock *Block2, const llvm::Twine &Name="")
X86AVXABILevel
The AVX ABI level for X86 targets.
Definition: TargetInfo.h:532
bool isEmptyField(ASTContext &Context, const FieldDecl *FD, bool AllowArrays, bool AsIfNoUniqueAddr=false)
isEmptyField - Return true iff a the field is "empty", that is it is an unnamed bit-field or an (arra...
llvm::Value * emitRoundPointerUpToAlignment(CodeGenFunction &CGF, llvm::Value *Ptr, CharUnits Align)
bool isAggregateTypeForABI(QualType T)
const Type * isSingleElementStruct(QualType T, ASTContext &Context)
isSingleElementStruct - Determine if a structure is a "single element struct", i.e.
void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, llvm::Value *Array, llvm::Value *Value, unsigned FirstIndex, unsigned LastIndex)
Definition: ABIInfoImpl.cpp:89
QualType useFirstFieldIfTransparentUnion(QualType Ty)
Pass transparent unions as if they were the type of the first element.
std::unique_ptr< TargetCodeGenInfo > createX86_32TargetCodeGenInfo(CodeGenModule &CGM, bool DarwinVectorABI, bool Win32StructABI, unsigned NumRegisterParameters, bool SoftFloatABI)
Definition: X86.cpp:3398
bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays, bool AsIfNoUniqueAddr=false)
isEmptyRecord - Return true iff a structure contains only empty fields.
std::unique_ptr< TargetCodeGenInfo > createWinX86_64TargetCodeGenInfo(CodeGenModule &CGM, X86AVXABILevel AVXLevel)
Definition: X86.cpp:3425
bool isSIMDVectorType(ASTContext &Context, QualType Ty)
const internal::VariadicAllOfMatcher< Type > type
Matches Types in the clang AST.
bool Ret(InterpState &S, CodePtr &PC, APValue &Result)
Definition: Interp.h:210
@ Result
The result type of a method or function.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:273
@ CC_C
Definition: Specifiers.h:274
@ Class
The "class" keyword introduces the elaborated-type-specifier.
unsigned long uint64_t
Definition: Format.h:5226
#define false
Definition: stdbool.h:22
llvm::IntegerType * Int8Ty
i8, i16, i32, and i64
bool isAlignRequired()
Definition: ASTContext.h:161
uint64_t Width
Definition: ASTContext.h:153
unsigned Align
Definition: ASTContext.h:154