clang  9.0.0svn
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // These classes wrap the information about a call or function
10 // definition used to handle ABI compliancy.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "TargetInfo.h"
15 #include "ABIInfo.h"
16 #include "CGBlocks.h"
17 #include "CGCXXABI.h"
18 #include "CGValue.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Triple.h"
27 #include "llvm/ADT/Twine.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include <algorithm> // std::sort
32 
33 using namespace clang;
34 using namespace CodeGen;
35 
36 // Helper for coercing an aggregate argument or return value into an integer
37 // array of the same size (including padding) and alignment. This alternate
38 // coercion happens only for the RenderScript ABI and can be removed after
39 // runtimes that rely on it are no longer supported.
40 //
41 // RenderScript assumes that the size of the argument / return value in the IR
42 // is the same as the size of the corresponding qualified type. This helper
43 // coerces the aggregate type into an array of the same size (including
44 // padding). This coercion is used in lieu of expansion of struct members or
45 // other canonical coercions that return a coerced-type of larger size.
46 //
47 // Ty - The argument / return value type
48 // Context - The associated ASTContext
49 // LLVMContext - The associated LLVMContext
51  ASTContext &Context,
52  llvm::LLVMContext &LLVMContext) {
53  // Alignment and Size are measured in bits.
54  const uint64_t Size = Context.getTypeSize(Ty);
55  const uint64_t Alignment = Context.getTypeAlign(Ty);
56  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
57  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
58  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
59 }
60 
62  llvm::Value *Array,
64  unsigned FirstIndex,
65  unsigned LastIndex) {
66  // Alternatively, we could emit this as a loop in the source.
67  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
68  llvm::Value *Cell =
69  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
70  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
71  }
72 }
73 
77 }
78 
80 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
81  llvm::Type *Padding) const {
82  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
83  ByRef, Realign, Padding);
84 }
85 
88  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
89  /*ByRef*/ false, Realign);
90 }
91 
93  QualType Ty) const {
94  return Address::invalid();
95 }
96 
98 
99 /// Does the given lowering require more than the given number of
100 /// registers when expanded?
101 ///
102 /// This is intended to be the basis of a reasonable basic implementation
103 /// of should{Pass,Return}IndirectlyForSwift.
104 ///
105 /// For most targets, a limit of four total registers is reasonable; this
106 /// limits the amount of code required in order to move around the value
107 /// in case it wasn't produced immediately prior to the call by the caller
108 /// (or wasn't produced in exactly the right registers) or isn't used
109 /// immediately within the callee. But some targets may need to further
110 /// limit the register count due to an inability to support that many
111 /// return registers.
113  ArrayRef<llvm::Type*> scalarTypes,
114  unsigned maxAllRegisters) {
115  unsigned intCount = 0, fpCount = 0;
116  for (llvm::Type *type : scalarTypes) {
117  if (type->isPointerTy()) {
118  intCount++;
119  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
120  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
121  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
122  } else {
123  assert(type->isVectorTy() || type->isFloatingPointTy());
124  fpCount++;
125  }
126  }
127 
128  return (intCount + fpCount > maxAllRegisters);
129 }
130 
132  llvm::Type *eltTy,
133  unsigned numElts) const {
134  // The default implementation of this assumes that the target guarantees
135  // 128-bit SIMD support but nothing more.
136  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
137 }
138 
140  CGCXXABI &CXXABI) {
141  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
142  if (!RD) {
143  if (!RT->getDecl()->canPassInRegisters())
144  return CGCXXABI::RAA_Indirect;
145  return CGCXXABI::RAA_Default;
146  }
147  return CXXABI.getRecordArgABI(RD);
148 }
149 
151  CGCXXABI &CXXABI) {
152  const RecordType *RT = T->getAs<RecordType>();
153  if (!RT)
154  return CGCXXABI::RAA_Default;
155  return getRecordArgABI(RT, CXXABI);
156 }
157 
159  const ABIInfo &Info) {
160  QualType Ty = FI.getReturnType();
161 
162  if (const auto *RT = Ty->getAs<RecordType>())
163  if (!isa<CXXRecordDecl>(RT->getDecl()) &&
164  !RT->getDecl()->canPassInRegisters()) {
165  FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
166  return true;
167  }
168 
169  return CXXABI.classifyReturnType(FI);
170 }
171 
172 /// Pass transparent unions as if they were the type of the first element. Sema
173 /// should ensure that all elements of the union have the same "machine type".
175  if (const RecordType *UT = Ty->getAsUnionType()) {
176  const RecordDecl *UD = UT->getDecl();
177  if (UD->hasAttr<TransparentUnionAttr>()) {
178  assert(!UD->field_empty() && "sema created an empty transparent union");
179  return UD->field_begin()->getType();
180  }
181  }
182  return Ty;
183 }
184 
186  return CGT.getCXXABI();
187 }
188 
190  return CGT.getContext();
191 }
192 
193 llvm::LLVMContext &ABIInfo::getVMContext() const {
194  return CGT.getLLVMContext();
195 }
196 
197 const llvm::DataLayout &ABIInfo::getDataLayout() const {
198  return CGT.getDataLayout();
199 }
200 
202  return CGT.getTarget();
203 }
204 
206  return CGT.getCodeGenOpts();
207 }
208 
209 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
210 
212  return false;
213 }
214 
216  uint64_t Members) const {
217  return false;
218 }
219 
220 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
221  raw_ostream &OS = llvm::errs();
222  OS << "(ABIArgInfo Kind=";
223  switch (TheKind) {
224  case Direct:
225  OS << "Direct Type=";
226  if (llvm::Type *Ty = getCoerceToType())
227  Ty->print(OS);
228  else
229  OS << "null";
230  break;
231  case Extend:
232  OS << "Extend";
233  break;
234  case Ignore:
235  OS << "Ignore";
236  break;
237  case InAlloca:
238  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
239  break;
240  case Indirect:
241  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
242  << " ByVal=" << getIndirectByVal()
243  << " Realign=" << getIndirectRealign();
244  break;
245  case Expand:
246  OS << "Expand";
247  break;
248  case CoerceAndExpand:
249  OS << "CoerceAndExpand Type=";
250  getCoerceAndExpandType()->print(OS);
251  break;
252  }
253  OS << ")\n";
254 }
255 
256 // Dynamically round a pointer up to a multiple of the given alignment.
258  llvm::Value *Ptr,
259  CharUnits Align) {
260  llvm::Value *PtrAsInt = Ptr;
261  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
262  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
263  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
264  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
265  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
266  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
267  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
268  Ptr->getType(),
269  Ptr->getName() + ".aligned");
270  return PtrAsInt;
271 }
272 
273 /// Emit va_arg for a platform using the common void* representation,
274 /// where arguments are simply emitted in an array of slots on the stack.
275 ///
276 /// This version implements the core direct-value passing rules.
277 ///
278 /// \param SlotSize - The size and alignment of a stack slot.
279 /// Each argument will be allocated to a multiple of this number of
280 /// slots, and all the slots will be aligned to this value.
281 /// \param AllowHigherAlign - The slot alignment is not a cap;
282 /// an argument type with an alignment greater than the slot size
283 /// will be emitted on a higher-alignment address, potentially
284 /// leaving one or more empty slots behind as padding. If this
285 /// is false, the returned address might be less-aligned than
286 /// DirectAlign.
288  Address VAListAddr,
289  llvm::Type *DirectTy,
290  CharUnits DirectSize,
291  CharUnits DirectAlign,
292  CharUnits SlotSize,
293  bool AllowHigherAlign) {
294  // Cast the element type to i8* if necessary. Some platforms define
295  // va_list as a struct containing an i8* instead of just an i8*.
296  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
297  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
298 
299  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
300 
301  // If the CC aligns values higher than the slot size, do so if needed.
302  Address Addr = Address::invalid();
303  if (AllowHigherAlign && DirectAlign > SlotSize) {
304  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
305  DirectAlign);
306  } else {
307  Addr = Address(Ptr, SlotSize);
308  }
309 
310  // Advance the pointer past the argument, then store that back.
311  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
312  Address NextPtr =
313  CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
314  CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
315 
316  // If the argument is smaller than a slot, and this is a big-endian
317  // target, the argument will be right-adjusted in its slot.
318  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
319  !DirectTy->isStructTy()) {
320  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
321  }
322 
323  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
324  return Addr;
325 }
326 
327 /// Emit va_arg for a platform using the common void* representation,
328 /// where arguments are simply emitted in an array of slots on the stack.
329 ///
330 /// \param IsIndirect - Values of this type are passed indirectly.
331 /// \param ValueInfo - The size and alignment of this type, generally
332 /// computed with getContext().getTypeInfoInChars(ValueTy).
333 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
334 /// Each argument will be allocated to a multiple of this number of
335 /// slots, and all the slots will be aligned to this value.
336 /// \param AllowHigherAlign - The slot alignment is not a cap;
337 /// an argument type with an alignment greater than the slot size
338 /// will be emitted on a higher-alignment address, potentially
339 /// leaving one or more empty slots behind as padding.
341  QualType ValueTy, bool IsIndirect,
342  std::pair<CharUnits, CharUnits> ValueInfo,
343  CharUnits SlotSizeAndAlign,
344  bool AllowHigherAlign) {
345  // The size and alignment of the value that was passed directly.
346  CharUnits DirectSize, DirectAlign;
347  if (IsIndirect) {
348  DirectSize = CGF.getPointerSize();
349  DirectAlign = CGF.getPointerAlign();
350  } else {
351  DirectSize = ValueInfo.first;
352  DirectAlign = ValueInfo.second;
353  }
354 
355  // Cast the address we've calculated to the right type.
356  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
357  if (IsIndirect)
358  DirectTy = DirectTy->getPointerTo(0);
359 
360  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
361  DirectSize, DirectAlign,
362  SlotSizeAndAlign,
363  AllowHigherAlign);
364 
365  if (IsIndirect) {
366  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
367  }
368 
369  return Addr;
370 
371 }
372 
374  Address Addr1, llvm::BasicBlock *Block1,
375  Address Addr2, llvm::BasicBlock *Block2,
376  const llvm::Twine &Name = "") {
377  assert(Addr1.getType() == Addr2.getType());
378  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
379  PHI->addIncoming(Addr1.getPointer(), Block1);
380  PHI->addIncoming(Addr2.getPointer(), Block2);
381  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
382  return Address(PHI, Align);
383 }
384 
386 
387 // If someone can figure out a general rule for this, that would be great.
388 // It's probably just doomed to be platform-dependent, though.
390  // Verified for:
391  // x86-64 FreeBSD, Linux, Darwin
392  // x86-32 FreeBSD, Linux, Darwin
393  // PowerPC Linux, Darwin
394  // ARM Darwin (*not* EABI)
395  // AArch64 Linux
396  return 32;
397 }
398 
400  const FunctionNoProtoType *fnType) const {
401  // The following conventions are known to require this to be false:
402  // x86_stdcall
403  // MIPS
404  // For everything else, we just prefer false unless we opt out.
405  return false;
406 }
407 
408 void
410  llvm::SmallString<24> &Opt) const {
411  // This assumes the user is passing a library name like "rt" instead of a
412  // filename like "librt.a/so", and that they don't care whether it's static or
413  // dynamic.
414  Opt = "-l";
415  Opt += Lib;
416 }
417 
419  // OpenCL kernels are called via an explicit runtime API with arguments
420  // set with clSetKernelArg(), not as normal sub-functions.
421  // Return SPIR_KERNEL by default as the kernel calling convention to
422  // ensure the fingerprint is fixed such way that each OpenCL argument
423  // gets one matching argument in the produced kernel function argument
424  // list to enable feasible implementation of clSetKernelArg() with
425  // aggregates etc. In case we would use the default C calling conv here,
426  // clSetKernelArg() might break depending on the target-specific
427  // conventions; different targets might split structs passed as values
428  // to multiple function arguments etc.
429  return llvm::CallingConv::SPIR_KERNEL;
430 }
431 
433  llvm::PointerType *T, QualType QT) const {
434  return llvm::ConstantPointerNull::get(T);
435 }
436 
438  const VarDecl *D) const {
439  assert(!CGM.getLangOpts().OpenCL &&
440  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
441  "Address space agnostic languages only");
442  return D ? D->getType().getAddressSpace() : LangAS::Default;
443 }
444 
446  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
447  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
448  // Since target may map different address spaces in AST to the same address
449  // space, an address space conversion may end up as a bitcast.
450  if (auto *C = dyn_cast<llvm::Constant>(Src))
451  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
452  // Try to preserve the source's name to make IR more readable.
454  Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : "");
455 }
456 
457 llvm::Constant *
459  LangAS SrcAddr, LangAS DestAddr,
460  llvm::Type *DestTy) const {
461  // Since target may map different address spaces in AST to the same address
462  // space, an address space conversion may end up as a bitcast.
463  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
464 }
465 
469  llvm::AtomicOrdering Ordering,
470  llvm::LLVMContext &Ctx) const {
471  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
472 }
473 
474 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
475 
476 /// isEmptyField - Return true iff a the field is "empty", that is it
477 /// is an unnamed bit-field or an (array of) empty record(s).
478 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
479  bool AllowArrays) {
480  if (FD->isUnnamedBitfield())
481  return true;
482 
483  QualType FT = FD->getType();
484 
485  // Constant arrays of empty records count as empty, strip them off.
486  // Constant arrays of zero length always count as empty.
487  if (AllowArrays)
488  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
489  if (AT->getSize() == 0)
490  return true;
491  FT = AT->getElementType();
492  }
493 
494  const RecordType *RT = FT->getAs<RecordType>();
495  if (!RT)
496  return false;
497 
498  // C++ record fields are never empty, at least in the Itanium ABI.
499  //
500  // FIXME: We should use a predicate for whether this behavior is true in the
501  // current ABI.
502  if (isa<CXXRecordDecl>(RT->getDecl()))
503  return false;
504 
505  return isEmptyRecord(Context, FT, AllowArrays);
506 }
507 
508 /// isEmptyRecord - Return true iff a structure contains only empty
509 /// fields. Note that a structure with a flexible array member is not
510 /// considered empty.
511 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
512  const RecordType *RT = T->getAs<RecordType>();
513  if (!RT)
514  return false;
515  const RecordDecl *RD = RT->getDecl();
516  if (RD->hasFlexibleArrayMember())
517  return false;
518 
519  // If this is a C++ record, check the bases first.
520  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
521  for (const auto &I : CXXRD->bases())
522  if (!isEmptyRecord(Context, I.getType(), true))
523  return false;
524 
525  for (const auto *I : RD->fields())
526  if (!isEmptyField(Context, I, AllowArrays))
527  return false;
528  return true;
529 }
530 
531 /// isSingleElementStruct - Determine if a structure is a "single
532 /// element struct", i.e. it has exactly one non-empty field or
533 /// exactly one field which is itself a single element
534 /// struct. Structures with flexible array members are never
535 /// considered single element structs.
536 ///
537 /// \return The field declaration for the single non-empty field, if
538 /// it exists.
539 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
540  const RecordType *RT = T->getAs<RecordType>();
541  if (!RT)
542  return nullptr;
543 
544  const RecordDecl *RD = RT->getDecl();
545  if (RD->hasFlexibleArrayMember())
546  return nullptr;
547 
548  const Type *Found = nullptr;
549 
550  // If this is a C++ record, check the bases first.
551  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
552  for (const auto &I : CXXRD->bases()) {
553  // Ignore empty records.
554  if (isEmptyRecord(Context, I.getType(), true))
555  continue;
556 
557  // If we already found an element then this isn't a single-element struct.
558  if (Found)
559  return nullptr;
560 
561  // If this is non-empty and not a single element struct, the composite
562  // cannot be a single element struct.
563  Found = isSingleElementStruct(I.getType(), Context);
564  if (!Found)
565  return nullptr;
566  }
567  }
568 
569  // Check for single element.
570  for (const auto *FD : RD->fields()) {
571  QualType FT = FD->getType();
572 
573  // Ignore empty fields.
574  if (isEmptyField(Context, FD, true))
575  continue;
576 
577  // If we already found an element then this isn't a single-element
578  // struct.
579  if (Found)
580  return nullptr;
581 
582  // Treat single element arrays as the element.
583  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
584  if (AT->getSize().getZExtValue() != 1)
585  break;
586  FT = AT->getElementType();
587  }
588 
589  if (!isAggregateTypeForABI(FT)) {
590  Found = FT.getTypePtr();
591  } else {
592  Found = isSingleElementStruct(FT, Context);
593  if (!Found)
594  return nullptr;
595  }
596  }
597 
598  // We don't consider a struct a single-element struct if it has
599  // padding beyond the element type.
600  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
601  return nullptr;
602 
603  return Found;
604 }
605 
606 namespace {
607 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
608  const ABIArgInfo &AI) {
609  // This default implementation defers to the llvm backend's va_arg
610  // instruction. It can handle only passing arguments directly
611  // (typically only handled in the backend for primitive types), or
612  // aggregates passed indirectly by pointer (NOTE: if the "byval"
613  // flag has ABI impact in the callee, this implementation cannot
614  // work.)
615 
616  // Only a few cases are covered here at the moment -- those needed
617  // by the default abi.
618  llvm::Value *Val;
619 
620  if (AI.isIndirect()) {
621  assert(!AI.getPaddingType() &&
622  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
623  assert(
624  !AI.getIndirectRealign() &&
625  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
626 
627  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
628  CharUnits TyAlignForABI = TyInfo.second;
629 
630  llvm::Type *BaseTy =
631  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
632  llvm::Value *Addr =
633  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
634  return Address(Addr, TyAlignForABI);
635  } else {
636  assert((AI.isDirect() || AI.isExtend()) &&
637  "Unexpected ArgInfo Kind in generic VAArg emitter!");
638 
639  assert(!AI.getInReg() &&
640  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
641  assert(!AI.getPaddingType() &&
642  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
643  assert(!AI.getDirectOffset() &&
644  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
645  assert(!AI.getCoerceToType() &&
646  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
647 
648  Address Temp = CGF.CreateMemTemp(Ty, "varet");
649  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
650  CGF.Builder.CreateStore(Val, Temp);
651  return Temp;
652  }
653 }
654 
655 /// DefaultABIInfo - The default implementation for ABI specific
656 /// details. This implementation provides information which results in
657 /// self-consistent and sensible LLVM IR generation, but does not
658 /// conform to any particular ABI.
659 class DefaultABIInfo : public ABIInfo {
660 public:
661  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
662 
665 
666  void computeInfo(CGFunctionInfo &FI) const override {
667  if (!getCXXABI().classifyReturnType(FI))
669  for (auto &I : FI.arguments())
670  I.info = classifyArgumentType(I.type);
671  }
672 
673  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
674  QualType Ty) const override {
675  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
676  }
677 };
678 
679 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
680 public:
681  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
682  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
683 };
684 
687 
688  if (isAggregateTypeForABI(Ty)) {
689  // Records with non-trivial destructors/copy-constructors should not be
690  // passed by value.
693 
694  return getNaturalAlignIndirect(Ty);
695  }
696 
697  // Treat an enum type as its underlying type.
698  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
699  Ty = EnumTy->getDecl()->getIntegerType();
700 
703 }
704 
706  if (RetTy->isVoidType())
707  return ABIArgInfo::getIgnore();
708 
709  if (isAggregateTypeForABI(RetTy))
710  return getNaturalAlignIndirect(RetTy);
711 
712  // Treat an enum type as its underlying type.
713  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
714  RetTy = EnumTy->getDecl()->getIntegerType();
715 
716  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
718 }
719 
720 //===----------------------------------------------------------------------===//
721 // WebAssembly ABI Implementation
722 //
723 // This is a very simple ABI that relies a lot on DefaultABIInfo.
724 //===----------------------------------------------------------------------===//
725 
726 class WebAssemblyABIInfo final : public SwiftABIInfo {
727  DefaultABIInfo defaultInfo;
728 
729 public:
730  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
731  : SwiftABIInfo(CGT), defaultInfo(CGT) {}
732 
733 private:
736 
737  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
738  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
739  // overload them.
740  void computeInfo(CGFunctionInfo &FI) const override {
741  if (!getCXXABI().classifyReturnType(FI))
743  for (auto &Arg : FI.arguments())
744  Arg.info = classifyArgumentType(Arg.type);
745  }
746 
747  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
748  QualType Ty) const override;
749 
750  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
751  bool asReturnValue) const override {
752  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
753  }
754 
755  bool isSwiftErrorInRegister() const override {
756  return false;
757  }
758 };
759 
760 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
761 public:
762  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
763  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
764 
765  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
766  CodeGen::CodeGenModule &CGM) const override {
768  if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
769  if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
770  llvm::Function *Fn = cast<llvm::Function>(GV);
771  llvm::AttrBuilder B;
772  B.addAttribute("wasm-import-module", Attr->getImportModule());
773  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
774  }
775  if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
776  llvm::Function *Fn = cast<llvm::Function>(GV);
777  llvm::AttrBuilder B;
778  B.addAttribute("wasm-import-name", Attr->getImportName());
779  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
780  }
781  }
782 
783  if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
784  llvm::Function *Fn = cast<llvm::Function>(GV);
785  if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
786  Fn->addFnAttr("no-prototype");
787  }
788  }
789 };
790 
791 /// Classify argument of given type \p Ty.
794 
795  if (isAggregateTypeForABI(Ty)) {
796  // Records with non-trivial destructors/copy-constructors should not be
797  // passed by value.
798  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
800  // Ignore empty structs/unions.
801  if (isEmptyRecord(getContext(), Ty, true))
802  return ABIArgInfo::getIgnore();
803  // Lower single-element structs to just pass a regular value. TODO: We
804  // could do reasonable-size multiple-element structs too, using getExpand(),
805  // though watch out for things like bitfields.
806  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
807  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
808  }
809 
810  // Otherwise just do the default thing.
811  return defaultInfo.classifyArgumentType(Ty);
812 }
813 
815  if (isAggregateTypeForABI(RetTy)) {
816  // Records with non-trivial destructors/copy-constructors should not be
817  // returned by value.
818  if (!getRecordArgABI(RetTy, getCXXABI())) {
819  // Ignore empty structs/unions.
820  if (isEmptyRecord(getContext(), RetTy, true))
821  return ABIArgInfo::getIgnore();
822  // Lower single-element structs to just return a regular value. TODO: We
823  // could do reasonable-size multiple-element structs too, using
824  // ABIArgInfo::getDirect().
825  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
826  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
827  }
828  }
829 
830  // Otherwise just do the default thing.
831  return defaultInfo.classifyReturnType(RetTy);
832 }
833 
834 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
835  QualType Ty) const {
836  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*IsIndirect=*/ false,
837  getContext().getTypeInfoInChars(Ty),
839  /*AllowHigherAlign=*/ true);
840 }
841 
842 //===----------------------------------------------------------------------===//
843 // le32/PNaCl bitcode ABI Implementation
844 //
845 // This is a simplified version of the x86_32 ABI. Arguments and return values
846 // are always passed on the stack.
847 //===----------------------------------------------------------------------===//
848 
849 class PNaClABIInfo : public ABIInfo {
850  public:
851  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
852 
855 
856  void computeInfo(CGFunctionInfo &FI) const override;
858  Address VAListAddr, QualType Ty) const override;
859 };
860 
861 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
862  public:
863  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
864  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
865 };
866 
867 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
868  if (!getCXXABI().classifyReturnType(FI))
870 
871  for (auto &I : FI.arguments())
872  I.info = classifyArgumentType(I.type);
873 }
874 
875 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
876  QualType Ty) const {
877  // The PNaCL ABI is a bit odd, in that varargs don't use normal
878  // function classification. Structs get passed directly for varargs
879  // functions, through a rewriting transform in
880  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
881  // this target to actually support a va_arg instructions with an
882  // aggregate type, unlike other targets.
883  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
884 }
885 
886 /// Classify argument of given type \p Ty.
888  if (isAggregateTypeForABI(Ty)) {
891  return getNaturalAlignIndirect(Ty);
892  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
893  // Treat an enum type as its underlying type.
894  Ty = EnumTy->getDecl()->getIntegerType();
895  } else if (Ty->isFloatingType()) {
896  // Floating-point types don't go inreg.
897  return ABIArgInfo::getDirect();
898  }
899 
902 }
903 
905  if (RetTy->isVoidType())
906  return ABIArgInfo::getIgnore();
907 
908  // In the PNaCl ABI we always return records/structures on the stack.
909  if (isAggregateTypeForABI(RetTy))
910  return getNaturalAlignIndirect(RetTy);
911 
912  // Treat an enum type as its underlying type.
913  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
914  RetTy = EnumTy->getDecl()->getIntegerType();
915 
916  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
918 }
919 
920 /// IsX86_MMXType - Return true if this is an MMX type.
921 bool IsX86_MMXType(llvm::Type *IRType) {
922  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
923  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
924  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
925  IRType->getScalarSizeInBits() != 64;
926 }
927 
928 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
929  StringRef Constraint,
930  llvm::Type* Ty) {
931  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
932  .Cases("y", "&y", "^Ym", true)
933  .Default(false);
934  if (IsMMXCons && Ty->isVectorTy()) {
935  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
936  // Invalid MMX constraint
937  return nullptr;
938  }
939 
940  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
941  }
942 
943  // No operation needed
944  return Ty;
945 }
946 
947 /// Returns true if this type can be passed in SSE registers with the
948 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
949 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
950  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
951  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
952  if (BT->getKind() == BuiltinType::LongDouble) {
953  if (&Context.getTargetInfo().getLongDoubleFormat() ==
954  &llvm::APFloat::x87DoubleExtended())
955  return false;
956  }
957  return true;
958  }
959  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
960  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
961  // registers specially.
962  unsigned VecSize = Context.getTypeSize(VT);
963  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
964  return true;
965  }
966  return false;
967 }
968 
969 /// Returns true if this aggregate is small enough to be passed in SSE registers
970 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
971 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
972  return NumMembers <= 4;
973 }
974 
975 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
976 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
977  auto AI = ABIArgInfo::getDirect(T);
978  AI.setInReg(true);
979  AI.setCanBeFlattened(false);
980  return AI;
981 }
982 
983 //===----------------------------------------------------------------------===//
984 // X86-32 ABI Implementation
985 //===----------------------------------------------------------------------===//
986 
987 /// Similar to llvm::CCState, but for Clang.
988 struct CCState {
989  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
990 
991  unsigned CC;
992  unsigned FreeRegs;
993  unsigned FreeSSERegs;
994 };
995 
996 enum {
997  // Vectorcall only allows the first 6 parameters to be passed in registers.
998  VectorcallMaxParamNumAsReg = 6
999 };
1000 
1001 /// X86_32ABIInfo - The X86-32 ABI information.
1002 class X86_32ABIInfo : public SwiftABIInfo {
1003  enum Class {
1004  Integer,
1005  Float
1006  };
1007 
1008  static const unsigned MinABIStackAlignInBytes = 4;
1009 
1010  bool IsDarwinVectorABI;
1011  bool IsRetSmallStructInRegABI;
1012  bool IsWin32StructABI;
1013  bool IsSoftFloatABI;
1014  bool IsMCUABI;
1015  unsigned DefaultNumRegisterParameters;
1016 
1017  static bool isRegisterSize(unsigned Size) {
1018  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
1019  }
1020 
1021  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1022  // FIXME: Assumes vectorcall is in use.
1023  return isX86VectorTypeForVectorCall(getContext(), Ty);
1024  }
1025 
1026  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1027  uint64_t NumMembers) const override {
1028  // FIXME: Assumes vectorcall is in use.
1029  return isX86VectorCallAggregateSmallEnough(NumMembers);
1030  }
1031 
1032  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1033 
1034  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1035  /// such that the argument will be passed in memory.
1036  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1037 
1038  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1039 
1040  /// Return the alignment to use for the given type on the stack.
1041  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1042 
1043  Class classify(QualType Ty) const;
1044  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1045  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1046 
1047  /// Updates the number of available free registers, returns
1048  /// true if any registers were allocated.
1049  bool updateFreeRegs(QualType Ty, CCState &State) const;
1050 
1051  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1052  bool &NeedsPadding) const;
1053  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1054 
1055  bool canExpandIndirectArgument(QualType Ty) const;
1056 
1057  /// Rewrite the function info so that all memory arguments use
1058  /// inalloca.
1059  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1060 
1061  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1062  CharUnits &StackOffset, ABIArgInfo &Info,
1063  QualType Type) const;
1064  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1065  bool &UsedInAlloca) const;
1066 
1067 public:
1068 
1069  void computeInfo(CGFunctionInfo &FI) const override;
1070  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1071  QualType Ty) const override;
1072 
1073  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1074  bool RetSmallStructInRegABI, bool Win32StructABI,
1075  unsigned NumRegisterParameters, bool SoftFloatABI)
1076  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1077  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1078  IsWin32StructABI(Win32StructABI),
1079  IsSoftFloatABI(SoftFloatABI),
1080  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1081  DefaultNumRegisterParameters(NumRegisterParameters) {}
1082 
1083  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1084  bool asReturnValue) const override {
1085  // LLVM's x86-32 lowering currently only assigns up to three
1086  // integer registers and three fp registers. Oddly, it'll use up to
1087  // four vector registers for vectors, but those can overlap with the
1088  // scalar registers.
1089  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1090  }
1091 
1092  bool isSwiftErrorInRegister() const override {
1093  // x86-32 lowering does not support passing swifterror in a register.
1094  return false;
1095  }
1096 };
1097 
1098 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1099 public:
1100  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1101  bool RetSmallStructInRegABI, bool Win32StructABI,
1102  unsigned NumRegisterParameters, bool SoftFloatABI)
1103  : TargetCodeGenInfo(new X86_32ABIInfo(
1104  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1105  NumRegisterParameters, SoftFloatABI)) {}
1106 
1107  static bool isStructReturnInRegABI(
1108  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1109 
1110  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1111  CodeGen::CodeGenModule &CGM) const override;
1112 
1113  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1114  // Darwin uses different dwarf register numbers for EH.
1115  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1116  return 4;
1117  }
1118 
1119  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1120  llvm::Value *Address) const override;
1121 
1122  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1123  StringRef Constraint,
1124  llvm::Type* Ty) const override {
1125  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1126  }
1127 
1128  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1129  std::string &Constraints,
1130  std::vector<llvm::Type *> &ResultRegTypes,
1131  std::vector<llvm::Type *> &ResultTruncRegTypes,
1132  std::vector<LValue> &ResultRegDests,
1133  std::string &AsmString,
1134  unsigned NumOutputs) const override;
1135 
1136  llvm::Constant *
1137  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1138  unsigned Sig = (0xeb << 0) | // jmp rel8
1139  (0x06 << 8) | // .+0x08
1140  ('v' << 16) |
1141  ('2' << 24);
1142  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1143  }
1144 
1145  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1146  return "movl\t%ebp, %ebp"
1147  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1148  }
1149 };
1150 
1151 }
1152 
1153 /// Rewrite input constraint references after adding some output constraints.
1154 /// In the case where there is one output and one input and we add one output,
1155 /// we need to replace all operand references greater than or equal to 1:
1156 /// mov $0, $1
1157 /// mov eax, $1
1158 /// The result will be:
1159 /// mov $0, $2
1160 /// mov eax, $2
1161 static void rewriteInputConstraintReferences(unsigned FirstIn,
1162  unsigned NumNewOuts,
1163  std::string &AsmString) {
1164  std::string Buf;
1165  llvm::raw_string_ostream OS(Buf);
1166  size_t Pos = 0;
1167  while (Pos < AsmString.size()) {
1168  size_t DollarStart = AsmString.find('$', Pos);
1169  if (DollarStart == std::string::npos)
1170  DollarStart = AsmString.size();
1171  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1172  if (DollarEnd == std::string::npos)
1173  DollarEnd = AsmString.size();
1174  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1175  Pos = DollarEnd;
1176  size_t NumDollars = DollarEnd - DollarStart;
1177  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1178  // We have an operand reference.
1179  size_t DigitStart = Pos;
1180  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1181  if (DigitEnd == std::string::npos)
1182  DigitEnd = AsmString.size();
1183  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1184  unsigned OperandIndex;
1185  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1186  if (OperandIndex >= FirstIn)
1187  OperandIndex += NumNewOuts;
1188  OS << OperandIndex;
1189  } else {
1190  OS << OperandStr;
1191  }
1192  Pos = DigitEnd;
1193  }
1194  }
1195  AsmString = std::move(OS.str());
1196 }
1197 
1198 /// Add output constraints for EAX:EDX because they are return registers.
1199 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1200  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1201  std::vector<llvm::Type *> &ResultRegTypes,
1202  std::vector<llvm::Type *> &ResultTruncRegTypes,
1203  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1204  unsigned NumOutputs) const {
1205  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1206 
1207  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1208  // larger.
1209  if (!Constraints.empty())
1210  Constraints += ',';
1211  if (RetWidth <= 32) {
1212  Constraints += "={eax}";
1213  ResultRegTypes.push_back(CGF.Int32Ty);
1214  } else {
1215  // Use the 'A' constraint for EAX:EDX.
1216  Constraints += "=A";
1217  ResultRegTypes.push_back(CGF.Int64Ty);
1218  }
1219 
1220  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1221  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1222  ResultTruncRegTypes.push_back(CoerceTy);
1223 
1224  // Coerce the integer by bitcasting the return slot pointer.
1225  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1226  CoerceTy->getPointerTo()));
1227  ResultRegDests.push_back(ReturnSlot);
1228 
1229  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1230 }
1231 
1232 /// shouldReturnTypeInRegister - Determine if the given type should be
1233 /// returned in a register (for the Darwin and MCU ABI).
1234 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1235  ASTContext &Context) const {
1236  uint64_t Size = Context.getTypeSize(Ty);
1237 
1238  // For i386, type must be register sized.
1239  // For the MCU ABI, it only needs to be <= 8-byte
1240  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1241  return false;
1242 
1243  if (Ty->isVectorType()) {
1244  // 64- and 128- bit vectors inside structures are not returned in
1245  // registers.
1246  if (Size == 64 || Size == 128)
1247  return false;
1248 
1249  return true;
1250  }
1251 
1252  // If this is a builtin, pointer, enum, complex type, member pointer, or
1253  // member function pointer it is ok.
1254  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1255  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1256  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1257  return true;
1258 
1259  // Arrays are treated like records.
1260  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1261  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1262 
1263  // Otherwise, it must be a record type.
1264  const RecordType *RT = Ty->getAs<RecordType>();
1265  if (!RT) return false;
1266 
1267  // FIXME: Traverse bases here too.
1268 
1269  // Structure types are passed in register if all fields would be
1270  // passed in a register.
1271  for (const auto *FD : RT->getDecl()->fields()) {
1272  // Empty fields are ignored.
1273  if (isEmptyField(Context, FD, true))
1274  continue;
1275 
1276  // Check fields recursively.
1277  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1278  return false;
1279  }
1280  return true;
1281 }
1282 
1283 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1284  // Treat complex types as the element type.
1285  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1286  Ty = CTy->getElementType();
1287 
1288  // Check for a type which we know has a simple scalar argument-passing
1289  // convention without any padding. (We're specifically looking for 32
1290  // and 64-bit integer and integer-equivalents, float, and double.)
1291  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1292  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1293  return false;
1294 
1295  uint64_t Size = Context.getTypeSize(Ty);
1296  return Size == 32 || Size == 64;
1297 }
1298 
1299 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1300  uint64_t &Size) {
1301  for (const auto *FD : RD->fields()) {
1302  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1303  // argument is smaller than 32-bits, expanding the struct will create
1304  // alignment padding.
1305  if (!is32Or64BitBasicType(FD->getType(), Context))
1306  return false;
1307 
1308  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1309  // how to expand them yet, and the predicate for telling if a bitfield still
1310  // counts as "basic" is more complicated than what we were doing previously.
1311  if (FD->isBitField())
1312  return false;
1313 
1314  Size += Context.getTypeSize(FD->getType());
1315  }
1316  return true;
1317 }
1318 
1319 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1320  uint64_t &Size) {
1321  // Don't do this if there are any non-empty bases.
1322  for (const CXXBaseSpecifier &Base : RD->bases()) {
1323  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1324  Size))
1325  return false;
1326  }
1327  if (!addFieldSizes(Context, RD, Size))
1328  return false;
1329  return true;
1330 }
1331 
1332 /// Test whether an argument type which is to be passed indirectly (on the
1333 /// stack) would have the equivalent layout if it was expanded into separate
1334 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1335 /// optimizations.
1336 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1337  // We can only expand structure types.
1338  const RecordType *RT = Ty->getAs<RecordType>();
1339  if (!RT)
1340  return false;
1341  const RecordDecl *RD = RT->getDecl();
1342  uint64_t Size = 0;
1343  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1344  if (!IsWin32StructABI) {
1345  // On non-Windows, we have to conservatively match our old bitcode
1346  // prototypes in order to be ABI-compatible at the bitcode level.
1347  if (!CXXRD->isCLike())
1348  return false;
1349  } else {
1350  // Don't do this for dynamic classes.
1351  if (CXXRD->isDynamicClass())
1352  return false;
1353  }
1354  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1355  return false;
1356  } else {
1357  if (!addFieldSizes(getContext(), RD, Size))
1358  return false;
1359  }
1360 
1361  // We can do this if there was no alignment padding.
1362  return Size == getContext().getTypeSize(Ty);
1363 }
1364 
1365 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1366  // If the return value is indirect, then the hidden argument is consuming one
1367  // integer register.
1368  if (State.FreeRegs) {
1369  --State.FreeRegs;
1370  if (!IsMCUABI)
1371  return getNaturalAlignIndirectInReg(RetTy);
1372  }
1373  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1374 }
1375 
1377  CCState &State) const {
1378  if (RetTy->isVoidType())
1379  return ABIArgInfo::getIgnore();
1380 
1381  const Type *Base = nullptr;
1382  uint64_t NumElts = 0;
1383  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1384  State.CC == llvm::CallingConv::X86_RegCall) &&
1385  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1386  // The LLVM struct type for such an aggregate should lower properly.
1387  return ABIArgInfo::getDirect();
1388  }
1389 
1390  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1391  // On Darwin, some vectors are returned in registers.
1392  if (IsDarwinVectorABI) {
1393  uint64_t Size = getContext().getTypeSize(RetTy);
1394 
1395  // 128-bit vectors are a special case; they are returned in
1396  // registers and we need to make sure to pick a type the LLVM
1397  // backend will like.
1398  if (Size == 128)
1399  return ABIArgInfo::getDirect(llvm::VectorType::get(
1400  llvm::Type::getInt64Ty(getVMContext()), 2));
1401 
1402  // Always return in register if it fits in a general purpose
1403  // register, or if it is 64 bits and has a single element.
1404  if ((Size == 8 || Size == 16 || Size == 32) ||
1405  (Size == 64 && VT->getNumElements() == 1))
1406  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1407  Size));
1408 
1409  return getIndirectReturnResult(RetTy, State);
1410  }
1411 
1412  return ABIArgInfo::getDirect();
1413  }
1414 
1415  if (isAggregateTypeForABI(RetTy)) {
1416  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1417  // Structures with flexible arrays are always indirect.
1418  if (RT->getDecl()->hasFlexibleArrayMember())
1419  return getIndirectReturnResult(RetTy, State);
1420  }
1421 
1422  // If specified, structs and unions are always indirect.
1423  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1424  return getIndirectReturnResult(RetTy, State);
1425 
1426  // Ignore empty structs/unions.
1427  if (isEmptyRecord(getContext(), RetTy, true))
1428  return ABIArgInfo::getIgnore();
1429 
1430  // Small structures which are register sized are generally returned
1431  // in a register.
1432  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1433  uint64_t Size = getContext().getTypeSize(RetTy);
1434 
1435  // As a special-case, if the struct is a "single-element" struct, and
1436  // the field is of type "float" or "double", return it in a
1437  // floating-point register. (MSVC does not apply this special case.)
1438  // We apply a similar transformation for pointer types to improve the
1439  // quality of the generated IR.
1440  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1441  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1442  || SeltTy->hasPointerRepresentation())
1443  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1444 
1445  // FIXME: We should be able to narrow this integer in cases with dead
1446  // padding.
1447  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1448  }
1449 
1450  return getIndirectReturnResult(RetTy, State);
1451  }
1452 
1453  // Treat an enum type as its underlying type.
1454  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1455  RetTy = EnumTy->getDecl()->getIntegerType();
1456 
1457  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1458  : ABIArgInfo::getDirect());
1459 }
1460 
1461 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1462  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1463 }
1464 
1465 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1466  const RecordType *RT = Ty->getAs<RecordType>();
1467  if (!RT)
1468  return 0;
1469  const RecordDecl *RD = RT->getDecl();
1470 
1471  // If this is a C++ record, check the bases first.
1472  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1473  for (const auto &I : CXXRD->bases())
1474  if (!isRecordWithSSEVectorType(Context, I.getType()))
1475  return false;
1476 
1477  for (const auto *i : RD->fields()) {
1478  QualType FT = i->getType();
1479 
1480  if (isSSEVectorType(Context, FT))
1481  return true;
1482 
1483  if (isRecordWithSSEVectorType(Context, FT))
1484  return true;
1485  }
1486 
1487  return false;
1488 }
1489 
1490 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1491  unsigned Align) const {
1492  // Otherwise, if the alignment is less than or equal to the minimum ABI
1493  // alignment, just use the default; the backend will handle this.
1494  if (Align <= MinABIStackAlignInBytes)
1495  return 0; // Use default alignment.
1496 
1497  // On non-Darwin, the stack type alignment is always 4.
1498  if (!IsDarwinVectorABI) {
1499  // Set explicit alignment, since we may need to realign the top.
1500  return MinABIStackAlignInBytes;
1501  }
1502 
1503  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1504  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1506  return 16;
1507 
1508  return MinABIStackAlignInBytes;
1509 }
1510 
1511 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1512  CCState &State) const {
1513  if (!ByVal) {
1514  if (State.FreeRegs) {
1515  --State.FreeRegs; // Non-byval indirects just use one pointer.
1516  if (!IsMCUABI)
1517  return getNaturalAlignIndirectInReg(Ty);
1518  }
1519  return getNaturalAlignIndirect(Ty, false);
1520  }
1521 
1522  // Compute the byval alignment.
1523  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1524  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1525  if (StackAlign == 0)
1526  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1527 
1528  // If the stack alignment is less than the type alignment, realign the
1529  // argument.
1530  bool Realign = TypeAlign > StackAlign;
1532  /*ByVal=*/true, Realign);
1533 }
1534 
1535 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1536  const Type *T = isSingleElementStruct(Ty, getContext());
1537  if (!T)
1538  T = Ty.getTypePtr();
1539 
1540  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1541  BuiltinType::Kind K = BT->getKind();
1542  if (K == BuiltinType::Float || K == BuiltinType::Double)
1543  return Float;
1544  }
1545  return Integer;
1546 }
1547 
1548 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1549  if (!IsSoftFloatABI) {
1550  Class C = classify(Ty);
1551  if (C == Float)
1552  return false;
1553  }
1554 
1555  unsigned Size = getContext().getTypeSize(Ty);
1556  unsigned SizeInRegs = (Size + 31) / 32;
1557 
1558  if (SizeInRegs == 0)
1559  return false;
1560 
1561  if (!IsMCUABI) {
1562  if (SizeInRegs > State.FreeRegs) {
1563  State.FreeRegs = 0;
1564  return false;
1565  }
1566  } else {
1567  // The MCU psABI allows passing parameters in-reg even if there are
1568  // earlier parameters that are passed on the stack. Also,
1569  // it does not allow passing >8-byte structs in-register,
1570  // even if there are 3 free registers available.
1571  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1572  return false;
1573  }
1574 
1575  State.FreeRegs -= SizeInRegs;
1576  return true;
1577 }
1578 
1579 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1580  bool &InReg,
1581  bool &NeedsPadding) const {
1582  // On Windows, aggregates other than HFAs are never passed in registers, and
1583  // they do not consume register slots. Homogenous floating-point aggregates
1584  // (HFAs) have already been dealt with at this point.
1585  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1586  return false;
1587 
1588  NeedsPadding = false;
1589  InReg = !IsMCUABI;
1590 
1591  if (!updateFreeRegs(Ty, State))
1592  return false;
1593 
1594  if (IsMCUABI)
1595  return true;
1596 
1597  if (State.CC == llvm::CallingConv::X86_FastCall ||
1598  State.CC == llvm::CallingConv::X86_VectorCall ||
1599  State.CC == llvm::CallingConv::X86_RegCall) {
1600  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1601  NeedsPadding = true;
1602 
1603  return false;
1604  }
1605 
1606  return true;
1607 }
1608 
1609 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1610  if (!updateFreeRegs(Ty, State))
1611  return false;
1612 
1613  if (IsMCUABI)
1614  return false;
1615 
1616  if (State.CC == llvm::CallingConv::X86_FastCall ||
1617  State.CC == llvm::CallingConv::X86_VectorCall ||
1618  State.CC == llvm::CallingConv::X86_RegCall) {
1619  if (getContext().getTypeSize(Ty) > 32)
1620  return false;
1621 
1622  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1623  Ty->isReferenceType());
1624  }
1625 
1626  return true;
1627 }
1628 
1630  CCState &State) const {
1631  // FIXME: Set alignment on indirect arguments.
1632 
1634 
1635  // Check with the C++ ABI first.
1636  const RecordType *RT = Ty->getAs<RecordType>();
1637  if (RT) {
1639  if (RAA == CGCXXABI::RAA_Indirect) {
1640  return getIndirectResult(Ty, false, State);
1641  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1642  // The field index doesn't matter, we'll fix it up later.
1643  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1644  }
1645  }
1646 
1647  // Regcall uses the concept of a homogenous vector aggregate, similar
1648  // to other targets.
1649  const Type *Base = nullptr;
1650  uint64_t NumElts = 0;
1651  if (State.CC == llvm::CallingConv::X86_RegCall &&
1652  isHomogeneousAggregate(Ty, Base, NumElts)) {
1653 
1654  if (State.FreeSSERegs >= NumElts) {
1655  State.FreeSSERegs -= NumElts;
1656  if (Ty->isBuiltinType() || Ty->isVectorType())
1657  return ABIArgInfo::getDirect();
1658  return ABIArgInfo::getExpand();
1659  }
1660  return getIndirectResult(Ty, /*ByVal=*/false, State);
1661  }
1662 
1663  if (isAggregateTypeForABI(Ty)) {
1664  // Structures with flexible arrays are always indirect.
1665  // FIXME: This should not be byval!
1666  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1667  return getIndirectResult(Ty, true, State);
1668 
1669  // Ignore empty structs/unions on non-Windows.
1670  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1671  return ABIArgInfo::getIgnore();
1672 
1673  llvm::LLVMContext &LLVMContext = getVMContext();
1674  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1675  bool NeedsPadding = false;
1676  bool InReg;
1677  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1678  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1679  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1680  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1681  if (InReg)
1682  return ABIArgInfo::getDirectInReg(Result);
1683  else
1684  return ABIArgInfo::getDirect(Result);
1685  }
1686  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1687 
1688  // Expand small (<= 128-bit) record types when we know that the stack layout
1689  // of those arguments will match the struct. This is important because the
1690  // LLVM backend isn't smart enough to remove byval, which inhibits many
1691  // optimizations.
1692  // Don't do this for the MCU if there are still free integer registers
1693  // (see X86_64 ABI for full explanation).
1694  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1695  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1697  State.CC == llvm::CallingConv::X86_FastCall ||
1698  State.CC == llvm::CallingConv::X86_VectorCall ||
1699  State.CC == llvm::CallingConv::X86_RegCall,
1700  PaddingType);
1701 
1702  return getIndirectResult(Ty, true, State);
1703  }
1704 
1705  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1706  // On Darwin, some vectors are passed in memory, we handle this by passing
1707  // it as an i8/i16/i32/i64.
1708  if (IsDarwinVectorABI) {
1709  uint64_t Size = getContext().getTypeSize(Ty);
1710  if ((Size == 8 || Size == 16 || Size == 32) ||
1711  (Size == 64 && VT->getNumElements() == 1))
1712  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1713  Size));
1714  }
1715 
1716  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1717  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1718 
1719  return ABIArgInfo::getDirect();
1720  }
1721 
1722 
1723  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1724  Ty = EnumTy->getDecl()->getIntegerType();
1725 
1726  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1727 
1728  if (Ty->isPromotableIntegerType()) {
1729  if (InReg)
1730  return ABIArgInfo::getExtendInReg(Ty);
1731  return ABIArgInfo::getExtend(Ty);
1732  }
1733 
1734  if (InReg)
1735  return ABIArgInfo::getDirectInReg();
1736  return ABIArgInfo::getDirect();
1737 }
1738 
1739 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1740  bool &UsedInAlloca) const {
1741  // Vectorcall x86 works subtly different than in x64, so the format is
1742  // a bit different than the x64 version. First, all vector types (not HVAs)
1743  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1744  // This differs from the x64 implementation, where the first 6 by INDEX get
1745  // registers.
1746  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1747  // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1748  // first take up the remaining YMM/XMM registers. If insufficient registers
1749  // remain but an integer register (ECX/EDX) is available, it will be passed
1750  // in that, else, on the stack.
1751  for (auto &I : FI.arguments()) {
1752  // First pass do all the vector types.
1753  const Type *Base = nullptr;
1754  uint64_t NumElts = 0;
1755  const QualType& Ty = I.type;
1756  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1757  isHomogeneousAggregate(Ty, Base, NumElts)) {
1758  if (State.FreeSSERegs >= NumElts) {
1759  State.FreeSSERegs -= NumElts;
1760  I.info = ABIArgInfo::getDirect();
1761  } else {
1762  I.info = classifyArgumentType(Ty, State);
1763  }
1764  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1765  }
1766  }
1767 
1768  for (auto &I : FI.arguments()) {
1769  // Second pass, do the rest!
1770  const Type *Base = nullptr;
1771  uint64_t NumElts = 0;
1772  const QualType& Ty = I.type;
1773  bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1774 
1775  if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1776  // Assign true HVAs (non vector/native FP types).
1777  if (State.FreeSSERegs >= NumElts) {
1778  State.FreeSSERegs -= NumElts;
1779  I.info = getDirectX86Hva();
1780  } else {
1781  I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1782  }
1783  } else if (!IsHva) {
1784  // Assign all Non-HVAs, so this will exclude Vector/FP args.
1785  I.info = classifyArgumentType(Ty, State);
1786  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1787  }
1788  }
1789 }
1790 
1791 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1792  CCState State(FI.getCallingConvention());
1793  if (IsMCUABI)
1794  State.FreeRegs = 3;
1795  else if (State.CC == llvm::CallingConv::X86_FastCall)
1796  State.FreeRegs = 2;
1797  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1798  State.FreeRegs = 2;
1799  State.FreeSSERegs = 6;
1800  } else if (FI.getHasRegParm())
1801  State.FreeRegs = FI.getRegParm();
1802  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1803  State.FreeRegs = 5;
1804  State.FreeSSERegs = 8;
1805  } else
1806  State.FreeRegs = DefaultNumRegisterParameters;
1807 
1808  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1810  } else if (FI.getReturnInfo().isIndirect()) {
1811  // The C++ ABI is not aware of register usage, so we have to check if the
1812  // return value was sret and put it in a register ourselves if appropriate.
1813  if (State.FreeRegs) {
1814  --State.FreeRegs; // The sret parameter consumes a register.
1815  if (!IsMCUABI)
1816  FI.getReturnInfo().setInReg(true);
1817  }
1818  }
1819 
1820  // The chain argument effectively gives us another free register.
1821  if (FI.isChainCall())
1822  ++State.FreeRegs;
1823 
1824  bool UsedInAlloca = false;
1825  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1826  computeVectorCallArgs(FI, State, UsedInAlloca);
1827  } else {
1828  // If not vectorcall, revert to normal behavior.
1829  for (auto &I : FI.arguments()) {
1830  I.info = classifyArgumentType(I.type, State);
1831  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1832  }
1833  }
1834 
1835  // If we needed to use inalloca for any argument, do a second pass and rewrite
1836  // all the memory arguments to use inalloca.
1837  if (UsedInAlloca)
1838  rewriteWithInAlloca(FI);
1839 }
1840 
1841 void
1842 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1843  CharUnits &StackOffset, ABIArgInfo &Info,
1844  QualType Type) const {
1845  // Arguments are always 4-byte-aligned.
1846  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1847 
1848  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1849  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1850  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1851  StackOffset += getContext().getTypeSizeInChars(Type);
1852 
1853  // Insert padding bytes to respect alignment.
1854  CharUnits FieldEnd = StackOffset;
1855  StackOffset = FieldEnd.alignTo(FieldAlign);
1856  if (StackOffset != FieldEnd) {
1857  CharUnits NumBytes = StackOffset - FieldEnd;
1858  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1859  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1860  FrameFields.push_back(Ty);
1861  }
1862 }
1863 
1864 static bool isArgInAlloca(const ABIArgInfo &Info) {
1865  // Leave ignored and inreg arguments alone.
1866  switch (Info.getKind()) {
1867  case ABIArgInfo::InAlloca:
1868  return true;
1869  case ABIArgInfo::Indirect:
1870  assert(Info.getIndirectByVal());
1871  return true;
1872  case ABIArgInfo::Ignore:
1873  return false;
1874  case ABIArgInfo::Direct:
1875  case ABIArgInfo::Extend:
1876  if (Info.getInReg())
1877  return false;
1878  return true;
1879  case ABIArgInfo::Expand:
1881  // These are aggregate types which are never passed in registers when
1882  // inalloca is involved.
1883  return true;
1884  }
1885  llvm_unreachable("invalid enum");
1886 }
1887 
1888 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1889  assert(IsWin32StructABI && "inalloca only supported on win32");
1890 
1891  // Build a packed struct type for all of the arguments in memory.
1892  SmallVector<llvm::Type *, 6> FrameFields;
1893 
1894  // The stack alignment is always 4.
1895  CharUnits StackAlign = CharUnits::fromQuantity(4);
1896 
1897  CharUnits StackOffset;
1898  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1899 
1900  // Put 'this' into the struct before 'sret', if necessary.
1901  bool IsThisCall =
1902  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1903  ABIArgInfo &Ret = FI.getReturnInfo();
1904  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1905  isArgInAlloca(I->info)) {
1906  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1907  ++I;
1908  }
1909 
1910  // Put the sret parameter into the inalloca struct if it's in memory.
1911  if (Ret.isIndirect() && !Ret.getInReg()) {
1913  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1914  // On Windows, the hidden sret parameter is always returned in eax.
1915  Ret.setInAllocaSRet(IsWin32StructABI);
1916  }
1917 
1918  // Skip the 'this' parameter in ecx.
1919  if (IsThisCall)
1920  ++I;
1921 
1922  // Put arguments passed in memory into the struct.
1923  for (; I != E; ++I) {
1924  if (isArgInAlloca(I->info))
1925  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1926  }
1927 
1928  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1929  /*isPacked=*/true),
1930  StackAlign);
1931 }
1932 
1933 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1934  Address VAListAddr, QualType Ty) const {
1935 
1936  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1937 
1938  // x86-32 changes the alignment of certain arguments on the stack.
1939  //
1940  // Just messing with TypeInfo like this works because we never pass
1941  // anything indirectly.
1943  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1944 
1945  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1947  /*AllowHigherAlign*/ true);
1948 }
1949 
1950 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1951  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1952  assert(Triple.getArch() == llvm::Triple::x86);
1953 
1954  switch (Opts.getStructReturnConvention()) {
1956  break;
1957  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1958  return false;
1959  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1960  return true;
1961  }
1962 
1963  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1964  return true;
1965 
1966  switch (Triple.getOS()) {
1967  case llvm::Triple::DragonFly:
1968  case llvm::Triple::FreeBSD:
1969  case llvm::Triple::OpenBSD:
1970  case llvm::Triple::Win32:
1971  return true;
1972  default:
1973  return false;
1974  }
1975 }
1976 
1977 void X86_32TargetCodeGenInfo::setTargetAttributes(
1978  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1979  if (GV->isDeclaration())
1980  return;
1981  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1982  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1983  llvm::Function *Fn = cast<llvm::Function>(GV);
1984  Fn->addFnAttr("stackrealign");
1985  }
1986  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1987  llvm::Function *Fn = cast<llvm::Function>(GV);
1988  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1989  }
1990  }
1991 }
1992 
1993 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1995  llvm::Value *Address) const {
1996  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1997 
1998  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1999 
2000  // 0-7 are the eight integer registers; the order is different
2001  // on Darwin (for EH), but the range is the same.
2002  // 8 is %eip.
2003  AssignToArrayRange(Builder, Address, Four8, 0, 8);
2004 
2005  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2006  // 12-16 are st(0..4). Not sure why we stop at 4.
2007  // These have size 16, which is sizeof(long double) on
2008  // platforms with 8-byte alignment for that type.
2009  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2010  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2011 
2012  } else {
2013  // 9 is %eflags, which doesn't get a size on Darwin for some
2014  // reason.
2015  Builder.CreateAlignedStore(
2016  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2017  CharUnits::One());
2018 
2019  // 11-16 are st(0..5). Not sure why we stop at 5.
2020  // These have size 12, which is sizeof(long double) on
2021  // platforms with 4-byte alignment for that type.
2022  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2023  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2024  }
2025 
2026  return false;
2027 }
2028 
2029 //===----------------------------------------------------------------------===//
2030 // X86-64 ABI Implementation
2031 //===----------------------------------------------------------------------===//
2032 
2033 
2034 namespace {
2035 /// The AVX ABI level for X86 targets.
2036 enum class X86AVXABILevel {
2037  None,
2038  AVX,
2039  AVX512
2040 };
2041 
2042 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2043 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2044  switch (AVXLevel) {
2045  case X86AVXABILevel::AVX512:
2046  return 512;
2047  case X86AVXABILevel::AVX:
2048  return 256;
2049  case X86AVXABILevel::None:
2050  return 128;
2051  }
2052  llvm_unreachable("Unknown AVXLevel");
2053 }
2054 
2055 /// X86_64ABIInfo - The X86_64 ABI information.
2056 class X86_64ABIInfo : public SwiftABIInfo {
2057  enum Class {
2058  Integer = 0,
2059  SSE,
2060  SSEUp,
2061  X87,
2062  X87Up,
2063  ComplexX87,
2064  NoClass,
2065  Memory
2066  };
2067 
2068  /// merge - Implement the X86_64 ABI merging algorithm.
2069  ///
2070  /// Merge an accumulating classification \arg Accum with a field
2071  /// classification \arg Field.
2072  ///
2073  /// \param Accum - The accumulating classification. This should
2074  /// always be either NoClass or the result of a previous merge
2075  /// call. In addition, this should never be Memory (the caller
2076  /// should just return Memory for the aggregate).
2077  static Class merge(Class Accum, Class Field);
2078 
2079  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2080  ///
2081  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2082  /// final MEMORY or SSE classes when necessary.
2083  ///
2084  /// \param AggregateSize - The size of the current aggregate in
2085  /// the classification process.
2086  ///
2087  /// \param Lo - The classification for the parts of the type
2088  /// residing in the low word of the containing object.
2089  ///
2090  /// \param Hi - The classification for the parts of the type
2091  /// residing in the higher words of the containing object.
2092  ///
2093  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2094 
2095  /// classify - Determine the x86_64 register classes in which the
2096  /// given type T should be passed.
2097  ///
2098  /// \param Lo - The classification for the parts of the type
2099  /// residing in the low word of the containing object.
2100  ///
2101  /// \param Hi - The classification for the parts of the type
2102  /// residing in the high word of the containing object.
2103  ///
2104  /// \param OffsetBase - The bit offset of this type in the
2105  /// containing object. Some parameters are classified different
2106  /// depending on whether they straddle an eightbyte boundary.
2107  ///
2108  /// \param isNamedArg - Whether the argument in question is a "named"
2109  /// argument, as used in AMD64-ABI 3.5.7.
2110  ///
2111  /// If a word is unused its result will be NoClass; if a type should
2112  /// be passed in Memory then at least the classification of \arg Lo
2113  /// will be Memory.
2114  ///
2115  /// The \arg Lo class will be NoClass iff the argument is ignored.
2116  ///
2117  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2118  /// also be ComplexX87.
2119  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2120  bool isNamedArg) const;
2121 
2122  llvm::Type *GetByteVectorType(QualType Ty) const;
2123  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2124  unsigned IROffset, QualType SourceTy,
2125  unsigned SourceOffset) const;
2126  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2127  unsigned IROffset, QualType SourceTy,
2128  unsigned SourceOffset) const;
2129 
2130  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2131  /// such that the argument will be returned in memory.
2132  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2133 
2134  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2135  /// such that the argument will be passed in memory.
2136  ///
2137  /// \param freeIntRegs - The number of free integer registers remaining
2138  /// available.
2139  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2140 
2141  ABIArgInfo classifyReturnType(QualType RetTy) const;
2142 
2143  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2144  unsigned &neededInt, unsigned &neededSSE,
2145  bool isNamedArg) const;
2146 
2147  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2148  unsigned &NeededSSE) const;
2149 
2150  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2151  unsigned &NeededSSE) const;
2152 
2153  bool IsIllegalVectorType(QualType Ty) const;
2154 
2155  /// The 0.98 ABI revision clarified a lot of ambiguities,
2156  /// unfortunately in ways that were not always consistent with
2157  /// certain previous compilers. In particular, platforms which
2158  /// required strict binary compatibility with older versions of GCC
2159  /// may need to exempt themselves.
2160  bool honorsRevision0_98() const {
2161  return !getTarget().getTriple().isOSDarwin();
2162  }
2163 
2164  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2165  /// classify it as INTEGER (for compatibility with older clang compilers).
2166  bool classifyIntegerMMXAsSSE() const {
2167  // Clang <= 3.8 did not do this.
2168  if (getContext().getLangOpts().getClangABICompat() <=
2170  return false;
2171 
2172  const llvm::Triple &Triple = getTarget().getTriple();
2173  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2174  return false;
2175  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2176  return false;
2177  return true;
2178  }
2179 
2180  X86AVXABILevel AVXLevel;
2181  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2182  // 64-bit hardware.
2183  bool Has64BitPointers;
2184 
2185 public:
2186  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2187  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2188  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2189  }
2190 
2191  bool isPassedUsingAVXType(QualType type) const {
2192  unsigned neededInt, neededSSE;
2193  // The freeIntRegs argument doesn't matter here.
2194  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2195  /*isNamedArg*/true);
2196  if (info.isDirect()) {
2197  llvm::Type *ty = info.getCoerceToType();
2198  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2199  return (vectorTy->getBitWidth() > 128);
2200  }
2201  return false;
2202  }
2203 
2204  void computeInfo(CGFunctionInfo &FI) const override;
2205 
2206  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2207  QualType Ty) const override;
2208  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2209  QualType Ty) const override;
2210 
2211  bool has64BitPointers() const {
2212  return Has64BitPointers;
2213  }
2214 
2215  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2216  bool asReturnValue) const override {
2217  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2218  }
2219  bool isSwiftErrorInRegister() const override {
2220  return true;
2221  }
2222 };
2223 
2224 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2225 class WinX86_64ABIInfo : public SwiftABIInfo {
2226 public:
2227  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2228  : SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2229  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2230 
2231  void computeInfo(CGFunctionInfo &FI) const override;
2232 
2233  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2234  QualType Ty) const override;
2235 
2236  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2237  // FIXME: Assumes vectorcall is in use.
2238  return isX86VectorTypeForVectorCall(getContext(), Ty);
2239  }
2240 
2241  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2242  uint64_t NumMembers) const override {
2243  // FIXME: Assumes vectorcall is in use.
2244  return isX86VectorCallAggregateSmallEnough(NumMembers);
2245  }
2246 
2247  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2248  bool asReturnValue) const override {
2249  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2250  }
2251 
2252  bool isSwiftErrorInRegister() const override {
2253  return true;
2254  }
2255 
2256 private:
2257  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2258  bool IsVectorCall, bool IsRegCall) const;
2259  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2260  const ABIArgInfo &current) const;
2261  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2262  bool IsVectorCall, bool IsRegCall) const;
2263 
2264  X86AVXABILevel AVXLevel;
2265 
2266  bool IsMingw64;
2267 };
2268 
2269 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2270 public:
2271  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2272  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2273 
2274  const X86_64ABIInfo &getABIInfo() const {
2275  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2276  }
2277 
2278  /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2279  /// the autoreleaseRV/retainRV optimization.
2280  bool shouldSuppressTailCallsOfRetainAutoreleasedReturnValue() const override {
2281  return true;
2282  }
2283 
2284  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2285  return 7;
2286  }
2287 
2288  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2289  llvm::Value *Address) const override {
2290  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2291 
2292  // 0-15 are the 16 integer registers.
2293  // 16 is %rip.
2294  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2295  return false;
2296  }
2297 
2298  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2299  StringRef Constraint,
2300  llvm::Type* Ty) const override {
2301  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2302  }
2303 
2304  bool isNoProtoCallVariadic(const CallArgList &args,
2305  const FunctionNoProtoType *fnType) const override {
2306  // The default CC on x86-64 sets %al to the number of SSA
2307  // registers used, and GCC sets this when calling an unprototyped
2308  // function, so we override the default behavior. However, don't do
2309  // that when AVX types are involved: the ABI explicitly states it is
2310  // undefined, and it doesn't work in practice because of how the ABI
2311  // defines varargs anyway.
2312  if (fnType->getCallConv() == CC_C) {
2313  bool HasAVXType = false;
2314  for (CallArgList::const_iterator
2315  it = args.begin(), ie = args.end(); it != ie; ++it) {
2316  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2317  HasAVXType = true;
2318  break;
2319  }
2320  }
2321 
2322  if (!HasAVXType)
2323  return true;
2324  }
2325 
2326  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2327  }
2328 
2329  llvm::Constant *
2330  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2331  unsigned Sig = (0xeb << 0) | // jmp rel8
2332  (0x06 << 8) | // .+0x08
2333  ('v' << 16) |
2334  ('2' << 24);
2335  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2336  }
2337 
2338  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2339  CodeGen::CodeGenModule &CGM) const override {
2340  if (GV->isDeclaration())
2341  return;
2342  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2343  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2344  llvm::Function *Fn = cast<llvm::Function>(GV);
2345  Fn->addFnAttr("stackrealign");
2346  }
2347  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2348  llvm::Function *Fn = cast<llvm::Function>(GV);
2349  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2350  }
2351  }
2352  }
2353 };
2354 
2355 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2356  // If the argument does not end in .lib, automatically add the suffix.
2357  // If the argument contains a space, enclose it in quotes.
2358  // This matches the behavior of MSVC.
2359  bool Quote = (Lib.find(" ") != StringRef::npos);
2360  std::string ArgStr = Quote ? "\"" : "";
2361  ArgStr += Lib;
2362  if (!Lib.endswith_lower(".lib") && !Lib.endswith_lower(".a"))
2363  ArgStr += ".lib";
2364  ArgStr += Quote ? "\"" : "";
2365  return ArgStr;
2366 }
2367 
2368 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2369 public:
2370  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2371  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2372  unsigned NumRegisterParameters)
2373  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2374  Win32StructABI, NumRegisterParameters, false) {}
2375 
2376  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2377  CodeGen::CodeGenModule &CGM) const override;
2378 
2379  void getDependentLibraryOption(llvm::StringRef Lib,
2380  llvm::SmallString<24> &Opt) const override {
2381  Opt = "/DEFAULTLIB:";
2382  Opt += qualifyWindowsLibrary(Lib);
2383  }
2384 
2385  void getDetectMismatchOption(llvm::StringRef Name,
2386  llvm::StringRef Value,
2387  llvm::SmallString<32> &Opt) const override {
2388  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2389  }
2390 };
2391 
2392 static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2393  CodeGen::CodeGenModule &CGM) {
2394  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2395 
2396  if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2397  Fn->addFnAttr("stack-probe-size",
2398  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2399  if (CGM.getCodeGenOpts().NoStackArgProbe)
2400  Fn->addFnAttr("no-stack-arg-probe");
2401  }
2402 }
2403 
2404 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2405  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2406  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2407  if (GV->isDeclaration())
2408  return;
2409  addStackProbeTargetAttributes(D, GV, CGM);
2410 }
2411 
2412 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2413 public:
2414  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2415  X86AVXABILevel AVXLevel)
2416  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT, AVXLevel)) {}
2417 
2418  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2419  CodeGen::CodeGenModule &CGM) const override;
2420 
2421  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2422  return 7;
2423  }
2424 
2425  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2426  llvm::Value *Address) const override {
2427  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2428 
2429  // 0-15 are the 16 integer registers.
2430  // 16 is %rip.
2431  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2432  return false;
2433  }
2434 
2435  void getDependentLibraryOption(llvm::StringRef Lib,
2436  llvm::SmallString<24> &Opt) const override {
2437  Opt = "/DEFAULTLIB:";
2438  Opt += qualifyWindowsLibrary(Lib);
2439  }
2440 
2441  void getDetectMismatchOption(llvm::StringRef Name,
2442  llvm::StringRef Value,
2443  llvm::SmallString<32> &Opt) const override {
2444  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2445  }
2446 };
2447 
2448 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2449  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2451  if (GV->isDeclaration())
2452  return;
2453  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2454  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2455  llvm::Function *Fn = cast<llvm::Function>(GV);
2456  Fn->addFnAttr("stackrealign");
2457  }
2458  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2459  llvm::Function *Fn = cast<llvm::Function>(GV);
2460  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2461  }
2462  }
2463 
2464  addStackProbeTargetAttributes(D, GV, CGM);
2465 }
2466 }
2467 
2468 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2469  Class &Hi) const {
2470  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2471  //
2472  // (a) If one of the classes is Memory, the whole argument is passed in
2473  // memory.
2474  //
2475  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2476  // memory.
2477  //
2478  // (c) If the size of the aggregate exceeds two eightbytes and the first
2479  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2480  // argument is passed in memory. NOTE: This is necessary to keep the
2481  // ABI working for processors that don't support the __m256 type.
2482  //
2483  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2484  //
2485  // Some of these are enforced by the merging logic. Others can arise
2486  // only with unions; for example:
2487  // union { _Complex double; unsigned; }
2488  //
2489  // Note that clauses (b) and (c) were added in 0.98.
2490  //
2491  if (Hi == Memory)
2492  Lo = Memory;
2493  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2494  Lo = Memory;
2495  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2496  Lo = Memory;
2497  if (Hi == SSEUp && Lo != SSE)
2498  Hi = SSE;
2499 }
2500 
2501 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2502  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2503  // classified recursively so that always two fields are
2504  // considered. The resulting class is calculated according to
2505  // the classes of the fields in the eightbyte:
2506  //
2507  // (a) If both classes are equal, this is the resulting class.
2508  //
2509  // (b) If one of the classes is NO_CLASS, the resulting class is
2510  // the other class.
2511  //
2512  // (c) If one of the classes is MEMORY, the result is the MEMORY
2513  // class.
2514  //
2515  // (d) If one of the classes is INTEGER, the result is the
2516  // INTEGER.
2517  //
2518  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2519  // MEMORY is used as class.
2520  //
2521  // (f) Otherwise class SSE is used.
2522 
2523  // Accum should never be memory (we should have returned) or
2524  // ComplexX87 (because this cannot be passed in a structure).
2525  assert((Accum != Memory && Accum != ComplexX87) &&
2526  "Invalid accumulated classification during merge.");
2527  if (Accum == Field || Field == NoClass)
2528  return Accum;
2529  if (Field == Memory)
2530  return Memory;
2531  if (Accum == NoClass)
2532  return Field;
2533  if (Accum == Integer || Field == Integer)
2534  return Integer;
2535  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2536  Accum == X87 || Accum == X87Up)
2537  return Memory;
2538  return SSE;
2539 }
2540 
2541 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2542  Class &Lo, Class &Hi, bool isNamedArg) const {
2543  // FIXME: This code can be simplified by introducing a simple value class for
2544  // Class pairs with appropriate constructor methods for the various
2545  // situations.
2546 
2547  // FIXME: Some of the split computations are wrong; unaligned vectors
2548  // shouldn't be passed in registers for example, so there is no chance they
2549  // can straddle an eightbyte. Verify & simplify.
2550 
2551  Lo = Hi = NoClass;
2552 
2553  Class &Current = OffsetBase < 64 ? Lo : Hi;
2554  Current = Memory;
2555 
2556  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2557  BuiltinType::Kind k = BT->getKind();
2558 
2559  if (k == BuiltinType::Void) {
2560  Current = NoClass;
2561  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2562  Lo = Integer;
2563  Hi = Integer;
2564  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2565  Current = Integer;
2566  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2567  Current = SSE;
2568  } else if (k == BuiltinType::LongDouble) {
2569  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2570  if (LDF == &llvm::APFloat::IEEEquad()) {
2571  Lo = SSE;
2572  Hi = SSEUp;
2573  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2574  Lo = X87;
2575  Hi = X87Up;
2576  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2577  Current = SSE;
2578  } else
2579  llvm_unreachable("unexpected long double representation!");
2580  }
2581  // FIXME: _Decimal32 and _Decimal64 are SSE.
2582  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2583  return;
2584  }
2585 
2586  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2587  // Classify the underlying integer type.
2588  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2589  return;
2590  }
2591 
2592  if (Ty->hasPointerRepresentation()) {
2593  Current = Integer;
2594  return;
2595  }
2596 
2597  if (Ty->isMemberPointerType()) {
2598  if (Ty->isMemberFunctionPointerType()) {
2599  if (Has64BitPointers) {
2600  // If Has64BitPointers, this is an {i64, i64}, so classify both
2601  // Lo and Hi now.
2602  Lo = Hi = Integer;
2603  } else {
2604  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2605  // straddles an eightbyte boundary, Hi should be classified as well.
2606  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2607  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2608  if (EB_FuncPtr != EB_ThisAdj) {
2609  Lo = Hi = Integer;
2610  } else {
2611  Current = Integer;
2612  }
2613  }
2614  } else {
2615  Current = Integer;
2616  }
2617  return;
2618  }
2619 
2620  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2621  uint64_t Size = getContext().getTypeSize(VT);
2622  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2623  // gcc passes the following as integer:
2624  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2625  // 2 bytes - <2 x char>, <1 x short>
2626  // 1 byte - <1 x char>
2627  Current = Integer;
2628 
2629  // If this type crosses an eightbyte boundary, it should be
2630  // split.
2631  uint64_t EB_Lo = (OffsetBase) / 64;
2632  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2633  if (EB_Lo != EB_Hi)
2634  Hi = Lo;
2635  } else if (Size == 64) {
2636  QualType ElementType = VT->getElementType();
2637 
2638  // gcc passes <1 x double> in memory. :(
2639  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2640  return;
2641 
2642  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2643  // pass them as integer. For platforms where clang is the de facto
2644  // platform compiler, we must continue to use integer.
2645  if (!classifyIntegerMMXAsSSE() &&
2646  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2647  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2648  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2649  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2650  Current = Integer;
2651  else
2652  Current = SSE;
2653 
2654  // If this type crosses an eightbyte boundary, it should be
2655  // split.
2656  if (OffsetBase && OffsetBase != 64)
2657  Hi = Lo;
2658  } else if (Size == 128 ||
2659  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2660  // Arguments of 256-bits are split into four eightbyte chunks. The
2661  // least significant one belongs to class SSE and all the others to class
2662  // SSEUP. The original Lo and Hi design considers that types can't be
2663  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2664  // This design isn't correct for 256-bits, but since there're no cases
2665  // where the upper parts would need to be inspected, avoid adding
2666  // complexity and just consider Hi to match the 64-256 part.
2667  //
2668  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2669  // registers if they are "named", i.e. not part of the "..." of a
2670  // variadic function.
2671  //
2672  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2673  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2674  Lo = SSE;
2675  Hi = SSEUp;
2676  }
2677  return;
2678  }
2679 
2680  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2681  QualType ET = getContext().getCanonicalType(CT->getElementType());
2682 
2683  uint64_t Size = getContext().getTypeSize(Ty);
2684  if (ET->isIntegralOrEnumerationType()) {
2685  if (Size <= 64)
2686  Current = Integer;
2687  else if (Size <= 128)
2688  Lo = Hi = Integer;
2689  } else if (ET == getContext().FloatTy) {
2690  Current = SSE;
2691  } else if (ET == getContext().DoubleTy) {
2692  Lo = Hi = SSE;
2693  } else if (ET == getContext().LongDoubleTy) {
2694  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2695  if (LDF == &llvm::APFloat::IEEEquad())
2696  Current = Memory;
2697  else if (LDF == &llvm::APFloat::x87DoubleExtended())
2698  Current = ComplexX87;
2699  else if (LDF == &llvm::APFloat::IEEEdouble())
2700  Lo = Hi = SSE;
2701  else
2702  llvm_unreachable("unexpected long double representation!");
2703  }
2704 
2705  // If this complex type crosses an eightbyte boundary then it
2706  // should be split.
2707  uint64_t EB_Real = (OffsetBase) / 64;
2708  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2709  if (Hi == NoClass && EB_Real != EB_Imag)
2710  Hi = Lo;
2711 
2712  return;
2713  }
2714 
2715  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2716  // Arrays are treated like structures.
2717 
2718  uint64_t Size = getContext().getTypeSize(Ty);
2719 
2720  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2721  // than eight eightbytes, ..., it has class MEMORY.
2722  if (Size > 512)
2723  return;
2724 
2725  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2726  // fields, it has class MEMORY.
2727  //
2728  // Only need to check alignment of array base.
2729  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2730  return;
2731 
2732  // Otherwise implement simplified merge. We could be smarter about
2733  // this, but it isn't worth it and would be harder to verify.
2734  Current = NoClass;
2735  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2736  uint64_t ArraySize = AT->getSize().getZExtValue();
2737 
2738  // The only case a 256-bit wide vector could be used is when the array
2739  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2740  // to work for sizes wider than 128, early check and fallback to memory.
2741  //
2742  if (Size > 128 &&
2743  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2744  return;
2745 
2746  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2747  Class FieldLo, FieldHi;
2748  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2749  Lo = merge(Lo, FieldLo);
2750  Hi = merge(Hi, FieldHi);
2751  if (Lo == Memory || Hi == Memory)
2752  break;
2753  }
2754 
2755  postMerge(Size, Lo, Hi);
2756  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2757  return;
2758  }
2759 
2760  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2761  uint64_t Size = getContext().getTypeSize(Ty);
2762 
2763  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2764  // than eight eightbytes, ..., it has class MEMORY.
2765  if (Size > 512)
2766  return;
2767 
2768  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2769  // copy constructor or a non-trivial destructor, it is passed by invisible
2770  // reference.
2771  if (getRecordArgABI(RT, getCXXABI()))
2772  return;
2773 
2774  const RecordDecl *RD = RT->getDecl();
2775 
2776  // Assume variable sized types are passed in memory.
2777  if (RD->hasFlexibleArrayMember())
2778  return;
2779 
2780  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2781 
2782  // Reset Lo class, this will be recomputed.
2783  Current = NoClass;
2784 
2785  // If this is a C++ record, classify the bases first.
2786  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2787  for (const auto &I : CXXRD->bases()) {
2788  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2789  "Unexpected base class!");
2790  const CXXRecordDecl *Base =
2791  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2792 
2793  // Classify this field.
2794  //
2795  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2796  // single eightbyte, each is classified separately. Each eightbyte gets
2797  // initialized to class NO_CLASS.
2798  Class FieldLo, FieldHi;
2799  uint64_t Offset =
2800  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2801  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2802  Lo = merge(Lo, FieldLo);
2803  Hi = merge(Hi, FieldHi);
2804  if (Lo == Memory || Hi == Memory) {
2805  postMerge(Size, Lo, Hi);
2806  return;
2807  }
2808  }
2809  }
2810 
2811  // Classify the fields one at a time, merging the results.
2812  unsigned idx = 0;
2813  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2814  i != e; ++i, ++idx) {
2815  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2816  bool BitField = i->isBitField();
2817 
2818  // Ignore padding bit-fields.
2819  if (BitField && i->isUnnamedBitfield())
2820  continue;
2821 
2822  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2823  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2824  //
2825  // The only case a 256-bit wide vector could be used is when the struct
2826  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2827  // to work for sizes wider than 128, early check and fallback to memory.
2828  //
2829  if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2830  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2831  Lo = Memory;
2832  postMerge(Size, Lo, Hi);
2833  return;
2834  }
2835  // Note, skip this test for bit-fields, see below.
2836  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2837  Lo = Memory;
2838  postMerge(Size, Lo, Hi);
2839  return;
2840  }
2841 
2842  // Classify this field.
2843  //
2844  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2845  // exceeds a single eightbyte, each is classified
2846  // separately. Each eightbyte gets initialized to class
2847  // NO_CLASS.
2848  Class FieldLo, FieldHi;
2849 
2850  // Bit-fields require special handling, they do not force the
2851  // structure to be passed in memory even if unaligned, and
2852  // therefore they can straddle an eightbyte.
2853  if (BitField) {
2854  assert(!i->isUnnamedBitfield());
2855  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2856  uint64_t Size = i->getBitWidthValue(getContext());
2857 
2858  uint64_t EB_Lo = Offset / 64;
2859  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2860 
2861  if (EB_Lo) {
2862  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2863  FieldLo = NoClass;
2864  FieldHi = Integer;
2865  } else {
2866  FieldLo = Integer;
2867  FieldHi = EB_Hi ? Integer : NoClass;
2868  }
2869  } else
2870  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2871  Lo = merge(Lo, FieldLo);
2872  Hi = merge(Hi, FieldHi);
2873  if (Lo == Memory || Hi == Memory)
2874  break;
2875  }
2876 
2877  postMerge(Size, Lo, Hi);
2878  }
2879 }
2880 
2881 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2882  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2883  // place naturally.
2884  if (!isAggregateTypeForABI(Ty)) {
2885  // Treat an enum type as its underlying type.
2886  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2887  Ty = EnumTy->getDecl()->getIntegerType();
2888 
2890  : ABIArgInfo::getDirect());
2891  }
2892 
2893  return getNaturalAlignIndirect(Ty);
2894 }
2895 
2896 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2897  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2898  uint64_t Size = getContext().getTypeSize(VecTy);
2899  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2900  if (Size <= 64 || Size > LargestVector)
2901  return true;
2902  }
2903 
2904  return false;
2905 }
2906 
2907 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2908  unsigned freeIntRegs) const {
2909  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2910  // place naturally.
2911  //
2912  // This assumption is optimistic, as there could be free registers available
2913  // when we need to pass this argument in memory, and LLVM could try to pass
2914  // the argument in the free register. This does not seem to happen currently,
2915  // but this code would be much safer if we could mark the argument with
2916  // 'onstack'. See PR12193.
2917  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2918  // Treat an enum type as its underlying type.
2919  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2920  Ty = EnumTy->getDecl()->getIntegerType();
2921 
2923  : ABIArgInfo::getDirect());
2924  }
2925 
2928 
2929  // Compute the byval alignment. We specify the alignment of the byval in all
2930  // cases so that the mid-level optimizer knows the alignment of the byval.
2931  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2932 
2933  // Attempt to avoid passing indirect results using byval when possible. This
2934  // is important for good codegen.
2935  //
2936  // We do this by coercing the value into a scalar type which the backend can
2937  // handle naturally (i.e., without using byval).
2938  //
2939  // For simplicity, we currently only do this when we have exhausted all of the
2940  // free integer registers. Doing this when there are free integer registers
2941  // would require more care, as we would have to ensure that the coerced value
2942  // did not claim the unused register. That would require either reording the
2943  // arguments to the function (so that any subsequent inreg values came first),
2944  // or only doing this optimization when there were no following arguments that
2945  // might be inreg.
2946  //
2947  // We currently expect it to be rare (particularly in well written code) for
2948  // arguments to be passed on the stack when there are still free integer
2949  // registers available (this would typically imply large structs being passed
2950  // by value), so this seems like a fair tradeoff for now.
2951  //
2952  // We can revisit this if the backend grows support for 'onstack' parameter
2953  // attributes. See PR12193.
2954  if (freeIntRegs == 0) {
2955  uint64_t Size = getContext().getTypeSize(Ty);
2956 
2957  // If this type fits in an eightbyte, coerce it into the matching integral
2958  // type, which will end up on the stack (with alignment 8).
2959  if (Align == 8 && Size <= 64)
2960  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2961  Size));
2962  }
2963 
2965 }
2966 
2967 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2968 /// register. Pick an LLVM IR type that will be passed as a vector register.
2969 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2970  // Wrapper structs/arrays that only contain vectors are passed just like
2971  // vectors; strip them off if present.
2972  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2973  Ty = QualType(InnerTy, 0);
2974 
2975  llvm::Type *IRType = CGT.ConvertType(Ty);
2976  if (isa<llvm::VectorType>(IRType) ||
2977  IRType->getTypeID() == llvm::Type::FP128TyID)
2978  return IRType;
2979 
2980  // We couldn't find the preferred IR vector type for 'Ty'.
2981  uint64_t Size = getContext().getTypeSize(Ty);
2982  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2983 
2984  // Return a LLVM IR vector type based on the size of 'Ty'.
2985  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2986  Size / 64);
2987 }
2988 
2989 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2990 /// is known to either be off the end of the specified type or being in
2991 /// alignment padding. The user type specified is known to be at most 128 bits
2992 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2993 /// classification that put one of the two halves in the INTEGER class.
2994 ///
2995 /// It is conservatively correct to return false.
2996 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2997  unsigned EndBit, ASTContext &Context) {
2998  // If the bytes being queried are off the end of the type, there is no user
2999  // data hiding here. This handles analysis of builtins, vectors and other
3000  // types that don't contain interesting padding.
3001  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3002  if (TySize <= StartBit)
3003  return true;
3004 
3005  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3006  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3007  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3008 
3009  // Check each element to see if the element overlaps with the queried range.
3010  for (unsigned i = 0; i != NumElts; ++i) {
3011  // If the element is after the span we care about, then we're done..
3012  unsigned EltOffset = i*EltSize;
3013  if (EltOffset >= EndBit) break;
3014 
3015  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
3016  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3017  EndBit-EltOffset, Context))
3018  return false;
3019  }
3020  // If it overlaps no elements, then it is safe to process as padding.
3021  return true;
3022  }
3023 
3024  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3025  const RecordDecl *RD = RT->getDecl();
3026  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3027 
3028  // If this is a C++ record, check the bases first.
3029  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3030  for (const auto &I : CXXRD->bases()) {
3031  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3032  "Unexpected base class!");
3033  const CXXRecordDecl *Base =
3034  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3035 
3036  // If the base is after the span we care about, ignore it.
3037  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3038  if (BaseOffset >= EndBit) continue;
3039 
3040  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3041  if (!BitsContainNoUserData(I.getType(), BaseStart,
3042  EndBit-BaseOffset, Context))
3043  return false;
3044  }
3045  }
3046 
3047  // Verify that no field has data that overlaps the region of interest. Yes
3048  // this could be sped up a lot by being smarter about queried fields,
3049  // however we're only looking at structs up to 16 bytes, so we don't care
3050  // much.
3051  unsigned idx = 0;
3052  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3053  i != e; ++i, ++idx) {
3054  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3055 
3056  // If we found a field after the region we care about, then we're done.
3057  if (FieldOffset >= EndBit) break;
3058 
3059  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3060  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3061  Context))
3062  return false;
3063  }
3064 
3065  // If nothing in this record overlapped the area of interest, then we're
3066  // clean.
3067  return true;
3068  }
3069 
3070  return false;
3071 }
3072 
3073 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3074 /// float member at the specified offset. For example, {int,{float}} has a
3075 /// float at offset 4. It is conservatively correct for this routine to return
3076 /// false.
3077 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3078  const llvm::DataLayout &TD) {
3079  // Base case if we find a float.
3080  if (IROffset == 0 && IRType->isFloatTy())
3081  return true;
3082 
3083  // If this is a struct, recurse into the field at the specified offset.
3084  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3085  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3086  unsigned Elt = SL->getElementContainingOffset(IROffset);
3087  IROffset -= SL->getElementOffset(Elt);
3088  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3089  }
3090 
3091  // If this is an array, recurse into the field at the specified offset.
3092  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3093  llvm::Type *EltTy = ATy->getElementType();
3094  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3095  IROffset -= IROffset/EltSize*EltSize;
3096  return ContainsFloatAtOffset(EltTy, IROffset, TD);
3097  }
3098 
3099  return false;
3100 }
3101 
3102 
3103 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3104 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3105 llvm::Type *X86_64ABIInfo::
3106 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3107  QualType SourceTy, unsigned SourceOffset) const {
3108  // The only three choices we have are either double, <2 x float>, or float. We
3109  // pass as float if the last 4 bytes is just padding. This happens for
3110  // structs that contain 3 floats.
3111  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3112  SourceOffset*8+64, getContext()))
3113  return llvm::Type::getFloatTy(getVMContext());
3114 
3115  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3116  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3117  // case.
3118  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3119  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3120  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3121 
3122  return llvm::Type::getDoubleTy(getVMContext());
3123 }
3124 
3125 
3126 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3127 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3128 /// about the high or low part of an up-to-16-byte struct. This routine picks
3129 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3130 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3131 /// etc).
3132 ///
3133 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3134 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3135 /// the 8-byte value references. PrefType may be null.
3136 ///
3137 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3138 /// an offset into this that we're processing (which is always either 0 or 8).
3139 ///
3140 llvm::Type *X86_64ABIInfo::
3141 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3142  QualType SourceTy, unsigned SourceOffset) const {
3143  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3144  // returning an 8-byte unit starting with it. See if we can safely use it.
3145  if (IROffset == 0) {
3146  // Pointers and int64's always fill the 8-byte unit.
3147  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3148  IRType->isIntegerTy(64))
3149  return IRType;
3150 
3151  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3152  // goodness in the source type is just tail padding. This is allowed to
3153  // kick in for struct {double,int} on the int, but not on
3154  // struct{double,int,int} because we wouldn't return the second int. We
3155  // have to do this analysis on the source type because we can't depend on
3156  // unions being lowered a specific way etc.
3157  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3158  IRType->isIntegerTy(32) ||
3159  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3160  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3161  cast<llvm::IntegerType>(IRType)->getBitWidth();
3162 
3163  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3164  SourceOffset*8+64, getContext()))
3165  return IRType;
3166  }
3167  }
3168 
3169  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3170  // If this is a struct, recurse into the field at the specified offset.
3171  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3172  if (IROffset < SL->getSizeInBytes()) {
3173  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3174  IROffset -= SL->getElementOffset(FieldIdx);
3175 
3176  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3177  SourceTy, SourceOffset);
3178  }
3179  }
3180 
3181  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3182  llvm::Type *EltTy = ATy->getElementType();
3183  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3184  unsigned EltOffset = IROffset/EltSize*EltSize;
3185  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3186  SourceOffset);
3187  }
3188 
3189  // Okay, we don't have any better idea of what to pass, so we pass this in an
3190  // integer register that isn't too big to fit the rest of the struct.
3191  unsigned TySizeInBytes =
3192  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3193 
3194  assert(TySizeInBytes != SourceOffset && "Empty field?");
3195 
3196  // It is always safe to classify this as an integer type up to i64 that
3197  // isn't larger than the structure.
3198  return llvm::IntegerType::get(getVMContext(),
3199  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3200 }
3201 
3202 
3203 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3204 /// be used as elements of a two register pair to pass or return, return a
3205 /// first class aggregate to represent them. For example, if the low part of
3206 /// a by-value argument should be passed as i32* and the high part as float,
3207 /// return {i32*, float}.
3208 static llvm::Type *
3210  const llvm::DataLayout &TD) {
3211  // In order to correctly satisfy the ABI, we need to the high part to start
3212  // at offset 8. If the high and low parts we inferred are both 4-byte types
3213  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3214  // the second element at offset 8. Check for this:
3215  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3216  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3217  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3218  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3219 
3220  // To handle this, we have to increase the size of the low part so that the
3221  // second element will start at an 8 byte offset. We can't increase the size
3222  // of the second element because it might make us access off the end of the
3223  // struct.
3224  if (HiStart != 8) {
3225  // There are usually two sorts of types the ABI generation code can produce
3226  // for the low part of a pair that aren't 8 bytes in size: float or
3227  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3228  // NaCl).
3229  // Promote these to a larger type.
3230  if (Lo->isFloatTy())
3231  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3232  else {
3233  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3234  && "Invalid/unknown lo type");
3235  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3236  }
3237  }
3238 
3239  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3240 
3241  // Verify that the second element is at an 8-byte offset.
3242  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3243  "Invalid x86-64 argument pair!");
3244  return Result;
3245 }
3246 
3248 classifyReturnType(QualType RetTy) const {
3249  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3250  // classification algorithm.
3251  X86_64ABIInfo::Class Lo, Hi;
3252  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3253 
3254  // Check some invariants.
3255  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3256  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3257 
3258  llvm::Type *ResType = nullptr;
3259  switch (Lo) {
3260  case NoClass:
3261  if (Hi == NoClass)
3262  return ABIArgInfo::getIgnore();
3263  // If the low part is just padding, it takes no register, leave ResType
3264  // null.
3265  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3266  "Unknown missing lo part");
3267  break;
3268 
3269  case SSEUp:
3270  case X87Up:
3271  llvm_unreachable("Invalid classification for lo word.");
3272 
3273  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3274  // hidden argument.
3275  case Memory:
3276  return getIndirectReturnResult(RetTy);
3277 
3278  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3279  // available register of the sequence %rax, %rdx is used.
3280  case Integer:
3281  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3282 
3283  // If we have a sign or zero extended integer, make sure to return Extend
3284  // so that the parameter gets the right LLVM IR attributes.
3285  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3286  // Treat an enum type as its underlying type.
3287  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3288  RetTy = EnumTy->getDecl()->getIntegerType();
3289 
3290  if (RetTy->isIntegralOrEnumerationType() &&
3291  RetTy->isPromotableIntegerType())
3292  return ABIArgInfo::getExtend(RetTy);
3293  }
3294  break;
3295 
3296  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3297  // available SSE register of the sequence %xmm0, %xmm1 is used.
3298  case SSE:
3299  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3300  break;
3301 
3302  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3303  // returned on the X87 stack in %st0 as 80-bit x87 number.
3304  case X87:
3305  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3306  break;
3307 
3308  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3309  // part of the value is returned in %st0 and the imaginary part in
3310  // %st1.
3311  case ComplexX87:
3312  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3313  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3314  llvm::Type::getX86_FP80Ty(getVMContext()));
3315  break;
3316  }
3317 
3318  llvm::Type *HighPart = nullptr;
3319  switch (Hi) {
3320  // Memory was handled previously and X87 should
3321  // never occur as a hi class.
3322  case Memory:
3323  case X87:
3324  llvm_unreachable("Invalid classification for hi word.");
3325 
3326  case ComplexX87: // Previously handled.
3327  case NoClass:
3328  break;
3329 
3330  case Integer:
3331  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3332  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3333  return ABIArgInfo::getDirect(HighPart, 8);
3334  break;
3335  case SSE:
3336  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3337  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3338  return ABIArgInfo::getDirect(HighPart, 8);
3339  break;
3340 
3341  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3342  // is passed in the next available eightbyte chunk if the last used
3343  // vector register.
3344  //
3345  // SSEUP should always be preceded by SSE, just widen.
3346  case SSEUp:
3347  assert(Lo == SSE && "Unexpected SSEUp classification.");
3348  ResType = GetByteVectorType(RetTy);
3349  break;
3350 
3351  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3352  // returned together with the previous X87 value in %st0.
3353  case X87Up:
3354  // If X87Up is preceded by X87, we don't need to do
3355  // anything. However, in some cases with unions it may not be
3356  // preceded by X87. In such situations we follow gcc and pass the
3357  // extra bits in an SSE reg.
3358  if (Lo != X87) {
3359  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3360  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3361  return ABIArgInfo::getDirect(HighPart, 8);
3362  }
3363  break;
3364  }
3365 
3366  // If a high part was specified, merge it together with the low part. It is
3367  // known to pass in the high eightbyte of the result. We do this by forming a
3368  // first class struct aggregate with the high and low part: {low, high}
3369  if (HighPart)
3370  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3371 
3372  return ABIArgInfo::getDirect(ResType);
3373 }
3374 
3376  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3377  bool isNamedArg)
3378  const
3379 {
3381 
3382  X86_64ABIInfo::Class Lo, Hi;
3383  classify(Ty, 0, Lo, Hi, isNamedArg);
3384 
3385  // Check some invariants.
3386  // FIXME: Enforce these by construction.
3387  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3388  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3389 
3390  neededInt = 0;
3391  neededSSE = 0;
3392  llvm::Type *ResType = nullptr;
3393  switch (Lo) {
3394  case NoClass:
3395  if (Hi == NoClass)
3396  return ABIArgInfo::getIgnore();
3397  // If the low part is just padding, it takes no register, leave ResType
3398  // null.
3399  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3400  "Unknown missing lo part");
3401  break;
3402 
3403  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3404  // on the stack.
3405  case Memory:
3406 
3407  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3408  // COMPLEX_X87, it is passed in memory.
3409  case X87:
3410  case ComplexX87:
3412  ++neededInt;
3413  return getIndirectResult(Ty, freeIntRegs);
3414 
3415  case SSEUp:
3416  case X87Up:
3417  llvm_unreachable("Invalid classification for lo word.");
3418 
3419  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3420  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3421  // and %r9 is used.
3422  case Integer:
3423  ++neededInt;
3424 
3425  // Pick an 8-byte type based on the preferred type.
3426  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3427 
3428  // If we have a sign or zero extended integer, make sure to return Extend
3429  // so that the parameter gets the right LLVM IR attributes.
3430  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3431  // Treat an enum type as its underlying type.
3432  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3433  Ty = EnumTy->getDecl()->getIntegerType();
3434 
3435  if (Ty->isIntegralOrEnumerationType() &&
3437  return ABIArgInfo::getExtend(Ty);
3438  }
3439 
3440  break;
3441 
3442  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3443  // available SSE register is used, the registers are taken in the
3444  // order from %xmm0 to %xmm7.
3445  case SSE: {
3446  llvm::Type *IRType = CGT.ConvertType(Ty);
3447  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3448  ++neededSSE;
3449  break;
3450  }
3451  }
3452 
3453  llvm::Type *HighPart = nullptr;
3454  switch (Hi) {
3455  // Memory was handled previously, ComplexX87 and X87 should
3456  // never occur as hi classes, and X87Up must be preceded by X87,
3457  // which is passed in memory.
3458  case Memory:
3459  case X87:
3460  case ComplexX87:
3461  llvm_unreachable("Invalid classification for hi word.");
3462 
3463  case NoClass: break;
3464 
3465  case Integer:
3466  ++neededInt;
3467  // Pick an 8-byte type based on the preferred type.
3468  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3469 
3470  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3471  return ABIArgInfo::getDirect(HighPart, 8);
3472  break;
3473 
3474  // X87Up generally doesn't occur here (long double is passed in
3475  // memory), except in situations involving unions.
3476  case X87Up:
3477  case SSE:
3478  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3479 
3480  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3481  return ABIArgInfo::getDirect(HighPart, 8);
3482 
3483  ++neededSSE;
3484  break;
3485 
3486  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3487  // eightbyte is passed in the upper half of the last used SSE
3488  // register. This only happens when 128-bit vectors are passed.
3489  case SSEUp:
3490  assert(Lo == SSE && "Unexpected SSEUp classification");
3491  ResType = GetByteVectorType(Ty);
3492  break;
3493  }
3494 
3495  // If a high part was specified, merge it together with the low part. It is
3496  // known to pass in the high eightbyte of the result. We do this by forming a
3497  // first class struct aggregate with the high and low part: {low, high}
3498  if (HighPart)
3499  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3500 
3501  return ABIArgInfo::getDirect(ResType);
3502 }
3503 
3504 ABIArgInfo
3505 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3506  unsigned &NeededSSE) const {
3507  auto RT = Ty->getAs<RecordType>();
3508  assert(RT && "classifyRegCallStructType only valid with struct types");
3509 
3510  if (RT->getDecl()->hasFlexibleArrayMember())
3511  return getIndirectReturnResult(Ty);
3512 
3513  // Sum up bases
3514  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3515  if (CXXRD->isDynamicClass()) {
3516  NeededInt = NeededSSE = 0;
3517  return getIndirectReturnResult(Ty);
3518  }
3519 
3520  for (const auto &I : CXXRD->bases())
3521  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3522  .isIndirect()) {
3523  NeededInt = NeededSSE = 0;
3524  return getIndirectReturnResult(Ty);
3525  }
3526  }
3527 
3528  // Sum up members
3529  for (const auto *FD : RT->getDecl()->fields()) {
3530  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3531  if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3532  .isIndirect()) {
3533  NeededInt = NeededSSE = 0;
3534  return getIndirectReturnResult(Ty);
3535  }
3536  } else {
3537  unsigned LocalNeededInt, LocalNeededSSE;
3538  if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3539  LocalNeededSSE, true)
3540  .isIndirect()) {
3541  NeededInt = NeededSSE = 0;
3542  return getIndirectReturnResult(Ty);
3543  }
3544  NeededInt += LocalNeededInt;
3545  NeededSSE += LocalNeededSSE;
3546  }
3547  }
3548 
3549  return ABIArgInfo::getDirect();
3550 }
3551 
3552 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3553  unsigned &NeededInt,
3554  unsigned &NeededSSE) const {
3555 
3556  NeededInt = 0;
3557  NeededSSE = 0;
3558 
3559  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3560 }
3561 
3562 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3563 
3564  const unsigned CallingConv = FI.getCallingConvention();
3565  // It is possible to force Win64 calling convention on any x86_64 target by
3566  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3567  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3568  if (CallingConv == llvm::CallingConv::Win64) {
3569  WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
3570  Win64ABIInfo.computeInfo(FI);
3571  return;
3572  }
3573 
3574  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3575 
3576  // Keep track of the number of assigned registers.
3577  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3578  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3579  unsigned NeededInt, NeededSSE;
3580 
3581  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3582  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3583  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3584  FI.getReturnInfo() =
3585  classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3586  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3587  FreeIntRegs -= NeededInt;
3588  FreeSSERegs -= NeededSSE;
3589  } else {
3590  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3591  }
3592  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3593  // Complex Long Double Type is passed in Memory when Regcall
3594  // calling convention is used.
3595  const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3598  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3599  } else
3601  }
3602 
3603  // If the return value is indirect, then the hidden argument is consuming one
3604  // integer register.
3605  if (FI.getReturnInfo().isIndirect())
3606  --FreeIntRegs;
3607 
3608  // The chain argument effectively gives us another free register.
3609  if (FI.isChainCall())
3610  ++FreeIntRegs;
3611 
3612  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3613  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3614  // get assigned (in left-to-right order) for passing as follows...
3615  unsigned ArgNo = 0;
3616  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3617  it != ie; ++it, ++ArgNo) {
3618  bool IsNamedArg = ArgNo < NumRequiredArgs;
3619 
3620  if (IsRegCall && it->type->isStructureOrClassType())
3621  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3622  else
3623  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3624  NeededSSE, IsNamedArg);
3625 
3626  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3627  // eightbyte of an argument, the whole argument is passed on the
3628  // stack. If registers have already been assigned for some
3629  // eightbytes of such an argument, the assignments get reverted.
3630  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3631  FreeIntRegs -= NeededInt;
3632  FreeSSERegs -= NeededSSE;
3633  } else {
3634  it->info = getIndirectResult(it->type, FreeIntRegs);
3635  }
3636  }
3637 }
3638 
3640  Address VAListAddr, QualType Ty) {
3641  Address overflow_arg_area_p =
3642  CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
3643  llvm::Value *overflow_arg_area =
3644  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3645 
3646  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3647  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3648  // It isn't stated explicitly in the standard, but in practice we use
3649  // alignment greater than 16 where necessary.
3650  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3651  if (Align > CharUnits::fromQuantity(8)) {
3652  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3653  Align);
3654  }
3655 
3656  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3657  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3658  llvm::Value *Res =
3659  CGF.Builder.CreateBitCast(overflow_arg_area,
3660  llvm::PointerType::getUnqual(LTy));
3661 
3662  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3663  // l->overflow_arg_area + sizeof(type).
3664  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3665  // an 8 byte boundary.
3666 
3667  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3668  llvm::Value *Offset =
3669  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3670  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3671  "overflow_arg_area.next");
3672  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3673 
3674  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3675  return Address(Res, Align);
3676 }
3677 
3678 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3679  QualType Ty) const {
3680  // Assume that va_list type is correct; should be pointer to LLVM type:
3681  // struct {
3682  // i32 gp_offset;
3683  // i32 fp_offset;
3684  // i8* overflow_arg_area;
3685  // i8* reg_save_area;
3686  // };
3687  unsigned neededInt, neededSSE;
3688 
3689  Ty = getContext().getCanonicalType(Ty);
3690  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3691  /*isNamedArg*/false);
3692 
3693  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3694  // in the registers. If not go to step 7.
3695  if (!neededInt && !neededSSE)
3696  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3697 
3698  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3699  // general purpose registers needed to pass type and num_fp to hold
3700  // the number of floating point registers needed.
3701 
3702  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3703  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3704  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3705  //
3706  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3707  // register save space).
3708 
3709  llvm::Value *InRegs = nullptr;
3710  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3711  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3712  if (neededInt) {
3713  gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
3714  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3715  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3716  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3717  }
3718 
3719  if (neededSSE) {
3720  fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
3721  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3722  llvm::Value *FitsInFP =
3723  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3724  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3725  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3726  }
3727 
3728  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3729  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3730  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3731  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3732 
3733  // Emit code to load the value if it was passed in registers.
3734 
3735  CGF.EmitBlock(InRegBlock);
3736 
3737  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3738  // an offset of l->gp_offset and/or l->fp_offset. This may require
3739  // copying to a temporary location in case the parameter is passed
3740  // in different register classes or requires an alignment greater
3741  // than 8 for general purpose registers and 16 for XMM registers.
3742  //
3743  // FIXME: This really results in shameful code when we end up needing to
3744  // collect arguments from different places; often what should result in a
3745  // simple assembling of a structure from scattered addresses has many more
3746  // loads than necessary. Can we clean this up?
3747  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3748  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3749  CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
3750 
3751  Address RegAddr = Address::invalid();
3752  if (neededInt && neededSSE) {
3753  // FIXME: Cleanup.
3754  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3755  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3756  Address Tmp = CGF.CreateMemTemp(Ty);
3757  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3758  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3759  llvm::Type *TyLo = ST->getElementType(0);
3760  llvm::Type *TyHi = ST->getElementType(1);
3761  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3762  "Unexpected ABI info for mixed regs");
3763  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3764  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3765  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3766  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3767  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3768  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3769 
3770  // Copy the first element.
3771  // FIXME: Our choice of alignment here and below is probably pessimistic.
3773  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3774  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3775  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3776 
3777  // Copy the second element.
3778  V = CGF.Builder.CreateAlignedLoad(
3779  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3780  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3781  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3782 
3783  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3784  } else if (neededInt) {
3785  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3787  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3788 
3789  // Copy to a temporary if necessary to ensure the appropriate alignment.
3790  std::pair<CharUnits, CharUnits> SizeAlign =
3792  uint64_t TySize = SizeAlign.first.getQuantity();
3793  CharUnits TyAlign = SizeAlign.second;
3794 
3795  // Copy into a temporary if the type is more aligned than the
3796  // register save area.
3797  if (TyAlign.getQuantity() > 8) {
3798  Address Tmp = CGF.CreateMemTemp(Ty);
3799  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3800  RegAddr = Tmp;
3801  }
3802 
3803  } else if (neededSSE == 1) {
3804  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3806  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3807  } else {
3808  assert(neededSSE == 2 && "Invalid number of needed registers!");
3809  // SSE registers are spaced 16 bytes apart in the register save
3810  // area, we need to collect the two eightbytes together.
3811  // The ABI isn't explicit about this, but it seems reasonable
3812  // to assume that the slots are 16-byte aligned, since the stack is
3813  // naturally 16-byte aligned and the prologue is expected to store
3814  // all the SSE registers to the RSA.
3815  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3817  Address RegAddrHi =
3818  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3820  llvm::Type *ST = AI.canHaveCoerceToType()
3821  ? AI.getCoerceToType()
3822  : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3823  llvm::Value *V;
3824  Address Tmp = CGF.CreateMemTemp(Ty);
3825  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3827  RegAddrLo, ST->getStructElementType(0)));
3828  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3830  RegAddrHi, ST->getStructElementType(1)));
3831  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3832 
3833  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3834  }
3835 
3836  // AMD64-ABI 3.5.7p5: Step 5. Set:
3837  // l->gp_offset = l->gp_offset + num_gp * 8
3838  // l->fp_offset = l->fp_offset + num_fp * 16.
3839  if (neededInt) {
3840  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3841  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3842  gp_offset_p);
3843  }
3844  if (neededSSE) {
3845  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3846  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3847  fp_offset_p);
3848  }
3849  CGF.EmitBranch(ContBlock);
3850 
3851  // Emit code to load the value if it was passed in memory.
3852 
3853  CGF.EmitBlock(InMemBlock);
3854  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3855 
3856  // Return the appropriate result.
3857 
3858  CGF.EmitBlock(ContBlock);
3859  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3860  "vaarg.addr");
3861  return ResAddr;
3862 }
3863 
3864 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3865  QualType Ty) const {
3866  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3867  CGF.getContext().getTypeInfoInChars(Ty),
3869  /*allowHigherAlign*/ false);
3870 }
3871 
3872 ABIArgInfo
3873 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3874  const ABIArgInfo &current) const {
3875  // Assumes vectorCall calling convention.
3876  const Type *Base = nullptr;
3877  uint64_t NumElts = 0;
3878 
3879  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3880  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3881  FreeSSERegs -= NumElts;
3882  return getDirectX86Hva();
3883  }
3884  return current;
3885 }
3886 
3887 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3888  bool IsReturnType, bool IsVectorCall,
3889  bool IsRegCall) const {
3890 
3891  if (Ty->isVoidType())
3892  return ABIArgInfo::getIgnore();
3893 
3894  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3895  Ty = EnumTy->getDecl()->getIntegerType();
3896 
3897  TypeInfo Info = getContext().getTypeInfo(Ty);
3898  uint64_t Width = Info.Width;
3900 
3901  const RecordType *RT = Ty->getAs<RecordType>();
3902  if (RT) {
3903  if (!IsReturnType) {
3906  }
3907 
3908  if (RT->getDecl()->hasFlexibleArrayMember())
3909  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3910 
3911  }
3912 
3913  const Type *Base = nullptr;
3914  uint64_t NumElts = 0;
3915  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3916  // other targets.
3917  if ((IsVectorCall || IsRegCall) &&
3918  isHomogeneousAggregate(Ty, Base, NumElts)) {
3919  if (IsRegCall) {
3920  if (FreeSSERegs >= NumElts) {
3921  FreeSSERegs -= NumElts;
3922  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3923  return ABIArgInfo::getDirect();
3924  return ABIArgInfo::getExpand();
3925  }
3926  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3927  } else if (IsVectorCall) {
3928  if (FreeSSERegs >= NumElts &&
3929  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3930  FreeSSERegs -= NumElts;
3931  return ABIArgInfo::getDirect();
3932  } else if (IsReturnType) {
3933  return ABIArgInfo::getExpand();
3934  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3935  // HVAs are delayed and reclassified in the 2nd step.
3936  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3937  }
3938  }
3939  }
3940 
3941  if (Ty->isMemberPointerType()) {
3942  // If the member pointer is represented by an LLVM int or ptr, pass it
3943  // directly.
3944  llvm::Type *LLTy = CGT.ConvertType(Ty);
3945  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3946  return ABIArgInfo::getDirect();
3947  }
3948 
3949  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3950  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3951  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3952  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3953  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3954 
3955  // Otherwise, coerce it to a small integer.
3956  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3957  }
3958 
3959  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3960  switch (BT->getKind()) {
3961  case BuiltinType::Bool:
3962  // Bool type is always extended to the ABI, other builtin types are not
3963  // extended.
3964  return ABIArgInfo::getExtend(Ty);
3965 
3966  case BuiltinType::LongDouble:
3967  // Mingw64 GCC uses the old 80 bit extended precision floating point
3968  // unit. It passes them indirectly through memory.
3969  if (IsMingw64) {
3970  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3971  if (LDF == &llvm::APFloat::x87DoubleExtended())
3972  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3973  }
3974  break;
3975 
3976  case BuiltinType::Int128:
3977  case BuiltinType::UInt128:
3978  // If it's a parameter type, the normal ABI rule is that arguments larger
3979  // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
3980  // even though it isn't particularly efficient.
3981  if (!IsReturnType)
3982  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3983 
3984  // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
3985  // Clang matches them for compatibility.
3986  return ABIArgInfo::getDirect(
3987  llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2));
3988 
3989  default:
3990  break;
3991  }
3992  }
3993 
3994  return ABIArgInfo::getDirect();
3995 }
3996 
3997 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3998  unsigned FreeSSERegs,
3999  bool IsVectorCall,
4000  bool IsRegCall) const {
4001  unsigned Count = 0;
4002  for (auto &I : FI.arguments()) {
4003  // Vectorcall in x64 only permits the first 6 arguments to be passed
4004  // as XMM/YMM registers.
4005  if (Count < VectorcallMaxParamNumAsReg)
4006  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4007  else {
4008  // Since these cannot be passed in registers, pretend no registers
4009  // are left.
4010  unsigned ZeroSSERegsAvail = 0;
4011  I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
4012  IsVectorCall, IsRegCall);
4013  }
4014  ++Count;
4015  }
4016 
4017  for (auto &I : FI.arguments()) {
4018  I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
4019  }
4020 }
4021 
4022 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4023  const unsigned CC = FI.getCallingConvention();
4024  bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
4025  bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
4026 
4027  // If __attribute__((sysv_abi)) is in use, use the SysV argument
4028  // classification rules.
4029  if (CC == llvm::CallingConv::X86_64_SysV) {
4030  X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
4031  SysVABIInfo.computeInfo(FI);
4032  return;
4033  }
4034 
4035  unsigned FreeSSERegs = 0;
4036  if (IsVectorCall) {
4037  // We can use up to 4 SSE return registers with vectorcall.
4038  FreeSSERegs = 4;
4039  } else if (IsRegCall) {
4040  // RegCall gives us 16 SSE registers.
4041  FreeSSERegs = 16;
4042  }
4043 
4044  if (!getCXXABI().classifyReturnType(FI))
4045  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4046  IsVectorCall, IsRegCall);
4047 
4048  if (IsVectorCall) {
4049  // We can use up to 6 SSE register parameters with vectorcall.
4050  FreeSSERegs = 6;
4051  } else if (IsRegCall) {
4052  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4053  FreeSSERegs = 16;
4054  }
4055 
4056  if (IsVectorCall) {
4057  computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4058  } else {
4059  for (auto &I : FI.arguments())
4060  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4061  }
4062 
4063 }
4064 
4065 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4066  QualType Ty) const {
4067 
4068  bool IsIndirect = false;
4069 
4070  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4071  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4072  if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4073  uint64_t Width = getContext().getTypeSize(Ty);
4074  IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4075  }
4076 
4077  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4078  CGF.getContext().getTypeInfoInChars(Ty),
4080  /*allowHigherAlign*/ false);
4081 }
4082 
4083 // PowerPC-32
4084 namespace {
4085 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4086 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4087  bool IsSoftFloatABI;
4088 
4089  CharUnits getParamTypeAlignment(QualType Ty) const;
4090 
4091 public:
4092  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4093  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4094 
4095  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4096  QualType Ty) const override;
4097 };
4098 
4099 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4100 public:
4101  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4102  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4103 
4104  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4105  // This is recovered from gcc output.
4106  return 1; // r1 is the dedicated stack pointer
4107  }
4108 
4109  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4110  llvm::Value *Address) const override;
4111 };
4112 }
4113 
4114 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4115  // Complex types are passed just like their elements
4116  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4117  Ty = CTy->getElementType();
4118 
4119  if (Ty->isVectorType())
4120  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4121  : 4);
4122 
4123  // For single-element float/vector structs, we consider the whole type
4124  // to have the same alignment requirements as its single element.
4125  const Type *AlignTy = nullptr;
4126  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4127  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4128  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4129  (BT && BT->isFloatingPoint()))
4130  AlignTy = EltType;
4131  }
4132 
4133  if (AlignTy)
4134  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4135  return CharUnits::fromQuantity(4);
4136 }
4137 
4138 // TODO: this implementation is now likely redundant with
4139 // DefaultABIInfo::EmitVAArg.
4140 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4141  QualType Ty) const {
4142  if (getTarget().getTriple().isOSDarwin()) {
4143  auto TI = getContext().getTypeInfoInChars(Ty);
4144  TI.second = getParamTypeAlignment(Ty);
4145 
4146  CharUnits SlotSize = CharUnits::fromQuantity(4);
4147  return emitVoidPtrVAArg(CGF, VAList, Ty,
4148  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4149  /*AllowHigherAlign=*/true);
4150  }
4151 
4152  const unsigned OverflowLimit = 8;
4153  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4154  // TODO: Implement this. For now ignore.
4155  (void)CTy;
4156  return Address::invalid(); // FIXME?
4157  }
4158 
4159  // struct __va_list_tag {
4160  // unsigned char gpr;
4161  // unsigned char fpr;
4162  // unsigned short reserved;
4163  // void *overflow_arg_area;
4164  // void *reg_save_area;
4165  // };
4166 
4167  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4168  bool isInt =
4169  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4170  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4171 
4172  // All aggregates are passed indirectly? That doesn't seem consistent
4173  // with the argument-lowering code.
4174  bool isIndirect = Ty->isAggregateType();
4175 
4176  CGBuilderTy &Builder = CGF.Builder;
4177 
4178  // The calling convention either uses 1-2 GPRs or 1 FPR.
4179  Address NumRegsAddr = Address::invalid();
4180  if (isInt || IsSoftFloatABI) {
4181  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4182  } else {
4183  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4184  }
4185 
4186  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4187 
4188  // "Align" the register count when TY is i64.
4189  if (isI64 || (isF64 && IsSoftFloatABI)) {
4190  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4191  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4192  }
4193 
4194  llvm::Value *CC =
4195  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4196 
4197  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4198  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4199  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4200 
4201  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4202 
4203  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4204  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4205 
4206  // Case 1: consume registers.
4207  Address RegAddr = Address::invalid();
4208  {
4209  CGF.EmitBlock(UsingRegs);
4210 
4211  Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4212  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4214  assert(RegAddr.getElementType() == CGF.Int8Ty);
4215 
4216  // Floating-point registers start after the general-purpose registers.
4217  if (!(isInt || IsSoftFloatABI)) {
4218  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4220  }
4221 
4222  // Get the address of the saved value by scaling the number of
4223  // registers we've used by the number of
4224  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4225  llvm::Value *RegOffset =
4226  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4227  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4228  RegAddr.getPointer(), RegOffset),
4229  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4230  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4231 
4232  // Increase the used-register count.
4233  NumRegs =
4234  Builder.CreateAdd(NumRegs,
4235  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4236  Builder.CreateStore(NumRegs, NumRegsAddr);
4237 
4238  CGF.EmitBranch(Cont);
4239  }
4240 
4241  // Case 2: consume space in the overflow area.
4242  Address MemAddr = Address::invalid();
4243  {
4244  CGF.EmitBlock(UsingOverflow);
4245 
4246  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4247 
4248  // Everything in the overflow area is rounded up to a size of at least 4.
4249  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4250 
4251  CharUnits Size;
4252  if (!isIndirect) {
4253  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4254  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4255  } else {
4256  Size = CGF.getPointerSize();
4257  }
4258 
4259  Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4260  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4261  OverflowAreaAlign);
4262  // Round up address of argument to alignment
4263  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4264  if (Align > OverflowAreaAlign) {
4265  llvm::Value *Ptr = OverflowArea.getPointer();
4266  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4267  Align);
4268  }
4269 
4270  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4271 
4272  // Increase the overflow area.
4273  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4274  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4275  CGF.EmitBranch(Cont);
4276  }
4277 
4278  CGF.EmitBlock(Cont);
4279 
4280  // Merge the cases with a phi.
4281  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4282  "vaarg.addr");
4283 
4284  // Load the pointer if the argument was passed indirectly.
4285  if (isIndirect) {
4286  Result = Address(Builder.CreateLoad(Result, "aggr"),
4288  }
4289 
4290  return Result;
4291 }
4292 
4293 bool
4294 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4295  llvm::Value *Address) const {
4296  // This is calculated from the LLVM and GCC tables and verified
4297  // against gcc output. AFAIK all ABIs use the same encoding.
4298 
4299  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4300 
4301  llvm::IntegerType *i8 = CGF.Int8Ty;
4302  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4303  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4304  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4305 
4306  // 0-31: r0-31, the 4-byte general-purpose registers
4307  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4308 
4309  // 32-63: fp0-31, the 8-byte floating-point registers
4310  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4311 
4312  // 64-76 are various 4-byte special-purpose registers:
4313  // 64: mq
4314  // 65: lr
4315  // 66: ctr
4316  // 67: ap
4317  // 68-75 cr0-7
4318  // 76: xer
4319  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4320 
4321  // 77-108: v0-31, the 16-byte vector registers
4322  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4323 
4324  // 109: vrsave
4325  // 110: vscr
4326  // 111: spe_acc
4327  // 112: spefscr
4328  // 113: sfp
4329  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4330 
4331  return false;
4332 }
4333 
4334 // PowerPC-64
4335 
4336 namespace {
4337 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4338 class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4339 public:
4340  enum ABIKind {
4341  ELFv1 = 0,
4342  ELFv2
4343  };
4344 
4345 private:
4346  static const unsigned GPRBits = 64;
4347  ABIKind Kind;
4348  bool HasQPX;
4349  bool IsSoftFloatABI;
4350 
4351  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4352  // will be passed in a QPX register.
4353  bool IsQPXVectorTy(const Type *Ty) const {
4354  if (!HasQPX)
4355  return false;
4356 
4357  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4358  unsigned NumElements = VT->getNumElements();
4359  if (NumElements == 1)
4360  return false;
4361 
4362  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4363  if (getContext().getTypeSize(Ty) <= 256)
4364  return true;
4365  } else if (VT->getElementType()->
4366  isSpecificBuiltinType(BuiltinType::Float)) {
4367  if (getContext().getTypeSize(Ty) <= 128)
4368  return true;
4369  }
4370  }
4371 
4372  return false;
4373  }
4374 
4375  bool IsQPXVectorTy(QualType Ty) const {
4376  return IsQPXVectorTy(Ty.getTypePtr());
4377  }
4378 
4379 public:
4380  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4381  bool SoftFloatABI)
4382  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4383  IsSoftFloatABI(SoftFloatABI) {}
4384 
4385  bool isPromotableTypeForABI(QualType Ty) const;
4386  CharUnits getParamTypeAlignment(QualType Ty) const;
4387 
4388  ABIArgInfo classifyReturnType(QualType RetTy) const;
4390 
4391  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4392  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4393  uint64_t Members) const override;
4394 
4395  // TODO: We can add more logic to computeInfo to improve performance.
4396  // Example: For aggregate arguments that fit in a register, we could
4397  // use getDirectInReg (as is done below for structs containing a single
4398  // floating-point value) to avoid pushing them to memory on function
4399  // entry. This would require changing the logic in PPCISelLowering
4400  // when lowering the parameters in the caller and args in the callee.
4401  void computeInfo(CGFunctionInfo &FI) const override {
4402  if (!getCXXABI().classifyReturnType(FI))
4404  for (auto &I : FI.arguments()) {
4405  // We rely on the default argument classification for the most part.
4406  // One exception: An aggregate containing a single floating-point
4407  // or vector item must be passed in a register if one is available.
4408  const Type *T = isSingleElementStruct(I.type, getContext());
4409  if (T) {
4410  const BuiltinType *BT = T->getAs<BuiltinType>();
4411  if (IsQPXVectorTy(T) ||
4412  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4413  (BT && BT->isFloatingPoint())) {
4414  QualType QT(T, 0);
4415  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4416  continue;
4417  }
4418  }
4419  I.info = classifyArgumentType(I.type);
4420  }
4421  }
4422 
4423  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4424  QualType Ty) const override;
4425 
4426  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4427  bool asReturnValue) const override {
4428  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4429  }
4430 
4431  bool isSwiftErrorInRegister() const override {
4432  return false;
4433  }
4434 };
4435 
4436 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4437 
4438 public:
4439  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4440  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4441  bool SoftFloatABI)
4442  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4443  SoftFloatABI)) {}
4444 
4445  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4446  // This is recovered from gcc output.
4447  return 1; // r1 is the dedicated stack pointer
4448  }
4449 
4450  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4451  llvm::Value *Address) const override;
4452 };
4453 
4454 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4455 public:
4456  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4457 
4458  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4459  // This is recovered from gcc output.
4460  return 1; // r1 is the dedicated stack pointer
4461  }
4462 
4463  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4464  llvm::Value *Address) const override;
4465 };
4466 
4467 }
4468 
4469 // Return true if the ABI requires Ty to be passed sign- or zero-
4470 // extended to 64 bits.
4471 bool
4472 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4473  // Treat an enum type as its underlying type.
4474  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4475  Ty = EnumTy->getDecl()->getIntegerType();
4476 
4477  // Promotable integer types are required to be promoted by the ABI.
4478  if (Ty->isPromotableIntegerType())
4479  return true;
4480 
4481  // In addition to the usual promotable integer types, we also need to
4482  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4483  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4484  switch (BT->getKind()) {
4485  case BuiltinType::Int:
4486  case BuiltinType::UInt:
4487  return true;
4488  default:
4489  break;
4490  }
4491 
4492  return false;
4493 }
4494 
4495 /// isAlignedParamType - Determine whether a type requires 16-byte or
4496 /// higher alignment in the parameter area. Always returns at least 8.
4497 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4498  // Complex types are passed just like their elements.
4499  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4500  Ty = CTy->getElementType();
4501 
4502  // Only vector types of size 16 bytes need alignment (larger types are
4503  // passed via reference, smaller types are not aligned).
4504  if (IsQPXVectorTy(Ty)) {
4505  if (getContext().getTypeSize(Ty) > 128)
4506  return CharUnits::fromQuantity(32);
4507 
4508  return CharUnits::fromQuantity(16);
4509  } else if (Ty->isVectorType()) {
4510  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4511  }
4512 
4513  // For single-element float/vector structs, we consider the whole type
4514  // to have the same alignment requirements as its single element.
4515  const Type *AlignAsType = nullptr;
4516  const Type *EltType = isSingleElementStruct(Ty, getContext());
4517  if (EltType) {
4518  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4519  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4520  getContext().getTypeSize(EltType) == 128) ||
4521  (BT && BT->isFloatingPoint()))
4522  AlignAsType = EltType;
4523  }
4524 
4525  // Likewise for ELFv2 homogeneous aggregates.
4526  const Type *Base = nullptr;
4527  uint64_t Members = 0;
4528  if (!AlignAsType && Kind == ELFv2 &&
4529  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4530  AlignAsType = Base;
4531 
4532  // With special case aggregates, only vector base types need alignment.
4533  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4534  if (getContext().getTypeSize(AlignAsType) > 128)
4535  return CharUnits::fromQuantity(32);
4536 
4537  return CharUnits::fromQuantity(16);
4538  } else if (AlignAsType) {
4539  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4540  }
4541 
4542  // Otherwise, we only need alignment for any aggregate type that
4543  // has an alignment requirement of >= 16 bytes.
4544  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4545  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4546  return CharUnits::fromQuantity(32);
4547  return CharUnits::fromQuantity(16);
4548  }
4549 
4550  return CharUnits::fromQuantity(8);
4551 }
4552 
4553 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4554 /// aggregate. Base is set to the base element type, and Members is set
4555 /// to the number of base elements.
4557  uint64_t &Members) const {
4558  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4559  uint64_t NElements = AT->getSize().getZExtValue();
4560  if (NElements == 0)
4561  return false;
4562  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4563  return false;
4564  Members *= NElements;
4565  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4566  const RecordDecl *RD = RT->getDecl();
4567  if (RD->hasFlexibleArrayMember())
4568  return false;
4569 
4570  Members = 0;
4571 
4572  // If this is a C++ record, check the bases first.
4573  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4574  for (const auto &I : CXXRD->bases()) {
4575  // Ignore empty records.
4576  if (isEmptyRecord(getContext(), I.getType(), true))
4577  continue;
4578 
4579  uint64_t FldMembers;
4580  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4581  return false;
4582 
4583  Members += FldMembers;
4584  }
4585  }
4586 
4587  for (const auto *FD : RD->fields()) {
4588  // Ignore (non-zero arrays of) empty records.
4589  QualType FT = FD->getType();
4590  while (const ConstantArrayType *AT =
4591  getContext().getAsConstantArrayType(FT)) {
4592  if (AT->getSize().getZExtValue() == 0)
4593  return false;
4594  FT = AT->getElementType();
4595  }
4596  if (isEmptyRecord(getContext(), FT, true))
4597  continue;
4598 
4599  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4600  if (getContext().getLangOpts().CPlusPlus &&
4601  FD->isZeroLengthBitField(getContext()))
4602  continue;
4603 
4604  uint64_t FldMembers;
4605  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4606  return false;
4607 
4608  Members = (RD->isUnion() ?
4609  std::max(Members, FldMembers) : Members + FldMembers);
4610  }
4611 
4612  if (!Base)
4613  return false;
4614 
4615  // Ensure there is no padding.
4616  if (getContext().getTypeSize(Base) * Members !=
4617  getContext().getTypeSize(Ty))
4618  return false;
4619  } else {
4620  Members = 1;
4621  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4622  Members = 2;
4623  Ty = CT->getElementType();
4624  }
4625 
4626  // Most ABIs only support float, double, and some vector type widths.
4628  return false;
4629 
4630  // The base type must be the same for all members. Types that
4631  // agree in both total size and mode (float vs. vector) are
4632  // treated as being equivalent here.
4633  const Type *TyPtr = Ty.getTypePtr();
4634  if (!Base) {
4635  Base = TyPtr;
4636  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4637  // so make sure to widen it explicitly.
4638  if (const VectorType *VT = Base->getAs<VectorType>()) {
4639  QualType EltTy = VT->getElementType();
4640  unsigned NumElements =
4641  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4642  Base = getContext()
4643  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4644  .getTypePtr();
4645  }
4646  }
4647 
4648  if (Base->isVectorType() != TyPtr->isVectorType() ||
4649  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4650  return false;
4651  }
4652  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4653 }
4654 
4655 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4656  // Homogeneous aggregates for ELFv2 must have base types of float,
4657  // double, long double, or 128-bit vectors.
4658  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4659  if (BT->getKind() == BuiltinType::Float ||
4660  BT->getKind() == BuiltinType::Double ||
4661  BT->getKind() == BuiltinType::LongDouble ||
4663  (BT->getKind() == BuiltinType::Float128))) {
4664  if (IsSoftFloatABI)
4665  return false;
4666  return true;
4667  }
4668  }
4669  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4670  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4671  return true;
4672  }
4673  return false;
4674 }
4675 
4676 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4677  const Type *Base, uint64_t Members) const {
4678  // Vector and fp128 types require one register, other floating point types
4679  // require one or two registers depending on their size.
4680  uint32_t NumRegs =
4682  Base->isFloat128Type()) ||
4683  Base->isVectorType()) ? 1
4684  : (getContext().getTypeSize(Base) + 63) / 64;
4685 
4686  // Homogeneous Aggregates may occupy at most 8 registers.
4687  return Members * NumRegs <= 8;
4688 }
4689 
4690 ABIArgInfo
4693 
4694  if (Ty->isAnyComplexType())
4695  return ABIArgInfo::getDirect();
4696 
4697  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4698  // or via reference (larger than 16 bytes).
4699  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4700  uint64_t Size = getContext().getTypeSize(Ty);
4701  if (Size > 128)
4702  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4703  else if (Size < 128) {
4704  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4705  return ABIArgInfo::getDirect(CoerceTy);
4706  }
4707  }
4708 
4709  if (isAggregateTypeForABI(Ty)) {
4712 
4713  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4714  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4715 
4716  // ELFv2 homogeneous aggregates are passed as array types.
4717  const Type *Base = nullptr;
4718  uint64_t Members = 0;
4719  if (Kind == ELFv2 &&
4720  isHomogeneousAggregate(Ty, Base, Members)) {
4721  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4722  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4723  return ABIArgInfo::getDirect(CoerceTy);
4724  }
4725 
4726  // If an aggregate may end up fully in registers, we do not
4727  // use the ByVal method, but pass the aggregate as array.
4728  // This is usually beneficial since we avoid forcing the
4729  // back-end to store the argument to memory.
4730  uint64_t Bits = getContext().getTypeSize(Ty);
4731  if (Bits > 0 && Bits <= 8 * GPRBits) {
4732  llvm::Type *CoerceTy;
4733 
4734  // Types up to 8 bytes are passed as integer type (which will be
4735  // properly aligned in the argument save area doubleword).
4736  if (Bits <= GPRBits)
4737  CoerceTy =
4738  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4739  // Larger types are passed as arrays, with the base type selected
4740  // according to the required alignment in the save area.
4741  else {
4742  uint64_t RegBits = ABIAlign * 8;
4743  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4744  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4745  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4746  }
4747 
4748  return ABIArgInfo::getDirect(CoerceTy);
4749  }
4750 
4751  // All other aggregates are passed ByVal.
4753  /*ByVal=*/true,
4754  /*Realign=*/TyAlign > ABIAlign);
4755  }
4756 
4757  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4758  : ABIArgInfo::getDirect());
4759 }
4760 
4761 ABIArgInfo
4763  if (RetTy->isVoidType())
4764  return ABIArgInfo::getIgnore();
4765 
4766  if (RetTy->isAnyComplexType())
4767  return ABIArgInfo::getDirect();
4768 
4769  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4770  // or via reference (larger than 16 bytes).
4771  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4772  uint64_t Size = getContext().getTypeSize(RetTy);
4773  if (Size > 128)
4774  return getNaturalAlignIndirect(RetTy);
4775  else if (Size < 128) {
4776  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4777  return ABIArgInfo::getDirect(CoerceTy);
4778  }
4779  }
4780 
4781  if (isAggregateTypeForABI(RetTy)) {
4782  // ELFv2 homogeneous aggregates are returned as array types.
4783  const Type *Base = nullptr;
4784  uint64_t Members = 0;
4785  if (Kind == ELFv2 &&
4786  isHomogeneousAggregate(RetTy, Base, Members)) {
4787  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4788  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4789  return ABIArgInfo::getDirect(CoerceTy);
4790  }
4791 
4792  // ELFv2 small aggregates are returned in up to two registers.
4793  uint64_t Bits = getContext().getTypeSize(RetTy);
4794  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4795  if (Bits == 0)
4796  return ABIArgInfo::getIgnore();
4797 
4798  llvm::Type *CoerceTy;
4799  if (Bits > GPRBits) {
4800  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4801  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4802  } else
4803  CoerceTy =
4804  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4805  return ABIArgInfo::getDirect(CoerceTy);
4806  }
4807 
4808  // All other aggregates are returned indirectly.
4809  return getNaturalAlignIndirect(RetTy);
4810  }
4811 
4812  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4813  : ABIArgInfo::getDirect());
4814 }
4815 
4816 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4817 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4818  QualType Ty) const {
4819  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4820  TypeInfo.second = getParamTypeAlignment(Ty);
4821 
4822  CharUnits SlotSize = CharUnits::fromQuantity(8);
4823 
4824  // If we have a complex type and the base type is smaller than 8 bytes,
4825  // the ABI calls for the real and imaginary parts to be right-adjusted
4826  // in separate doublewords. However, Clang expects us to produce a
4827  // pointer to a structure with the two parts packed tightly. So generate
4828  // loads of the real and imaginary parts relative to the va_list pointer,
4829  // and store them to a temporary structure.
4830  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4831  CharUnits EltSize = TypeInfo.first / 2;
4832  if (EltSize < SlotSize) {
4833  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4834  SlotSize * 2, SlotSize,
4835  SlotSize, /*AllowHigher*/ true);
4836 
4837  Address RealAddr = Addr;
4838  Address ImagAddr = RealAddr;
4839  if (CGF.CGM.getDataLayout().isBigEndian()) {
4840  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4841  SlotSize - EltSize);
4842  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4843  2 * SlotSize - EltSize);
4844  } else {
4845  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4846  }
4847 
4848  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4849  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4850  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4851  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4852  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4853 
4854  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4855  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4856  /*init*/ true);
4857  return Temp;
4858  }
4859  }
4860 
4861  // Otherwise, just use the general rule.
4862  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4863  TypeInfo, SlotSize, /*AllowHigher*/ true);
4864 }
4865 
4866 static bool
4868  llvm::Value *Address) {
4869  // This is calculated from the LLVM and GCC tables and verified
4870  // against gcc output. AFAIK all ABIs use the same encoding.
4871 
4872  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4873 
4874  llvm::IntegerType *i8 = CGF.Int8Ty;
4875  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4876  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4877  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4878 
4879  // 0-31: r0-31, the 8-byte general-purpose registers
4880  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4881 
4882  // 32-63: fp0-31, the 8-byte floating-point registers
4883  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4884 
4885  // 64-67 are various 8-byte special-purpose registers:
4886  // 64: mq
4887  // 65: lr
4888  // 66: ctr
4889  // 67: ap
4890  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4891 
4892  // 68-76 are various 4-byte special-purpose registers:
4893  // 68-75 cr0-7
4894  // 76: xer
4895  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4896 
4897  // 77-108: v0-31, the 16-byte vector registers
4898  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4899 
4900  // 109: vrsave
4901  // 110: vscr
4902  // 111: spe_acc
4903  // 112: spefscr
4904  // 113: sfp
4905  // 114: tfhar
4906  // 115: tfiar
4907  // 116: texasr
4908  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4909 
4910  return false;
4911 }
4912 
4913 bool
4914 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4916  llvm::Value *Address) const {
4917 
4918  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4919 }
4920 
4921 bool
4922 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4923  llvm::Value *Address) const {
4924 
4925  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4926 }
4927 
4928 //===----------------------------------------------------------------------===//
4929 // AArch64 ABI Implementation
4930 //===----------------------------------------------------------------------===//
4931 
4932 namespace {
4933 
4934 class AArch64ABIInfo : public SwiftABIInfo {
4935 public:
4936  enum ABIKind {
4937  AAPCS = 0,
4938  DarwinPCS,
4939  Win64
4940  };
4941 
4942 private:
4943  ABIKind Kind;
4944 
4945 public:
4946  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4947  : SwiftABIInfo(CGT), Kind(Kind) {}
4948 
4949 private:
4950  ABIKind getABIKind() const { return Kind; }
4951  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4952 
4953  ABIArgInfo classifyReturnType(QualType RetTy) const;
4955  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4956  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4957  uint64_t Members) const override;
4958 
4959  bool isIllegalVectorType(QualType Ty) const;
4960 
4961  void computeInfo(CGFunctionInfo &FI) const override {
4962  if (!::classifyReturnType(getCXXABI(), FI, *this))
4964 
4965  for (auto &it : FI.arguments())
4966  it.info = classifyArgumentType(it.type);
4967  }
4968 
4969  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4970  CodeGenFunction &CGF) const;
4971 
4972  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4973  CodeGenFunction &CGF) const;
4974 
4975  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4976  QualType Ty) const override {
4977  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4978  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4979  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4980  }
4981 
4982  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4983  QualType Ty) const override;
4984 
4985  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4986  bool asReturnValue) const override {
4987  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4988  }
4989  bool isSwiftErrorInRegister() const override {
4990  return true;
4991  }
4992 
4993  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4994  unsigned elts) const override;
4995 };
4996 
4997 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4998 public:
4999  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
5000  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
5001 
5002  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5003  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
5004  }
5005 
5006  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5007  return 31;
5008  }
5009 
5010  bool doesReturnSlotInterfereWithArgs() const override { return false; }
5011 
5012  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5013  CodeGen::CodeGenModule &CGM) const override {
5014  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5015  if (!FD)
5016  return;
5017  llvm::Function *Fn = cast<llvm::Function>(GV);
5018 
5019  auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
5021  Fn->addFnAttr("sign-return-address",
5022  Kind == CodeGenOptions::SignReturnAddressScope::All
5023  ? "all"
5024  : "non-leaf");
5025 
5026  auto Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
5027  Fn->addFnAttr("sign-return-address-key",
5028  Key == CodeGenOptions::SignReturnAddressKeyValue::AKey
5029  ? "a_key"
5030  : "b_key");
5031  }
5032 
5033  if (CGM.getCodeGenOpts().BranchTargetEnforcement)
5034  Fn->addFnAttr("branch-target-enforcement");
5035  }
5036 };
5037 
5038 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5039 public:
5040  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
5041  : AArch64TargetCodeGenInfo(CGT, K) {}
5042 
5043  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5044  CodeGen::CodeGenModule &CGM) const override;
5045 
5046  void getDependentLibraryOption(llvm::StringRef Lib,
5047  llvm::SmallString<24> &Opt) const override {
5048  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5049  }
5050 
5051  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5052  llvm::SmallString<32> &Opt) const override {
5053  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5054  }
5055 };
5056 
5057 void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
5058  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5059  AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5060  if (GV->isDeclaration())
5061  return;
5062  addStackProbeTargetAttributes(D, GV, CGM);
5063 }
5064 }
5065 
5068 
5069  // Handle illegal vector types here.
5070  if (isIllegalVectorType(Ty)) {
5071  uint64_t Size = getContext().getTypeSize(Ty);
5072  // Android promotes <2 x i8> to i16, not i32
5073  if (isAndroid() && (Size <= 16)) {
5074  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5075  return ABIArgInfo::getDirect(ResType);
5076  }
5077  if (Size <= 32) {
5078  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5079  return ABIArgInfo::getDirect(ResType);
5080  }
5081  if (Size == 64) {
5082  llvm::Type *ResType =
5083  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5084  return ABIArgInfo::getDirect(ResType);
5085  }
5086  if (Size == 128) {
5087  llvm::Type *ResType =
5088  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5089  return ABIArgInfo::getDirect(ResType);
5090  }
5091  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5092  }
5093 
5094  if (!isAggregateTypeForABI(Ty)) {
5095  // Treat an enum type as its underlying type.
5096  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5097  Ty = EnumTy->getDecl()->getIntegerType();
5098 
5099  return (Ty->isPromotableIntegerType() && isDarwinPCS()
5100  ? ABIArgInfo::getExtend(Ty)
5101  : ABIArgInfo::getDirect());
5102  }
5103 
5104  // Structures with either a non-trivial destructor or a non-trivial
5105  // copy constructor are always indirect.
5107  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5109  }
5110 
5111  // Empty records are always ignored on Darwin, but actually passed in C++ mode
5112  // elsewhere for GNU compatibility.
5113  uint64_t Size = getContext().getTypeSize(Ty);
5114  bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5115  if (IsEmpty || Size == 0) {
5116  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5117  return ABIArgInfo::getIgnore();
5118 
5119  // GNU C mode. The only argument that gets ignored is an empty one with size
5120  // 0.
5121  if (IsEmpty && Size == 0)
5122  return ABIArgInfo::getIgnore();
5123  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5124  }
5125 
5126  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5127  const Type *Base = nullptr;
5128  uint64_t Members = 0;
5129  if (isHomogeneousAggregate(Ty, Base, Members)) {
5130  return ABIArgInfo::getDirect(
5131  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5132  }
5133 
5134  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5135  if (Size <= 128) {
5136  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5137  // same size and alignment.
5138  if (getTarget().isRenderScriptTarget()) {
5139  return coerceToIntArray(Ty, getContext(), getVMContext());
5140  }
5141  unsigned Alignment;
5142  if (Kind == AArch64ABIInfo::AAPCS) {
5143  Alignment = getContext().getTypeUnadjustedAlign(Ty);
5144  Alignment = Alignment < 128 ? 64 : 128;
5145  } else {
5146  Alignment = getContext().getTypeAlign(Ty);
5147  }
5148  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5149 
5150  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5151  // For aggregates with 16-byte alignment, we use i128.
5152  if (Alignment < 128 && Size == 128) {
5153  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5154  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5155  }
5156  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5157  }
5158 
5159  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5160 }
5161 
5163  if (RetTy->isVoidType())
5164  return ABIArgInfo::getIgnore();
5165 
5166  // Large vector types should be returned via memory.
5167  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5168  return getNaturalAlignIndirect(RetTy);
5169 
5170  if (!isAggregateTypeForABI(RetTy)) {
5171  // Treat an enum type as its underlying type.
5172  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5173  RetTy = EnumTy->getDecl()->getIntegerType();
5174 
5175  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5176  ? ABIArgInfo::getExtend(RetTy)
5177  : ABIArgInfo::getDirect());
5178  }
5179 
5180  uint64_t Size = getContext().getTypeSize(RetTy);
5181  if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5182  return ABIArgInfo::getIgnore();
5183 
5184  const Type *Base = nullptr;
5185  uint64_t Members = 0;
5186  if (isHomogeneousAggregate(RetTy, Base, Members))
5187  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5188  return ABIArgInfo::getDirect();
5189 
5190  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5191  if (Size <= 128) {
5192  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5193  // same size and alignment.
5194  if (getTarget().isRenderScriptTarget()) {
5195  return coerceToIntArray(RetTy, getContext(), getVMContext());
5196  }
5197  unsigned Alignment = getContext().getTypeAlign(RetTy);
5198  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5199 
5200  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5201  // For aggregates with 16-byte alignment, we use i128.
5202  if (Alignment < 128 && Size == 128) {
5203  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5204  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5205  }
5206  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5207  }
5208 
5209  return getNaturalAlignIndirect(RetTy);
5210 }
5211 
5212 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5213 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5214  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5215  // Check whether VT is legal.
5216  unsigned NumElements = VT->getNumElements();
5217  uint64_t Size = getContext().getTypeSize(VT);
5218  // NumElements should be power of 2.
5219  if (!llvm::isPowerOf2_32(NumElements))
5220  return true;
5221  return Size != 64 && (Size != 128 || NumElements == 1);
5222  }
5223  return false;
5224 }
5225 
5226 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5227  llvm::Type *eltTy,
5228  unsigned elts) const {
5229  if (!llvm::isPowerOf2_32(elts))
5230  return false;
5231  if (totalSize.getQuantity() != 8 &&
5232  (totalSize.getQuantity() != 16 || elts == 1))
5233  return false;
5234  return true;
5235 }
5236 
5237 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5238  // Homogeneous aggregates for AAPCS64 must have base types of a floating
5239  // point type or a short-vector type. This is the same as the 32-bit ABI,
5240  // but with the difference that any floating-point type is allowed,
5241  // including __fp16.
5242  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5243  if (BT->isFloatingPoint())
5244  return true;
5245  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5246  unsigned VecSize = getContext().getTypeSize(VT);
5247  if (VecSize == 64 || VecSize == 128)
5248  return true;
5249  }
5250  return false;
5251 }
5252 
5253 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5254  uint64_t Members) const {
5255  return Members <= 4;
5256 }
5257 
5258 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5259  QualType Ty,
5260  CodeGenFunction &CGF) const {
5262  bool IsIndirect = AI.isIndirect();
5263 
5264  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5265  if (IsIndirect)
5266  BaseTy = llvm::PointerType::getUnqual(BaseTy);
5267  else if (AI.getCoerceToType())
5268  BaseTy = AI.getCoerceToType();
5269 
5270  unsigned NumRegs = 1;
5271  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5272  BaseTy = ArrTy->getElementType();
5273  NumRegs = ArrTy->getNumElements();
5274  }
5275  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5276 
5277  // The AArch64 va_list type and handling is specified in the Procedure Call
5278  // Standard, section B.4:
5279  //
5280  // struct {
5281  // void *__stack;
5282  // void *__gr_top;
5283  // void *__vr_top;
5284  // int __gr_offs;
5285  // int __vr_offs;
5286  // };
5287 
5288  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5289  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5290  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5291  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5292 
5293  CharUnits TySize = getContext().getTypeSizeInChars(Ty);
5295 
5296  Address reg_offs_p = Address::invalid();
5297  llvm::Value *reg_offs = nullptr;
5298  int reg_top_index;
5299  int RegSize = IsIndirect ? 8 : TySize.getQuantity();
5300  if (!IsFPR) {
5301  // 3 is the field number of __gr_offs
5302  reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p");
5303  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5304  reg_top_index = 1; // field number for __gr_top
5305  RegSize = llvm::alignTo(RegSize, 8);
5306  } else {
5307  // 4 is the field number of __vr_offs.
5308  reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p");
5309  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5310  reg_top_index = 2; // field number for __vr_top
5311  RegSize = 16 * NumRegs;
5312  }
5313 
5314  //=======================================
5315  // Find out where argument was passed
5316  //=======================================
5317 
5318  // If reg_offs >= 0 we're already using the stack for this type of
5319  // argument. We don't want to keep updating reg_offs (in case it overflows,
5320  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5321  // whatever they get).
5322  llvm::Value *UsingStack = nullptr;
5323  UsingStack = CGF.Builder.CreateICmpSGE(
5324  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5325 
5326  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5327 
5328  // Otherwise, at least some kind of argument could go in these registers, the
5329  // question is whether this particular type is too big.
5330  CGF.EmitBlock(MaybeRegBlock);
5331 
5332  // Integer arguments may need to correct register alignment (for example a
5333  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5334  // align __gr_offs to calculate the potential address.
5335  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5336  int Align = TyAlign.getQuantity();
5337 
5338  reg_offs = CGF.Builder.CreateAdd(
5339  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5340  "align_regoffs");
5341  reg_offs = CGF.Builder.CreateAnd(
5342  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5343  "aligned_regoffs");
5344  }
5345 
5346  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5347  // The fact that this is done unconditionally reflects the fact that
5348  // allocating an argument to the stack also uses up all the remaining
5349  // registers of the appropriate kind.
5350  llvm::Value *NewOffset = nullptr;
5351  NewOffset = CGF.Builder.CreateAdd(
5352  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5353  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5354 
5355  // Now we're in a position to decide whether this argument really was in
5356  // registers or not.
5357  llvm::Value *InRegs = nullptr;
5358  InRegs = CGF.Builder.CreateICmpSLE(
5359  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5360 
5361  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5362 
5363  //=======================================
5364  // Argument was in registers
5365  //=======================================
5366 
5367  // Now we emit the code for if the argument was originally passed in
5368  // registers. First start the appropriate block:
5369  CGF.EmitBlock(InRegBlock);
5370 
5371  llvm::Value *reg_top = nullptr;
5372  Address reg_top_p =
5373  CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p");
5374  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5375  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5376  CharUnits::fromQuantity(IsFPR ? 16 : 8));
5377  Address RegAddr = Address::invalid();
5378  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5379 
5380  if (IsIndirect) {
5381  // If it's been passed indirectly (actually a struct), whatever we find from
5382  // stored registers or on the stack will actually be a struct **.
5383  MemTy = llvm::PointerType::getUnqual(MemTy);
5384  }
5385 
5386  const Type *Base = nullptr;
5387  uint64_t NumMembers = 0;
5388  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5389  if (IsHFA && NumMembers > 1) {
5390  // Homogeneous aggregates passed in registers will have their elements split
5391  // and stored 16-bytes apart regardless of size (they're notionally in qN,
5392  // qN+1, ...). We reload and store into a temporary local variable
5393  // contiguously.
5394  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5395  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5396  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5397  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5398  Address Tmp = CGF.CreateTempAlloca(HFATy,
5399  std::max(TyAlign, BaseTyInfo.second));
5400 
5401  // On big-endian platforms, the value will be right-aligned in its slot.
5402  int Offset = 0;
5403  if (CGF.CGM.getDataLayout().isBigEndian() &&
5404  BaseTyInfo.first.getQuantity() < 16)
5405  Offset = 16 - BaseTyInfo.first.getQuantity();
5406 
5407  for (unsigned i = 0; i < NumMembers; ++i) {
5408  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5409  Address LoadAddr =
5410  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5411  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5412 
5413  Address StoreAddr = CGF.Builder.CreateConstArrayGEP(Tmp, i);
5414 
5415  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5416  CGF.Builder.CreateStore(Elem, StoreAddr);
5417  }
5418 
5419  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5420  } else {
5421  // Otherwise the object is contiguous in memory.
5422 
5423  // It might be right-aligned in its slot.
5424  CharUnits SlotSize = BaseAddr.getAlignment();
5425  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5426  (IsHFA || !isAggregateTypeForABI(Ty)) &&
5427  TySize < SlotSize) {
5428  CharUnits Offset = SlotSize - TySize;
5429  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5430  }
5431 
5432  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5433  }
5434 
5435  CGF.EmitBranch(ContBlock);
5436 
5437  //=======================================
5438  // Argument was on the stack
5439  //=======================================
5440  CGF.EmitBlock(OnStackBlock);
5441 
5442  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p");
5443  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5444 
5445  // Again, stack arguments may need realignment. In this case both integer and
5446  // floating-point ones might be affected.
5447  if (!IsIndirect && TyAlign.getQuantity() > 8) {
5448  int Align = TyAlign.getQuantity();
5449 
5450  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5451 
5452  OnStackPtr = CGF.Builder.CreateAdd(
5453  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5454  "align_stack");
5455  OnStackPtr = CGF.Builder.CreateAnd(
5456  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5457  "align_stack");
5458 
5459  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5460  }
5461  Address OnStackAddr(OnStackPtr,
5462  std::max(CharUnits::fromQuantity(8), TyAlign));
5463 
5464  // All stack slots are multiples of 8 bytes.
5465  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5466  CharUnits StackSize;
5467  if (IsIndirect)
5468  StackSize = StackSlotSize;
5469  else
5470  StackSize = TySize.alignTo(StackSlotSize);
5471 
5472  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5473  llvm::Value *NewStack =
5474  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5475 
5476  // Write the new value of __stack for the next call to va_arg
5477  CGF.Builder.CreateStore(NewStack, stack_p);
5478 
5479  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5480  TySize < StackSlotSize) {
5481  CharUnits Offset = StackSlotSize - TySize;
5482  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5483  }
5484 
5485  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5486 
5487  CGF.EmitBranch(ContBlock);
5488 
5489  //=======================================
5490  // Tidy up
5491  //=======================================
5492  CGF.EmitBlock(ContBlock);
5493 
5494  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5495  OnStackAddr, OnStackBlock, "vaargs.addr");
5496 
5497  if (IsIndirect)
5498  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5499  TyAlign);
5500 
5501  return ResAddr;
5502 }
5503 
5504 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5505  CodeGenFunction &CGF) const {
5506  // The backend's lowering doesn't support va_arg for aggregates or
5507  // illegal vector types. Lower VAArg here for these cases and use
5508  // the LLVM va_arg instruction for everything else.
5509  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5510  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5511 
5512  CharUnits SlotSize = CharUnits::fromQuantity(8);
5513 
5514  // Empty records are ignored for parameter passing purposes.
5515  if (isEmptyRecord(getContext(), Ty, true)) {
5516  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5517  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5518  return Addr;
5519  }
5520 
5521  // The size of the actual thing passed, which might end up just
5522  // being a pointer for indirect types.
5523  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5524 
5525  // Arguments bigger than 16 bytes which aren't homogeneous
5526  // aggregates should be passed indirectly.
5527  bool IsIndirect = false;
5528  if (TyInfo.first.getQuantity() > 16) {
5529  const Type *Base = nullptr;
5530  uint64_t Members = 0;
5531  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5532  }
5533 
5534  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5535  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5536 }
5537 
5538 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5539  QualType Ty) const {
5540  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5541  CGF.getContext().getTypeInfoInChars(Ty),
5543  /*allowHigherAlign*/ false);
5544 }
5545 
5546 //===----------------------------------------------------------------------===//
5547 // ARM ABI Implementation
5548 //===----------------------------------------------------------------------===//
5549 
5550 namespace {
5551 
5552 class ARMABIInfo : public SwiftABIInfo {
5553 public:
5554  enum ABIKind {
5555  APCS = 0,
5556  AAPCS = 1,
5557  AAPCS_VFP = 2,
5558  AAPCS16_VFP = 3,
5559  };
5560 
5561 private:
5562  ABIKind Kind;
5563 
5564 public:
5565  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5566  : SwiftABIInfo(CGT), Kind(_Kind) {
5567  setCCs();
5568  }
5569 
5570  bool isEABI() const {
5571  switch (getTarget().getTriple().getEnvironment()) {
5572  case llvm::Triple::Android:
5573  case llvm::Triple::EABI:
5574  case llvm::Triple::EABIHF:
5575  case llvm::Triple::GNUEABI:
5576  case llvm::Triple::GNUEABIHF:
5577  case llvm::Triple::MuslEABI:
5578  case llvm::Triple::MuslEABIHF:
5579  return true;
5580  default:
5581  return false;
5582  }
5583  }
5584 
5585  bool isEABIHF() const {
5586  switch (getTarget().getTriple().getEnvironment()) {
5587  case llvm::Triple::EABIHF:
5588  case llvm::Triple::GNUEABIHF:
5589  case llvm::Triple::MuslEABIHF:
5590  return true;
5591  default:
5592  return false;
5593  }
5594  }
5595 
5596  ABIKind getABIKind() const { return Kind; }
5597 
5598 private:
5599  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic,
5600  unsigned functionCallConv) const;
5601  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic,
5602  unsigned functionCallConv) const;
5603  ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base,
5604  uint64_t Members) const;
5605  ABIArgInfo coerceIllegalVector(QualType Ty) const;
5606  bool isIllegalVectorType(QualType Ty) const;
5607  bool containsAnyFP16Vectors(QualType Ty) const;
5608 
5609  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5610  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5611  uint64_t Members) const override;
5612 
5613  bool isEffectivelyAAPCS_VFP(unsigned callConvention, bool acceptHalf) const;
5614 
5615  void