clang  6.0.0svn
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "TargetInfo.h"
16 #include "ABIInfo.h"
17 #include "CGBlocks.h"
18 #include "CGCXXABI.h"
19 #include "CGValue.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
33 
34 using namespace clang;
35 using namespace CodeGen;
36 
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
41 //
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
47 //
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
52  ASTContext &Context,
53  llvm::LLVMContext &LLVMContext) {
54  // Alignment and Size are measured in bits.
55  const uint64_t Size = Context.getTypeSize(Ty);
56  const uint64_t Alignment = Context.getTypeAlign(Ty);
57  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
60 }
61 
63  llvm::Value *Array,
65  unsigned FirstIndex,
66  unsigned LastIndex) {
67  // Alternatively, we could emit this as a loop in the source.
68  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
69  llvm::Value *Cell =
70  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
72  }
73 }
74 
78 }
79 
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82  llvm::Type *Padding) const {
83  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84  ByRef, Realign, Padding);
85 }
86 
89  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90  /*ByRef*/ false, Realign);
91 }
92 
94  QualType Ty) const {
95  return Address::invalid();
96 }
97 
99 
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
102 ///
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
105 ///
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
114  ArrayRef<llvm::Type*> scalarTypes,
115  unsigned maxAllRegisters) {
116  unsigned intCount = 0, fpCount = 0;
117  for (llvm::Type *type : scalarTypes) {
118  if (type->isPointerTy()) {
119  intCount++;
120  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
123  } else {
124  assert(type->isVectorTy() || type->isFloatingPointTy());
125  fpCount++;
126  }
127  }
128 
129  return (intCount + fpCount > maxAllRegisters);
130 }
131 
133  llvm::Type *eltTy,
134  unsigned numElts) const {
135  // The default implementation of this assumes that the target guarantees
136  // 128-bit SIMD support but nothing more.
137  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
138 }
139 
141  CGCXXABI &CXXABI) {
142  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
143  if (!RD)
144  return CGCXXABI::RAA_Default;
145  return CXXABI.getRecordArgABI(RD);
146 }
147 
149  CGCXXABI &CXXABI) {
150  const RecordType *RT = T->getAs<RecordType>();
151  if (!RT)
152  return CGCXXABI::RAA_Default;
153  return getRecordArgABI(RT, CXXABI);
154 }
155 
156 /// Pass transparent unions as if they were the type of the first element. Sema
157 /// should ensure that all elements of the union have the same "machine type".
159  if (const RecordType *UT = Ty->getAsUnionType()) {
160  const RecordDecl *UD = UT->getDecl();
161  if (UD->hasAttr<TransparentUnionAttr>()) {
162  assert(!UD->field_empty() && "sema created an empty transparent union");
163  return UD->field_begin()->getType();
164  }
165  }
166  return Ty;
167 }
168 
170  return CGT.getCXXABI();
171 }
172 
174  return CGT.getContext();
175 }
176 
177 llvm::LLVMContext &ABIInfo::getVMContext() const {
178  return CGT.getLLVMContext();
179 }
180 
181 const llvm::DataLayout &ABIInfo::getDataLayout() const {
182  return CGT.getDataLayout();
183 }
184 
186  return CGT.getTarget();
187 }
188 
190  return CGT.getCodeGenOpts();
191 }
192 
193 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
194 
196  return false;
197 }
198 
200  uint64_t Members) const {
201  return false;
202 }
203 
205  return false;
206 }
207 
208 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
209  raw_ostream &OS = llvm::errs();
210  OS << "(ABIArgInfo Kind=";
211  switch (TheKind) {
212  case Direct:
213  OS << "Direct Type=";
214  if (llvm::Type *Ty = getCoerceToType())
215  Ty->print(OS);
216  else
217  OS << "null";
218  break;
219  case Extend:
220  OS << "Extend";
221  break;
222  case Ignore:
223  OS << "Ignore";
224  break;
225  case InAlloca:
226  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
227  break;
228  case Indirect:
229  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
230  << " ByVal=" << getIndirectByVal()
231  << " Realign=" << getIndirectRealign();
232  break;
233  case Expand:
234  OS << "Expand";
235  break;
236  case CoerceAndExpand:
237  OS << "CoerceAndExpand Type=";
238  getCoerceAndExpandType()->print(OS);
239  break;
240  }
241  OS << ")\n";
242 }
243 
244 // Dynamically round a pointer up to a multiple of the given alignment.
246  llvm::Value *Ptr,
247  CharUnits Align) {
248  llvm::Value *PtrAsInt = Ptr;
249  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
250  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
251  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
252  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
253  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
254  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
255  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
256  Ptr->getType(),
257  Ptr->getName() + ".aligned");
258  return PtrAsInt;
259 }
260 
261 /// Emit va_arg for a platform using the common void* representation,
262 /// where arguments are simply emitted in an array of slots on the stack.
263 ///
264 /// This version implements the core direct-value passing rules.
265 ///
266 /// \param SlotSize - The size and alignment of a stack slot.
267 /// Each argument will be allocated to a multiple of this number of
268 /// slots, and all the slots will be aligned to this value.
269 /// \param AllowHigherAlign - The slot alignment is not a cap;
270 /// an argument type with an alignment greater than the slot size
271 /// will be emitted on a higher-alignment address, potentially
272 /// leaving one or more empty slots behind as padding. If this
273 /// is false, the returned address might be less-aligned than
274 /// DirectAlign.
276  Address VAListAddr,
277  llvm::Type *DirectTy,
278  CharUnits DirectSize,
279  CharUnits DirectAlign,
280  CharUnits SlotSize,
281  bool AllowHigherAlign) {
282  // Cast the element type to i8* if necessary. Some platforms define
283  // va_list as a struct containing an i8* instead of just an i8*.
284  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
285  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
286 
287  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
288 
289  // If the CC aligns values higher than the slot size, do so if needed.
290  Address Addr = Address::invalid();
291  if (AllowHigherAlign && DirectAlign > SlotSize) {
292  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
293  DirectAlign);
294  } else {
295  Addr = Address(Ptr, SlotSize);
296  }
297 
298  // Advance the pointer past the argument, then store that back.
299  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
300  llvm::Value *NextPtr =
301  CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
302  "argp.next");
303  CGF.Builder.CreateStore(NextPtr, VAListAddr);
304 
305  // If the argument is smaller than a slot, and this is a big-endian
306  // target, the argument will be right-adjusted in its slot.
307  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
308  !DirectTy->isStructTy()) {
309  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
310  }
311 
312  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
313  return Addr;
314 }
315 
316 /// Emit va_arg for a platform using the common void* representation,
317 /// where arguments are simply emitted in an array of slots on the stack.
318 ///
319 /// \param IsIndirect - Values of this type are passed indirectly.
320 /// \param ValueInfo - The size and alignment of this type, generally
321 /// computed with getContext().getTypeInfoInChars(ValueTy).
322 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
323 /// Each argument will be allocated to a multiple of this number of
324 /// slots, and all the slots will be aligned to this value.
325 /// \param AllowHigherAlign - The slot alignment is not a cap;
326 /// an argument type with an alignment greater than the slot size
327 /// will be emitted on a higher-alignment address, potentially
328 /// leaving one or more empty slots behind as padding.
330  QualType ValueTy, bool IsIndirect,
331  std::pair<CharUnits, CharUnits> ValueInfo,
332  CharUnits SlotSizeAndAlign,
333  bool AllowHigherAlign) {
334  // The size and alignment of the value that was passed directly.
335  CharUnits DirectSize, DirectAlign;
336  if (IsIndirect) {
337  DirectSize = CGF.getPointerSize();
338  DirectAlign = CGF.getPointerAlign();
339  } else {
340  DirectSize = ValueInfo.first;
341  DirectAlign = ValueInfo.second;
342  }
343 
344  // Cast the address we've calculated to the right type.
345  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
346  if (IsIndirect)
347  DirectTy = DirectTy->getPointerTo(0);
348 
349  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
350  DirectSize, DirectAlign,
351  SlotSizeAndAlign,
352  AllowHigherAlign);
353 
354  if (IsIndirect) {
355  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
356  }
357 
358  return Addr;
359 
360 }
361 
363  Address Addr1, llvm::BasicBlock *Block1,
364  Address Addr2, llvm::BasicBlock *Block2,
365  const llvm::Twine &Name = "") {
366  assert(Addr1.getType() == Addr2.getType());
367  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
368  PHI->addIncoming(Addr1.getPointer(), Block1);
369  PHI->addIncoming(Addr2.getPointer(), Block2);
370  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
371  return Address(PHI, Align);
372 }
373 
375 
376 // If someone can figure out a general rule for this, that would be great.
377 // It's probably just doomed to be platform-dependent, though.
379  // Verified for:
380  // x86-64 FreeBSD, Linux, Darwin
381  // x86-32 FreeBSD, Linux, Darwin
382  // PowerPC Linux, Darwin
383  // ARM Darwin (*not* EABI)
384  // AArch64 Linux
385  return 32;
386 }
387 
389  const FunctionNoProtoType *fnType) const {
390  // The following conventions are known to require this to be false:
391  // x86_stdcall
392  // MIPS
393  // For everything else, we just prefer false unless we opt out.
394  return false;
395 }
396 
397 void
399  llvm::SmallString<24> &Opt) const {
400  // This assumes the user is passing a library name like "rt" instead of a
401  // filename like "librt.a/so", and that they don't care whether it's static or
402  // dynamic.
403  Opt = "-l";
404  Opt += Lib;
405 }
406 
408  // OpenCL kernels are called via an explicit runtime API with arguments
409  // set with clSetKernelArg(), not as normal sub-functions.
410  // Return SPIR_KERNEL by default as the kernel calling convention to
411  // ensure the fingerprint is fixed such way that each OpenCL argument
412  // gets one matching argument in the produced kernel function argument
413  // list to enable feasible implementation of clSetKernelArg() with
414  // aggregates etc. In case we would use the default C calling conv here,
415  // clSetKernelArg() might break depending on the target-specific
416  // conventions; different targets might split structs passed as values
417  // to multiple function arguments etc.
418  return llvm::CallingConv::SPIR_KERNEL;
419 }
420 
422  llvm::PointerType *T, QualType QT) const {
423  return llvm::ConstantPointerNull::get(T);
424 }
425 
427  const VarDecl *D) const {
428  assert(!CGM.getLangOpts().OpenCL &&
429  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
430  "Address space agnostic languages only");
431  return D ? D->getType().getAddressSpace() : LangAS::Default;
432 }
433 
435  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
436  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
437  // Since target may map different address spaces in AST to the same address
438  // space, an address space conversion may end up as a bitcast.
439  if (auto *C = dyn_cast<llvm::Constant>(Src))
440  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
441  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
442 }
443 
444 llvm::Constant *
446  LangAS SrcAddr, LangAS DestAddr,
447  llvm::Type *DestTy) const {
448  // Since target may map different address spaces in AST to the same address
449  // space, an address space conversion may end up as a bitcast.
450  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
451 }
452 
454 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
455  return C.getOrInsertSyncScopeID(""); /* default sync scope */
456 }
457 
458 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
459 
460 /// isEmptyField - Return true iff a the field is "empty", that is it
461 /// is an unnamed bit-field or an (array of) empty record(s).
462 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
463  bool AllowArrays) {
464  if (FD->isUnnamedBitfield())
465  return true;
466 
467  QualType FT = FD->getType();
468 
469  // Constant arrays of empty records count as empty, strip them off.
470  // Constant arrays of zero length always count as empty.
471  if (AllowArrays)
472  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
473  if (AT->getSize() == 0)
474  return true;
475  FT = AT->getElementType();
476  }
477 
478  const RecordType *RT = FT->getAs<RecordType>();
479  if (!RT)
480  return false;
481 
482  // C++ record fields are never empty, at least in the Itanium ABI.
483  //
484  // FIXME: We should use a predicate for whether this behavior is true in the
485  // current ABI.
486  if (isa<CXXRecordDecl>(RT->getDecl()))
487  return false;
488 
489  return isEmptyRecord(Context, FT, AllowArrays);
490 }
491 
492 /// isEmptyRecord - Return true iff a structure contains only empty
493 /// fields. Note that a structure with a flexible array member is not
494 /// considered empty.
495 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
496  const RecordType *RT = T->getAs<RecordType>();
497  if (!RT)
498  return false;
499  const RecordDecl *RD = RT->getDecl();
500  if (RD->hasFlexibleArrayMember())
501  return false;
502 
503  // If this is a C++ record, check the bases first.
504  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
505  for (const auto &I : CXXRD->bases())
506  if (!isEmptyRecord(Context, I.getType(), true))
507  return false;
508 
509  for (const auto *I : RD->fields())
510  if (!isEmptyField(Context, I, AllowArrays))
511  return false;
512  return true;
513 }
514 
515 /// isSingleElementStruct - Determine if a structure is a "single
516 /// element struct", i.e. it has exactly one non-empty field or
517 /// exactly one field which is itself a single element
518 /// struct. Structures with flexible array members are never
519 /// considered single element structs.
520 ///
521 /// \return The field declaration for the single non-empty field, if
522 /// it exists.
523 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
524  const RecordType *RT = T->getAs<RecordType>();
525  if (!RT)
526  return nullptr;
527 
528  const RecordDecl *RD = RT->getDecl();
529  if (RD->hasFlexibleArrayMember())
530  return nullptr;
531 
532  const Type *Found = nullptr;
533 
534  // If this is a C++ record, check the bases first.
535  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
536  for (const auto &I : CXXRD->bases()) {
537  // Ignore empty records.
538  if (isEmptyRecord(Context, I.getType(), true))
539  continue;
540 
541  // If we already found an element then this isn't a single-element struct.
542  if (Found)
543  return nullptr;
544 
545  // If this is non-empty and not a single element struct, the composite
546  // cannot be a single element struct.
547  Found = isSingleElementStruct(I.getType(), Context);
548  if (!Found)
549  return nullptr;
550  }
551  }
552 
553  // Check for single element.
554  for (const auto *FD : RD->fields()) {
555  QualType FT = FD->getType();
556 
557  // Ignore empty fields.
558  if (isEmptyField(Context, FD, true))
559  continue;
560 
561  // If we already found an element then this isn't a single-element
562  // struct.
563  if (Found)
564  return nullptr;
565 
566  // Treat single element arrays as the element.
567  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
568  if (AT->getSize().getZExtValue() != 1)
569  break;
570  FT = AT->getElementType();
571  }
572 
573  if (!isAggregateTypeForABI(FT)) {
574  Found = FT.getTypePtr();
575  } else {
576  Found = isSingleElementStruct(FT, Context);
577  if (!Found)
578  return nullptr;
579  }
580  }
581 
582  // We don't consider a struct a single-element struct if it has
583  // padding beyond the element type.
584  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
585  return nullptr;
586 
587  return Found;
588 }
589 
590 namespace {
591 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
592  const ABIArgInfo &AI) {
593  // This default implementation defers to the llvm backend's va_arg
594  // instruction. It can handle only passing arguments directly
595  // (typically only handled in the backend for primitive types), or
596  // aggregates passed indirectly by pointer (NOTE: if the "byval"
597  // flag has ABI impact in the callee, this implementation cannot
598  // work.)
599 
600  // Only a few cases are covered here at the moment -- those needed
601  // by the default abi.
602  llvm::Value *Val;
603 
604  if (AI.isIndirect()) {
605  assert(!AI.getPaddingType() &&
606  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
607  assert(
608  !AI.getIndirectRealign() &&
609  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
610 
611  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
612  CharUnits TyAlignForABI = TyInfo.second;
613 
614  llvm::Type *BaseTy =
615  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
616  llvm::Value *Addr =
617  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
618  return Address(Addr, TyAlignForABI);
619  } else {
620  assert((AI.isDirect() || AI.isExtend()) &&
621  "Unexpected ArgInfo Kind in generic VAArg emitter!");
622 
623  assert(!AI.getInReg() &&
624  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
625  assert(!AI.getPaddingType() &&
626  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
627  assert(!AI.getDirectOffset() &&
628  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
629  assert(!AI.getCoerceToType() &&
630  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
631 
632  Address Temp = CGF.CreateMemTemp(Ty, "varet");
633  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
634  CGF.Builder.CreateStore(Val, Temp);
635  return Temp;
636  }
637 }
638 
639 /// DefaultABIInfo - The default implementation for ABI specific
640 /// details. This implementation provides information which results in
641 /// self-consistent and sensible LLVM IR generation, but does not
642 /// conform to any particular ABI.
643 class DefaultABIInfo : public ABIInfo {
644 public:
645  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
646 
649 
650  void computeInfo(CGFunctionInfo &FI) const override {
651  if (!getCXXABI().classifyReturnType(FI))
653  for (auto &I : FI.arguments())
654  I.info = classifyArgumentType(I.type);
655  }
656 
657  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
658  QualType Ty) const override {
659  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
660  }
661 };
662 
663 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
664 public:
665  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
666  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
667 };
668 
671 
672  if (isAggregateTypeForABI(Ty)) {
673  // Records with non-trivial destructors/copy-constructors should not be
674  // passed by value.
677 
678  return getNaturalAlignIndirect(Ty);
679  }
680 
681  // Treat an enum type as its underlying type.
682  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
683  Ty = EnumTy->getDecl()->getIntegerType();
684 
685  return (Ty->isPromotableIntegerType() ?
687 }
688 
690  if (RetTy->isVoidType())
691  return ABIArgInfo::getIgnore();
692 
693  if (isAggregateTypeForABI(RetTy))
694  return getNaturalAlignIndirect(RetTy);
695 
696  // Treat an enum type as its underlying type.
697  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
698  RetTy = EnumTy->getDecl()->getIntegerType();
699 
700  return (RetTy->isPromotableIntegerType() ?
702 }
703 
704 //===----------------------------------------------------------------------===//
705 // WebAssembly ABI Implementation
706 //
707 // This is a very simple ABI that relies a lot on DefaultABIInfo.
708 //===----------------------------------------------------------------------===//
709 
710 class WebAssemblyABIInfo final : public DefaultABIInfo {
711 public:
712  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
713  : DefaultABIInfo(CGT) {}
714 
715 private:
718 
719  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
720  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
721  // overload them.
722  void computeInfo(CGFunctionInfo &FI) const override {
723  if (!getCXXABI().classifyReturnType(FI))
725  for (auto &Arg : FI.arguments())
726  Arg.info = classifyArgumentType(Arg.type);
727  }
728 
729  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
730  QualType Ty) const override;
731 };
732 
733 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
734 public:
735  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
736  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
737 };
738 
739 /// \brief Classify argument of given type \p Ty.
742 
743  if (isAggregateTypeForABI(Ty)) {
744  // Records with non-trivial destructors/copy-constructors should not be
745  // passed by value.
746  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
748  // Ignore empty structs/unions.
749  if (isEmptyRecord(getContext(), Ty, true))
750  return ABIArgInfo::getIgnore();
751  // Lower single-element structs to just pass a regular value. TODO: We
752  // could do reasonable-size multiple-element structs too, using getExpand(),
753  // though watch out for things like bitfields.
754  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
755  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
756  }
757 
758  // Otherwise just do the default thing.
760 }
761 
763  if (isAggregateTypeForABI(RetTy)) {
764  // Records with non-trivial destructors/copy-constructors should not be
765  // returned by value.
766  if (!getRecordArgABI(RetTy, getCXXABI())) {
767  // Ignore empty structs/unions.
768  if (isEmptyRecord(getContext(), RetTy, true))
769  return ABIArgInfo::getIgnore();
770  // Lower single-element structs to just return a regular value. TODO: We
771  // could do reasonable-size multiple-element structs too, using
772  // ABIArgInfo::getDirect().
773  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
774  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
775  }
776  }
777 
778  // Otherwise just do the default thing.
780 }
781 
782 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
783  QualType Ty) const {
784  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
785  getContext().getTypeInfoInChars(Ty),
787  /*AllowHigherAlign=*/ true);
788 }
789 
790 //===----------------------------------------------------------------------===//
791 // le32/PNaCl bitcode ABI Implementation
792 //
793 // This is a simplified version of the x86_32 ABI. Arguments and return values
794 // are always passed on the stack.
795 //===----------------------------------------------------------------------===//
796 
797 class PNaClABIInfo : public ABIInfo {
798  public:
799  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
800 
803 
804  void computeInfo(CGFunctionInfo &FI) const override;
806  Address VAListAddr, QualType Ty) const override;
807 };
808 
809 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
810  public:
811  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
812  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
813 };
814 
815 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
816  if (!getCXXABI().classifyReturnType(FI))
818 
819  for (auto &I : FI.arguments())
820  I.info = classifyArgumentType(I.type);
821 }
822 
823 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
824  QualType Ty) const {
825  // The PNaCL ABI is a bit odd, in that varargs don't use normal
826  // function classification. Structs get passed directly for varargs
827  // functions, through a rewriting transform in
828  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
829  // this target to actually support a va_arg instructions with an
830  // aggregate type, unlike other targets.
831  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
832 }
833 
834 /// \brief Classify argument of given type \p Ty.
836  if (isAggregateTypeForABI(Ty)) {
839  return getNaturalAlignIndirect(Ty);
840  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
841  // Treat an enum type as its underlying type.
842  Ty = EnumTy->getDecl()->getIntegerType();
843  } else if (Ty->isFloatingType()) {
844  // Floating-point types don't go inreg.
845  return ABIArgInfo::getDirect();
846  }
847 
848  return (Ty->isPromotableIntegerType() ?
850 }
851 
853  if (RetTy->isVoidType())
854  return ABIArgInfo::getIgnore();
855 
856  // In the PNaCl ABI we always return records/structures on the stack.
857  if (isAggregateTypeForABI(RetTy))
858  return getNaturalAlignIndirect(RetTy);
859 
860  // Treat an enum type as its underlying type.
861  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
862  RetTy = EnumTy->getDecl()->getIntegerType();
863 
864  return (RetTy->isPromotableIntegerType() ?
866 }
867 
868 /// IsX86_MMXType - Return true if this is an MMX type.
869 bool IsX86_MMXType(llvm::Type *IRType) {
870  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
871  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
872  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
873  IRType->getScalarSizeInBits() != 64;
874 }
875 
876 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
877  StringRef Constraint,
878  llvm::Type* Ty) {
879  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
880  .Cases("y", "&y", "^Ym", true)
881  .Default(false);
882  if (IsMMXCons && Ty->isVectorTy()) {
883  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
884  // Invalid MMX constraint
885  return nullptr;
886  }
887 
888  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
889  }
890 
891  // No operation needed
892  return Ty;
893 }
894 
895 /// Returns true if this type can be passed in SSE registers with the
896 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
897 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
898  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
899  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
900  if (BT->getKind() == BuiltinType::LongDouble) {
901  if (&Context.getTargetInfo().getLongDoubleFormat() ==
902  &llvm::APFloat::x87DoubleExtended())
903  return false;
904  }
905  return true;
906  }
907  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
908  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
909  // registers specially.
910  unsigned VecSize = Context.getTypeSize(VT);
911  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
912  return true;
913  }
914  return false;
915 }
916 
917 /// Returns true if this aggregate is small enough to be passed in SSE registers
918 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
919 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
920  return NumMembers <= 4;
921 }
922 
923 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
924 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
925  auto AI = ABIArgInfo::getDirect(T);
926  AI.setInReg(true);
927  AI.setCanBeFlattened(false);
928  return AI;
929 }
930 
931 //===----------------------------------------------------------------------===//
932 // X86-32 ABI Implementation
933 //===----------------------------------------------------------------------===//
934 
935 /// \brief Similar to llvm::CCState, but for Clang.
936 struct CCState {
937  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
938 
939  unsigned CC;
940  unsigned FreeRegs;
941  unsigned FreeSSERegs;
942 };
943 
944 enum {
945  // Vectorcall only allows the first 6 parameters to be passed in registers.
946  VectorcallMaxParamNumAsReg = 6
947 };
948 
949 /// X86_32ABIInfo - The X86-32 ABI information.
950 class X86_32ABIInfo : public SwiftABIInfo {
951  enum Class {
952  Integer,
953  Float
954  };
955 
956  static const unsigned MinABIStackAlignInBytes = 4;
957 
958  bool IsDarwinVectorABI;
959  bool IsRetSmallStructInRegABI;
960  bool IsWin32StructABI;
961  bool IsSoftFloatABI;
962  bool IsMCUABI;
963  unsigned DefaultNumRegisterParameters;
964 
965  static bool isRegisterSize(unsigned Size) {
966  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
967  }
968 
969  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
970  // FIXME: Assumes vectorcall is in use.
971  return isX86VectorTypeForVectorCall(getContext(), Ty);
972  }
973 
975  uint64_t NumMembers) const override {
976  // FIXME: Assumes vectorcall is in use.
977  return isX86VectorCallAggregateSmallEnough(NumMembers);
978  }
979 
980  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
981 
982  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
983  /// such that the argument will be passed in memory.
984  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
985 
986  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
987 
988  /// \brief Return the alignment to use for the given type on the stack.
989  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
990 
991  Class classify(QualType Ty) const;
992  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
993  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
994 
995  /// \brief Updates the number of available free registers, returns
996  /// true if any registers were allocated.
997  bool updateFreeRegs(QualType Ty, CCState &State) const;
998 
999  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1000  bool &NeedsPadding) const;
1001  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1002 
1003  bool canExpandIndirectArgument(QualType Ty) const;
1004 
1005  /// \brief Rewrite the function info so that all memory arguments use
1006  /// inalloca.
1007  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1008 
1009  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1010  CharUnits &StackOffset, ABIArgInfo &Info,
1011  QualType Type) const;
1012  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1013  bool &UsedInAlloca) const;
1014 
1015 public:
1016 
1017  void computeInfo(CGFunctionInfo &FI) const override;
1018  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1019  QualType Ty) const override;
1020 
1021  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1022  bool RetSmallStructInRegABI, bool Win32StructABI,
1023  unsigned NumRegisterParameters, bool SoftFloatABI)
1024  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1025  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1026  IsWin32StructABI(Win32StructABI),
1027  IsSoftFloatABI(SoftFloatABI),
1028  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1029  DefaultNumRegisterParameters(NumRegisterParameters) {}
1030 
1031  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
1032  ArrayRef<llvm::Type*> scalars,
1033  bool asReturnValue) const override {
1034  // LLVM's x86-32 lowering currently only assigns up to three
1035  // integer registers and three fp registers. Oddly, it'll use up to
1036  // four vector registers for vectors, but those can overlap with the
1037  // scalar registers.
1038  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1039  }
1040 
1041  bool isSwiftErrorInRegister() const override {
1042  // x86-32 lowering does not support passing swifterror in a register.
1043  return false;
1044  }
1045 };
1046 
1047 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1048 public:
1049  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1050  bool RetSmallStructInRegABI, bool Win32StructABI,
1051  unsigned NumRegisterParameters, bool SoftFloatABI)
1052  : TargetCodeGenInfo(new X86_32ABIInfo(
1053  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1054  NumRegisterParameters, SoftFloatABI)) {}
1055 
1056  static bool isStructReturnInRegABI(
1057  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1058 
1059  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1061  ForDefinition_t IsForDefinition) const override;
1062 
1063  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1064  // Darwin uses different dwarf register numbers for EH.
1065  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1066  return 4;
1067  }
1068 
1069  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1070  llvm::Value *Address) const override;
1071 
1072  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1073  StringRef Constraint,
1074  llvm::Type* Ty) const override {
1075  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1076  }
1077 
1078  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1079  std::string &Constraints,
1080  std::vector<llvm::Type *> &ResultRegTypes,
1081  std::vector<llvm::Type *> &ResultTruncRegTypes,
1082  std::vector<LValue> &ResultRegDests,
1083  std::string &AsmString,
1084  unsigned NumOutputs) const override;
1085 
1086  llvm::Constant *
1087  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1088  unsigned Sig = (0xeb << 0) | // jmp rel8
1089  (0x06 << 8) | // .+0x08
1090  ('v' << 16) |
1091  ('2' << 24);
1092  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1093  }
1094 
1095  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1096  return "movl\t%ebp, %ebp"
1097  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1098  }
1099 };
1100 
1101 }
1102 
1103 /// Rewrite input constraint references after adding some output constraints.
1104 /// In the case where there is one output and one input and we add one output,
1105 /// we need to replace all operand references greater than or equal to 1:
1106 /// mov $0, $1
1107 /// mov eax, $1
1108 /// The result will be:
1109 /// mov $0, $2
1110 /// mov eax, $2
1111 static void rewriteInputConstraintReferences(unsigned FirstIn,
1112  unsigned NumNewOuts,
1113  std::string &AsmString) {
1114  std::string Buf;
1115  llvm::raw_string_ostream OS(Buf);
1116  size_t Pos = 0;
1117  while (Pos < AsmString.size()) {
1118  size_t DollarStart = AsmString.find('$', Pos);
1119  if (DollarStart == std::string::npos)
1120  DollarStart = AsmString.size();
1121  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1122  if (DollarEnd == std::string::npos)
1123  DollarEnd = AsmString.size();
1124  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1125  Pos = DollarEnd;
1126  size_t NumDollars = DollarEnd - DollarStart;
1127  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1128  // We have an operand reference.
1129  size_t DigitStart = Pos;
1130  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1131  if (DigitEnd == std::string::npos)
1132  DigitEnd = AsmString.size();
1133  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1134  unsigned OperandIndex;
1135  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1136  if (OperandIndex >= FirstIn)
1137  OperandIndex += NumNewOuts;
1138  OS << OperandIndex;
1139  } else {
1140  OS << OperandStr;
1141  }
1142  Pos = DigitEnd;
1143  }
1144  }
1145  AsmString = std::move(OS.str());
1146 }
1147 
1148 /// Add output constraints for EAX:EDX because they are return registers.
1149 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1150  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1151  std::vector<llvm::Type *> &ResultRegTypes,
1152  std::vector<llvm::Type *> &ResultTruncRegTypes,
1153  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1154  unsigned NumOutputs) const {
1155  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1156 
1157  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1158  // larger.
1159  if (!Constraints.empty())
1160  Constraints += ',';
1161  if (RetWidth <= 32) {
1162  Constraints += "={eax}";
1163  ResultRegTypes.push_back(CGF.Int32Ty);
1164  } else {
1165  // Use the 'A' constraint for EAX:EDX.
1166  Constraints += "=A";
1167  ResultRegTypes.push_back(CGF.Int64Ty);
1168  }
1169 
1170  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1171  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1172  ResultTruncRegTypes.push_back(CoerceTy);
1173 
1174  // Coerce the integer by bitcasting the return slot pointer.
1175  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1176  CoerceTy->getPointerTo()));
1177  ResultRegDests.push_back(ReturnSlot);
1178 
1179  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1180 }
1181 
1182 /// shouldReturnTypeInRegister - Determine if the given type should be
1183 /// returned in a register (for the Darwin and MCU ABI).
1184 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1185  ASTContext &Context) const {
1186  uint64_t Size = Context.getTypeSize(Ty);
1187 
1188  // For i386, type must be register sized.
1189  // For the MCU ABI, it only needs to be <= 8-byte
1190  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1191  return false;
1192 
1193  if (Ty->isVectorType()) {
1194  // 64- and 128- bit vectors inside structures are not returned in
1195  // registers.
1196  if (Size == 64 || Size == 128)
1197  return false;
1198 
1199  return true;
1200  }
1201 
1202  // If this is a builtin, pointer, enum, complex type, member pointer, or
1203  // member function pointer it is ok.
1204  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1205  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1206  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1207  return true;
1208 
1209  // Arrays are treated like records.
1210  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1211  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1212 
1213  // Otherwise, it must be a record type.
1214  const RecordType *RT = Ty->getAs<RecordType>();
1215  if (!RT) return false;
1216 
1217  // FIXME: Traverse bases here too.
1218 
1219  // Structure types are passed in register if all fields would be
1220  // passed in a register.
1221  for (const auto *FD : RT->getDecl()->fields()) {
1222  // Empty fields are ignored.
1223  if (isEmptyField(Context, FD, true))
1224  continue;
1225 
1226  // Check fields recursively.
1227  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1228  return false;
1229  }
1230  return true;
1231 }
1232 
1233 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1234  // Treat complex types as the element type.
1235  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1236  Ty = CTy->getElementType();
1237 
1238  // Check for a type which we know has a simple scalar argument-passing
1239  // convention without any padding. (We're specifically looking for 32
1240  // and 64-bit integer and integer-equivalents, float, and double.)
1241  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1242  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1243  return false;
1244 
1245  uint64_t Size = Context.getTypeSize(Ty);
1246  return Size == 32 || Size == 64;
1247 }
1248 
1249 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1250  uint64_t &Size) {
1251  for (const auto *FD : RD->fields()) {
1252  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1253  // argument is smaller than 32-bits, expanding the struct will create
1254  // alignment padding.
1255  if (!is32Or64BitBasicType(FD->getType(), Context))
1256  return false;
1257 
1258  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1259  // how to expand them yet, and the predicate for telling if a bitfield still
1260  // counts as "basic" is more complicated than what we were doing previously.
1261  if (FD->isBitField())
1262  return false;
1263 
1264  Size += Context.getTypeSize(FD->getType());
1265  }
1266  return true;
1267 }
1268 
1269 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1270  uint64_t &Size) {
1271  // Don't do this if there are any non-empty bases.
1272  for (const CXXBaseSpecifier &Base : RD->bases()) {
1273  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1274  Size))
1275  return false;
1276  }
1277  if (!addFieldSizes(Context, RD, Size))
1278  return false;
1279  return true;
1280 }
1281 
1282 /// Test whether an argument type which is to be passed indirectly (on the
1283 /// stack) would have the equivalent layout if it was expanded into separate
1284 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1285 /// optimizations.
1286 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1287  // We can only expand structure types.
1288  const RecordType *RT = Ty->getAs<RecordType>();
1289  if (!RT)
1290  return false;
1291  const RecordDecl *RD = RT->getDecl();
1292  uint64_t Size = 0;
1293  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1294  if (!IsWin32StructABI) {
1295  // On non-Windows, we have to conservatively match our old bitcode
1296  // prototypes in order to be ABI-compatible at the bitcode level.
1297  if (!CXXRD->isCLike())
1298  return false;
1299  } else {
1300  // Don't do this for dynamic classes.
1301  if (CXXRD->isDynamicClass())
1302  return false;
1303  }
1304  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1305  return false;
1306  } else {
1307  if (!addFieldSizes(getContext(), RD, Size))
1308  return false;
1309  }
1310 
1311  // We can do this if there was no alignment padding.
1312  return Size == getContext().getTypeSize(Ty);
1313 }
1314 
1315 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1316  // If the return value is indirect, then the hidden argument is consuming one
1317  // integer register.
1318  if (State.FreeRegs) {
1319  --State.FreeRegs;
1320  if (!IsMCUABI)
1321  return getNaturalAlignIndirectInReg(RetTy);
1322  }
1323  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1324 }
1325 
1327  CCState &State) const {
1328  if (RetTy->isVoidType())
1329  return ABIArgInfo::getIgnore();
1330 
1331  const Type *Base = nullptr;
1332  uint64_t NumElts = 0;
1333  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1334  State.CC == llvm::CallingConv::X86_RegCall) &&
1335  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1336  // The LLVM struct type for such an aggregate should lower properly.
1337  return ABIArgInfo::getDirect();
1338  }
1339 
1340  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1341  // On Darwin, some vectors are returned in registers.
1342  if (IsDarwinVectorABI) {
1343  uint64_t Size = getContext().getTypeSize(RetTy);
1344 
1345  // 128-bit vectors are a special case; they are returned in
1346  // registers and we need to make sure to pick a type the LLVM
1347  // backend will like.
1348  if (Size == 128)
1349  return ABIArgInfo::getDirect(llvm::VectorType::get(
1350  llvm::Type::getInt64Ty(getVMContext()), 2));
1351 
1352  // Always return in register if it fits in a general purpose
1353  // register, or if it is 64 bits and has a single element.
1354  if ((Size == 8 || Size == 16 || Size == 32) ||
1355  (Size == 64 && VT->getNumElements() == 1))
1356  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1357  Size));
1358 
1359  return getIndirectReturnResult(RetTy, State);
1360  }
1361 
1362  return ABIArgInfo::getDirect();
1363  }
1364 
1365  if (isAggregateTypeForABI(RetTy)) {
1366  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1367  // Structures with flexible arrays are always indirect.
1368  if (RT->getDecl()->hasFlexibleArrayMember())
1369  return getIndirectReturnResult(RetTy, State);
1370  }
1371 
1372  // If specified, structs and unions are always indirect.
1373  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1374  return getIndirectReturnResult(RetTy, State);
1375 
1376  // Ignore empty structs/unions.
1377  if (isEmptyRecord(getContext(), RetTy, true))
1378  return ABIArgInfo::getIgnore();
1379 
1380  // Small structures which are register sized are generally returned
1381  // in a register.
1382  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1383  uint64_t Size = getContext().getTypeSize(RetTy);
1384 
1385  // As a special-case, if the struct is a "single-element" struct, and
1386  // the field is of type "float" or "double", return it in a
1387  // floating-point register. (MSVC does not apply this special case.)
1388  // We apply a similar transformation for pointer types to improve the
1389  // quality of the generated IR.
1390  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1391  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1392  || SeltTy->hasPointerRepresentation())
1393  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1394 
1395  // FIXME: We should be able to narrow this integer in cases with dead
1396  // padding.
1397  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1398  }
1399 
1400  return getIndirectReturnResult(RetTy, State);
1401  }
1402 
1403  // Treat an enum type as its underlying type.
1404  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1405  RetTy = EnumTy->getDecl()->getIntegerType();
1406 
1407  return (RetTy->isPromotableIntegerType() ?
1409 }
1410 
1411 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1412  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1413 }
1414 
1415 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1416  const RecordType *RT = Ty->getAs<RecordType>();
1417  if (!RT)
1418  return 0;
1419  const RecordDecl *RD = RT->getDecl();
1420 
1421  // If this is a C++ record, check the bases first.
1422  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1423  for (const auto &I : CXXRD->bases())
1424  if (!isRecordWithSSEVectorType(Context, I.getType()))
1425  return false;
1426 
1427  for (const auto *i : RD->fields()) {
1428  QualType FT = i->getType();
1429 
1430  if (isSSEVectorType(Context, FT))
1431  return true;
1432 
1433  if (isRecordWithSSEVectorType(Context, FT))
1434  return true;
1435  }
1436 
1437  return false;
1438 }
1439 
1440 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1441  unsigned Align) const {
1442  // Otherwise, if the alignment is less than or equal to the minimum ABI
1443  // alignment, just use the default; the backend will handle this.
1444  if (Align <= MinABIStackAlignInBytes)
1445  return 0; // Use default alignment.
1446 
1447  // On non-Darwin, the stack type alignment is always 4.
1448  if (!IsDarwinVectorABI) {
1449  // Set explicit alignment, since we may need to realign the top.
1450  return MinABIStackAlignInBytes;
1451  }
1452 
1453  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1454  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1456  return 16;
1457 
1458  return MinABIStackAlignInBytes;
1459 }
1460 
1461 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1462  CCState &State) const {
1463  if (!ByVal) {
1464  if (State.FreeRegs) {
1465  --State.FreeRegs; // Non-byval indirects just use one pointer.
1466  if (!IsMCUABI)
1467  return getNaturalAlignIndirectInReg(Ty);
1468  }
1469  return getNaturalAlignIndirect(Ty, false);
1470  }
1471 
1472  // Compute the byval alignment.
1473  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1474  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1475  if (StackAlign == 0)
1476  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1477 
1478  // If the stack alignment is less than the type alignment, realign the
1479  // argument.
1480  bool Realign = TypeAlign > StackAlign;
1482  /*ByVal=*/true, Realign);
1483 }
1484 
1485 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1486  const Type *T = isSingleElementStruct(Ty, getContext());
1487  if (!T)
1488  T = Ty.getTypePtr();
1489 
1490  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1491  BuiltinType::Kind K = BT->getKind();
1492  if (K == BuiltinType::Float || K == BuiltinType::Double)
1493  return Float;
1494  }
1495  return Integer;
1496 }
1497 
1498 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1499  if (!IsSoftFloatABI) {
1500  Class C = classify(Ty);
1501  if (C == Float)
1502  return false;
1503  }
1504 
1505  unsigned Size = getContext().getTypeSize(Ty);
1506  unsigned SizeInRegs = (Size + 31) / 32;
1507 
1508  if (SizeInRegs == 0)
1509  return false;
1510 
1511  if (!IsMCUABI) {
1512  if (SizeInRegs > State.FreeRegs) {
1513  State.FreeRegs = 0;
1514  return false;
1515  }
1516  } else {
1517  // The MCU psABI allows passing parameters in-reg even if there are
1518  // earlier parameters that are passed on the stack. Also,
1519  // it does not allow passing >8-byte structs in-register,
1520  // even if there are 3 free registers available.
1521  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1522  return false;
1523  }
1524 
1525  State.FreeRegs -= SizeInRegs;
1526  return true;
1527 }
1528 
1529 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1530  bool &InReg,
1531  bool &NeedsPadding) const {
1532  // On Windows, aggregates other than HFAs are never passed in registers, and
1533  // they do not consume register slots. Homogenous floating-point aggregates
1534  // (HFAs) have already been dealt with at this point.
1535  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1536  return false;
1537 
1538  NeedsPadding = false;
1539  InReg = !IsMCUABI;
1540 
1541  if (!updateFreeRegs(Ty, State))
1542  return false;
1543 
1544  if (IsMCUABI)
1545  return true;
1546 
1547  if (State.CC == llvm::CallingConv::X86_FastCall ||
1548  State.CC == llvm::CallingConv::X86_VectorCall ||
1549  State.CC == llvm::CallingConv::X86_RegCall) {
1550  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1551  NeedsPadding = true;
1552 
1553  return false;
1554  }
1555 
1556  return true;
1557 }
1558 
1559 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1560  if (!updateFreeRegs(Ty, State))
1561  return false;
1562 
1563  if (IsMCUABI)
1564  return false;
1565 
1566  if (State.CC == llvm::CallingConv::X86_FastCall ||
1567  State.CC == llvm::CallingConv::X86_VectorCall ||
1568  State.CC == llvm::CallingConv::X86_RegCall) {
1569  if (getContext().getTypeSize(Ty) > 32)
1570  return false;
1571 
1572  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1573  Ty->isReferenceType());
1574  }
1575 
1576  return true;
1577 }
1578 
1580  CCState &State) const {
1581  // FIXME: Set alignment on indirect arguments.
1582 
1584 
1585  // Check with the C++ ABI first.
1586  const RecordType *RT = Ty->getAs<RecordType>();
1587  if (RT) {
1589  if (RAA == CGCXXABI::RAA_Indirect) {
1590  return getIndirectResult(Ty, false, State);
1591  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1592  // The field index doesn't matter, we'll fix it up later.
1593  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1594  }
1595  }
1596 
1597  // Regcall uses the concept of a homogenous vector aggregate, similar
1598  // to other targets.
1599  const Type *Base = nullptr;
1600  uint64_t NumElts = 0;
1601  if (State.CC == llvm::CallingConv::X86_RegCall &&
1602  isHomogeneousAggregate(Ty, Base, NumElts)) {
1603 
1604  if (State.FreeSSERegs >= NumElts) {
1605  State.FreeSSERegs -= NumElts;
1606  if (Ty->isBuiltinType() || Ty->isVectorType())
1607  return ABIArgInfo::getDirect();
1608  return ABIArgInfo::getExpand();
1609  }
1610  return getIndirectResult(Ty, /*ByVal=*/false, State);
1611  }
1612 
1613  if (isAggregateTypeForABI(Ty)) {
1614  // Structures with flexible arrays are always indirect.
1615  // FIXME: This should not be byval!
1616  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1617  return getIndirectResult(Ty, true, State);
1618 
1619  // Ignore empty structs/unions on non-Windows.
1620  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1621  return ABIArgInfo::getIgnore();
1622 
1623  llvm::LLVMContext &LLVMContext = getVMContext();
1624  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1625  bool NeedsPadding = false;
1626  bool InReg;
1627  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1628  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1629  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1630  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1631  if (InReg)
1632  return ABIArgInfo::getDirectInReg(Result);
1633  else
1634  return ABIArgInfo::getDirect(Result);
1635  }
1636  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1637 
1638  // Expand small (<= 128-bit) record types when we know that the stack layout
1639  // of those arguments will match the struct. This is important because the
1640  // LLVM backend isn't smart enough to remove byval, which inhibits many
1641  // optimizations.
1642  // Don't do this for the MCU if there are still free integer registers
1643  // (see X86_64 ABI for full explanation).
1644  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1645  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1647  State.CC == llvm::CallingConv::X86_FastCall ||
1648  State.CC == llvm::CallingConv::X86_VectorCall ||
1649  State.CC == llvm::CallingConv::X86_RegCall,
1650  PaddingType);
1651 
1652  return getIndirectResult(Ty, true, State);
1653  }
1654 
1655  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1656  // On Darwin, some vectors are passed in memory, we handle this by passing
1657  // it as an i8/i16/i32/i64.
1658  if (IsDarwinVectorABI) {
1659  uint64_t Size = getContext().getTypeSize(Ty);
1660  if ((Size == 8 || Size == 16 || Size == 32) ||
1661  (Size == 64 && VT->getNumElements() == 1))
1662  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1663  Size));
1664  }
1665 
1666  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1667  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1668 
1669  return ABIArgInfo::getDirect();
1670  }
1671 
1672 
1673  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1674  Ty = EnumTy->getDecl()->getIntegerType();
1675 
1676  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1677 
1678  if (Ty->isPromotableIntegerType()) {
1679  if (InReg)
1680  return ABIArgInfo::getExtendInReg();
1681  return ABIArgInfo::getExtend();
1682  }
1683 
1684  if (InReg)
1685  return ABIArgInfo::getDirectInReg();
1686  return ABIArgInfo::getDirect();
1687 }
1688 
1689 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1690  bool &UsedInAlloca) const {
1691  // Vectorcall x86 works subtly different than in x64, so the format is
1692  // a bit different than the x64 version. First, all vector types (not HVAs)
1693  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1694  // This differs from the x64 implementation, where the first 6 by INDEX get
1695  // registers.
1696  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1697  // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1698  // first take up the remaining YMM/XMM registers. If insufficient registers
1699  // remain but an integer register (ECX/EDX) is available, it will be passed
1700  // in that, else, on the stack.
1701  for (auto &I : FI.arguments()) {
1702  // First pass do all the vector types.
1703  const Type *Base = nullptr;
1704  uint64_t NumElts = 0;
1705  const QualType& Ty = I.type;
1706  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1707  isHomogeneousAggregate(Ty, Base, NumElts)) {
1708  if (State.FreeSSERegs >= NumElts) {
1709  State.FreeSSERegs -= NumElts;
1710  I.info = ABIArgInfo::getDirect();
1711  } else {
1712  I.info = classifyArgumentType(Ty, State);
1713  }
1714  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1715  }
1716  }
1717 
1718  for (auto &I : FI.arguments()) {
1719  // Second pass, do the rest!
1720  const Type *Base = nullptr;
1721  uint64_t NumElts = 0;
1722  const QualType& Ty = I.type;
1723  bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1724 
1725  if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1726  // Assign true HVAs (non vector/native FP types).
1727  if (State.FreeSSERegs >= NumElts) {
1728  State.FreeSSERegs -= NumElts;
1729  I.info = getDirectX86Hva();
1730  } else {
1731  I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1732  }
1733  } else if (!IsHva) {
1734  // Assign all Non-HVAs, so this will exclude Vector/FP args.
1735  I.info = classifyArgumentType(Ty, State);
1736  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1737  }
1738  }
1739 }
1740 
1741 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1742  CCState State(FI.getCallingConvention());
1743  if (IsMCUABI)
1744  State.FreeRegs = 3;
1745  else if (State.CC == llvm::CallingConv::X86_FastCall)
1746  State.FreeRegs = 2;
1747  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1748  State.FreeRegs = 2;
1749  State.FreeSSERegs = 6;
1750  } else if (FI.getHasRegParm())
1751  State.FreeRegs = FI.getRegParm();
1752  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1753  State.FreeRegs = 5;
1754  State.FreeSSERegs = 8;
1755  } else
1756  State.FreeRegs = DefaultNumRegisterParameters;
1757 
1758  if (!getCXXABI().classifyReturnType(FI)) {
1760  } else if (FI.getReturnInfo().isIndirect()) {
1761  // The C++ ABI is not aware of register usage, so we have to check if the
1762  // return value was sret and put it in a register ourselves if appropriate.
1763  if (State.FreeRegs) {
1764  --State.FreeRegs; // The sret parameter consumes a register.
1765  if (!IsMCUABI)
1766  FI.getReturnInfo().setInReg(true);
1767  }
1768  }
1769 
1770  // The chain argument effectively gives us another free register.
1771  if (FI.isChainCall())
1772  ++State.FreeRegs;
1773 
1774  bool UsedInAlloca = false;
1775  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1776  computeVectorCallArgs(FI, State, UsedInAlloca);
1777  } else {
1778  // If not vectorcall, revert to normal behavior.
1779  for (auto &I : FI.arguments()) {
1780  I.info = classifyArgumentType(I.type, State);
1781  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1782  }
1783  }
1784 
1785  // If we needed to use inalloca for any argument, do a second pass and rewrite
1786  // all the memory arguments to use inalloca.
1787  if (UsedInAlloca)
1788  rewriteWithInAlloca(FI);
1789 }
1790 
1791 void
1792 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1793  CharUnits &StackOffset, ABIArgInfo &Info,
1794  QualType Type) const {
1795  // Arguments are always 4-byte-aligned.
1796  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1797 
1798  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1799  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1800  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1801  StackOffset += getContext().getTypeSizeInChars(Type);
1802 
1803  // Insert padding bytes to respect alignment.
1804  CharUnits FieldEnd = StackOffset;
1805  StackOffset = FieldEnd.alignTo(FieldAlign);
1806  if (StackOffset != FieldEnd) {
1807  CharUnits NumBytes = StackOffset - FieldEnd;
1808  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1809  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1810  FrameFields.push_back(Ty);
1811  }
1812 }
1813 
1814 static bool isArgInAlloca(const ABIArgInfo &Info) {
1815  // Leave ignored and inreg arguments alone.
1816  switch (Info.getKind()) {
1817  case ABIArgInfo::InAlloca:
1818  return true;
1819  case ABIArgInfo::Indirect:
1820  assert(Info.getIndirectByVal());
1821  return true;
1822  case ABIArgInfo::Ignore:
1823  return false;
1824  case ABIArgInfo::Direct:
1825  case ABIArgInfo::Extend:
1826  if (Info.getInReg())
1827  return false;
1828  return true;
1829  case ABIArgInfo::Expand:
1831  // These are aggregate types which are never passed in registers when
1832  // inalloca is involved.
1833  return true;
1834  }
1835  llvm_unreachable("invalid enum");
1836 }
1837 
1838 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1839  assert(IsWin32StructABI && "inalloca only supported on win32");
1840 
1841  // Build a packed struct type for all of the arguments in memory.
1842  SmallVector<llvm::Type *, 6> FrameFields;
1843 
1844  // The stack alignment is always 4.
1845  CharUnits StackAlign = CharUnits::fromQuantity(4);
1846 
1847  CharUnits StackOffset;
1848  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1849 
1850  // Put 'this' into the struct before 'sret', if necessary.
1851  bool IsThisCall =
1852  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1853  ABIArgInfo &Ret = FI.getReturnInfo();
1854  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1855  isArgInAlloca(I->info)) {
1856  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1857  ++I;
1858  }
1859 
1860  // Put the sret parameter into the inalloca struct if it's in memory.
1861  if (Ret.isIndirect() && !Ret.getInReg()) {
1863  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1864  // On Windows, the hidden sret parameter is always returned in eax.
1865  Ret.setInAllocaSRet(IsWin32StructABI);
1866  }
1867 
1868  // Skip the 'this' parameter in ecx.
1869  if (IsThisCall)
1870  ++I;
1871 
1872  // Put arguments passed in memory into the struct.
1873  for (; I != E; ++I) {
1874  if (isArgInAlloca(I->info))
1875  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1876  }
1877 
1878  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1879  /*isPacked=*/true),
1880  StackAlign);
1881 }
1882 
1883 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1884  Address VAListAddr, QualType Ty) const {
1885 
1886  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1887 
1888  // x86-32 changes the alignment of certain arguments on the stack.
1889  //
1890  // Just messing with TypeInfo like this works because we never pass
1891  // anything indirectly.
1893  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1894 
1895  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1897  /*AllowHigherAlign*/ true);
1898 }
1899 
1900 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1901  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1902  assert(Triple.getArch() == llvm::Triple::x86);
1903 
1904  switch (Opts.getStructReturnConvention()) {
1906  break;
1907  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1908  return false;
1909  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1910  return true;
1911  }
1912 
1913  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1914  return true;
1915 
1916  switch (Triple.getOS()) {
1917  case llvm::Triple::DragonFly:
1918  case llvm::Triple::FreeBSD:
1919  case llvm::Triple::OpenBSD:
1920  case llvm::Triple::Win32:
1921  return true;
1922  default:
1923  return false;
1924  }
1925 }
1926 
1927 void X86_32TargetCodeGenInfo::setTargetAttributes(
1928  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
1929  ForDefinition_t IsForDefinition) const {
1930  if (!IsForDefinition)
1931  return;
1932  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1933  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1934  // Get the LLVM function.
1935  llvm::Function *Fn = cast<llvm::Function>(GV);
1936 
1937  // Now add the 'alignstack' attribute with a value of 16.
1938  llvm::AttrBuilder B;
1939  B.addStackAlignmentAttr(16);
1940  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
1941  }
1942  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1943  llvm::Function *Fn = cast<llvm::Function>(GV);
1944  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1945  }
1946  }
1947 }
1948 
1949 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1951  llvm::Value *Address) const {
1952  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1953 
1954  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1955 
1956  // 0-7 are the eight integer registers; the order is different
1957  // on Darwin (for EH), but the range is the same.
1958  // 8 is %eip.
1959  AssignToArrayRange(Builder, Address, Four8, 0, 8);
1960 
1961  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1962  // 12-16 are st(0..4). Not sure why we stop at 4.
1963  // These have size 16, which is sizeof(long double) on
1964  // platforms with 8-byte alignment for that type.
1965  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1966  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1967 
1968  } else {
1969  // 9 is %eflags, which doesn't get a size on Darwin for some
1970  // reason.
1971  Builder.CreateAlignedStore(
1972  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1973  CharUnits::One());
1974 
1975  // 11-16 are st(0..5). Not sure why we stop at 5.
1976  // These have size 12, which is sizeof(long double) on
1977  // platforms with 4-byte alignment for that type.
1978  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1979  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1980  }
1981 
1982  return false;
1983 }
1984 
1985 //===----------------------------------------------------------------------===//
1986 // X86-64 ABI Implementation
1987 //===----------------------------------------------------------------------===//
1988 
1989 
1990 namespace {
1991 /// The AVX ABI level for X86 targets.
1992 enum class X86AVXABILevel {
1993  None,
1994  AVX,
1995  AVX512
1996 };
1997 
1998 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1999 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2000  switch (AVXLevel) {
2001  case X86AVXABILevel::AVX512:
2002  return 512;
2003  case X86AVXABILevel::AVX:
2004  return 256;
2005  case X86AVXABILevel::None:
2006  return 128;
2007  }
2008  llvm_unreachable("Unknown AVXLevel");
2009 }
2010 
2011 /// X86_64ABIInfo - The X86_64 ABI information.
2012 class X86_64ABIInfo : public SwiftABIInfo {
2013  enum Class {
2014  Integer = 0,
2015  SSE,
2016  SSEUp,
2017  X87,
2018  X87Up,
2019  ComplexX87,
2020  NoClass,
2021  Memory
2022  };
2023 
2024  /// merge - Implement the X86_64 ABI merging algorithm.
2025  ///
2026  /// Merge an accumulating classification \arg Accum with a field
2027  /// classification \arg Field.
2028  ///
2029  /// \param Accum - The accumulating classification. This should
2030  /// always be either NoClass or the result of a previous merge
2031  /// call. In addition, this should never be Memory (the caller
2032  /// should just return Memory for the aggregate).
2033  static Class merge(Class Accum, Class Field);
2034 
2035  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2036  ///
2037  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2038  /// final MEMORY or SSE classes when necessary.
2039  ///
2040  /// \param AggregateSize - The size of the current aggregate in
2041  /// the classification process.
2042  ///
2043  /// \param Lo - The classification for the parts of the type
2044  /// residing in the low word of the containing object.
2045  ///
2046  /// \param Hi - The classification for the parts of the type
2047  /// residing in the higher words of the containing object.
2048  ///
2049  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2050 
2051  /// classify - Determine the x86_64 register classes in which the
2052  /// given type T should be passed.
2053  ///
2054  /// \param Lo - The classification for the parts of the type
2055  /// residing in the low word of the containing object.
2056  ///
2057  /// \param Hi - The classification for the parts of the type
2058  /// residing in the high word of the containing object.
2059  ///
2060  /// \param OffsetBase - The bit offset of this type in the
2061  /// containing object. Some parameters are classified different
2062  /// depending on whether they straddle an eightbyte boundary.
2063  ///
2064  /// \param isNamedArg - Whether the argument in question is a "named"
2065  /// argument, as used in AMD64-ABI 3.5.7.
2066  ///
2067  /// If a word is unused its result will be NoClass; if a type should
2068  /// be passed in Memory then at least the classification of \arg Lo
2069  /// will be Memory.
2070  ///
2071  /// The \arg Lo class will be NoClass iff the argument is ignored.
2072  ///
2073  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2074  /// also be ComplexX87.
2075  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2076  bool isNamedArg) const;
2077 
2078  llvm::Type *GetByteVectorType(QualType Ty) const;
2079  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2080  unsigned IROffset, QualType SourceTy,
2081  unsigned SourceOffset) const;
2082  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2083  unsigned IROffset, QualType SourceTy,
2084  unsigned SourceOffset) const;
2085 
2086  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2087  /// such that the argument will be returned in memory.
2088  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2089 
2090  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2091  /// such that the argument will be passed in memory.
2092  ///
2093  /// \param freeIntRegs - The number of free integer registers remaining
2094  /// available.
2095  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2096 
2097  ABIArgInfo classifyReturnType(QualType RetTy) const;
2098 
2099  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2100  unsigned &neededInt, unsigned &neededSSE,
2101  bool isNamedArg) const;
2102 
2103  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2104  unsigned &NeededSSE) const;
2105 
2106  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2107  unsigned &NeededSSE) const;
2108 
2109  bool IsIllegalVectorType(QualType Ty) const;
2110 
2111  /// The 0.98 ABI revision clarified a lot of ambiguities,
2112  /// unfortunately in ways that were not always consistent with
2113  /// certain previous compilers. In particular, platforms which
2114  /// required strict binary compatibility with older versions of GCC
2115  /// may need to exempt themselves.
2116  bool honorsRevision0_98() const {
2117  return !getTarget().getTriple().isOSDarwin();
2118  }
2119 
2120  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2121  /// classify it as INTEGER (for compatibility with older clang compilers).
2122  bool classifyIntegerMMXAsSSE() const {
2123  // Clang <= 3.8 did not do this.
2124  if (getCodeGenOpts().getClangABICompat() <=
2126  return false;
2127 
2128  const llvm::Triple &Triple = getTarget().getTriple();
2129  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2130  return false;
2131  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2132  return false;
2133  return true;
2134  }
2135 
2136  X86AVXABILevel AVXLevel;
2137  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2138  // 64-bit hardware.
2139  bool Has64BitPointers;
2140 
2141 public:
2142  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2143  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2144  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2145  }
2146 
2147  bool isPassedUsingAVXType(QualType type) const {
2148  unsigned neededInt, neededSSE;
2149  // The freeIntRegs argument doesn't matter here.
2150  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2151  /*isNamedArg*/true);
2152  if (info.isDirect()) {
2153  llvm::Type *ty = info.getCoerceToType();
2154  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2155  return (vectorTy->getBitWidth() > 128);
2156  }
2157  return false;
2158  }
2159 
2160  void computeInfo(CGFunctionInfo &FI) const override;
2161 
2162  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2163  QualType Ty) const override;
2164  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2165  QualType Ty) const override;
2166 
2167  bool has64BitPointers() const {
2168  return Has64BitPointers;
2169  }
2170 
2171  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2172  ArrayRef<llvm::Type*> scalars,
2173  bool asReturnValue) const override {
2174  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2175  }
2176  bool isSwiftErrorInRegister() const override {
2177  return true;
2178  }
2179 };
2180 
2181 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2182 class WinX86_64ABIInfo : public SwiftABIInfo {
2183 public:
2184  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2185  : SwiftABIInfo(CGT),
2186  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2187 
2188  void computeInfo(CGFunctionInfo &FI) const override;
2189 
2190  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2191  QualType Ty) const override;
2192 
2193  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2194  // FIXME: Assumes vectorcall is in use.
2195  return isX86VectorTypeForVectorCall(getContext(), Ty);
2196  }
2197 
2198  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2199  uint64_t NumMembers) const override {
2200  // FIXME: Assumes vectorcall is in use.
2201  return isX86VectorCallAggregateSmallEnough(NumMembers);
2202  }
2203 
2204  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
2205  ArrayRef<llvm::Type *> scalars,
2206  bool asReturnValue) const override {
2207  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2208  }
2209 
2210  bool isSwiftErrorInRegister() const override {
2211  return true;
2212  }
2213 
2214 private:
2215  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2216  bool IsVectorCall, bool IsRegCall) const;
2217  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2218  const ABIArgInfo &current) const;
2219  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2220  bool IsVectorCall, bool IsRegCall) const;
2221 
2222  bool IsMingw64;
2223 };
2224 
2225 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2226 public:
2227  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2228  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2229 
2230  const X86_64ABIInfo &getABIInfo() const {
2231  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2232  }
2233 
2234  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2235  return 7;
2236  }
2237 
2238  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2239  llvm::Value *Address) const override {
2240  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2241 
2242  // 0-15 are the 16 integer registers.
2243  // 16 is %rip.
2244  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2245  return false;
2246  }
2247 
2248  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2249  StringRef Constraint,
2250  llvm::Type* Ty) const override {
2251  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2252  }
2253 
2254  bool isNoProtoCallVariadic(const CallArgList &args,
2255  const FunctionNoProtoType *fnType) const override {
2256  // The default CC on x86-64 sets %al to the number of SSA
2257  // registers used, and GCC sets this when calling an unprototyped
2258  // function, so we override the default behavior. However, don't do
2259  // that when AVX types are involved: the ABI explicitly states it is
2260  // undefined, and it doesn't work in practice because of how the ABI
2261  // defines varargs anyway.
2262  if (fnType->getCallConv() == CC_C) {
2263  bool HasAVXType = false;
2264  for (CallArgList::const_iterator
2265  it = args.begin(), ie = args.end(); it != ie; ++it) {
2266  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2267  HasAVXType = true;
2268  break;
2269  }
2270  }
2271 
2272  if (!HasAVXType)
2273  return true;
2274  }
2275 
2276  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2277  }
2278 
2279  llvm::Constant *
2280  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2281  unsigned Sig = (0xeb << 0) | // jmp rel8
2282  (0x06 << 8) | // .+0x08
2283  ('v' << 16) |
2284  ('2' << 24);
2285  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2286  }
2287 
2288  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2290  ForDefinition_t IsForDefinition) const override {
2291  if (!IsForDefinition)
2292  return;
2293  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2294  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2295  // Get the LLVM function.
2296  auto *Fn = cast<llvm::Function>(GV);
2297 
2298  // Now add the 'alignstack' attribute with a value of 16.
2299  llvm::AttrBuilder B;
2300  B.addStackAlignmentAttr(16);
2301  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
2302  }
2303  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2304  llvm::Function *Fn = cast<llvm::Function>(GV);
2305  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2306  }
2307  }
2308  }
2309 };
2310 
2311 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2312 public:
2313  PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2314  : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2315 
2316  void getDependentLibraryOption(llvm::StringRef Lib,
2317  llvm::SmallString<24> &Opt) const override {
2318  Opt = "\01";
2319  // If the argument contains a space, enclose it in quotes.
2320  if (Lib.find(" ") != StringRef::npos)
2321  Opt += "\"" + Lib.str() + "\"";
2322  else
2323  Opt += Lib;
2324  }
2325 };
2326 
2327 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2328  // If the argument does not end in .lib, automatically add the suffix.
2329  // If the argument contains a space, enclose it in quotes.
2330  // This matches the behavior of MSVC.
2331  bool Quote = (Lib.find(" ") != StringRef::npos);
2332  std::string ArgStr = Quote ? "\"" : "";
2333  ArgStr += Lib;
2334  if (!Lib.endswith_lower(".lib"))
2335  ArgStr += ".lib";
2336  ArgStr += Quote ? "\"" : "";
2337  return ArgStr;
2338 }
2339 
2340 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2341 public:
2342  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2343  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2344  unsigned NumRegisterParameters)
2345  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2346  Win32StructABI, NumRegisterParameters, false) {}
2347 
2348  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2350  ForDefinition_t IsForDefinition) const override;
2351 
2352  void getDependentLibraryOption(llvm::StringRef Lib,
2353  llvm::SmallString<24> &Opt) const override {
2354  Opt = "/DEFAULTLIB:";
2355  Opt += qualifyWindowsLibrary(Lib);
2356  }
2357 
2358  void getDetectMismatchOption(llvm::StringRef Name,
2359  llvm::StringRef Value,
2360  llvm::SmallString<32> &Opt) const override {
2361  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2362  }
2363 };
2364 
2365 static void addStackProbeSizeTargetAttribute(const Decl *D,
2366  llvm::GlobalValue *GV,
2367  CodeGen::CodeGenModule &CGM) {
2368  if (D && isa<FunctionDecl>(D)) {
2369  if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2370  llvm::Function *Fn = cast<llvm::Function>(GV);
2371 
2372  Fn->addFnAttr("stack-probe-size",
2373  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2374  }
2375  }
2376 }
2377 
2378 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2379  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
2380  ForDefinition_t IsForDefinition) const {
2381  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
2382  if (!IsForDefinition)
2383  return;
2384  addStackProbeSizeTargetAttribute(D, GV, CGM);
2385 }
2386 
2387 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2388 public:
2389  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2390  X86AVXABILevel AVXLevel)
2391  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2392 
2393  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2395  ForDefinition_t IsForDefinition) const override;
2396 
2397  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2398  return 7;
2399  }
2400 
2401  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2402  llvm::Value *Address) const override {
2403  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2404 
2405  // 0-15 are the 16 integer registers.
2406  // 16 is %rip.
2407  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2408  return false;
2409  }
2410 
2411  void getDependentLibraryOption(llvm::StringRef Lib,
2412  llvm::SmallString<24> &Opt) const override {
2413  Opt = "/DEFAULTLIB:";
2414  Opt += qualifyWindowsLibrary(Lib);
2415  }
2416 
2417  void getDetectMismatchOption(llvm::StringRef Name,
2418  llvm::StringRef Value,
2419  llvm::SmallString<32> &Opt) const override {
2420  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2421  }
2422 };
2423 
2424 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2425  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
2426  ForDefinition_t IsForDefinition) const {
2427  TargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
2428  if (!IsForDefinition)
2429  return;
2430  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2431  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2432  // Get the LLVM function.
2433  auto *Fn = cast<llvm::Function>(GV);
2434 
2435  // Now add the 'alignstack' attribute with a value of 16.
2436  llvm::AttrBuilder B;
2437  B.addStackAlignmentAttr(16);
2438  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
2439  }
2440  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2441  llvm::Function *Fn = cast<llvm::Function>(GV);
2442  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2443  }
2444  }
2445 
2446  addStackProbeSizeTargetAttribute(D, GV, CGM);
2447 }
2448 }
2449 
2450 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2451  Class &Hi) const {
2452  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2453  //
2454  // (a) If one of the classes is Memory, the whole argument is passed in
2455  // memory.
2456  //
2457  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2458  // memory.
2459  //
2460  // (c) If the size of the aggregate exceeds two eightbytes and the first
2461  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2462  // argument is passed in memory. NOTE: This is necessary to keep the
2463  // ABI working for processors that don't support the __m256 type.
2464  //
2465  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2466  //
2467  // Some of these are enforced by the merging logic. Others can arise
2468  // only with unions; for example:
2469  // union { _Complex double; unsigned; }
2470  //
2471  // Note that clauses (b) and (c) were added in 0.98.
2472  //
2473  if (Hi == Memory)
2474  Lo = Memory;
2475  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2476  Lo = Memory;
2477  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2478  Lo = Memory;
2479  if (Hi == SSEUp && Lo != SSE)
2480  Hi = SSE;
2481 }
2482 
2483 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2484  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2485  // classified recursively so that always two fields are
2486  // considered. The resulting class is calculated according to
2487  // the classes of the fields in the eightbyte:
2488  //
2489  // (a) If both classes are equal, this is the resulting class.
2490  //
2491  // (b) If one of the classes is NO_CLASS, the resulting class is
2492  // the other class.
2493  //
2494  // (c) If one of the classes is MEMORY, the result is the MEMORY
2495  // class.
2496  //
2497  // (d) If one of the classes is INTEGER, the result is the
2498  // INTEGER.
2499  //
2500  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2501  // MEMORY is used as class.
2502  //
2503  // (f) Otherwise class SSE is used.
2504 
2505  // Accum should never be memory (we should have returned) or
2506  // ComplexX87 (because this cannot be passed in a structure).
2507  assert((Accum != Memory && Accum != ComplexX87) &&
2508  "Invalid accumulated classification during merge.");
2509  if (Accum == Field || Field == NoClass)
2510  return Accum;
2511  if (Field == Memory)
2512  return Memory;
2513  if (Accum == NoClass)
2514  return Field;
2515  if (Accum == Integer || Field == Integer)
2516  return Integer;
2517  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2518  Accum == X87 || Accum == X87Up)
2519  return Memory;
2520  return SSE;
2521 }
2522 
2523 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2524  Class &Lo, Class &Hi, bool isNamedArg) const {
2525  // FIXME: This code can be simplified by introducing a simple value class for
2526  // Class pairs with appropriate constructor methods for the various
2527  // situations.
2528 
2529  // FIXME: Some of the split computations are wrong; unaligned vectors
2530  // shouldn't be passed in registers for example, so there is no chance they
2531  // can straddle an eightbyte. Verify & simplify.
2532 
2533  Lo = Hi = NoClass;
2534 
2535  Class &Current = OffsetBase < 64 ? Lo : Hi;
2536  Current = Memory;
2537 
2538  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2539  BuiltinType::Kind k = BT->getKind();
2540 
2541  if (k == BuiltinType::Void) {
2542  Current = NoClass;
2543  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2544  Lo = Integer;
2545  Hi = Integer;
2546  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2547  Current = Integer;
2548  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2549  Current = SSE;
2550  } else if (k == BuiltinType::LongDouble) {
2551  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2552  if (LDF == &llvm::APFloat::IEEEquad()) {
2553  Lo = SSE;
2554  Hi = SSEUp;
2555  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2556  Lo = X87;
2557  Hi = X87Up;
2558  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2559  Current = SSE;
2560  } else
2561  llvm_unreachable("unexpected long double representation!");
2562  }
2563  // FIXME: _Decimal32 and _Decimal64 are SSE.
2564  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2565  return;
2566  }
2567 
2568  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2569  // Classify the underlying integer type.
2570  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2571  return;
2572  }
2573 
2574  if (Ty->hasPointerRepresentation()) {
2575  Current = Integer;
2576  return;
2577  }
2578 
2579  if (Ty->isMemberPointerType()) {
2580  if (Ty->isMemberFunctionPointerType()) {
2581  if (Has64BitPointers) {
2582  // If Has64BitPointers, this is an {i64, i64}, so classify both
2583  // Lo and Hi now.
2584  Lo = Hi = Integer;
2585  } else {
2586  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2587  // straddles an eightbyte boundary, Hi should be classified as well.
2588  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2589  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2590  if (EB_FuncPtr != EB_ThisAdj) {
2591  Lo = Hi = Integer;
2592  } else {
2593  Current = Integer;
2594  }
2595  }
2596  } else {
2597  Current = Integer;
2598  }
2599  return;
2600  }
2601 
2602  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2603  uint64_t Size = getContext().getTypeSize(VT);
2604  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2605  // gcc passes the following as integer:
2606  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2607  // 2 bytes - <2 x char>, <1 x short>
2608  // 1 byte - <1 x char>
2609  Current = Integer;
2610 
2611  // If this type crosses an eightbyte boundary, it should be
2612  // split.
2613  uint64_t EB_Lo = (OffsetBase) / 64;
2614  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2615  if (EB_Lo != EB_Hi)
2616  Hi = Lo;
2617  } else if (Size == 64) {
2618  QualType ElementType = VT->getElementType();
2619 
2620  // gcc passes <1 x double> in memory. :(
2621  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2622  return;
2623 
2624  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2625  // pass them as integer. For platforms where clang is the de facto
2626  // platform compiler, we must continue to use integer.
2627  if (!classifyIntegerMMXAsSSE() &&
2628  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2629  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2630  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2631  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2632  Current = Integer;
2633  else
2634  Current = SSE;
2635 
2636  // If this type crosses an eightbyte boundary, it should be
2637  // split.
2638  if (OffsetBase && OffsetBase != 64)
2639  Hi = Lo;
2640  } else if (Size == 128 ||
2641  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2642  // Arguments of 256-bits are split into four eightbyte chunks. The
2643  // least significant one belongs to class SSE and all the others to class
2644  // SSEUP. The original Lo and Hi design considers that types can't be
2645  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2646  // This design isn't correct for 256-bits, but since there're no cases
2647  // where the upper parts would need to be inspected, avoid adding
2648  // complexity and just consider Hi to match the 64-256 part.
2649  //
2650  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2651  // registers if they are "named", i.e. not part of the "..." of a
2652  // variadic function.
2653  //
2654  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2655  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2656  Lo = SSE;
2657  Hi = SSEUp;
2658  }
2659  return;
2660  }
2661 
2662  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2663  QualType ET = getContext().getCanonicalType(CT->getElementType());
2664 
2665  uint64_t Size = getContext().getTypeSize(Ty);
2666  if (ET->isIntegralOrEnumerationType()) {
2667  if (Size <= 64)
2668  Current = Integer;
2669  else if (Size <= 128)
2670  Lo = Hi = Integer;
2671  } else if (ET == getContext().FloatTy) {
2672  Current = SSE;
2673  } else if (ET == getContext().DoubleTy) {
2674  Lo = Hi = SSE;
2675  } else if (ET == getContext().LongDoubleTy) {
2676  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2677  if (LDF == &llvm::APFloat::IEEEquad())
2678  Current = Memory;
2679  else if (LDF == &llvm::APFloat::x87DoubleExtended())
2680  Current = ComplexX87;
2681  else if (LDF == &llvm::APFloat::IEEEdouble())
2682  Lo = Hi = SSE;
2683  else
2684  llvm_unreachable("unexpected long double representation!");
2685  }
2686 
2687  // If this complex type crosses an eightbyte boundary then it
2688  // should be split.
2689  uint64_t EB_Real = (OffsetBase) / 64;
2690  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2691  if (Hi == NoClass && EB_Real != EB_Imag)
2692  Hi = Lo;
2693 
2694  return;
2695  }
2696 
2697  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2698  // Arrays are treated like structures.
2699 
2700  uint64_t Size = getContext().getTypeSize(Ty);
2701 
2702  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2703  // than eight eightbytes, ..., it has class MEMORY.
2704  if (Size > 512)
2705  return;
2706 
2707  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2708  // fields, it has class MEMORY.
2709  //
2710  // Only need to check alignment of array base.
2711  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2712  return;
2713 
2714  // Otherwise implement simplified merge. We could be smarter about
2715  // this, but it isn't worth it and would be harder to verify.
2716  Current = NoClass;
2717  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2718  uint64_t ArraySize = AT->getSize().getZExtValue();
2719 
2720  // The only case a 256-bit wide vector could be used is when the array
2721  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2722  // to work for sizes wider than 128, early check and fallback to memory.
2723  //
2724  if (Size > 128 &&
2725  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2726  return;
2727 
2728  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2729  Class FieldLo, FieldHi;
2730  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2731  Lo = merge(Lo, FieldLo);
2732  Hi = merge(Hi, FieldHi);
2733  if (Lo == Memory || Hi == Memory)
2734  break;
2735  }
2736 
2737  postMerge(Size, Lo, Hi);
2738  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2739  return;
2740  }
2741 
2742  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2743  uint64_t Size = getContext().getTypeSize(Ty);
2744 
2745  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2746  // than eight eightbytes, ..., it has class MEMORY.
2747  if (Size > 512)
2748  return;
2749 
2750  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2751  // copy constructor or a non-trivial destructor, it is passed by invisible
2752  // reference.
2753  if (getRecordArgABI(RT, getCXXABI()))
2754  return;
2755 
2756  const RecordDecl *RD = RT->getDecl();
2757 
2758  // Assume variable sized types are passed in memory.
2759  if (RD->hasFlexibleArrayMember())
2760  return;
2761 
2762  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2763 
2764  // Reset Lo class, this will be recomputed.
2765  Current = NoClass;
2766 
2767  // If this is a C++ record, classify the bases first.
2768  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2769  for (const auto &I : CXXRD->bases()) {
2770  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2771  "Unexpected base class!");
2772  const CXXRecordDecl *Base =
2773  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2774 
2775  // Classify this field.
2776  //
2777  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2778  // single eightbyte, each is classified separately. Each eightbyte gets
2779  // initialized to class NO_CLASS.
2780  Class FieldLo, FieldHi;
2781  uint64_t Offset =
2782  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2783  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2784  Lo = merge(Lo, FieldLo);
2785  Hi = merge(Hi, FieldHi);
2786  if (Lo == Memory || Hi == Memory) {
2787  postMerge(Size, Lo, Hi);
2788  return;
2789  }
2790  }
2791  }
2792 
2793  // Classify the fields one at a time, merging the results.
2794  unsigned idx = 0;
2795  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2796  i != e; ++i, ++idx) {
2797  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2798  bool BitField = i->isBitField();
2799 
2800  // Ignore padding bit-fields.
2801  if (BitField && i->isUnnamedBitfield())
2802  continue;
2803 
2804  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2805  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2806  //
2807  // The only case a 256-bit wide vector could be used is when the struct
2808  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2809  // to work for sizes wider than 128, early check and fallback to memory.
2810  //
2811  if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2812  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2813  Lo = Memory;
2814  postMerge(Size, Lo, Hi);
2815  return;
2816  }
2817  // Note, skip this test for bit-fields, see below.
2818  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2819  Lo = Memory;
2820  postMerge(Size, Lo, Hi);
2821  return;
2822  }
2823 
2824  // Classify this field.
2825  //
2826  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2827  // exceeds a single eightbyte, each is classified
2828  // separately. Each eightbyte gets initialized to class
2829  // NO_CLASS.
2830  Class FieldLo, FieldHi;
2831 
2832  // Bit-fields require special handling, they do not force the
2833  // structure to be passed in memory even if unaligned, and
2834  // therefore they can straddle an eightbyte.
2835  if (BitField) {
2836  assert(!i->isUnnamedBitfield());
2837  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2838  uint64_t Size = i->getBitWidthValue(getContext());
2839 
2840  uint64_t EB_Lo = Offset / 64;
2841  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2842 
2843  if (EB_Lo) {
2844  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2845  FieldLo = NoClass;
2846  FieldHi = Integer;
2847  } else {
2848  FieldLo = Integer;
2849  FieldHi = EB_Hi ? Integer : NoClass;
2850  }
2851  } else
2852  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2853  Lo = merge(Lo, FieldLo);
2854  Hi = merge(Hi, FieldHi);
2855  if (Lo == Memory || Hi == Memory)
2856  break;
2857  }
2858 
2859  postMerge(Size, Lo, Hi);
2860  }
2861 }
2862 
2863 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2864  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2865  // place naturally.
2866  if (!isAggregateTypeForABI(Ty)) {
2867  // Treat an enum type as its underlying type.
2868  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2869  Ty = EnumTy->getDecl()->getIntegerType();
2870 
2871  return (Ty->isPromotableIntegerType() ?
2873  }
2874 
2875  return getNaturalAlignIndirect(Ty);
2876 }
2877 
2878 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2879  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2880  uint64_t Size = getContext().getTypeSize(VecTy);
2881  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2882  if (Size <= 64 || Size > LargestVector)
2883  return true;
2884  }
2885 
2886  return false;
2887 }
2888 
2889 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2890  unsigned freeIntRegs) const {
2891  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2892  // place naturally.
2893  //
2894  // This assumption is optimistic, as there could be free registers available
2895  // when we need to pass this argument in memory, and LLVM could try to pass
2896  // the argument in the free register. This does not seem to happen currently,
2897  // but this code would be much safer if we could mark the argument with
2898  // 'onstack'. See PR12193.
2899  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2900  // Treat an enum type as its underlying type.
2901  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2902  Ty = EnumTy->getDecl()->getIntegerType();
2903 
2904  return (Ty->isPromotableIntegerType() ?
2906  }
2907 
2910 
2911  // Compute the byval alignment. We specify the alignment of the byval in all
2912  // cases so that the mid-level optimizer knows the alignment of the byval.
2913  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2914 
2915  // Attempt to avoid passing indirect results using byval when possible. This
2916  // is important for good codegen.
2917  //
2918  // We do this by coercing the value into a scalar type which the backend can
2919  // handle naturally (i.e., without using byval).
2920  //
2921  // For simplicity, we currently only do this when we have exhausted all of the
2922  // free integer registers. Doing this when there are free integer registers
2923  // would require more care, as we would have to ensure that the coerced value
2924  // did not claim the unused register. That would require either reording the
2925  // arguments to the function (so that any subsequent inreg values came first),
2926  // or only doing this optimization when there were no following arguments that
2927  // might be inreg.
2928  //
2929  // We currently expect it to be rare (particularly in well written code) for
2930  // arguments to be passed on the stack when there are still free integer
2931  // registers available (this would typically imply large structs being passed
2932  // by value), so this seems like a fair tradeoff for now.
2933  //
2934  // We can revisit this if the backend grows support for 'onstack' parameter
2935  // attributes. See PR12193.
2936  if (freeIntRegs == 0) {
2937  uint64_t Size = getContext().getTypeSize(Ty);
2938 
2939  // If this type fits in an eightbyte, coerce it into the matching integral
2940  // type, which will end up on the stack (with alignment 8).
2941  if (Align == 8 && Size <= 64)
2942  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2943  Size));
2944  }
2945 
2947 }
2948 
2949 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2950 /// register. Pick an LLVM IR type that will be passed as a vector register.
2951 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2952  // Wrapper structs/arrays that only contain vectors are passed just like
2953  // vectors; strip them off if present.
2954  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2955  Ty = QualType(InnerTy, 0);
2956 
2957  llvm::Type *IRType = CGT.ConvertType(Ty);
2958  if (isa<llvm::VectorType>(IRType) ||
2959  IRType->getTypeID() == llvm::Type::FP128TyID)
2960  return IRType;
2961 
2962  // We couldn't find the preferred IR vector type for 'Ty'.
2963  uint64_t Size = getContext().getTypeSize(Ty);
2964  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2965 
2966  // Return a LLVM IR vector type based on the size of 'Ty'.
2967  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2968  Size / 64);
2969 }
2970 
2971 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2972 /// is known to either be off the end of the specified type or being in
2973 /// alignment padding. The user type specified is known to be at most 128 bits
2974 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2975 /// classification that put one of the two halves in the INTEGER class.
2976 ///
2977 /// It is conservatively correct to return false.
2978 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2979  unsigned EndBit, ASTContext &Context) {
2980  // If the bytes being queried are off the end of the type, there is no user
2981  // data hiding here. This handles analysis of builtins, vectors and other
2982  // types that don't contain interesting padding.
2983  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2984  if (TySize <= StartBit)
2985  return true;
2986 
2987  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2988  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2989  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2990 
2991  // Check each element to see if the element overlaps with the queried range.
2992  for (unsigned i = 0; i != NumElts; ++i) {
2993  // If the element is after the span we care about, then we're done..
2994  unsigned EltOffset = i*EltSize;
2995  if (EltOffset >= EndBit) break;
2996 
2997  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2998  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2999  EndBit-EltOffset, Context))
3000  return false;
3001  }
3002  // If it overlaps no elements, then it is safe to process as padding.
3003  return true;
3004  }
3005 
3006  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3007  const RecordDecl *RD = RT->getDecl();
3008  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3009 
3010  // If this is a C++ record, check the bases first.
3011  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3012  for (const auto &I : CXXRD->bases()) {
3013  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3014  "Unexpected base class!");
3015  const CXXRecordDecl *Base =
3016  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3017 
3018  // If the base is after the span we care about, ignore it.
3019  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3020  if (BaseOffset >= EndBit) continue;
3021 
3022  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3023  if (!BitsContainNoUserData(I.getType(), BaseStart,
3024  EndBit-BaseOffset, Context))
3025  return false;
3026  }
3027  }
3028 
3029  // Verify that no field has data that overlaps the region of interest. Yes
3030  // this could be sped up a lot by being smarter about queried fields,
3031  // however we're only looking at structs up to 16 bytes, so we don't care
3032  // much.
3033  unsigned idx = 0;
3034  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3035  i != e; ++i, ++idx) {
3036  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3037 
3038  // If we found a field after the region we care about, then we're done.
3039  if (FieldOffset >= EndBit) break;
3040 
3041  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3042  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3043  Context))
3044  return false;
3045  }
3046 
3047  // If nothing in this record overlapped the area of interest, then we're
3048  // clean.
3049  return true;
3050  }
3051 
3052  return false;
3053 }
3054 
3055 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3056 /// float member at the specified offset. For example, {int,{float}} has a
3057 /// float at offset 4. It is conservatively correct for this routine to return
3058 /// false.
3059 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3060  const llvm::DataLayout &TD) {
3061  // Base case if we find a float.
3062  if (IROffset == 0 && IRType->isFloatTy())
3063  return true;
3064 
3065  // If this is a struct, recurse into the field at the specified offset.
3066  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3067  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3068  unsigned Elt = SL->getElementContainingOffset(IROffset);
3069  IROffset -= SL->getElementOffset(Elt);
3070  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3071  }
3072 
3073  // If this is an array, recurse into the field at the specified offset.
3074  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3075  llvm::Type *EltTy = ATy->getElementType();
3076  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3077  IROffset -= IROffset/EltSize*EltSize;
3078  return ContainsFloatAtOffset(EltTy, IROffset, TD);
3079  }
3080 
3081  return false;
3082 }
3083 
3084 
3085 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3086 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3087 llvm::Type *X86_64ABIInfo::
3088 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3089  QualType SourceTy, unsigned SourceOffset) const {
3090  // The only three choices we have are either double, <2 x float>, or float. We
3091  // pass as float if the last 4 bytes is just padding. This happens for
3092  // structs that contain 3 floats.
3093  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3094  SourceOffset*8+64, getContext()))
3095  return llvm::Type::getFloatTy(getVMContext());
3096 
3097  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3098  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3099  // case.
3100  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3101  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3102  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3103 
3104  return llvm::Type::getDoubleTy(getVMContext());
3105 }
3106 
3107 
3108 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3109 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3110 /// about the high or low part of an up-to-16-byte struct. This routine picks
3111 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3112 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3113 /// etc).
3114 ///
3115 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3116 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3117 /// the 8-byte value references. PrefType may be null.
3118 ///
3119 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3120 /// an offset into this that we're processing (which is always either 0 or 8).
3121 ///
3122 llvm::Type *X86_64ABIInfo::
3123 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3124  QualType SourceTy, unsigned SourceOffset) const {
3125  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3126  // returning an 8-byte unit starting with it. See if we can safely use it.
3127  if (IROffset == 0) {
3128  // Pointers and int64's always fill the 8-byte unit.
3129  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3130  IRType->isIntegerTy(64))
3131  return IRType;
3132 
3133  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3134  // goodness in the source type is just tail padding. This is allowed to
3135  // kick in for struct {double,int} on the int, but not on
3136  // struct{double,int,int} because we wouldn't return the second int. We
3137  // have to do this analysis on the source type because we can't depend on
3138  // unions being lowered a specific way etc.
3139  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3140  IRType->isIntegerTy(32) ||
3141  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3142  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3143  cast<llvm::IntegerType>(IRType)->getBitWidth();
3144 
3145  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3146  SourceOffset*8+64, getContext()))
3147  return IRType;
3148  }
3149  }
3150 
3151  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3152  // If this is a struct, recurse into the field at the specified offset.
3153  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3154  if (IROffset < SL->getSizeInBytes()) {
3155  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3156  IROffset -= SL->getElementOffset(FieldIdx);
3157 
3158  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3159  SourceTy, SourceOffset);
3160  }
3161  }
3162 
3163  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3164  llvm::Type *EltTy = ATy->getElementType();
3165  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3166  unsigned EltOffset = IROffset/EltSize*EltSize;
3167  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3168  SourceOffset);
3169  }
3170 
3171  // Okay, we don't have any better idea of what to pass, so we pass this in an
3172  // integer register that isn't too big to fit the rest of the struct.
3173  unsigned TySizeInBytes =
3174  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3175 
3176  assert(TySizeInBytes != SourceOffset && "Empty field?");
3177 
3178  // It is always safe to classify this as an integer type up to i64 that
3179  // isn't larger than the structure.
3180  return llvm::IntegerType::get(getVMContext(),
3181  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3182 }
3183 
3184 
3185 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3186 /// be used as elements of a two register pair to pass or return, return a
3187 /// first class aggregate to represent them. For example, if the low part of
3188 /// a by-value argument should be passed as i32* and the high part as float,
3189 /// return {i32*, float}.
3190 static llvm::Type *
3192  const llvm::DataLayout &TD) {
3193  // In order to correctly satisfy the ABI, we need to the high part to start
3194  // at offset 8. If the high and low parts we inferred are both 4-byte types
3195  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3196  // the second element at offset 8. Check for this:
3197  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3198  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3199  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3200  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3201 
3202  // To handle this, we have to increase the size of the low part so that the
3203  // second element will start at an 8 byte offset. We can't increase the size
3204  // of the second element because it might make us access off the end of the
3205  // struct.
3206  if (HiStart != 8) {
3207  // There are usually two sorts of types the ABI generation code can produce
3208  // for the low part of a pair that aren't 8 bytes in size: float or
3209  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3210  // NaCl).
3211  // Promote these to a larger type.
3212  if (Lo->isFloatTy())
3213  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3214  else {
3215  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3216  && "Invalid/unknown lo type");
3217  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3218  }
3219  }
3220 
3221  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3222 
3223  // Verify that the second element is at an 8-byte offset.
3224  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3225  "Invalid x86-64 argument pair!");
3226  return Result;
3227 }
3228 
3230 classifyReturnType(QualType RetTy) const {
3231  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3232  // classification algorithm.
3233  X86_64ABIInfo::Class Lo, Hi;
3234  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3235 
3236  // Check some invariants.
3237  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3238  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3239 
3240  llvm::Type *ResType = nullptr;
3241  switch (Lo) {
3242  case NoClass:
3243  if (Hi == NoClass)
3244  return ABIArgInfo::getIgnore();
3245  // If the low part is just padding, it takes no register, leave ResType
3246  // null.
3247  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3248  "Unknown missing lo part");
3249  break;
3250 
3251  case SSEUp:
3252  case X87Up:
3253  llvm_unreachable("Invalid classification for lo word.");
3254 
3255  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3256  // hidden argument.
3257  case Memory:
3258  return getIndirectReturnResult(RetTy);
3259 
3260  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3261  // available register of the sequence %rax, %rdx is used.
3262  case Integer:
3263  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3264 
3265  // If we have a sign or zero extended integer, make sure to return Extend
3266  // so that the parameter gets the right LLVM IR attributes.
3267  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3268  // Treat an enum type as its underlying type.
3269  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3270  RetTy = EnumTy->getDecl()->getIntegerType();
3271 
3272  if (RetTy->isIntegralOrEnumerationType() &&
3273  RetTy->isPromotableIntegerType())
3274  return ABIArgInfo::getExtend();
3275  }
3276  break;
3277 
3278  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3279  // available SSE register of the sequence %xmm0, %xmm1 is used.
3280  case SSE:
3281  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3282  break;
3283 
3284  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3285  // returned on the X87 stack in %st0 as 80-bit x87 number.
3286  case X87:
3287  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3288  break;
3289 
3290  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3291  // part of the value is returned in %st0 and the imaginary part in
3292  // %st1.
3293  case ComplexX87:
3294  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3295  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3296  llvm::Type::getX86_FP80Ty(getVMContext()));
3297  break;
3298  }
3299 
3300  llvm::Type *HighPart = nullptr;
3301  switch (Hi) {
3302  // Memory was handled previously and X87 should
3303  // never occur as a hi class.
3304  case Memory:
3305  case X87:
3306  llvm_unreachable("Invalid classification for hi word.");
3307 
3308  case ComplexX87: // Previously handled.
3309  case NoClass:
3310  break;
3311 
3312  case Integer:
3313  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3314  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3315  return ABIArgInfo::getDirect(HighPart, 8);
3316  break;
3317  case SSE:
3318  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3319  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3320  return ABIArgInfo::getDirect(HighPart, 8);
3321  break;
3322 
3323  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3324  // is passed in the next available eightbyte chunk if the last used
3325  // vector register.
3326  //
3327  // SSEUP should always be preceded by SSE, just widen.
3328  case SSEUp:
3329  assert(Lo == SSE && "Unexpected SSEUp classification.");
3330  ResType = GetByteVectorType(RetTy);
3331  break;
3332 
3333  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3334  // returned together with the previous X87 value in %st0.
3335  case X87Up:
3336  // If X87Up is preceded by X87, we don't need to do
3337  // anything. However, in some cases with unions it may not be
3338  // preceded by X87. In such situations we follow gcc and pass the
3339  // extra bits in an SSE reg.
3340  if (Lo != X87) {
3341  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3342  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3343  return ABIArgInfo::getDirect(HighPart, 8);
3344  }
3345  break;
3346  }
3347 
3348  // If a high part was specified, merge it together with the low part. It is
3349  // known to pass in the high eightbyte of the result. We do this by forming a
3350  // first class struct aggregate with the high and low part: {low, high}
3351  if (HighPart)
3352  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3353 
3354  return ABIArgInfo::getDirect(ResType);
3355 }
3356 
3358  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3359  bool isNamedArg)
3360  const
3361 {
3363 
3364  X86_64ABIInfo::Class Lo, Hi;
3365  classify(Ty, 0, Lo, Hi, isNamedArg);
3366 
3367  // Check some invariants.
3368  // FIXME: Enforce these by construction.
3369  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3370  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3371 
3372  neededInt = 0;
3373  neededSSE = 0;
3374  llvm::Type *ResType = nullptr;
3375  switch (Lo) {
3376  case NoClass:
3377  if (Hi == NoClass)
3378  return ABIArgInfo::getIgnore();
3379  // If the low part is just padding, it takes no register, leave ResType
3380  // null.
3381  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3382  "Unknown missing lo part");
3383  break;
3384 
3385  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3386  // on the stack.
3387  case Memory:
3388 
3389  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3390  // COMPLEX_X87, it is passed in memory.
3391  case X87:
3392  case ComplexX87:
3394  ++neededInt;
3395  return getIndirectResult(Ty, freeIntRegs);
3396 
3397  case SSEUp:
3398  case X87Up:
3399  llvm_unreachable("Invalid classification for lo word.");
3400 
3401  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3402  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3403  // and %r9 is used.
3404  case Integer:
3405  ++neededInt;
3406 
3407  // Pick an 8-byte type based on the preferred type.
3408  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3409 
3410  // If we have a sign or zero extended integer, make sure to return Extend
3411  // so that the parameter gets the right LLVM IR attributes.
3412  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3413  // Treat an enum type as its underlying type.
3414  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3415  Ty = EnumTy->getDecl()->getIntegerType();
3416 
3417  if (Ty->isIntegralOrEnumerationType() &&
3419  return ABIArgInfo::getExtend();
3420  }
3421 
3422  break;
3423 
3424  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3425  // available SSE register is used, the registers are taken in the
3426  // order from %xmm0 to %xmm7.
3427  case SSE: {
3428  llvm::Type *IRType = CGT.ConvertType(Ty);
3429  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3430  ++neededSSE;
3431  break;
3432  }
3433  }
3434 
3435  llvm::Type *HighPart = nullptr;
3436  switch (Hi) {
3437  // Memory was handled previously, ComplexX87 and X87 should
3438  // never occur as hi classes, and X87Up must be preceded by X87,
3439  // which is passed in memory.
3440  case Memory:
3441  case X87:
3442  case ComplexX87:
3443  llvm_unreachable("Invalid classification for hi word.");
3444 
3445  case NoClass: break;
3446 
3447  case Integer:
3448  ++neededInt;
3449  // Pick an 8-byte type based on the preferred type.
3450  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3451 
3452  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3453  return ABIArgInfo::getDirect(HighPart, 8);
3454  break;
3455 
3456  // X87Up generally doesn't occur here (long double is passed in
3457  // memory), except in situations involving unions.
3458  case X87Up:
3459  case SSE:
3460  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3461 
3462  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3463  return ABIArgInfo::getDirect(HighPart, 8);
3464 
3465  ++neededSSE;
3466  break;
3467 
3468  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3469  // eightbyte is passed in the upper half of the last used SSE
3470  // register. This only happens when 128-bit vectors are passed.
3471  case SSEUp:
3472  assert(Lo == SSE && "Unexpected SSEUp classification");
3473  ResType = GetByteVectorType(Ty);
3474  break;
3475  }
3476 
3477  // If a high part was specified, merge it together with the low part. It is
3478  // known to pass in the high eightbyte of the result. We do this by forming a
3479  // first class struct aggregate with the high and low part: {low, high}
3480  if (HighPart)
3481  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3482 
3483  return ABIArgInfo::getDirect(ResType);
3484 }
3485 
3486 ABIArgInfo
3487 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3488  unsigned &NeededSSE) const {
3489  auto RT = Ty->getAs<RecordType>();
3490  assert(RT && "classifyRegCallStructType only valid with struct types");
3491 
3492  if (RT->getDecl()->hasFlexibleArrayMember())
3493  return getIndirectReturnResult(Ty);
3494 
3495  // Sum up bases
3496  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3497  if (CXXRD->isDynamicClass()) {
3498  NeededInt = NeededSSE = 0;
3499  return getIndirectReturnResult(Ty);
3500  }
3501 
3502  for (const auto &I : CXXRD->bases())
3503  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3504  .isIndirect()) {
3505  NeededInt = NeededSSE = 0;
3506  return getIndirectReturnResult(Ty);
3507  }
3508  }
3509 
3510  // Sum up members
3511  for (const auto *FD : RT->getDecl()->fields()) {
3512  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3513  if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3514  .isIndirect()) {
3515  NeededInt = NeededSSE = 0;
3516  return getIndirectReturnResult(Ty);
3517  }
3518  } else {
3519  unsigned LocalNeededInt, LocalNeededSSE;
3520  if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3521  LocalNeededSSE, true)
3522  .isIndirect()) {
3523  NeededInt = NeededSSE = 0;
3524  return getIndirectReturnResult(Ty);
3525  }
3526  NeededInt += LocalNeededInt;
3527  NeededSSE += LocalNeededSSE;
3528  }
3529  }
3530 
3531  return ABIArgInfo::getDirect();
3532 }
3533 
3534 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3535  unsigned &NeededInt,
3536  unsigned &NeededSSE) const {
3537 
3538  NeededInt = 0;
3539  NeededSSE = 0;
3540 
3541  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3542 }
3543 
3544 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3545 
3546  bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3547 
3548  // Keep track of the number of assigned registers.
3549  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3550  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3551  unsigned NeededInt, NeededSSE;
3552 
3553  if (!getCXXABI().classifyReturnType(FI)) {
3554  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3555  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3556  FI.getReturnInfo() =
3557  classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3558  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3559  FreeIntRegs -= NeededInt;
3560  FreeSSERegs -= NeededSSE;
3561  } else {
3562  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3563  }
3564  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3565  // Complex Long Double Type is passed in Memory when Regcall
3566  // calling convention is used.
3567  const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3570  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3571  } else
3573  }
3574 
3575  // If the return value is indirect, then the hidden argument is consuming one
3576  // integer register.
3577  if (FI.getReturnInfo().isIndirect())
3578  --FreeIntRegs;
3579 
3580  // The chain argument effectively gives us another free register.
3581  if (FI.isChainCall())
3582  ++FreeIntRegs;
3583 
3584  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3585  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3586  // get assigned (in left-to-right order) for passing as follows...
3587  unsigned ArgNo = 0;
3588  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3589  it != ie; ++it, ++ArgNo) {
3590  bool IsNamedArg = ArgNo < NumRequiredArgs;
3591 
3592  if (IsRegCall && it->type->isStructureOrClassType())
3593  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3594  else
3595  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3596  NeededSSE, IsNamedArg);
3597 
3598  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3599  // eightbyte of an argument, the whole argument is passed on the
3600  // stack. If registers have already been assigned for some
3601  // eightbytes of such an argument, the assignments get reverted.
3602  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3603  FreeIntRegs -= NeededInt;
3604  FreeSSERegs -= NeededSSE;
3605  } else {
3606  it->info = getIndirectResult(it->type, FreeIntRegs);
3607  }
3608  }
3609 }
3610 
3612  Address VAListAddr, QualType Ty) {
3613  Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3614  VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3615  llvm::Value *overflow_arg_area =
3616  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3617 
3618  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3619  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3620  // It isn't stated explicitly in the standard, but in practice we use
3621  // alignment greater than 16 where necessary.
3622  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3623  if (Align > CharUnits::fromQuantity(8)) {
3624  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3625  Align);
3626  }
3627 
3628  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3629  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3630  llvm::Value *Res =
3631  CGF.Builder.CreateBitCast(overflow_arg_area,
3632  llvm::PointerType::getUnqual(LTy));
3633 
3634  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3635  // l->overflow_arg_area + sizeof(type).
3636  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3637  // an 8 byte boundary.
3638 
3639  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3640  llvm::Value *Offset =
3641  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3642  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3643  "overflow_arg_area.next");
3644  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3645 
3646  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3647  return Address(Res, Align);
3648 }
3649 
3650 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3651  QualType Ty) const {
3652  // Assume that va_list type is correct; should be pointer to LLVM type:
3653  // struct {
3654  // i32 gp_offset;
3655  // i32 fp_offset;
3656  // i8* overflow_arg_area;
3657  // i8* reg_save_area;
3658  // };
3659  unsigned neededInt, neededSSE;
3660 
3661  Ty = getContext().getCanonicalType(Ty);
3662  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3663  /*isNamedArg*/false);
3664 
3665  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3666  // in the registers. If not go to step 7.
3667  if (!neededInt && !neededSSE)
3668  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3669 
3670  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3671  // general purpose registers needed to pass type and num_fp to hold
3672  // the number of floating point registers needed.
3673 
3674  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3675  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3676  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3677  //
3678  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3679  // register save space).
3680 
3681  llvm::Value *InRegs = nullptr;
3682  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3683  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3684  if (neededInt) {
3685  gp_offset_p =
3686  CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3687  "gp_offset_p");
3688  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3689  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3690  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3691  }
3692 
3693  if (neededSSE) {
3694  fp_offset_p =
3695  CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3696  "fp_offset_p");
3697  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3698  llvm::Value *FitsInFP =
3699  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3700  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3701  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3702  }
3703 
3704  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3705  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3706  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3707  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3708 
3709  // Emit code to load the value if it was passed in registers.
3710 
3711  CGF.EmitBlock(InRegBlock);
3712 
3713  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3714  // an offset of l->gp_offset and/or l->fp_offset. This may require
3715  // copying to a temporary location in case the parameter is passed
3716  // in different register classes or requires an alignment greater
3717  // than 8 for general purpose registers and 16 for XMM registers.
3718  //
3719  // FIXME: This really results in shameful code when we end up needing to
3720  // collect arguments from different places; often what should result in a
3721  // simple assembling of a structure from scattered addresses has many more
3722  // loads than necessary. Can we clean this up?
3723  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3724  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3725  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3726  "reg_save_area");
3727 
3728  Address RegAddr = Address::invalid();
3729  if (neededInt && neededSSE) {
3730  // FIXME: Cleanup.
3731  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3732  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3733  Address Tmp = CGF.CreateMemTemp(Ty);
3734  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3735  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3736  llvm::Type *TyLo = ST->getElementType(0);
3737  llvm::Type *TyHi = ST->getElementType(1);
3738  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3739  "Unexpected ABI info for mixed regs");
3740  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3741  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3742  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3743  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3744  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3745  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3746 
3747  // Copy the first element.
3748  // FIXME: Our choice of alignment here and below is probably pessimistic.
3750  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3751  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3752  CGF.Builder.CreateStore(V,
3753  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3754 
3755  // Copy the second element.
3756  V = CGF.Builder.CreateAlignedLoad(
3757  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3758  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3760  getDataLayout().getStructLayout(ST)->getElementOffset(1));
3761  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3762 
3763  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3764  } else if (neededInt) {
3765  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3767  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3768 
3769  // Copy to a temporary if necessary to ensure the appropriate alignment.
3770  std::pair<CharUnits, CharUnits> SizeAlign =
3772  uint64_t TySize = SizeAlign.first.getQuantity();
3773  CharUnits TyAlign = SizeAlign.second;
3774 
3775  // Copy into a temporary if the type is more aligned than the
3776  // register save area.
3777  if (TyAlign.getQuantity() > 8) {
3778  Address Tmp = CGF.CreateMemTemp(Ty);
3779  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3780  RegAddr = Tmp;
3781  }
3782 
3783  } else if (neededSSE == 1) {
3784  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3786  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3787  } else {
3788  assert(neededSSE == 2 && "Invalid number of needed registers!");
3789  // SSE registers are spaced 16 bytes apart in the register save
3790  // area, we need to collect the two eightbytes together.
3791  // The ABI isn't explicit about this, but it seems reasonable
3792  // to assume that the slots are 16-byte aligned, since the stack is
3793  // naturally 16-byte aligned and the prologue is expected to store
3794  // all the SSE registers to the RSA.
3795  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3797  Address RegAddrHi =
3798  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3800  llvm::Type *DoubleTy = CGF.DoubleTy;
3801  llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy);
3802  llvm::Value *V;
3803  Address Tmp = CGF.CreateMemTemp(Ty);
3804  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3805  V = CGF.Builder.CreateLoad(
3806  CGF.Builder.CreateElementBitCast(RegAddrLo, DoubleTy));
3807  CGF.Builder.CreateStore(V,
3808  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3809  V = CGF.Builder.CreateLoad(
3810  CGF.Builder.CreateElementBitCast(RegAddrHi, DoubleTy));
3811  CGF.Builder.CreateStore(V,
3813 
3814  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3815  }
3816 
3817  // AMD64-ABI 3.5.7p5: Step 5. Set:
3818  // l->gp_offset = l->gp_offset + num_gp * 8
3819  // l->fp_offset = l->fp_offset + num_fp * 16.
3820  if (neededInt) {
3821  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3822  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3823  gp_offset_p);
3824  }
3825  if (neededSSE) {
3826  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3827  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3828  fp_offset_p);
3829  }
3830  CGF.EmitBranch(ContBlock);
3831 
3832  // Emit code to load the value if it was passed in memory.
3833 
3834  CGF.EmitBlock(InMemBlock);
3835  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3836 
3837  // Return the appropriate result.
3838 
3839  CGF.EmitBlock(ContBlock);
3840  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3841  "vaarg.addr");
3842  return ResAddr;
3843 }
3844 
3845 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3846  QualType Ty) const {
3847  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3848  CGF.getContext().getTypeInfoInChars(Ty),
3850  /*allowHigherAlign*/ false);
3851 }
3852 
3853 ABIArgInfo
3854 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3855  const ABIArgInfo &current) const {
3856  // Assumes vectorCall calling convention.
3857  const Type *Base = nullptr;
3858  uint64_t NumElts = 0;
3859 
3860  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3861  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3862  FreeSSERegs -= NumElts;
3863  return getDirectX86Hva();
3864  }
3865  return current;
3866 }
3867 
3868 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3869  bool IsReturnType, bool IsVectorCall,
3870  bool IsRegCall) const {
3871 
3872  if (Ty->isVoidType())
3873  return ABIArgInfo::getIgnore();
3874 
3875  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3876  Ty = EnumTy->getDecl()->getIntegerType();
3877 
3878  TypeInfo Info = getContext().getTypeInfo(Ty);
3879  uint64_t Width = Info.Width;
3881 
3882  const RecordType *RT = Ty->getAs<RecordType>();
3883  if (RT) {
3884  if (!IsReturnType) {
3887  }
3888 
3889  if (RT->getDecl()->hasFlexibleArrayMember())
3890  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3891 
3892  }
3893 
3894  const Type *Base = nullptr;
3895  uint64_t NumElts = 0;
3896  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3897  // other targets.
3898  if ((IsVectorCall || IsRegCall) &&
3899  isHomogeneousAggregate(Ty, Base, NumElts)) {
3900  if (IsRegCall) {
3901  if (FreeSSERegs >= NumElts) {
3902  FreeSSERegs -= NumElts;
3903  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3904  return ABIArgInfo::getDirect();
3905  return ABIArgInfo::getExpand();
3906  }
3907  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3908  } else if (IsVectorCall) {
3909  if (FreeSSERegs >= NumElts &&
3910  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3911  FreeSSERegs -= NumElts;
3912  return ABIArgInfo::getDirect();
3913  } else if (IsReturnType) {
3914  return ABIArgInfo::getExpand();
3915  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3916  // HVAs are delayed and reclassified in the 2nd step.
3917  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3918  }
3919  }
3920  }
3921 
3922  if (Ty->isMemberPointerType()) {
3923  // If the member pointer is represented by an LLVM int or ptr, pass it
3924  // directly.
3925  llvm::Type *LLTy = CGT.ConvertType(Ty);
3926  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3927  return ABIArgInfo::getDirect();
3928  }
3929 
3930  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3931  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3932  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3933  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3934  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3935 
3936  // Otherwise, coerce it to a small integer.
3937  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3938  }
3939 
3940  // Bool type is always extended to the ABI, other builtin types are not
3941  // extended.
3942  const BuiltinType *BT = Ty->getAs<BuiltinType>();
3943  if (BT && BT->getKind() == BuiltinType::Bool)
3944  return ABIArgInfo::getExtend();
3945 
3946  // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3947  // passes them indirectly through memory.
3948  if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3949  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3950  if (LDF == &llvm::APFloat::x87DoubleExtended())
3951  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3952  }
3953 
3954  return ABIArgInfo::getDirect();
3955 }
3956 
3957 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3958  unsigned FreeSSERegs,
3959  bool IsVectorCall,
3960  bool IsRegCall) const {
3961  unsigned Count = 0;
3962  for (auto &I : FI.arguments()) {
3963  // Vectorcall in x64 only permits the first 6 arguments to be passed
3964  // as XMM/YMM registers.
3965  if (Count < VectorcallMaxParamNumAsReg)
3966  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3967  else {
3968  // Since these cannot be passed in registers, pretend no registers
3969  // are left.
3970  unsigned ZeroSSERegsAvail = 0;
3971  I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3972  IsVectorCall, IsRegCall);
3973  }
3974  ++Count;
3975  }
3976 
3977  for (auto &I : FI.arguments()) {
3978  I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3979  }
3980 }
3981 
3982 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3983  bool IsVectorCall =
3984  FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3985  bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3986 
3987  unsigned FreeSSERegs = 0;
3988  if (IsVectorCall) {
3989  // We can use up to 4 SSE return registers with vectorcall.
3990  FreeSSERegs = 4;
3991  } else if (IsRegCall) {
3992  // RegCall gives us 16 SSE registers.
3993  FreeSSERegs = 16;
3994  }
3995 
3996  if (!getCXXABI().classifyReturnType(FI))
3997  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3998  IsVectorCall, IsRegCall);
3999 
4000  if (IsVectorCall) {
4001  // We can use up to 6 SSE register parameters with vectorcall.
4002  FreeSSERegs = 6;
4003  } else if (IsRegCall) {
4004  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4005  FreeSSERegs = 16;
4006  }
4007 
4008  if (IsVectorCall) {
4009  computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4010  } else {
4011  for (auto &I : FI.arguments())
4012  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4013  }
4014 
4015 }
4016 
4017 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4018  QualType Ty) const {
4019 
4020  bool IsIndirect = false;
4021 
4022  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4023  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4024  if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4025  uint64_t Width = getContext().getTypeSize(Ty);
4026  IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4027  }
4028 
4029  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4030  CGF.getContext().getTypeInfoInChars(Ty),
4032  /*allowHigherAlign*/ false);
4033 }
4034 
4035 // PowerPC-32
4036 namespace {
4037 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4038 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4039  bool IsSoftFloatABI;
4040 
4041  CharUnits getParamTypeAlignment(QualType Ty) const;
4042 
4043 public:
4044  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4045  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4046 
4047  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4048  QualType Ty) const override;
4049 };
4050 
4051 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4052 public:
4053  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4054  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4055 
4056  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4057  // This is recovered from gcc output.
4058  return 1; // r1 is the dedicated stack pointer
4059  }
4060 
4061  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4062  llvm::Value *Address) const override;
4063 };
4064 }
4065 
4066 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4067  // Complex types are passed just like their elements
4068  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4069  Ty = CTy->getElementType();
4070 
4071  if (Ty->isVectorType())
4072  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4073  : 4);
4074 
4075  // For single-element float/vector structs, we consider the whole type
4076  // to have the same alignment requirements as its single element.
4077  const Type *AlignTy = nullptr;
4078  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4079  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4080  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4081  (BT && BT->isFloatingPoint()))
4082  AlignTy = EltType;
4083  }
4084 
4085  if (AlignTy)
4086  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4087  return CharUnits::fromQuantity(4);
4088 }
4089 
4090 // TODO: this implementation is now likely redundant with
4091 // DefaultABIInfo::EmitVAArg.
4092 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4093  QualType Ty) const {
4094  if (getTarget().getTriple().isOSDarwin()) {
4095  auto TI = getContext().getTypeInfoInChars(Ty);
4096  TI.second = getParamTypeAlignment(Ty);
4097 
4098  CharUnits SlotSize = CharUnits::fromQuantity(4);
4099  return emitVoidPtrVAArg(CGF, VAList, Ty,
4100  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4101  /*AllowHigherAlign=*/true);
4102  }
4103 
4104  const unsigned OverflowLimit = 8;
4105  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4106  // TODO: Implement this. For now ignore.
4107  (void)CTy;
4108  return Address::invalid(); // FIXME?
4109  }
4110 
4111  // struct __va_list_tag {
4112  // unsigned char gpr;
4113  // unsigned char fpr;
4114  // unsigned short reserved;
4115  // void *overflow_arg_area;
4116  // void *reg_save_area;
4117  // };
4118 
4119  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4120  bool isInt =
4121  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4122  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4123 
4124  // All aggregates are passed indirectly? That doesn't seem consistent
4125  // with the argument-lowering code.
4126  bool isIndirect = Ty->isAggregateType();
4127 
4128  CGBuilderTy &Builder = CGF.Builder;
4129 
4130  // The calling convention either uses 1-2 GPRs or 1 FPR.
4131  Address NumRegsAddr = Address::invalid();
4132  if (isInt || IsSoftFloatABI) {
4133  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4134  } else {
4135  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4136  }
4137 
4138  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4139 
4140  // "Align" the register count when TY is i64.
4141  if (isI64 || (isF64 && IsSoftFloatABI)) {
4142  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4143  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4144  }
4145 
4146  llvm::Value *CC =
4147  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4148 
4149  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4150  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4151  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4152 
4153  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4154 
4155  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4156  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4157 
4158  // Case 1: consume registers.
4159  Address RegAddr = Address::invalid();
4160  {
4161  CGF.EmitBlock(UsingRegs);
4162 
4163  Address RegSaveAreaPtr =
4164  Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4165  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4167  assert(RegAddr.getElementType() == CGF.Int8Ty);
4168 
4169  // Floating-point registers start after the general-purpose registers.
4170  if (!(isInt || IsSoftFloatABI)) {
4171  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4173  }
4174 
4175  // Get the address of the saved value by scaling the number of
4176  // registers we've used by the number of
4177  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4178  llvm::Value *RegOffset =
4179  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4180  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4181  RegAddr.getPointer(), RegOffset),
4182  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4183  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4184 
4185  // Increase the used-register count.
4186  NumRegs =
4187  Builder.CreateAdd(NumRegs,
4188  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4189  Builder.CreateStore(NumRegs, NumRegsAddr);
4190 
4191  CGF.EmitBranch(Cont);
4192  }
4193 
4194  // Case 2: consume space in the overflow area.
4195  Address MemAddr = Address::invalid();
4196  {
4197  CGF.EmitBlock(UsingOverflow);
4198 
4199  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4200 
4201  // Everything in the overflow area is rounded up to a size of at least 4.
4202  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4203 
4204  CharUnits Size;
4205  if (!isIndirect) {
4206  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4207  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4208  } else {
4209  Size = CGF.getPointerSize();
4210  }
4211 
4212  Address OverflowAreaAddr =
4213  Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4214  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4215  OverflowAreaAlign);
4216  // Round up address of argument to alignment
4217  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4218  if (Align > OverflowAreaAlign) {
4219  llvm::Value *Ptr = OverflowArea.getPointer();
4220  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4221  Align);
4222  }
4223 
4224  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4225 
4226  // Increase the overflow area.
4227  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4228  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4229  CGF.EmitBranch(Cont);
4230  }
4231 
4232  CGF.EmitBlock(Cont);
4233 
4234  // Merge the cases with a phi.
4235  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4236  "vaarg.addr");
4237 
4238  // Load the pointer if the argument was passed indirectly.
4239  if (isIndirect) {
4240  Result = Address(Builder.CreateLoad(Result, "aggr"),
4242  }
4243 
4244  return Result;
4245 }
4246 
4247 bool
4248 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4249  llvm::Value *Address) const {
4250  // This is calculated from the LLVM and GCC tables and verified
4251  // against gcc output. AFAIK all ABIs use the same encoding.
4252 
4253  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4254 
4255  llvm::IntegerType *i8 = CGF.Int8Ty;
4256  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4257  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4258  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4259 
4260  // 0-31: r0-31, the 4-byte general-purpose registers
4261  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4262 
4263  // 32-63: fp0-31, the 8-byte floating-point registers
4264  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4265 
4266  // 64-76 are various 4-byte special-purpose registers:
4267  // 64: mq
4268  // 65: lr
4269  // 66: ctr
4270  // 67: ap
4271  // 68-75 cr0-7
4272  // 76: xer
4273  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4274 
4275  // 77-108: v0-31, the 16-byte vector registers
4276  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4277 
4278  // 109: vrsave
4279  // 110: vscr
4280  // 111: spe_acc
4281  // 112: spefscr
4282  // 113: sfp
4283  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4284 
4285  return false;
4286 }
4287 
4288 // PowerPC-64
4289 
4290 namespace {
4291 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4292 class PPC64_SVR4_ABIInfo : public ABIInfo {
4293 public:
4294  enum ABIKind {
4295  ELFv1 = 0,
4296  ELFv2
4297  };
4298 
4299 private:
4300  static const unsigned GPRBits = 64;
4301  ABIKind Kind;
4302  bool HasQPX;
4303  bool IsSoftFloatABI;
4304 
4305  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4306  // will be passed in a QPX register.
4307  bool IsQPXVectorTy(const Type *Ty) const {
4308  if (!HasQPX)
4309  return false;
4310 
4311  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4312  unsigned NumElements = VT->getNumElements();
4313  if (NumElements == 1)
4314  return false;
4315 
4316  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4317  if (getContext().getTypeSize(Ty) <= 256)
4318  return true;
4319  } else if (VT->getElementType()->
4320  isSpecificBuiltinType(BuiltinType::Float)) {
4321  if (getContext().getTypeSize(Ty) <= 128)
4322  return true;
4323  }
4324  }
4325 
4326  return false;
4327  }
4328 
4329  bool IsQPXVectorTy(QualType Ty) const {
4330  return IsQPXVectorTy(Ty.getTypePtr());
4331  }
4332 
4333 public:
4334  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4335  bool SoftFloatABI)
4336  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4337  IsSoftFloatABI(SoftFloatABI) {}
4338 
4339  bool isPromotableTypeForABI(QualType Ty) const;
4340  CharUnits getParamTypeAlignment(QualType Ty) const;
4341 
4342  ABIArgInfo classifyReturnType(QualType RetTy) const;
4344 
4345  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4346  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4347  uint64_t Members) const override;
4348 
4349  // TODO: We can add more logic to computeInfo to improve performance.
4350  // Example: For aggregate arguments that fit in a register, we could
4351  // use getDirectInReg (as is done below for structs containing a single
4352  // floating-point value) to avoid pushing them to memory on function
4353  // entry. This would require changing the logic in PPCISelLowering
4354  // when lowering the parameters in the caller and args in the callee.
4355  void computeInfo(CGFunctionInfo &FI) const override {
4356  if (!getCXXABI().classifyReturnType(FI))
4358  for (auto &I : FI.arguments()) {
4359  // We rely on the default argument classification for the most part.
4360  // One exception: An aggregate containing a single floating-point
4361  // or vector item must be passed in a register if one is available.
4362  const Type *T = isSingleElementStruct(I.type, getContext());
4363  if (T) {
4364  const BuiltinType *BT = T->getAs<BuiltinType>();
4365  if (IsQPXVectorTy(T) ||
4366  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4367  (BT && BT->isFloatingPoint())) {
4368  QualType QT(T, 0);
4369  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4370  continue;
4371  }
4372  }
4373  I.info = classifyArgumentType(I.type);
4374  }
4375  }
4376 
4377  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4378  QualType Ty) const override;
4379 };
4380 
4381 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4382 
4383 public:
4384  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4385  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4386  bool SoftFloatABI)
4387  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4388  SoftFloatABI)) {}
4389 
4390  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4391  // This is recovered from gcc output.
4392  return 1; // r1 is the dedicated stack pointer
4393  }
4394 
4395  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4396  llvm::Value *Address) const override;
4397 };
4398 
4399 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4400 public:
4401  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4402 
4403  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4404  // This is recovered from gcc output.
4405  return 1; // r1 is the dedicated stack pointer
4406  }
4407 
4408  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4409  llvm::Value *Address) const override;
4410 };
4411 
4412 }
4413 
4414 // Return true if the ABI requires Ty to be passed sign- or zero-
4415 // extended to 64 bits.
4416 bool
4417 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4418  // Treat an enum type as its underlying type.
4419  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4420  Ty = EnumTy->getDecl()->getIntegerType();
4421 
4422  // Promotable integer types are required to be promoted by the ABI.
4423  if (Ty->isPromotableIntegerType())
4424  return true;
4425 
4426  // In addition to the usual promotable integer types, we also need to
4427  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4428  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4429  switch (BT->getKind()) {
4430  case BuiltinType::Int:
4431  case BuiltinType::UInt:
4432  return true;
4433  default:
4434  break;
4435  }
4436 
4437  return false;
4438 }
4439 
4440 /// isAlignedParamType - Determine whether a type requires 16-byte or
4441 /// higher alignment in the parameter area. Always returns at least 8.
4442 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4443  // Complex types are passed just like their elements.
4444  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4445  Ty = CTy->getElementType();
4446 
4447  // Only vector types of size 16 bytes need alignment (larger types are
4448  // passed via reference, smaller types are not aligned).
4449  if (IsQPXVectorTy(Ty)) {
4450  if (getContext().getTypeSize(Ty) > 128)
4451  return CharUnits::fromQuantity(32);
4452 
4453  return CharUnits::fromQuantity(16);
4454  } else if (Ty->isVectorType()) {
4455  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4456  }
4457 
4458  // For single-element float/vector structs, we consider the whole type
4459  // to have the same alignment requirements as its single element.
4460  const Type *AlignAsType = nullptr;
4461  const Type *EltType = isSingleElementStruct(Ty, getContext());
4462  if (EltType) {
4463  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4464  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4465  getContext().getTypeSize(EltType) == 128) ||
4466  (BT && BT->isFloatingPoint()))
4467  AlignAsType = EltType;
4468  }
4469 
4470  // Likewise for ELFv2 homogeneous aggregates.
4471  const Type *Base = nullptr;
4472  uint64_t Members = 0;
4473  if (!AlignAsType && Kind == ELFv2 &&
4474  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4475  AlignAsType = Base;
4476 
4477  // With special case aggregates, only vector base types need alignment.
4478  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4479  if (getContext().getTypeSize(AlignAsType) > 128)
4480  return CharUnits::fromQuantity(32);
4481 
4482  return CharUnits::fromQuantity(16);
4483  } else if (AlignAsType) {
4484  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4485  }
4486 
4487  // Otherwise, we only need alignment for any aggregate type that
4488  // has an alignment requirement of >= 16 bytes.
4489  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4490  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4491  return CharUnits::fromQuantity(32);
4492  return CharUnits::fromQuantity(16);
4493  }
4494 
4495  return CharUnits::fromQuantity(8);
4496 }
4497 
4498 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4499 /// aggregate. Base is set to the base element type, and Members is set
4500 /// to the number of base elements.
4502  uint64_t &Members) const {
4503  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4504  uint64_t NElements = AT->getSize().getZExtValue();
4505  if (NElements == 0)
4506  return false;
4507  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4508  return false;
4509  Members *= NElements;
4510  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4511  const RecordDecl *RD = RT->getDecl();
4512  if (RD->hasFlexibleArrayMember())
4513  return false;
4514 
4515  Members = 0;
4516 
4517  // If this is a C++ record, check the bases first.
4518  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4519  for (const auto &I : CXXRD->bases()) {
4520  // Ignore empty records.
4521  if (isEmptyRecord(getContext(), I.getType(), true))
4522  continue;
4523 
4524  uint64_t FldMembers;
4525  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4526  return false;
4527 
4528  Members += FldMembers;
4529  }
4530  }
4531 
4532  for (const auto *FD : RD->fields()) {
4533  // Ignore (non-zero arrays of) empty records.
4534  QualType FT = FD->getType();
4535  while (const ConstantArrayType *AT =
4536  getContext().getAsConstantArrayType(FT)) {
4537  if (AT->getSize().getZExtValue() == 0)
4538  return false;
4539  FT = AT->getElementType();
4540  }
4541  if (isEmptyRecord(getContext(), FT, true))
4542  continue;
4543 
4544  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4545  if (getContext().getLangOpts().CPlusPlus &&
4546  FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4547  continue;
4548 
4549  uint64_t FldMembers;
4550  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4551  return false;
4552 
4553  Members = (RD->isUnion() ?
4554  std::max(Members, FldMembers) : Members + FldMembers);
4555  }
4556 
4557  if (!Base)
4558  return false;
4559 
4560  // Ensure there is no padding.
4561  if (getContext().getTypeSize(Base) * Members !=
4562  getContext().getTypeSize(Ty))
4563  return false;
4564  } else {
4565  Members = 1;
4566  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4567  Members = 2;
4568  Ty = CT->getElementType();
4569  }
4570 
4571  // Most ABIs only support float, double, and some vector type widths.
4573  return false;
4574 
4575  // The base type must be the same for all members. Types that
4576  // agree in both total size and mode (float vs. vector) are
4577  // treated as being equivalent here.
4578  const Type *TyPtr = Ty.getTypePtr();
4579  if (!Base) {
4580  Base = TyPtr;
4581  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4582  // so make sure to widen it explicitly.
4583  if (const VectorType *VT = Base->getAs<VectorType>()) {
4584  QualType EltTy = VT->getElementType();
4585  unsigned NumElements =
4586  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4587  Base = getContext()
4588  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4589  .getTypePtr();
4590  }
4591  }
4592 
4593  if (Base->isVectorType() != TyPtr->isVectorType() ||
4594  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4595  return false;
4596  }
4597  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4598 }
4599 
4600 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4601  // Homogeneous aggregates for ELFv2 must have base types of float,
4602  // double, long double, or 128-bit vectors.
4603  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4604  if (BT->getKind() == BuiltinType::Float ||
4605  BT->getKind() == BuiltinType::Double ||
4606  BT->getKind() == BuiltinType::LongDouble) {
4607  if (IsSoftFloatABI)
4608  return false;
4609  return true;
4610  }
4611  }
4612  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4613  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4614  return true;
4615  }
4616  return false;
4617 }
4618 
4619 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4620  const Type *Base, uint64_t Members) const {
4621  // Vector types require one register, floating point types require one
4622  // or two registers depending on their size.
4623  uint32_t NumRegs =
4624  Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4625 
4626  // Homogeneous Aggregates may occupy at most 8 registers.
4627  return Members * NumRegs <= 8;
4628 }
4629 
4630 ABIArgInfo
4633 
4634  if (Ty->isAnyComplexType())
4635  return ABIArgInfo::getDirect();
4636 
4637  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4638  // or via reference (larger than 16 bytes).
4639  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4640  uint64_t Size = getContext().getTypeSize(Ty);
4641  if (Size > 128)
4642  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4643  else if (Size < 128) {
4644  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4645  return ABIArgInfo::getDirect(CoerceTy);
4646  }
4647  }
4648 
4649  if (isAggregateTypeForABI(Ty)) {
4652 
4653  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4654  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4655 
4656  // ELFv2 homogeneous aggregates are passed as array types.
4657  const Type *Base = nullptr;
4658  uint64_t Members = 0;
4659  if (Kind == ELFv2 &&
4660  isHomogeneousAggregate(Ty, Base, Members)) {
4661  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4662  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4663  return ABIArgInfo::getDirect(CoerceTy);
4664  }
4665 
4666  // If an aggregate may end up fully in registers, we do not
4667  // use the ByVal method, but pass the aggregate as array.
4668  // This is usually beneficial since we avoid forcing the
4669  // back-end to store the argument to memory.
4670  uint64_t Bits = getContext().getTypeSize(Ty);
4671  if (Bits > 0 && Bits <= 8 * GPRBits) {
4672  llvm::Type *CoerceTy;
4673 
4674  // Types up to 8 bytes are passed as integer type (which will be
4675  // properly aligned in the argument save area doubleword).
4676  if (Bits <= GPRBits)
4677  CoerceTy =
4678  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4679  // Larger types are passed as arrays, with the base type selected
4680  // according to the required alignment in the save area.
4681  else {
4682  uint64_t RegBits = ABIAlign * 8;
4683  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4684  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4685  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4686  }
4687 
4688  return ABIArgInfo::getDirect(CoerceTy);
4689  }
4690 
4691  // All other aggregates are passed ByVal.
4693  /*ByVal=*/true,
4694  /*Realign=*/TyAlign > ABIAlign);
4695  }
4696 
4697  return (isPromotableTypeForABI(Ty) ?
4699 }
4700 
4701 ABIArgInfo
4703  if (RetTy->isVoidType())
4704  return ABIArgInfo::getIgnore();
4705 
4706  if (RetTy->isAnyComplexType())
4707  return ABIArgInfo::getDirect();
4708 
4709  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4710  // or via reference (larger than 16 bytes).
4711  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4712  uint64_t Size = getContext().getTypeSize(RetTy);
4713  if (Size > 128)
4714  return getNaturalAlignIndirect(RetTy);
4715  else if (Size < 128) {
4716  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4717  return ABIArgInfo::getDirect(CoerceTy);
4718  }
4719  }
4720 
4721  if (isAggregateTypeForABI(RetTy)) {
4722  // ELFv2 homogeneous aggregates are returned as array types.
4723  const Type *Base = nullptr;
4724  uint64_t Members = 0;
4725  if (Kind == ELFv2 &&
4726  isHomogeneousAggregate(RetTy, Base, Members)) {
4727  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4728  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4729  return ABIArgInfo::getDirect(CoerceTy);
4730  }
4731 
4732  // ELFv2 small aggregates are returned in up to two registers.
4733  uint64_t Bits = getContext().getTypeSize(RetTy);
4734  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4735  if (Bits == 0)
4736  return ABIArgInfo::getIgnore();
4737 
4738  llvm::Type *CoerceTy;
4739  if (Bits > GPRBits) {
4740  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4741  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4742  } else
4743  CoerceTy =
4744  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4745  return ABIArgInfo::getDirect(CoerceTy);
4746  }
4747 
4748  // All other aggregates are returned indirectly.
4749  return getNaturalAlignIndirect(RetTy);
4750  }
4751 
4752  return (isPromotableTypeForABI(RetTy) ?
4754 }
4755 
4756 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4757 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4758  QualType Ty) const {
4759  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4760  TypeInfo.second = getParamTypeAlignment(Ty);
4761 
4762  CharUnits SlotSize = CharUnits::fromQuantity(8);
4763 
4764  // If we have a complex type and the base type is smaller than 8 bytes,
4765  // the ABI calls for the real and imaginary parts to be right-adjusted
4766  // in separate doublewords. However, Clang expects us to produce a
4767  // pointer to a structure with the two parts packed tightly. So generate
4768  // loads of the real and imaginary parts relative to the va_list pointer,
4769  // and store them to a temporary structure.
4770  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4771  CharUnits EltSize = TypeInfo.first / 2;
4772  if (EltSize < SlotSize) {
4773  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4774  SlotSize * 2, SlotSize,
4775  SlotSize, /*AllowHigher*/ true);
4776 
4777  Address RealAddr = Addr;
4778  Address ImagAddr = RealAddr;
4779  if (CGF.CGM.getDataLayout().isBigEndian()) {
4780  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4781  SlotSize - EltSize);
4782  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4783  2 * SlotSize - EltSize);
4784  } else {
4785  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4786  }
4787 
4788  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4789  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4790  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4791  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4792  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4793 
4794  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4795  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4796  /*init*/ true);
4797  return Temp;
4798  }
4799  }
4800 
4801  // Otherwise, just use the general rule.
4802  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4803  TypeInfo, SlotSize, /*AllowHigher*/ true);
4804 }
4805 
4806 static bool
4808  llvm::Value *Address) {
4809  // This is calculated from the LLVM and GCC tables and verified
4810  // against gcc output. AFAIK all ABIs use the same encoding.
4811 
4812  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4813 
4814  llvm::IntegerType *i8 = CGF.Int8Ty;
4815  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4816  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4817  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4818 
4819  // 0-31: r0-31, the 8-byte general-purpose registers
4820  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4821 
4822  // 32-63: fp0-31, the 8-byte floating-point registers
4823  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4824 
4825  // 64-67 are various 8-byte special-purpose registers:
4826  // 64: mq
4827  // 65: lr
4828  // 66: ctr
4829  // 67: ap
4830  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4831 
4832  // 68-76 are various 4-byte special-purpose registers:
4833  // 68-75 cr0-7
4834  // 76: xer
4835  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4836 
4837  // 77-108: v0-31, the 16-byte vector registers
4838  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4839 
4840  // 109: vrsave
4841  // 110: vscr
4842  // 111: spe_acc
4843  // 112: spefscr
4844  // 113: sfp
4845  // 114: tfhar
4846  // 115: tfiar
4847  // 116: texasr
4848  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4849 
4850  return false;
4851 }
4852 
4853 bool
4854 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4856  llvm::Value *Address) const {
4857 
4858  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4859 }
4860 
4861 bool
4862 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4863  llvm::Value *Address) const {
4864 
4865  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4866 }
4867 
4868 //===----------------------------------------------------------------------===//
4869 // AArch64 ABI Implementation
4870 //===----------------------------------------------------------------------===//
4871 
4872 namespace {
4873 
4874 class AArch64ABIInfo : public SwiftABIInfo {
4875 public:
4876  enum ABIKind {
4877  AAPCS = 0,
4878  DarwinPCS,
4879  Win64
4880  };
4881 
4882 private:
4883  ABIKind Kind;
4884 
4885 public:
4886  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4887  : SwiftABIInfo(CGT), Kind(Kind) {}
4888 
4889 private:
4890  ABIKind getABIKind() const { return Kind; }
4891  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4892 
4893  ABIArgInfo classifyReturnType(QualType RetTy) const;
4895  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4896  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4897  uint64_t Members) const override;
4898 
4899  bool isIllegalVectorType(QualType Ty) const;
4900 
4901  void computeInfo(CGFunctionInfo &FI) const override {
4902  if (!getCXXABI().classifyReturnType(FI))
4904 
4905  for (auto &it : FI.arguments())
4906  it.info = classifyArgumentType(it.type);
4907  }
4908 
4909  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4910  CodeGenFunction &CGF) const;
4911 
4912  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4913  CodeGenFunction &CGF) const;
4914 
4915  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4916  QualType Ty) const override {
4917  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4918  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4919  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4920  }
4921 
4922  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4923  QualType Ty) const override;
4924 
4925  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
4926  ArrayRef<llvm::Type*> scalars,
4927  bool asReturnValue) const override {
4928  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4929  }
4930  bool isSwiftErrorInRegister() const override {
4931  return true;
4932  }
4933 
4934  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4935  unsigned elts) const override;
4936 };
4937 
4938 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4939 public:
4940  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4941  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4942 
4943  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4944  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4945  }
4946 
4947  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4948  return 31;
4949  }
4950 
4951  bool doesReturnSlotInterfereWithArgs() const override { return false; }
4952 };
4953 
4954 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
4955 public:
4956  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
4957  : AArch64TargetCodeGenInfo(CGT, K) {}
4958 
4959  void getDependentLibraryOption(llvm::StringRef Lib,
4960  llvm::SmallString<24> &Opt) const override {
4961  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
4962  }
4963 
4964  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
4965  llvm::SmallString<32> &Opt) const override {
4966  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
4967  }
4968 };
4969 }
4970 
4973 
4974  // Handle illegal vector types here.
4975  if (isIllegalVectorType(Ty)) {
4976  uint64_t Size = getContext().getTypeSize(Ty);
4977  // Android promotes <2 x i8> to i16, not i32
4978  if (isAndroid() && (Size <= 16)) {
4979  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4980  return ABIArgInfo::getDirect(ResType);
4981  }
4982  if (Size <= 32) {
4983  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4984  return ABIArgInfo::getDirect(ResType);
4985  }
4986  if (Size == 64) {
4987  llvm::Type *ResType =
4988  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4989  return ABIArgInfo::getDirect(ResType);
4990  }
4991  if (Size == 128) {
4992  llvm::Type *ResType =
4993  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4994  return ABIArgInfo::getDirect(ResType);
4995  }
4996  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4997  }
4998 
4999  if (!isAggregateTypeForABI(Ty)) {
5000  // Treat an enum type as its underlying type.
5001  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5002  Ty = EnumTy->getDecl()->getIntegerType();
5003 
5004  return (Ty->isPromotableIntegerType() && isDarwinPCS()
5006  : ABIArgInfo::getDirect());
5007  }
5008 
5009  // Structures with either a non-trivial destructor or a non-trivial
5010  // copy constructor are always indirect.
5012  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5014  }
5015 
5016  // Empty records are always ignored on Darwin, but actually passed in C++ mode
5017  // elsewhere for GNU compatibility.
5018  uint64_t Size = getContext().getTypeSize(Ty);
5019  bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5020  if (IsEmpty || Size == 0) {
5021  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5022  return ABIArgInfo::getIgnore();
5023 
5024  // GNU C mode. The only argument that gets ignored is an empty one with size
5025  // 0.
5026  if (IsEmpty && Size == 0)
5027  return ABIArgInfo::getIgnore();
5028  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5029  }
5030 
5031  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5032  const Type *Base = nullptr;
5033  uint64_t Members = 0;
5034  if (isHomogeneousAggregate(Ty, Base, Members)) {
5035  return ABIArgInfo::getDirect(
5036  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5037  }
5038 
5039  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5040  if (Size <= 128) {
5041  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5042  // same size and alignment.
5043  if (getTarget().isRenderScriptTarget()) {
5044  return coerceToIntArray(Ty, getContext(), getVMContext());
5045  }
5046  unsigned Alignment = getContext().getTypeAlign(Ty);
5047  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5048 
5049  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5050  // For aggregates with 16-byte alignment, we use i128.
5051  if (Alignment < 128 && Size == 128) {
5052  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5053  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5054  }
5055  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5056  }
5057 
5058  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5059 }
5060 
5062  if (RetTy->isVoidType())
5063  return ABIArgInfo::getIgnore();
5064 
5065  // Large vector types should be returned via memory.
5066  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5067  return getNaturalAlignIndirect(RetTy);
5068 
5069  if (!isAggregateTypeForABI(RetTy)) {
5070  // Treat an enum type as its underlying type.
5071  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5072  RetTy = EnumTy->getDecl()->getIntegerType();
5073 
5074  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5076  : ABIArgInfo::getDirect());
5077  }
5078 
5079  uint64_t Size = getContext().getTypeSize(RetTy);
5080  if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5081  return ABIArgInfo::getIgnore();
5082 
5083  const Type *Base = nullptr;
5084  uint64_t Members = 0;
5085  if (isHomogeneousAggregate(RetTy, Base, Members))
5086  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5087  return ABIArgInfo::getDirect();
5088 
5089  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5090  if (Size <= 128) {
5091  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5092  // same size and alignment.
5093  if (getTarget().isRenderScriptTarget()) {
5094  return coerceToIntArray(RetTy, getContext(), getVMContext());
5095  }
5096  unsigned Alignment = getContext().getTypeAlign(RetTy);
5097  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5098 
5099  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5100  // For aggregates with 16-byte alignment, we use i128.
5101  if (Alignment < 128 && Size == 128) {
5102  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5103  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5104  }
5105  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5106  }
5107 
5108  return getNaturalAlignIndirect(RetTy);
5109 }
5110 
5111 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5112 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5113  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5114  // Check whether VT is legal.
5115  unsigned NumElements = VT->getNumElements();
5116  uint64_t Size = getContext().getTypeSize(VT);
5117  // NumElements should be power of 2.
5118  if (!llvm::isPowerOf2_32(NumElements))
5119  return true;
5120  return Size != 64 && (Size != 128 || NumElements == 1);
5121  }
5122  return false;
5123 }
5124 
5125 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5126  llvm::Type *eltTy,
5127  unsigned elts) const {
5128  if (!llvm::isPowerOf2_32(elts))
5129  return false;
5130  if (totalSize.getQuantity() != 8 &&
5131  (totalSize.getQuantity() != 16 || elts == 1))
5132  return false;
5133  return true;
5134 }
5135 
5136 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5137  // Homogeneous aggregates for AAPCS64 must have base types of a floating
5138  // point type or a short-vector type. This is the same as the 32-bit ABI,
5139  // but with the difference that any floating-point type is allowed,
5140  // including __fp16.
5141  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5142  if (BT->isFloatingPoint())
5143  return true;
5144  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5145  unsigned VecSize = getContext().getTypeSize(VT);
5146  if (VecSize == 64 || VecSize == 128)
5147  return true;
5148  }
5149  return false;
5150 }
5151 
5152 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5153  uint64_t Members) const {
5154  return Members <= 4;
5155 }
5156 
5157 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5158  QualType Ty,
5159  CodeGenFunction &CGF) const {
5161  bool IsIndirect = AI.isIndirect();
5162 
5163  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5164  if (IsIndirect)
5165  BaseTy = llvm::PointerType::getUnqual(BaseTy);
5166  else if (AI.getCoerceToType())
5167  BaseTy = AI.getCoerceToType();
5168 
5169  unsigned NumRegs = 1;
5170  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5171  BaseTy = ArrTy->getElementType();
5172  NumRegs = ArrTy->getNumElements();
5173  }
5174  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5175 
5176  // The AArch64 va_list type and handling is specified in the Procedure Call
5177  // Standard, section B.4:
5178  //
5179  // struct {
5180  // void *__stack;
5181  // void *__gr_top;
5182  // void *__vr_top;
5183  // int __gr_offs;
5184  // int __vr_offs;
5185  // };
5186 
5187  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5188  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5189  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5190  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5191 
5192  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5193  CharUnits TyAlign = TyInfo.second;
5194 
5195  Address reg_offs_p = Address::invalid();
5196  llvm::Value *reg_offs = nullptr;
5197  int reg_top_index;
5198  CharUnits reg_top_offset;
5199  int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5200  if (!IsFPR) {
5201  // 3 is the field number of __gr_offs
5202  reg_offs_p =
5203  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5204  "gr_offs_p");
5205  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5206  reg_top_index = 1; // field number for __gr_top
5207  reg_top_offset = CharUnits::fromQuantity(8);
5208  RegSize = llvm::alignTo(RegSize, 8);
5209  } else {
5210  // 4 is the field number of __vr_offs.
5211  reg_offs_p =
5212  CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5213  "vr_offs_p");
5214  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5215  reg_top_index = 2; // field number for __vr_top
5216  reg_top_offset = CharUnits::fromQuantity(16);
5217  RegSize = 16 * NumRegs;
5218  }
5219 
5220  //=======================================
5221  // Find out where argument was passed
5222  //=======================================
5223 
5224  // If reg_offs >= 0 we're already using the stack for this type of
5225  // argument. We don't want to keep updating reg_offs (in case it overflows,
5226  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5227  // whatever they get).
5228  llvm::Value *UsingStack = nullptr;
5229  UsingStack = CGF.Builder.CreateICmpSGE(
5230  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5231 
5232  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5233 
5234  // Otherwise, at least some kind of argument could go in these registers, the
5235  // question is whether this particular type is too big.
5236  CGF.EmitBlock(MaybeRegBlock);
5237 
5238  // Integer arguments may need to correct register alignment (for example a
5239  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5240  // align __gr_offs to calculate the potential address.
5241  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5242  int Align = TyAlign.getQuantity();
5243 
5244  reg_offs = CGF.Builder.CreateAdd(
5245  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5246  "align_regoffs");
5247  reg_offs = CGF.Builder.CreateAnd(
5248  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5249  "aligned_regoffs");
5250  }
5251 
5252  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5253  // The fact that this is done unconditionally reflects the fact that
5254  // allocating an argument to the stack also uses up all the remaining
5255  // registers of the appropriate kind.
5256  llvm::Value *NewOffset = nullptr;
5257  NewOffset = CGF.Builder.CreateAdd(
5258  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5259  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5260 
5261  // Now we're in a position to decide whether this argument really was in
5262  // registers or not.
5263  llvm::Value *InRegs = nullptr;
5264  InRegs = CGF.Builder.CreateICmpSLE(
5265  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5266 
5267  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5268 
5269  //=======================================
5270  // Argument was in registers
5271  //=======================================
5272 
5273  // Now we emit the code for if the argument was originally passed in
5274  // registers. First start the appropriate block:
5275  CGF.EmitBlock(InRegBlock);
5276 
5277  llvm::Value *reg_top = nullptr;
5278  Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5279  reg_top_offset, "reg_top_p");
5280  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5281  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5282  CharUnits::fromQuantity(IsFPR ? 16 : 8));
5283  Address RegAddr = Address::invalid();
5284  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5285 
5286  if (IsIndirect) {
5287  // If it's been passed indirectly (actually a struct), whatever we find from
5288  // stored registers or on the stack will actually be a struct **.
5289  MemTy = llvm::PointerType::getUnqual(MemTy);
5290  }
5291 
5292  const Type *Base = nullptr;
5293  uint64_t NumMembers = 0;
5294  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5295  if (IsHFA && NumMembers > 1) {
5296  // Homogeneous aggregates passed in registers will have their elements split
5297  // and stored 16-bytes apart regardless of size (they're notionally in qN,
5298  // qN+1, ...). We reload and store into a temporary local variable
5299  // contiguously.
5300  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5301  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5302  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5303  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5304  Address Tmp = CGF.CreateTempAlloca(HFATy,
5305  std::max(TyAlign, BaseTyInfo.second));
5306 
5307  // On big-endian platforms, the value will be right-aligned in its slot.
5308  int Offset = 0;
5309  if (CGF.CGM.getDataLayout().isBigEndian() &&
5310  BaseTyInfo.first.getQuantity() < 16)
5311  Offset = 16 - BaseTyInfo.first.getQuantity();
5312 
5313  for (unsigned i = 0; i < NumMembers; ++i) {
5314  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5315  Address LoadAddr =
5316  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5317  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5318 
5319  Address StoreAddr =
5320  CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5321 
5322  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5323  CGF.Builder.CreateStore(Elem, StoreAddr);
5324  }
5325 
5326  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5327  } else {
5328  // Otherwise the object is contiguous in memory.
5329 
5330  // It might be right-aligned in its slot.
5331  CharUnits SlotSize = BaseAddr.getAlignment();
5332  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5333  (IsHFA || !isAggregateTypeForABI(Ty)) &&
5334  TyInfo.first < SlotSize) {
5335  CharUnits Offset = SlotSize - TyInfo.first;
5336  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5337  }
5338 
5339  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5340  }
5341 
5342  CGF.EmitBranch(ContBlock);
5343 
5344  //=======================================
5345  // Argument was on the stack
5346  //=======================================
5347  CGF.EmitBlock(OnStackBlock);
5348 
5349  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5350  CharUnits::Zero(), "stack_p");
5351  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5352 
5353  // Again, stack arguments may need realignment. In this case both integer and
5354  // floating-point ones might be affected.
5355  if (!IsIndirect && TyAlign.getQuantity() > 8) {
5356  int Align = TyAlign.getQuantity();
5357 
5358  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5359 
5360  OnStackPtr = CGF.Builder.CreateAdd(
5361  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5362  "align_stack");
5363  OnStackPtr = CGF.Builder.CreateAnd(
5364  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5365  "align_stack");
5366 
5367  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5368  }
5369  Address OnStackAddr(OnStackPtr,
5370  std::max(CharUnits::fromQuantity(8), TyAlign));
5371 
5372  // All stack slots are multiples of 8 bytes.
5373  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5374  CharUnits StackSize;
5375  if (IsIndirect)
5376  StackSize = StackSlotSize;
5377  else
5378  StackSize = TyInfo.first.alignTo(StackSlotSize);
5379 
5380  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5381  llvm::Value *NewStack =
5382  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5383 
5384  // Write the new value of __stack for the next call to va_arg
5385  CGF.Builder.CreateStore(NewStack, stack_p);
5386 
5387  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5388  TyInfo.first < StackSlotSize) {
5389  CharUnits Offset = StackSlotSize - TyInfo.first;
5390  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5391  }
5392 
5393  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5394 
5395  CGF.EmitBranch(ContBlock);
5396 
5397  //=======================================
5398  // Tidy up
5399  //=======================================
5400  CGF.EmitBlock(ContBlock);
5401 
5402  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5403  OnStackAddr, OnStackBlock, "vaargs.addr");
5404 
5405  if (IsIndirect)
5406  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5407  TyInfo.second);
5408 
5409  return ResAddr;
5410 }
5411 
5412 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5413  CodeGenFunction &CGF) const {
5414  // The backend's lowering doesn't support va_arg for aggregates or
5415  // illegal vector types. Lower VAArg here for these cases and use
5416  // the LLVM va_arg instruction for everything else.
5417  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5418  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5419 
5420  CharUnits SlotSize = CharUnits::fromQuantity(8);
5421 
5422  // Empty records are ignored for parameter passing purposes.
5423  if (isEmptyRecord(getContext(), Ty, true)) {
5424  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5425  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5426  return Addr;
5427  }
5428 
5429  // The size of the actual thing passed, which might end up just
5430  // being a pointer for indirect types.
5431  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5432 
5433  // Arguments bigger than 16 bytes which aren't homogeneous
5434  // aggregates should be passed indirectly.
5435  bool IsIndirect = false;
5436  if (TyInfo.first.getQuantity() > 16) {
5437  const Type *Base = nullptr;
5438  uint64_t Members = 0;
5439  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5440  }
5441 
5442  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5443  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5444 }
5445 
5446 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5447  QualType Ty) const {
5448  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5449  CGF.getContext().getTypeInfoInChars(Ty),
5451  /*allowHigherAlign*/ false);
5452 }
5453 
5454 //===----------------------------------------------------------------------===//
5455 // ARM ABI Implementation
5456 //===----------------------------------------------------------------------===//
5457 
5458 namespace {
5459 
5460 class ARMABIInfo : public SwiftABIInfo {
5461 public:
5462  enum ABIKind {
5463  APCS = 0,
5464  AAPCS = 1,
5465  AAPCS_VFP = 2,
5466  AAPCS16_VFP = 3,
5467  };
5468 
5469 private:
5470  ABIKind Kind;
5471 
5472 public:
5473  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5474  : SwiftABIInfo(CGT), Kind(_Kind) {
5475  setCCs();
5476  }
5477 
5478  bool isEABI() const {
5479  switch (getTarget().getTriple().getEnvironment()) {
5480  case llvm::Triple::Android:
5481  case llvm::Triple::EABI:
5482  case llvm::Triple::EABIHF:
5483  case llvm::Triple::GNUEABI:
5484  case llvm::Triple::GNUEABIHF:
5485  case llvm::Triple::MuslEABI:
5486  case llvm::Triple::MuslEABIHF:
5487  return true;
5488  default:
5489  return false;
5490  }
5491  }
5492 
5493  bool isEABIHF() const {
5494  switch (getTarget().getTriple().getEnvironment()) {
5495  case llvm::Triple::EABIHF:
5496  case llvm::Triple::GNUEABIHF:
5497  case llvm::Triple::MuslEABIHF:
5498  return true;
5499  default:
5500  return false;
5501  }
5502  }
5503 
5504  ABIKind getABIKind() const { return Kind; }
5505 
5506 private:
5507  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5508  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5509  bool isIllegalVectorType(QualType Ty) const;
5510 
5511  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5512  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5513  uint64_t Members) const override;
5514 
5515  void computeInfo(CGFunctionInfo &FI) const override;
5516 
5517  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5518  QualType Ty) const override;
5519 
5520  llvm::CallingConv::ID getLLVMDefaultCC() const;
5521  llvm::CallingConv::ID getABIDefaultCC() const;
5522  void setCCs();
5523 
5524  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5525  ArrayRef<llvm::Type*> scalars,
5526  bool asReturnValue) const override {
5527  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5528  }
5529  bool isSwiftErrorInRegister() const override {
5530  return true;
5531  }
5532  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5533  unsigned elts) const override;
5534 };
5535 
5536 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5537 public:
5538  ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5539  :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5540 
5541  const ARMABIInfo &getABIInfo() const {
5542  return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5543  }
5544 
5545  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5546  return 13;
5547  }
5548 
5549  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5550  return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5551  }
5552 
5553  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5554  llvm::Value *Address) const override {
5555  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5556 
5557  // 0-15 are the 16 integer registers.
5558  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5559  return false;
5560  }
5561 
5562  unsigned getSizeOfUnwindException() const override {
5563  if (getABIInfo().isEABI()) return 88;
5565  }
5566 
5567  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5569  ForDefinition_t IsForDefinition) const override {
5570  if (!IsForDefinition)
5571  return;
5572  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5573  if (!FD)
5574  return;
5575 
5576  const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5577  if (!Attr)
5578  return;
5579 
5580  const char *Kind;
5581  switch (Attr->getInterrupt()) {
5582  case ARMInterruptAttr::Generic: Kind = ""; break;
5583  case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5584  case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5585  case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5586  case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5587  case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5588  }
5589 
5590  llvm::Function *Fn = cast<llvm::Function>(GV);
5591 
5592  Fn->addFnAttr("interrupt", Kind);
5593 
5594  ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5595  if (ABI == ARMABIInfo::APCS)
5596  return;
5597 
5598  // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5599  // however this is not necessarily true on taking any interrupt. Instruct
5600  // the backend to perform a realignment as part of the function prologue.
5601  llvm::AttrBuilder B;
5602  B.addStackAlignmentAttr(8);
5603  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5604  }
5605 };
5606 
5607 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5608 public:
5609  WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5610  : ARMTargetCodeGenInfo(CGT, K) {}
5611 
5612  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5614  ForDefinition_t IsForDefinition) const override;
5615 
5616  void getDependentLibraryOption(llvm::StringRef Lib,
5617  llvm::SmallString<24> &Opt) const override {
5618  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5619  }
5620 
5621  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5622  llvm::SmallString<32> &Opt) const override {
5623  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5624  }
5625 };
5626 
5627 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5628  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM,
5629  ForDefinition_t IsForDefinition) const {
5630  ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM, IsForDefinition);
5631  if (!IsForDefinition)
5632  return;
5633  addStackProbeSizeTargetAttribute(D, GV, CGM);
5634 }
5635 }
5636 
5637 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5638  if (!getCXXABI().classifyReturnType(FI))
5639  FI.getReturnInfo() =
5641 
5642  for (auto &I : FI.arguments())
5643