clang  16.0.0git
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // These classes wrap the information about a call or function
10 // definition used to handle ABI compliancy.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "TargetInfo.h"
15 #include "ABIInfo.h"
16 #include "CGBlocks.h"
17 #include "CGCXXABI.h"
18 #include "CGValue.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/Attr.h"
21 #include "clang/AST/RecordLayout.h"
22 #include "clang/Basic/Builtins.h"
26 #include "llvm/ADT/SmallBitVector.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/IntrinsicsNVPTX.h"
33 #include "llvm/IR/IntrinsicsS390.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include <algorithm>
38 
39 using namespace clang;
40 using namespace CodeGen;
41 
42 // Helper for coercing an aggregate argument or return value into an integer
43 // array of the same size (including padding) and alignment. This alternate
44 // coercion happens only for the RenderScript ABI and can be removed after
45 // runtimes that rely on it are no longer supported.
46 //
47 // RenderScript assumes that the size of the argument / return value in the IR
48 // is the same as the size of the corresponding qualified type. This helper
49 // coerces the aggregate type into an array of the same size (including
50 // padding). This coercion is used in lieu of expansion of struct members or
51 // other canonical coercions that return a coerced-type of larger size.
52 //
53 // Ty - The argument / return value type
54 // Context - The associated ASTContext
55 // LLVMContext - The associated LLVMContext
57  ASTContext &Context,
58  llvm::LLVMContext &LLVMContext) {
59  // Alignment and Size are measured in bits.
60  const uint64_t Size = Context.getTypeSize(Ty);
61  const uint64_t Alignment = Context.getTypeAlign(Ty);
62  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
63  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
64  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
65 }
66 
68  llvm::Value *Array,
69  llvm::Value *Value,
70  unsigned FirstIndex,
71  unsigned LastIndex) {
72  // Alternatively, we could emit this as a loop in the source.
73  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
74  llvm::Value *Cell =
75  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
76  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
77  }
78 }
79 
83 }
84 
86  bool Realign,
87  llvm::Type *Padding) const {
88  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty), ByVal,
89  Realign, Padding);
90 }
91 
94  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
95  /*ByVal*/ false, Realign);
96 }
97 
99  QualType Ty) const {
100  return Address::invalid();
101 }
102 
103 static llvm::Type *getVAListElementType(CodeGenFunction &CGF) {
104  return CGF.ConvertTypeForMem(
106 }
107 
109  if (getContext().isPromotableIntegerType(Ty))
110  return true;
111 
112  if (const auto *EIT = Ty->getAs<BitIntType>())
113  if (EIT->getNumBits() < getContext().getTypeSize(getContext().IntTy))
114  return true;
115 
116  return false;
117 }
118 
119 ABIInfo::~ABIInfo() = default;
120 
121 SwiftABIInfo::~SwiftABIInfo() = default;
122 
123 /// Does the given lowering require more than the given number of
124 /// registers when expanded?
125 ///
126 /// This is intended to be the basis of a reasonable basic implementation
127 /// of should{Pass,Return}IndirectlyForSwift.
128 ///
129 /// For most targets, a limit of four total registers is reasonable; this
130 /// limits the amount of code required in order to move around the value
131 /// in case it wasn't produced immediately prior to the call by the caller
132 /// (or wasn't produced in exactly the right registers) or isn't used
133 /// immediately within the callee. But some targets may need to further
134 /// limit the register count due to an inability to support that many
135 /// return registers.
137  ArrayRef<llvm::Type*> scalarTypes,
138  unsigned maxAllRegisters) {
139  unsigned intCount = 0, fpCount = 0;
140  for (llvm::Type *type : scalarTypes) {
141  if (type->isPointerTy()) {
142  intCount++;
143  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
144  auto ptrWidth = cgt.getTarget().getPointerWidth(LangAS::Default);
145  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
146  } else {
147  assert(type->isVectorTy() || type->isFloatingPointTy());
148  fpCount++;
149  }
150  }
151 
152  return (intCount + fpCount > maxAllRegisters);
153 }
154 
156  bool AsReturnValue) const {
157  return occupiesMoreThan(CGT, ComponentTys, /*total=*/4);
158 }
159 
160 bool SwiftABIInfo::isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
161  unsigned NumElts) const {
162  // The default implementation of this assumes that the target guarantees
163  // 128-bit SIMD support but nothing more.
164  return (VectorSize.getQuantity() > 8 && VectorSize.getQuantity() <= 16);
165 }
166 
168  CGCXXABI &CXXABI) {
169  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
170  if (!RD) {
171  if (!RT->getDecl()->canPassInRegisters())
172  return CGCXXABI::RAA_Indirect;
173  return CGCXXABI::RAA_Default;
174  }
175  return CXXABI.getRecordArgABI(RD);
176 }
177 
179  CGCXXABI &CXXABI) {
180  const RecordType *RT = T->getAs<RecordType>();
181  if (!RT)
182  return CGCXXABI::RAA_Default;
183  return getRecordArgABI(RT, CXXABI);
184 }
185 
187  const ABIInfo &Info) {
188  QualType Ty = FI.getReturnType();
189 
190  if (const auto *RT = Ty->getAs<RecordType>())
191  if (!isa<CXXRecordDecl>(RT->getDecl()) &&
192  !RT->getDecl()->canPassInRegisters()) {
193  FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
194  return true;
195  }
196 
197  return CXXABI.classifyReturnType(FI);
198 }
199 
200 /// Pass transparent unions as if they were the type of the first element. Sema
201 /// should ensure that all elements of the union have the same "machine type".
203  if (const RecordType *UT = Ty->getAsUnionType()) {
204  const RecordDecl *UD = UT->getDecl();
205  if (UD->hasAttr<TransparentUnionAttr>()) {
206  assert(!UD->field_empty() && "sema created an empty transparent union");
207  return UD->field_begin()->getType();
208  }
209  }
210  return Ty;
211 }
212 
214  return CGT.getCXXABI();
215 }
216 
218  return CGT.getContext();
219 }
220 
221 llvm::LLVMContext &ABIInfo::getVMContext() const {
222  return CGT.getLLVMContext();
223 }
224 
225 const llvm::DataLayout &ABIInfo::getDataLayout() const {
226  return CGT.getDataLayout();
227 }
228 
230  return CGT.getTarget();
231 }
232 
234  return CGT.getCodeGenOpts();
235 }
236 
237 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
238 
240  return false;
241 }
242 
244  uint64_t Members) const {
245  return false;
246 }
247 
249  // For compatibility with GCC, ignore empty bitfields in C++ mode.
250  return getContext().getLangOpts().CPlusPlus;
251 }
252 
253 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
254  raw_ostream &OS = llvm::errs();
255  OS << "(ABIArgInfo Kind=";
256  switch (TheKind) {
257  case Direct:
258  OS << "Direct Type=";
259  if (llvm::Type *Ty = getCoerceToType())
260  Ty->print(OS);
261  else
262  OS << "null";
263  break;
264  case Extend:
265  OS << "Extend";
266  break;
267  case Ignore:
268  OS << "Ignore";
269  break;
270  case InAlloca:
271  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
272  break;
273  case Indirect:
274  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
275  << " ByVal=" << getIndirectByVal()
276  << " Realign=" << getIndirectRealign();
277  break;
278  case IndirectAliased:
279  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
280  << " AadrSpace=" << getIndirectAddrSpace()
281  << " Realign=" << getIndirectRealign();
282  break;
283  case Expand:
284  OS << "Expand";
285  break;
286  case CoerceAndExpand:
287  OS << "CoerceAndExpand Type=";
288  getCoerceAndExpandType()->print(OS);
289  break;
290  }
291  OS << ")\n";
292 }
293 
294 // Dynamically round a pointer up to a multiple of the given alignment.
296  llvm::Value *Ptr,
297  CharUnits Align) {
298  llvm::Value *PtrAsInt = Ptr;
299  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
300  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
301  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
302  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
303  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
304  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
305  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
306  Ptr->getType(),
307  Ptr->getName() + ".aligned");
308  return PtrAsInt;
309 }
310 
311 /// Emit va_arg for a platform using the common void* representation,
312 /// where arguments are simply emitted in an array of slots on the stack.
313 ///
314 /// This version implements the core direct-value passing rules.
315 ///
316 /// \param SlotSize - The size and alignment of a stack slot.
317 /// Each argument will be allocated to a multiple of this number of
318 /// slots, and all the slots will be aligned to this value.
319 /// \param AllowHigherAlign - The slot alignment is not a cap;
320 /// an argument type with an alignment greater than the slot size
321 /// will be emitted on a higher-alignment address, potentially
322 /// leaving one or more empty slots behind as padding. If this
323 /// is false, the returned address might be less-aligned than
324 /// DirectAlign.
325 /// \param ForceRightAdjust - Default is false. On big-endian platform and
326 /// if the argument is smaller than a slot, set this flag will force
327 /// right-adjust the argument in its slot irrespective of the type.
329  Address VAListAddr,
330  llvm::Type *DirectTy,
331  CharUnits DirectSize,
332  CharUnits DirectAlign,
333  CharUnits SlotSize,
334  bool AllowHigherAlign,
335  bool ForceRightAdjust = false) {
336  // Cast the element type to i8* if necessary. Some platforms define
337  // va_list as a struct containing an i8* instead of just an i8*.
338  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
339  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
340 
341  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
342 
343  // If the CC aligns values higher than the slot size, do so if needed.
344  Address Addr = Address::invalid();
345  if (AllowHigherAlign && DirectAlign > SlotSize) {
346  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
347  CGF.Int8Ty, DirectAlign);
348  } else {
349  Addr = Address(Ptr, CGF.Int8Ty, SlotSize);
350  }
351 
352  // Advance the pointer past the argument, then store that back.
353  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
354  Address NextPtr =
355  CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
356  CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
357 
358  // If the argument is smaller than a slot, and this is a big-endian
359  // target, the argument will be right-adjusted in its slot.
360  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
361  (!DirectTy->isStructTy() || ForceRightAdjust)) {
362  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
363  }
364 
365  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
366  return Addr;
367 }
368 
369 /// Emit va_arg for a platform using the common void* representation,
370 /// where arguments are simply emitted in an array of slots on the stack.
371 ///
372 /// \param IsIndirect - Values of this type are passed indirectly.
373 /// \param ValueInfo - The size and alignment of this type, generally
374 /// computed with getContext().getTypeInfoInChars(ValueTy).
375 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
376 /// Each argument will be allocated to a multiple of this number of
377 /// slots, and all the slots will be aligned to this value.
378 /// \param AllowHigherAlign - The slot alignment is not a cap;
379 /// an argument type with an alignment greater than the slot size
380 /// will be emitted on a higher-alignment address, potentially
381 /// leaving one or more empty slots behind as padding.
382 /// \param ForceRightAdjust - Default is false. On big-endian platform and
383 /// if the argument is smaller than a slot, set this flag will force
384 /// right-adjust the argument in its slot irrespective of the type.
386  QualType ValueTy, bool IsIndirect,
387  TypeInfoChars ValueInfo,
388  CharUnits SlotSizeAndAlign,
389  bool AllowHigherAlign,
390  bool ForceRightAdjust = false) {
391  // The size and alignment of the value that was passed directly.
392  CharUnits DirectSize, DirectAlign;
393  if (IsIndirect) {
394  DirectSize = CGF.getPointerSize();
395  DirectAlign = CGF.getPointerAlign();
396  } else {
397  DirectSize = ValueInfo.Width;
398  DirectAlign = ValueInfo.Align;
399  }
400 
401  // Cast the address we've calculated to the right type.
402  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy), *ElementTy = DirectTy;
403  if (IsIndirect)
404  DirectTy = DirectTy->getPointerTo(0);
405 
406  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, DirectSize,
407  DirectAlign, SlotSizeAndAlign,
408  AllowHigherAlign, ForceRightAdjust);
409 
410  if (IsIndirect) {
411  Addr = Address(CGF.Builder.CreateLoad(Addr), ElementTy, ValueInfo.Align);
412  }
413 
414  return Addr;
415 }
416 
418  QualType Ty, CharUnits SlotSize,
419  CharUnits EltSize, const ComplexType *CTy) {
420  Address Addr =
421  emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, SlotSize * 2,
422  SlotSize, SlotSize, /*AllowHigher*/ true);
423 
424  Address RealAddr = Addr;
425  Address ImagAddr = RealAddr;
426  if (CGF.CGM.getDataLayout().isBigEndian()) {
427  RealAddr =
428  CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize - EltSize);
429  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
430  2 * SlotSize - EltSize);
431  } else {
432  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
433  }
434 
435  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
436  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
437  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
438  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
439  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
440 
441  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
442  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
443  /*init*/ true);
444  return Temp;
445 }
446 
448  Address Addr1, llvm::BasicBlock *Block1,
449  Address Addr2, llvm::BasicBlock *Block2,
450  const llvm::Twine &Name = "") {
451  assert(Addr1.getType() == Addr2.getType());
452  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
453  PHI->addIncoming(Addr1.getPointer(), Block1);
454  PHI->addIncoming(Addr2.getPointer(), Block2);
455  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
456  return Address(PHI, Addr1.getElementType(), Align);
457 }
458 
459 TargetCodeGenInfo::TargetCodeGenInfo(std::unique_ptr<ABIInfo> Info)
460  : Info(std::move(Info)) {}
461 
463 
464 // If someone can figure out a general rule for this, that would be great.
465 // It's probably just doomed to be platform-dependent, though.
467  // Verified for:
468  // x86-64 FreeBSD, Linux, Darwin
469  // x86-32 FreeBSD, Linux, Darwin
470  // PowerPC Linux, Darwin
471  // ARM Darwin (*not* EABI)
472  // AArch64 Linux
473  return 32;
474 }
475 
477  const FunctionNoProtoType *fnType) const {
478  // The following conventions are known to require this to be false:
479  // x86_stdcall
480  // MIPS
481  // For everything else, we just prefer false unless we opt out.
482  return false;
483 }
484 
485 void
487  llvm::SmallString<24> &Opt) const {
488  // This assumes the user is passing a library name like "rt" instead of a
489  // filename like "librt.a/so", and that they don't care whether it's static or
490  // dynamic.
491  Opt = "-l";
492  Opt += Lib;
493 }
494 
496  // OpenCL kernels are called via an explicit runtime API with arguments
497  // set with clSetKernelArg(), not as normal sub-functions.
498  // Return SPIR_KERNEL by default as the kernel calling convention to
499  // ensure the fingerprint is fixed such way that each OpenCL argument
500  // gets one matching argument in the produced kernel function argument
501  // list to enable feasible implementation of clSetKernelArg() with
502  // aggregates etc. In case we would use the default C calling conv here,
503  // clSetKernelArg() might break depending on the target-specific
504  // conventions; different targets might split structs passed as values
505  // to multiple function arguments etc.
506  return llvm::CallingConv::SPIR_KERNEL;
507 }
508 
510  llvm::PointerType *T, QualType QT) const {
511  return llvm::ConstantPointerNull::get(T);
512 }
513 
515  const VarDecl *D) const {
516  assert(!CGM.getLangOpts().OpenCL &&
517  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
518  "Address space agnostic languages only");
519  return D ? D->getType().getAddressSpace() : LangAS::Default;
520 }
521 
523  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
524  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
525  // Since target may map different address spaces in AST to the same address
526  // space, an address space conversion may end up as a bitcast.
527  if (auto *C = dyn_cast<llvm::Constant>(Src))
528  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
529  // Try to preserve the source's name to make IR more readable.
531  Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : "");
532 }
533 
534 llvm::Constant *
536  LangAS SrcAddr, LangAS DestAddr,
537  llvm::Type *DestTy) const {
538  // Since target may map different address spaces in AST to the same address
539  // space, an address space conversion may end up as a bitcast.
540  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
541 }
542 
546  llvm::AtomicOrdering Ordering,
547  llvm::LLVMContext &Ctx) const {
548  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
549 }
550 
551 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
552 
553 /// isEmptyField - Return true iff a the field is "empty", that is it
554 /// is an unnamed bit-field or an (array of) empty record(s).
555 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
556  bool AllowArrays) {
557  if (FD->isUnnamedBitfield())
558  return true;
559 
560  QualType FT = FD->getType();
561 
562  // Constant arrays of empty records count as empty, strip them off.
563  // Constant arrays of zero length always count as empty.
564  bool WasArray = false;
565  if (AllowArrays)
566  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
567  if (AT->getSize() == 0)
568  return true;
569  FT = AT->getElementType();
570  // The [[no_unique_address]] special case below does not apply to
571  // arrays of C++ empty records, so we need to remember this fact.
572  WasArray = true;
573  }
574 
575  const RecordType *RT = FT->getAs<RecordType>();
576  if (!RT)
577  return false;
578 
579  // C++ record fields are never empty, at least in the Itanium ABI.
580  //
581  // FIXME: We should use a predicate for whether this behavior is true in the
582  // current ABI.
583  //
584  // The exception to the above rule are fields marked with the
585  // [[no_unique_address]] attribute (since C++20). Those do count as empty
586  // according to the Itanium ABI. The exception applies only to records,
587  // not arrays of records, so we must also check whether we stripped off an
588  // array type above.
589  if (isa<CXXRecordDecl>(RT->getDecl()) &&
590  (WasArray || !FD->hasAttr<NoUniqueAddressAttr>()))
591  return false;
592 
593  return isEmptyRecord(Context, FT, AllowArrays);
594 }
595 
596 /// isEmptyRecord - Return true iff a structure contains only empty
597 /// fields. Note that a structure with a flexible array member is not
598 /// considered empty.
599 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
600  const RecordType *RT = T->getAs<RecordType>();
601  if (!RT)
602  return false;
603  const RecordDecl *RD = RT->getDecl();
604  if (RD->hasFlexibleArrayMember())
605  return false;
606 
607  // If this is a C++ record, check the bases first.
608  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
609  for (const auto &I : CXXRD->bases())
610  if (!isEmptyRecord(Context, I.getType(), true))
611  return false;
612 
613  for (const auto *I : RD->fields())
614  if (!isEmptyField(Context, I, AllowArrays))
615  return false;
616  return true;
617 }
618 
619 /// isSingleElementStruct - Determine if a structure is a "single
620 /// element struct", i.e. it has exactly one non-empty field or
621 /// exactly one field which is itself a single element
622 /// struct. Structures with flexible array members are never
623 /// considered single element structs.
624 ///
625 /// \return The field declaration for the single non-empty field, if
626 /// it exists.
627 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
628  const RecordType *RT = T->getAs<RecordType>();
629  if (!RT)
630  return nullptr;
631 
632  const RecordDecl *RD = RT->getDecl();
633  if (RD->hasFlexibleArrayMember())
634  return nullptr;
635 
636  const Type *Found = nullptr;
637 
638  // If this is a C++ record, check the bases first.
639  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
640  for (const auto &I : CXXRD->bases()) {
641  // Ignore empty records.
642  if (isEmptyRecord(Context, I.getType(), true))
643  continue;
644 
645  // If we already found an element then this isn't a single-element struct.
646  if (Found)
647  return nullptr;
648 
649  // If this is non-empty and not a single element struct, the composite
650  // cannot be a single element struct.
651  Found = isSingleElementStruct(I.getType(), Context);
652  if (!Found)
653  return nullptr;
654  }
655  }
656 
657  // Check for single element.
658  for (const auto *FD : RD->fields()) {
659  QualType FT = FD->getType();
660 
661  // Ignore empty fields.
662  if (isEmptyField(Context, FD, true))
663  continue;
664 
665  // If we already found an element then this isn't a single-element
666  // struct.
667  if (Found)
668  return nullptr;
669 
670  // Treat single element arrays as the element.
671  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
672  if (AT->getSize().getZExtValue() != 1)
673  break;
674  FT = AT->getElementType();
675  }
676 
677  if (!isAggregateTypeForABI(FT)) {
678  Found = FT.getTypePtr();
679  } else {
680  Found = isSingleElementStruct(FT, Context);
681  if (!Found)
682  return nullptr;
683  }
684  }
685 
686  // We don't consider a struct a single-element struct if it has
687  // padding beyond the element type.
688  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
689  return nullptr;
690 
691  return Found;
692 }
693 
694 namespace {
695 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
696  const ABIArgInfo &AI) {
697  // This default implementation defers to the llvm backend's va_arg
698  // instruction. It can handle only passing arguments directly
699  // (typically only handled in the backend for primitive types), or
700  // aggregates passed indirectly by pointer (NOTE: if the "byval"
701  // flag has ABI impact in the callee, this implementation cannot
702  // work.)
703 
704  // Only a few cases are covered here at the moment -- those needed
705  // by the default abi.
706  llvm::Value *Val;
707 
708  if (AI.isIndirect()) {
709  assert(!AI.getPaddingType() &&
710  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
711  assert(
712  !AI.getIndirectRealign() &&
713  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
714 
715  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
716  CharUnits TyAlignForABI = TyInfo.Align;
717 
718  llvm::Type *ElementTy = CGF.ConvertTypeForMem(Ty);
719  llvm::Type *BaseTy = llvm::PointerType::getUnqual(ElementTy);
720  llvm::Value *Addr =
721  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
722  return Address(Addr, ElementTy, TyAlignForABI);
723  } else {
724  assert((AI.isDirect() || AI.isExtend()) &&
725  "Unexpected ArgInfo Kind in generic VAArg emitter!");
726 
727  assert(!AI.getInReg() &&
728  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
729  assert(!AI.getPaddingType() &&
730  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
731  assert(!AI.getDirectOffset() &&
732  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
733  assert(!AI.getCoerceToType() &&
734  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
735 
736  Address Temp = CGF.CreateMemTemp(Ty, "varet");
737  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(),
738  CGF.ConvertTypeForMem(Ty));
739  CGF.Builder.CreateStore(Val, Temp);
740  return Temp;
741  }
742 }
743 
744 /// DefaultABIInfo - The default implementation for ABI specific
745 /// details. This implementation provides information which results in
746 /// self-consistent and sensible LLVM IR generation, but does not
747 /// conform to any particular ABI.
748 class DefaultABIInfo : public ABIInfo {
749 public:
750  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
751 
754 
755  void computeInfo(CGFunctionInfo &FI) const override {
756  if (!getCXXABI().classifyReturnType(FI))
758  for (auto &I : FI.arguments())
759  I.info = classifyArgumentType(I.type);
760  }
761 
762  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
763  QualType Ty) const override {
764  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
765  }
766 };
767 
768 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
769 public:
770  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
771  : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {}
772 };
773 
776 
777  if (isAggregateTypeForABI(Ty)) {
778  // Records with non-trivial destructors/copy-constructors should not be
779  // passed by value.
780  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
781  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
782 
783  return getNaturalAlignIndirect(Ty);
784  }
785 
786  // Treat an enum type as its underlying type.
787  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
788  Ty = EnumTy->getDecl()->getIntegerType();
789 
790  ASTContext &Context = getContext();
791  if (const auto *EIT = Ty->getAs<BitIntType>())
792  if (EIT->getNumBits() >
793  Context.getTypeSize(Context.getTargetInfo().hasInt128Type()
794  ? Context.Int128Ty
795  : Context.LongLongTy))
796  return getNaturalAlignIndirect(Ty);
797 
798  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
800 }
801 
803  if (RetTy->isVoidType())
804  return ABIArgInfo::getIgnore();
805 
806  if (isAggregateTypeForABI(RetTy))
807  return getNaturalAlignIndirect(RetTy);
808 
809  // Treat an enum type as its underlying type.
810  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
811  RetTy = EnumTy->getDecl()->getIntegerType();
812 
813  if (const auto *EIT = RetTy->getAs<BitIntType>())
814  if (EIT->getNumBits() >
815  getContext().getTypeSize(getContext().getTargetInfo().hasInt128Type()
816  ? getContext().Int128Ty
817  : getContext().LongLongTy))
818  return getNaturalAlignIndirect(RetTy);
819 
820  return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
822 }
823 
824 //===----------------------------------------------------------------------===//
825 // WebAssembly ABI Implementation
826 //
827 // This is a very simple ABI that relies a lot on DefaultABIInfo.
828 //===----------------------------------------------------------------------===//
829 
830 class WebAssemblyABIInfo final : public ABIInfo {
831 public:
832  enum ABIKind {
833  MVP = 0,
834  ExperimentalMV = 1,
835  };
836 
837 private:
838  DefaultABIInfo defaultInfo;
839  ABIKind Kind;
840 
841 public:
842  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind)
843  : ABIInfo(CGT), defaultInfo(CGT), Kind(Kind) {}
844 
845 private:
848 
849  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
850  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
851  // overload them.
852  void computeInfo(CGFunctionInfo &FI) const override {
853  if (!getCXXABI().classifyReturnType(FI))
855  for (auto &Arg : FI.arguments())
856  Arg.info = classifyArgumentType(Arg.type);
857  }
858 
859  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
860  QualType Ty) const override;
861 };
862 
863 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
864 public:
865  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
866  WebAssemblyABIInfo::ABIKind K)
867  : TargetCodeGenInfo(std::make_unique<WebAssemblyABIInfo>(CGT, K)) {
868  SwiftInfo =
869  std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
870  }
871 
872  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
873  CodeGen::CodeGenModule &CGM) const override {
875  if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
876  if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
877  llvm::Function *Fn = cast<llvm::Function>(GV);
878  llvm::AttrBuilder B(GV->getContext());
879  B.addAttribute("wasm-import-module", Attr->getImportModule());
880  Fn->addFnAttrs(B);
881  }
882  if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
883  llvm::Function *Fn = cast<llvm::Function>(GV);
884  llvm::AttrBuilder B(GV->getContext());
885  B.addAttribute("wasm-import-name", Attr->getImportName());
886  Fn->addFnAttrs(B);
887  }
888  if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) {
889  llvm::Function *Fn = cast<llvm::Function>(GV);
890  llvm::AttrBuilder B(GV->getContext());
891  B.addAttribute("wasm-export-name", Attr->getExportName());
892  Fn->addFnAttrs(B);
893  }
894  }
895 
896  if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
897  llvm::Function *Fn = cast<llvm::Function>(GV);
898  if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
899  Fn->addFnAttr("no-prototype");
900  }
901  }
902 };
903 
904 /// Classify argument of given type \p Ty.
907 
908  if (isAggregateTypeForABI(Ty)) {
909  // Records with non-trivial destructors/copy-constructors should not be
910  // passed by value.
911  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
912  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
913  // Ignore empty structs/unions.
914  if (isEmptyRecord(getContext(), Ty, true))
915  return ABIArgInfo::getIgnore();
916  // Lower single-element structs to just pass a regular value. TODO: We
917  // could do reasonable-size multiple-element structs too, using getExpand(),
918  // though watch out for things like bitfields.
919  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
920  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
921  // For the experimental multivalue ABI, fully expand all other aggregates
922  if (Kind == ABIKind::ExperimentalMV) {
923  const RecordType *RT = Ty->getAs<RecordType>();
924  assert(RT);
925  bool HasBitField = false;
926  for (auto *Field : RT->getDecl()->fields()) {
927  if (Field->isBitField()) {
928  HasBitField = true;
929  break;
930  }
931  }
932  if (!HasBitField)
933  return ABIArgInfo::getExpand();
934  }
935  }
936 
937  // Otherwise just do the default thing.
938  return defaultInfo.classifyArgumentType(Ty);
939 }
940 
942  if (isAggregateTypeForABI(RetTy)) {
943  // Records with non-trivial destructors/copy-constructors should not be
944  // returned by value.
945  if (!getRecordArgABI(RetTy, getCXXABI())) {
946  // Ignore empty structs/unions.
947  if (isEmptyRecord(getContext(), RetTy, true))
948  return ABIArgInfo::getIgnore();
949  // Lower single-element structs to just return a regular value. TODO: We
950  // could do reasonable-size multiple-element structs too, using
951  // ABIArgInfo::getDirect().
952  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
953  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
954  // For the experimental multivalue ABI, return all other aggregates
955  if (Kind == ABIKind::ExperimentalMV)
956  return ABIArgInfo::getDirect();
957  }
958  }
959 
960  // Otherwise just do the default thing.
961  return defaultInfo.classifyReturnType(RetTy);
962 }
963 
964 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
965  QualType Ty) const {
966  bool IsIndirect = isAggregateTypeForABI(Ty) &&
967  !isEmptyRecord(getContext(), Ty, true) &&
968  !isSingleElementStruct(Ty, getContext());
969  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
970  getContext().getTypeInfoInChars(Ty),
972  /*AllowHigherAlign=*/true);
973 }
974 
975 //===----------------------------------------------------------------------===//
976 // le32/PNaCl bitcode ABI Implementation
977 //
978 // This is a simplified version of the x86_32 ABI. Arguments and return values
979 // are always passed on the stack.
980 //===----------------------------------------------------------------------===//
981 
982 class PNaClABIInfo : public ABIInfo {
983  public:
984  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
985 
988 
989  void computeInfo(CGFunctionInfo &FI) const override;
990  Address EmitVAArg(CodeGenFunction &CGF,
991  Address VAListAddr, QualType Ty) const override;
992 };
993 
994 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
995  public:
996  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
997  : TargetCodeGenInfo(std::make_unique<PNaClABIInfo>(CGT)) {}
998 };
999 
1000 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
1001  if (!getCXXABI().classifyReturnType(FI))
1003 
1004  for (auto &I : FI.arguments())
1005  I.info = classifyArgumentType(I.type);
1006 }
1007 
1008 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1009  QualType Ty) const {
1010  // The PNaCL ABI is a bit odd, in that varargs don't use normal
1011  // function classification. Structs get passed directly for varargs
1012  // functions, through a rewriting transform in
1013  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
1014  // this target to actually support a va_arg instructions with an
1015  // aggregate type, unlike other targets.
1016  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
1017 }
1018 
1019 /// Classify argument of given type \p Ty.
1021  if (isAggregateTypeForABI(Ty)) {
1022  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
1023  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
1024  return getNaturalAlignIndirect(Ty);
1025  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
1026  // Treat an enum type as its underlying type.
1027  Ty = EnumTy->getDecl()->getIntegerType();
1028  } else if (Ty->isFloatingType()) {
1029  // Floating-point types don't go inreg.
1030  return ABIArgInfo::getDirect();
1031  } else if (const auto *EIT = Ty->getAs<BitIntType>()) {
1032  // Treat bit-precise integers as integers if <= 64, otherwise pass
1033  // indirectly.
1034  if (EIT->getNumBits() > 64)
1035  return getNaturalAlignIndirect(Ty);
1036  return ABIArgInfo::getDirect();
1037  }
1038 
1039  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
1040  : ABIArgInfo::getDirect());
1041 }
1042 
1044  if (RetTy->isVoidType())
1045  return ABIArgInfo::getIgnore();
1046 
1047  // In the PNaCl ABI we always return records/structures on the stack.
1048  if (isAggregateTypeForABI(RetTy))
1049  return getNaturalAlignIndirect(RetTy);
1050 
1051  // Treat bit-precise integers as integers if <= 64, otherwise pass indirectly.
1052  if (const auto *EIT = RetTy->getAs<BitIntType>()) {
1053  if (EIT->getNumBits() > 64)
1054  return getNaturalAlignIndirect(RetTy);
1055  return ABIArgInfo::getDirect();
1056  }
1057 
1058  // Treat an enum type as its underlying type.
1059  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1060  RetTy = EnumTy->getDecl()->getIntegerType();
1061 
1062  return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
1063  : ABIArgInfo::getDirect());
1064 }
1065 
1066 /// IsX86_MMXType - Return true if this is an MMX type.
1067 bool IsX86_MMXType(llvm::Type *IRType) {
1068  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
1069  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
1070  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
1071  IRType->getScalarSizeInBits() != 64;
1072 }
1073 
1074 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1075  StringRef Constraint,
1076  llvm::Type* Ty) {
1077  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
1078  .Cases("y", "&y", "^Ym", true)
1079  .Default(false);
1080  if (IsMMXCons && Ty->isVectorTy()) {
1081  if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedSize() !=
1082  64) {
1083  // Invalid MMX constraint
1084  return nullptr;
1085  }
1086 
1087  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
1088  }
1089 
1090  // No operation needed
1091  return Ty;
1092 }
1093 
1094 /// Returns true if this type can be passed in SSE registers with the
1095 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1096 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
1097  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1098  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
1099  if (BT->getKind() == BuiltinType::LongDouble) {
1100  if (&Context.getTargetInfo().getLongDoubleFormat() ==
1101  &llvm::APFloat::x87DoubleExtended())
1102  return false;
1103  }
1104  return true;
1105  }
1106  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
1107  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
1108  // registers specially.
1109  unsigned VecSize = Context.getTypeSize(VT);
1110  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
1111  return true;
1112  }
1113  return false;
1114 }
1115 
1116 /// Returns true if this aggregate is small enough to be passed in SSE registers
1117 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1118 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
1119  return NumMembers <= 4;
1120 }
1121 
1122 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
1123 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
1124  auto AI = ABIArgInfo::getDirect(T);
1125  AI.setInReg(true);
1126  AI.setCanBeFlattened(false);
1127  return AI;
1128 }
1129 
1130 //===----------------------------------------------------------------------===//
1131 // X86-32 ABI Implementation
1132 //===----------------------------------------------------------------------===//
1133 
1134 /// Similar to llvm::CCState, but for Clang.
1135 struct CCState {
1136  CCState(CGFunctionInfo &FI)
1137  : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {}
1138 
1139  llvm::SmallBitVector IsPreassigned;
1140  unsigned CC = CallingConv::CC_C;
1141  unsigned FreeRegs = 0;
1142  unsigned FreeSSERegs = 0;
1143 };
1144 
1145 /// X86_32ABIInfo - The X86-32 ABI information.
1146 class X86_32ABIInfo : public ABIInfo {
1147  enum Class {
1148  Integer,
1149  Float
1150  };
1151 
1152  static const unsigned MinABIStackAlignInBytes = 4;
1153 
1154  bool IsDarwinVectorABI;
1155  bool IsRetSmallStructInRegABI;
1156  bool IsWin32StructABI;
1157  bool IsSoftFloatABI;
1158  bool IsMCUABI;
1159  bool IsLinuxABI;
1160  unsigned DefaultNumRegisterParameters;
1161 
1162  static bool isRegisterSize(unsigned Size) {
1163  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
1164  }
1165 
1166  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1167  // FIXME: Assumes vectorcall is in use.
1168  return isX86VectorTypeForVectorCall(getContext(), Ty);
1169  }
1170 
1171  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1172  uint64_t NumMembers) const override {
1173  // FIXME: Assumes vectorcall is in use.
1174  return isX86VectorCallAggregateSmallEnough(NumMembers);
1175  }
1176 
1177  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1178 
1179  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1180  /// such that the argument will be passed in memory.
1181  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1182 
1183  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1184 
1185  /// Return the alignment to use for the given type on the stack.
1186  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1187 
1188  Class classify(QualType Ty) const;
1189  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1190  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1191 
1192  /// Updates the number of available free registers, returns
1193  /// true if any registers were allocated.
1194  bool updateFreeRegs(QualType Ty, CCState &State) const;
1195 
1196  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1197  bool &NeedsPadding) const;
1198  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1199 
1200  bool canExpandIndirectArgument(QualType Ty) const;
1201 
1202  /// Rewrite the function info so that all memory arguments use
1203  /// inalloca.
1204  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1205 
1206  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1207  CharUnits &StackOffset, ABIArgInfo &Info,
1208  QualType Type) const;
1209  void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
1210 
1211 public:
1212 
1213  void computeInfo(CGFunctionInfo &FI) const override;
1214  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1215  QualType Ty) const override;
1216 
1217  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1218  bool RetSmallStructInRegABI, bool Win32StructABI,
1219  unsigned NumRegisterParameters, bool SoftFloatABI)
1220  : ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1221  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1222  IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI),
1223  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1224  IsLinuxABI(CGT.getTarget().getTriple().isOSLinux() ||
1225  CGT.getTarget().getTriple().isOSCygMing()),
1226  DefaultNumRegisterParameters(NumRegisterParameters) {}
1227 };
1228 
1229 class X86_32SwiftABIInfo : public SwiftABIInfo {
1230 public:
1231  explicit X86_32SwiftABIInfo(CodeGenTypes &CGT)
1232  : SwiftABIInfo(CGT, /*SwiftErrorInRegister=*/false) {}
1233 
1234  bool shouldPassIndirectly(ArrayRef<llvm::Type *> ComponentTys,
1235  bool AsReturnValue) const override {
1236  // LLVM's x86-32 lowering currently only assigns up to three
1237  // integer registers and three fp registers. Oddly, it'll use up to
1238  // four vector registers for vectors, but those can overlap with the
1239  // scalar registers.
1240  return occupiesMoreThan(CGT, ComponentTys, /*total=*/3);
1241  }
1242 };
1243 
1244 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1245 public:
1246  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1247  bool RetSmallStructInRegABI, bool Win32StructABI,
1248  unsigned NumRegisterParameters, bool SoftFloatABI)
1249  : TargetCodeGenInfo(std::make_unique<X86_32ABIInfo>(
1250  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1251  NumRegisterParameters, SoftFloatABI)) {
1252  SwiftInfo = std::make_unique<X86_32SwiftABIInfo>(CGT);
1253  }
1254 
1255  static bool isStructReturnInRegABI(
1256  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1257 
1258  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1259  CodeGen::CodeGenModule &CGM) const override;
1260 
1261  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1262  // Darwin uses different dwarf register numbers for EH.
1263  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1264  return 4;
1265  }
1266 
1267  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1268  llvm::Value *Address) const override;
1269 
1270  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1271  StringRef Constraint,
1272  llvm::Type* Ty) const override {
1273  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1274  }
1275 
1276  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1277  std::string &Constraints,
1278  std::vector<llvm::Type *> &ResultRegTypes,
1279  std::vector<llvm::Type *> &ResultTruncRegTypes,
1280  std::vector<LValue> &ResultRegDests,
1281  std::string &AsmString,
1282  unsigned NumOutputs) const override;
1283 
1284  llvm::Constant *
1285  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1286  unsigned Sig = (0xeb << 0) | // jmp rel8
1287  (0x06 << 8) | // .+0x08
1288  ('v' << 16) |
1289  ('2' << 24);
1290  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1291  }
1292 
1293  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1294  return "movl\t%ebp, %ebp"
1295  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1296  }
1297 };
1298 
1299 }
1300 
1301 /// Rewrite input constraint references after adding some output constraints.
1302 /// In the case where there is one output and one input and we add one output,
1303 /// we need to replace all operand references greater than or equal to 1:
1304 /// mov $0, $1
1305 /// mov eax, $1
1306 /// The result will be:
1307 /// mov $0, $2
1308 /// mov eax, $2
1309 static void rewriteInputConstraintReferences(unsigned FirstIn,
1310  unsigned NumNewOuts,
1311  std::string &AsmString) {
1312  std::string Buf;
1313  llvm::raw_string_ostream OS(Buf);
1314  size_t Pos = 0;
1315  while (Pos < AsmString.size()) {
1316  size_t DollarStart = AsmString.find('$', Pos);
1317  if (DollarStart == std::string::npos)
1318  DollarStart = AsmString.size();
1319  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1320  if (DollarEnd == std::string::npos)
1321  DollarEnd = AsmString.size();
1322  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1323  Pos = DollarEnd;
1324  size_t NumDollars = DollarEnd - DollarStart;
1325  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1326  // We have an operand reference.
1327  size_t DigitStart = Pos;
1328  if (AsmString[DigitStart] == '{') {
1329  OS << '{';
1330  ++DigitStart;
1331  }
1332  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1333  if (DigitEnd == std::string::npos)
1334  DigitEnd = AsmString.size();
1335  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1336  unsigned OperandIndex;
1337  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1338  if (OperandIndex >= FirstIn)
1339  OperandIndex += NumNewOuts;
1340  OS << OperandIndex;
1341  } else {
1342  OS << OperandStr;
1343  }
1344  Pos = DigitEnd;
1345  }
1346  }
1347  AsmString = std::move(OS.str());
1348 }
1349 
1350 /// Add output constraints for EAX:EDX because they are return registers.
1351 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1352  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1353  std::vector<llvm::Type *> &ResultRegTypes,
1354  std::vector<llvm::Type *> &ResultTruncRegTypes,
1355  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1356  unsigned NumOutputs) const {
1357  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1358 
1359  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1360  // larger.
1361  if (!Constraints.empty())
1362  Constraints += ',';
1363  if (RetWidth <= 32) {
1364  Constraints += "={eax}";
1365  ResultRegTypes.push_back(CGF.Int32Ty);
1366  } else {
1367  // Use the 'A' constraint for EAX:EDX.
1368  Constraints += "=A";
1369  ResultRegTypes.push_back(CGF.Int64Ty);
1370  }
1371 
1372  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1373  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1374  ResultTruncRegTypes.push_back(CoerceTy);
1375 
1376  // Coerce the integer by bitcasting the return slot pointer.
1377  ReturnSlot.setAddress(
1378  CGF.Builder.CreateElementBitCast(ReturnSlot.getAddress(CGF), CoerceTy));
1379  ResultRegDests.push_back(ReturnSlot);
1380 
1381  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1382 }
1383 
1384 /// shouldReturnTypeInRegister - Determine if the given type should be
1385 /// returned in a register (for the Darwin and MCU ABI).
1386 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1387  ASTContext &Context) const {
1388  uint64_t Size = Context.getTypeSize(Ty);
1389 
1390  // For i386, type must be register sized.
1391  // For the MCU ABI, it only needs to be <= 8-byte
1392  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1393  return false;
1394 
1395  if (Ty->isVectorType()) {
1396  // 64- and 128- bit vectors inside structures are not returned in
1397  // registers.
1398  if (Size == 64 || Size == 128)
1399  return false;
1400 
1401  return true;
1402  }
1403 
1404  // If this is a builtin, pointer, enum, complex type, member pointer, or
1405  // member function pointer it is ok.
1406  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1407  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1408  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1409  return true;
1410 
1411  // Arrays are treated like records.
1412  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1413  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1414 
1415  // Otherwise, it must be a record type.
1416  const RecordType *RT = Ty->getAs<RecordType>();
1417  if (!RT) return false;
1418 
1419  // FIXME: Traverse bases here too.
1420 
1421  // Structure types are passed in register if all fields would be
1422  // passed in a register.
1423  for (const auto *FD : RT->getDecl()->fields()) {
1424  // Empty fields are ignored.
1425  if (isEmptyField(Context, FD, true))
1426  continue;
1427 
1428  // Check fields recursively.
1429  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1430  return false;
1431  }
1432  return true;
1433 }
1434 
1435 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1436  // Treat complex types as the element type.
1437  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1438  Ty = CTy->getElementType();
1439 
1440  // Check for a type which we know has a simple scalar argument-passing
1441  // convention without any padding. (We're specifically looking for 32
1442  // and 64-bit integer and integer-equivalents, float, and double.)
1443  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1444  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1445  return false;
1446 
1447  uint64_t Size = Context.getTypeSize(Ty);
1448  return Size == 32 || Size == 64;
1449 }
1450 
1451 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1452  uint64_t &Size) {
1453  for (const auto *FD : RD->fields()) {
1454  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1455  // argument is smaller than 32-bits, expanding the struct will create
1456  // alignment padding.
1457  if (!is32Or64BitBasicType(FD->getType(), Context))
1458  return false;
1459 
1460  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1461  // how to expand them yet, and the predicate for telling if a bitfield still
1462  // counts as "basic" is more complicated than what we were doing previously.
1463  if (FD->isBitField())
1464  return false;
1465 
1466  Size += Context.getTypeSize(FD->getType());
1467  }
1468  return true;
1469 }
1470 
1471 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1472  uint64_t &Size) {
1473  // Don't do this if there are any non-empty bases.
1474  for (const CXXBaseSpecifier &Base : RD->bases()) {
1475  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1476  Size))
1477  return false;
1478  }
1479  if (!addFieldSizes(Context, RD, Size))
1480  return false;
1481  return true;
1482 }
1483 
1484 /// Test whether an argument type which is to be passed indirectly (on the
1485 /// stack) would have the equivalent layout if it was expanded into separate
1486 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1487 /// optimizations.
1488 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1489  // We can only expand structure types.
1490  const RecordType *RT = Ty->getAs<RecordType>();
1491  if (!RT)
1492  return false;
1493  const RecordDecl *RD = RT->getDecl();
1494  uint64_t Size = 0;
1495  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1496  if (!IsWin32StructABI) {
1497  // On non-Windows, we have to conservatively match our old bitcode
1498  // prototypes in order to be ABI-compatible at the bitcode level.
1499  if (!CXXRD->isCLike())
1500  return false;
1501  } else {
1502  // Don't do this for dynamic classes.
1503  if (CXXRD->isDynamicClass())
1504  return false;
1505  }
1506  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1507  return false;
1508  } else {
1509  if (!addFieldSizes(getContext(), RD, Size))
1510  return false;
1511  }
1512 
1513  // We can do this if there was no alignment padding.
1514  return Size == getContext().getTypeSize(Ty);
1515 }
1516 
1517 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1518  // If the return value is indirect, then the hidden argument is consuming one
1519  // integer register.
1520  if (State.FreeRegs) {
1521  --State.FreeRegs;
1522  if (!IsMCUABI)
1523  return getNaturalAlignIndirectInReg(RetTy);
1524  }
1525  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1526 }
1527 
1529  CCState &State) const {
1530  if (RetTy->isVoidType())
1531  return ABIArgInfo::getIgnore();
1532 
1533  const Type *Base = nullptr;
1534  uint64_t NumElts = 0;
1535  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1536  State.CC == llvm::CallingConv::X86_RegCall) &&
1537  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1538  // The LLVM struct type for such an aggregate should lower properly.
1539  return ABIArgInfo::getDirect();
1540  }
1541 
1542  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1543  // On Darwin, some vectors are returned in registers.
1544  if (IsDarwinVectorABI) {
1545  uint64_t Size = getContext().getTypeSize(RetTy);
1546 
1547  // 128-bit vectors are a special case; they are returned in
1548  // registers and we need to make sure to pick a type the LLVM
1549  // backend will like.
1550  if (Size == 128)
1551  return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
1552  llvm::Type::getInt64Ty(getVMContext()), 2));
1553 
1554  // Always return in register if it fits in a general purpose
1555  // register, or if it is 64 bits and has a single element.
1556  if ((Size == 8 || Size == 16 || Size == 32) ||
1557  (Size == 64 && VT->getNumElements() == 1))
1558  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1559  Size));
1560 
1561  return getIndirectReturnResult(RetTy, State);
1562  }
1563 
1564  return ABIArgInfo::getDirect();
1565  }
1566 
1567  if (isAggregateTypeForABI(RetTy)) {
1568  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1569  // Structures with flexible arrays are always indirect.
1570  if (RT->getDecl()->hasFlexibleArrayMember())
1571  return getIndirectReturnResult(RetTy, State);
1572  }
1573 
1574  // If specified, structs and unions are always indirect.
1575  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1576  return getIndirectReturnResult(RetTy, State);
1577 
1578  // Ignore empty structs/unions.
1579  if (isEmptyRecord(getContext(), RetTy, true))
1580  return ABIArgInfo::getIgnore();
1581 
1582  // Return complex of _Float16 as <2 x half> so the backend will use xmm0.
1583  if (const ComplexType *CT = RetTy->getAs<ComplexType>()) {
1584  QualType ET = getContext().getCanonicalType(CT->getElementType());
1585  if (ET->isFloat16Type())
1586  return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
1587  llvm::Type::getHalfTy(getVMContext()), 2));
1588  }
1589 
1590  // Small structures which are register sized are generally returned
1591  // in a register.
1592  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1593  uint64_t Size = getContext().getTypeSize(RetTy);
1594 
1595  // As a special-case, if the struct is a "single-element" struct, and
1596  // the field is of type "float" or "double", return it in a
1597  // floating-point register. (MSVC does not apply this special case.)
1598  // We apply a similar transformation for pointer types to improve the
1599  // quality of the generated IR.
1600  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1601  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1602  || SeltTy->hasPointerRepresentation())
1603  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1604 
1605  // FIXME: We should be able to narrow this integer in cases with dead
1606  // padding.
1607  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1608  }
1609 
1610  return getIndirectReturnResult(RetTy, State);
1611  }
1612 
1613  // Treat an enum type as its underlying type.
1614  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1615  RetTy = EnumTy->getDecl()->getIntegerType();
1616 
1617  if (const auto *EIT = RetTy->getAs<BitIntType>())
1618  if (EIT->getNumBits() > 64)
1619  return getIndirectReturnResult(RetTy, State);
1620 
1621  return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
1622  : ABIArgInfo::getDirect());
1623 }
1624 
1625 static bool isSIMDVectorType(ASTContext &Context, QualType Ty) {
1626  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1627 }
1628 
1630  const RecordType *RT = Ty->getAs<RecordType>();
1631  if (!RT)
1632  return false;
1633  const RecordDecl *RD = RT->getDecl();
1634 
1635  // If this is a C++ record, check the bases first.
1636  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1637  for (const auto &I : CXXRD->bases())
1638  if (!isRecordWithSIMDVectorType(Context, I.getType()))
1639  return false;
1640 
1641  for (const auto *i : RD->fields()) {
1642  QualType FT = i->getType();
1643 
1644  if (isSIMDVectorType(Context, FT))
1645  return true;
1646 
1647  if (isRecordWithSIMDVectorType(Context, FT))
1648  return true;
1649  }
1650 
1651  return false;
1652 }
1653 
1654 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1655  unsigned Align) const {
1656  // Otherwise, if the alignment is less than or equal to the minimum ABI
1657  // alignment, just use the default; the backend will handle this.
1658  if (Align <= MinABIStackAlignInBytes)
1659  return 0; // Use default alignment.
1660 
1661  if (IsLinuxABI) {
1662  // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't
1663  // want to spend any effort dealing with the ramifications of ABI breaks.
1664  //
1665  // If the vector type is __m128/__m256/__m512, return the default alignment.
1666  if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64))
1667  return Align;
1668  }
1669  // On non-Darwin, the stack type alignment is always 4.
1670  if (!IsDarwinVectorABI) {
1671  // Set explicit alignment, since we may need to realign the top.
1672  return MinABIStackAlignInBytes;
1673  }
1674 
1675  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1676  if (Align >= 16 && (isSIMDVectorType(getContext(), Ty) ||
1677  isRecordWithSIMDVectorType(getContext(), Ty)))
1678  return 16;
1679 
1680  return MinABIStackAlignInBytes;
1681 }
1682 
1683 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1684  CCState &State) const {
1685  if (!ByVal) {
1686  if (State.FreeRegs) {
1687  --State.FreeRegs; // Non-byval indirects just use one pointer.
1688  if (!IsMCUABI)
1689  return getNaturalAlignIndirectInReg(Ty);
1690  }
1691  return getNaturalAlignIndirect(Ty, false);
1692  }
1693 
1694  // Compute the byval alignment.
1695  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1696  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1697  if (StackAlign == 0)
1698  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1699 
1700  // If the stack alignment is less than the type alignment, realign the
1701  // argument.
1702  bool Realign = TypeAlign > StackAlign;
1704  /*ByVal=*/true, Realign);
1705 }
1706 
1707 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1708  const Type *T = isSingleElementStruct(Ty, getContext());
1709  if (!T)
1710  T = Ty.getTypePtr();
1711 
1712  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1713  BuiltinType::Kind K = BT->getKind();
1714  if (K == BuiltinType::Float || K == BuiltinType::Double)
1715  return Float;
1716  }
1717  return Integer;
1718 }
1719 
1720 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1721  if (!IsSoftFloatABI) {
1722  Class C = classify(Ty);
1723  if (C == Float)
1724  return false;
1725  }
1726 
1727  unsigned Size = getContext().getTypeSize(Ty);
1728  unsigned SizeInRegs = (Size + 31) / 32;
1729 
1730  if (SizeInRegs == 0)
1731  return false;
1732 
1733  if (!IsMCUABI) {
1734  if (SizeInRegs > State.FreeRegs) {
1735  State.FreeRegs = 0;
1736  return false;
1737  }
1738  } else {
1739  // The MCU psABI allows passing parameters in-reg even if there are
1740  // earlier parameters that are passed on the stack. Also,
1741  // it does not allow passing >8-byte structs in-register,
1742  // even if there are 3 free registers available.
1743  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1744  return false;
1745  }
1746 
1747  State.FreeRegs -= SizeInRegs;
1748  return true;
1749 }
1750 
1751 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1752  bool &InReg,
1753  bool &NeedsPadding) const {
1754  // On Windows, aggregates other than HFAs are never passed in registers, and
1755  // they do not consume register slots. Homogenous floating-point aggregates
1756  // (HFAs) have already been dealt with at this point.
1757  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1758  return false;
1759 
1760  NeedsPadding = false;
1761  InReg = !IsMCUABI;
1762 
1763  if (!updateFreeRegs(Ty, State))
1764  return false;
1765 
1766  if (IsMCUABI)
1767  return true;
1768 
1769  if (State.CC == llvm::CallingConv::X86_FastCall ||
1770  State.CC == llvm::CallingConv::X86_VectorCall ||
1771  State.CC == llvm::CallingConv::X86_RegCall) {
1772  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1773  NeedsPadding = true;
1774 
1775  return false;
1776  }
1777 
1778  return true;
1779 }
1780 
1781 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1782  bool IsPtrOrInt = (getContext().getTypeSize(Ty) <= 32) &&
1783  (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1784  Ty->isReferenceType());
1785 
1786  if (!IsPtrOrInt && (State.CC == llvm::CallingConv::X86_FastCall ||
1787  State.CC == llvm::CallingConv::X86_VectorCall))
1788  return false;
1789 
1790  if (!updateFreeRegs(Ty, State))
1791  return false;
1792 
1793  if (!IsPtrOrInt && State.CC == llvm::CallingConv::X86_RegCall)
1794  return false;
1795 
1796  // Return true to apply inreg to all legal parameters except for MCU targets.
1797  return !IsMCUABI;
1798 }
1799 
1800 void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
1801  // Vectorcall x86 works subtly different than in x64, so the format is
1802  // a bit different than the x64 version. First, all vector types (not HVAs)
1803  // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
1804  // This differs from the x64 implementation, where the first 6 by INDEX get
1805  // registers.
1806  // In the second pass over the arguments, HVAs are passed in the remaining
1807  // vector registers if possible, or indirectly by address. The address will be
1808  // passed in ECX/EDX if available. Any other arguments are passed according to
1809  // the usual fastcall rules.
1811  for (int I = 0, E = Args.size(); I < E; ++I) {
1812  const Type *Base = nullptr;
1813  uint64_t NumElts = 0;
1814  const QualType &Ty = Args[I].type;
1815  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1816  isHomogeneousAggregate(Ty, Base, NumElts)) {
1817  if (State.FreeSSERegs >= NumElts) {
1818  State.FreeSSERegs -= NumElts;
1819  Args[I].info = ABIArgInfo::getDirectInReg();
1820  State.IsPreassigned.set(I);
1821  }
1822  }
1823  }
1824 }
1825 
1827  CCState &State) const {
1828  // FIXME: Set alignment on indirect arguments.
1829  bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
1830  bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
1831  bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
1832 
1834  TypeInfo TI = getContext().getTypeInfo(Ty);
1835 
1836  // Check with the C++ ABI first.
1837  const RecordType *RT = Ty->getAs<RecordType>();
1838  if (RT) {
1839  CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1840  if (RAA == CGCXXABI::RAA_Indirect) {
1841  return getIndirectResult(Ty, false, State);
1842  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1843  // The field index doesn't matter, we'll fix it up later.
1844  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1845  }
1846  }
1847 
1848  // Regcall uses the concept of a homogenous vector aggregate, similar
1849  // to other targets.
1850  const Type *Base = nullptr;
1851  uint64_t NumElts = 0;
1852  if ((IsRegCall || IsVectorCall) &&
1853  isHomogeneousAggregate(Ty, Base, NumElts)) {
1854  if (State.FreeSSERegs >= NumElts) {
1855  State.FreeSSERegs -= NumElts;
1856 
1857  // Vectorcall passes HVAs directly and does not flatten them, but regcall
1858  // does.
1859  if (IsVectorCall)
1860  return getDirectX86Hva();
1861 
1862  if (Ty->isBuiltinType() || Ty->isVectorType())
1863  return ABIArgInfo::getDirect();
1864  return ABIArgInfo::getExpand();
1865  }
1866  return getIndirectResult(Ty, /*ByVal=*/false, State);
1867  }
1868 
1869  if (isAggregateTypeForABI(Ty)) {
1870  // Structures with flexible arrays are always indirect.
1871  // FIXME: This should not be byval!
1872  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1873  return getIndirectResult(Ty, true, State);
1874 
1875  // Ignore empty structs/unions on non-Windows.
1876  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1877  return ABIArgInfo::getIgnore();
1878 
1879  llvm::LLVMContext &LLVMContext = getVMContext();
1880  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1881  bool NeedsPadding = false;
1882  bool InReg;
1883  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1884  unsigned SizeInRegs = (TI.Width + 31) / 32;
1885  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1886  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1887  if (InReg)
1888  return ABIArgInfo::getDirectInReg(Result);
1889  else
1890  return ABIArgInfo::getDirect(Result);
1891  }
1892  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1893 
1894  // Pass over-aligned aggregates on Windows indirectly. This behavior was
1895  // added in MSVC 2015.
1896  if (IsWin32StructABI && TI.isAlignRequired() && TI.Align > 32)
1897  return getIndirectResult(Ty, /*ByVal=*/false, State);
1898 
1899  // Expand small (<= 128-bit) record types when we know that the stack layout
1900  // of those arguments will match the struct. This is important because the
1901  // LLVM backend isn't smart enough to remove byval, which inhibits many
1902  // optimizations.
1903  // Don't do this for the MCU if there are still free integer registers
1904  // (see X86_64 ABI for full explanation).
1905  if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) &&
1906  canExpandIndirectArgument(Ty))
1908  IsFastCall || IsVectorCall || IsRegCall, PaddingType);
1909 
1910  return getIndirectResult(Ty, true, State);
1911  }
1912 
1913  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1914  // On Windows, vectors are passed directly if registers are available, or
1915  // indirectly if not. This avoids the need to align argument memory. Pass
1916  // user-defined vector types larger than 512 bits indirectly for simplicity.
1917  if (IsWin32StructABI) {
1918  if (TI.Width <= 512 && State.FreeSSERegs > 0) {
1919  --State.FreeSSERegs;
1920  return ABIArgInfo::getDirectInReg();
1921  }
1922  return getIndirectResult(Ty, /*ByVal=*/false, State);
1923  }
1924 
1925  // On Darwin, some vectors are passed in memory, we handle this by passing
1926  // it as an i8/i16/i32/i64.
1927  if (IsDarwinVectorABI) {
1928  if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
1929  (TI.Width == 64 && VT->getNumElements() == 1))
1930  return ABIArgInfo::getDirect(
1931  llvm::IntegerType::get(getVMContext(), TI.Width));
1932  }
1933 
1934  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1935  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1936 
1937  return ABIArgInfo::getDirect();
1938  }
1939 
1940 
1941  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1942  Ty = EnumTy->getDecl()->getIntegerType();
1943 
1944  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1945 
1946  if (isPromotableIntegerTypeForABI(Ty)) {
1947  if (InReg)
1948  return ABIArgInfo::getExtendInReg(Ty);
1949  return ABIArgInfo::getExtend(Ty);
1950  }
1951 
1952  if (const auto *EIT = Ty->getAs<BitIntType>()) {
1953  if (EIT->getNumBits() <= 64) {
1954  if (InReg)
1955  return ABIArgInfo::getDirectInReg();
1956  return ABIArgInfo::getDirect();
1957  }
1958  return getIndirectResult(Ty, /*ByVal=*/false, State);
1959  }
1960 
1961  if (InReg)
1962  return ABIArgInfo::getDirectInReg();
1963  return ABIArgInfo::getDirect();
1964 }
1965 
1966 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1967  CCState State(FI);
1968  if (IsMCUABI)
1969  State.FreeRegs = 3;
1970  else if (State.CC == llvm::CallingConv::X86_FastCall) {
1971  State.FreeRegs = 2;
1972  State.FreeSSERegs = 3;
1973  } else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1974  State.FreeRegs = 2;
1975  State.FreeSSERegs = 6;
1976  } else if (FI.getHasRegParm())
1977  State.FreeRegs = FI.getRegParm();
1978  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1979  State.FreeRegs = 5;
1980  State.FreeSSERegs = 8;
1981  } else if (IsWin32StructABI) {
1982  // Since MSVC 2015, the first three SSE vectors have been passed in
1983  // registers. The rest are passed indirectly.
1984  State.FreeRegs = DefaultNumRegisterParameters;
1985  State.FreeSSERegs = 3;
1986  } else
1987  State.FreeRegs = DefaultNumRegisterParameters;
1988 
1989  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1991  } else if (FI.getReturnInfo().isIndirect()) {
1992  // The C++ ABI is not aware of register usage, so we have to check if the
1993  // return value was sret and put it in a register ourselves if appropriate.
1994  if (State.FreeRegs) {
1995  --State.FreeRegs; // The sret parameter consumes a register.
1996  if (!IsMCUABI)
1997  FI.getReturnInfo().setInReg(true);
1998  }
1999  }
2000 
2001  // The chain argument effectively gives us another free register.
2002  if (FI.isChainCall())
2003  ++State.FreeRegs;
2004 
2005  // For vectorcall, do a first pass over the arguments, assigning FP and vector
2006  // arguments to XMM registers as available.
2007  if (State.CC == llvm::CallingConv::X86_VectorCall)
2008  runVectorCallFirstPass(FI, State);
2009 
2010  bool UsedInAlloca = false;
2012  for (int I = 0, E = Args.size(); I < E; ++I) {
2013  // Skip arguments that have already been assigned.
2014  if (State.IsPreassigned.test(I))
2015  continue;
2016 
2017  Args[I].info = classifyArgumentType(Args[I].type, State);
2018  UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
2019  }
2020 
2021  // If we needed to use inalloca for any argument, do a second pass and rewrite
2022  // all the memory arguments to use inalloca.
2023  if (UsedInAlloca)
2024  rewriteWithInAlloca(FI);
2025 }
2026 
2027 void
2028 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
2029  CharUnits &StackOffset, ABIArgInfo &Info,
2030  QualType Type) const {
2031  // Arguments are always 4-byte-aligned.
2032  CharUnits WordSize = CharUnits::fromQuantity(4);
2033  assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct");
2034 
2035  // sret pointers and indirect things will require an extra pointer
2036  // indirection, unless they are byval. Most things are byval, and will not
2037  // require this indirection.
2038  bool IsIndirect = false;
2039  if (Info.isIndirect() && !Info.getIndirectByVal())
2040  IsIndirect = true;
2041  Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
2042  llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
2043  if (IsIndirect)
2044  LLTy = LLTy->getPointerTo(0);
2045  FrameFields.push_back(LLTy);
2046  StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type);
2047 
2048  // Insert padding bytes to respect alignment.
2049  CharUnits FieldEnd = StackOffset;
2050  StackOffset = FieldEnd.alignTo(WordSize);
2051  if (StackOffset != FieldEnd) {
2052  CharUnits NumBytes = StackOffset - FieldEnd;
2053  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
2054  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
2055  FrameFields.push_back(Ty);
2056  }
2057 }
2058 
2059 static bool isArgInAlloca(const ABIArgInfo &Info) {
2060  // Leave ignored and inreg arguments alone.
2061  switch (Info.getKind()) {
2062  case ABIArgInfo::InAlloca:
2063  return true;
2064  case ABIArgInfo::Ignore:
2066  return false;
2067  case ABIArgInfo::Indirect:
2068  case ABIArgInfo::Direct:
2069  case ABIArgInfo::Extend:
2070  return !Info.getInReg();
2071  case ABIArgInfo::Expand:
2073  // These are aggregate types which are never passed in registers when
2074  // inalloca is involved.
2075  return true;
2076  }
2077  llvm_unreachable("invalid enum");
2078 }
2079 
2080 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
2081  assert(IsWin32StructABI && "inalloca only supported on win32");
2082 
2083  // Build a packed struct type for all of the arguments in memory.
2084  SmallVector<llvm::Type *, 6> FrameFields;
2085 
2086  // The stack alignment is always 4.
2087  CharUnits StackAlign = CharUnits::fromQuantity(4);
2088 
2089  CharUnits StackOffset;
2090  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
2091 
2092  // Put 'this' into the struct before 'sret', if necessary.
2093  bool IsThisCall =
2094  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
2095  ABIArgInfo &Ret = FI.getReturnInfo();
2096  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
2097  isArgInAlloca(I->info)) {
2098  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
2099  ++I;
2100  }
2101 
2102  // Put the sret parameter into the inalloca struct if it's in memory.
2103  if (Ret.isIndirect() && !Ret.getInReg()) {
2104  addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
2105  // On Windows, the hidden sret parameter is always returned in eax.
2106  Ret.setInAllocaSRet(IsWin32StructABI);
2107  }
2108 
2109  // Skip the 'this' parameter in ecx.
2110  if (IsThisCall)
2111  ++I;
2112 
2113  // Put arguments passed in memory into the struct.
2114  for (; I != E; ++I) {
2115  if (isArgInAlloca(I->info))
2116  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
2117  }
2118 
2119  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
2120  /*isPacked=*/true),
2121  StackAlign);
2122 }
2123 
2124 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
2125  Address VAListAddr, QualType Ty) const {
2126 
2127  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
2128 
2129  // x86-32 changes the alignment of certain arguments on the stack.
2130  //
2131  // Just messing with TypeInfo like this works because we never pass
2132  // anything indirectly.
2134  getTypeStackAlignInBytes(Ty, TypeInfo.Align.getQuantity()));
2135 
2136  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
2138  /*AllowHigherAlign*/ true);
2139 }
2140 
2141 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
2142  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
2143  assert(Triple.getArch() == llvm::Triple::x86);
2144 
2145  switch (Opts.getStructReturnConvention()) {
2147  break;
2148  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
2149  return false;
2150  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
2151  return true;
2152  }
2153 
2154  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
2155  return true;
2156 
2157  switch (Triple.getOS()) {
2158  case llvm::Triple::DragonFly:
2159  case llvm::Triple::FreeBSD:
2160  case llvm::Triple::OpenBSD:
2161  case llvm::Triple::Win32:
2162  return true;
2163  default:
2164  return false;
2165  }
2166 }
2167 
2168 static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV,
2169  CodeGen::CodeGenModule &CGM) {
2170  if (!FD->hasAttr<AnyX86InterruptAttr>())
2171  return;
2172 
2173  llvm::Function *Fn = cast<llvm::Function>(GV);
2174  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2175  if (FD->getNumParams() == 0)
2176  return;
2177 
2178  auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
2179  llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
2180  llvm::Attribute NewAttr = llvm::Attribute::getWithByValType(
2181  Fn->getContext(), ByValTy);
2182  Fn->addParamAttr(0, NewAttr);
2183 }
2184 
2185 void X86_32TargetCodeGenInfo::setTargetAttributes(
2186  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2187  if (GV->isDeclaration())
2188  return;
2189  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2190  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2191  llvm::Function *Fn = cast<llvm::Function>(GV);
2192  Fn->addFnAttr("stackrealign");
2193  }
2194 
2195  addX86InterruptAttrs(FD, GV, CGM);
2196  }
2197 }
2198 
2199 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
2201  llvm::Value *Address) const {
2202  CodeGen::CGBuilderTy &Builder = CGF.Builder;
2203 
2204  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
2205 
2206  // 0-7 are the eight integer registers; the order is different
2207  // on Darwin (for EH), but the range is the same.
2208  // 8 is %eip.
2209  AssignToArrayRange(Builder, Address, Four8, 0, 8);
2210 
2211  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2212  // 12-16 are st(0..4). Not sure why we stop at 4.
2213  // These have size 16, which is sizeof(long double) on
2214  // platforms with 8-byte alignment for that type.
2215  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2216  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2217 
2218  } else {
2219  // 9 is %eflags, which doesn't get a size on Darwin for some
2220  // reason.
2221  Builder.CreateAlignedStore(
2222  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2223  CharUnits::One());
2224 
2225  // 11-16 are st(0..5). Not sure why we stop at 5.
2226  // These have size 12, which is sizeof(long double) on
2227  // platforms with 4-byte alignment for that type.
2228  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2229  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2230  }
2231 
2232  return false;
2233 }
2234 
2235 //===----------------------------------------------------------------------===//
2236 // X86-64 ABI Implementation
2237 //===----------------------------------------------------------------------===//
2238 
2239 
2240 namespace {
2241 /// The AVX ABI level for X86 targets.
2242 enum class X86AVXABILevel {
2243  None,
2244  AVX,
2245  AVX512
2246 };
2247 
2248 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2249 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2250  switch (AVXLevel) {
2251  case X86AVXABILevel::AVX512:
2252  return 512;
2253  case X86AVXABILevel::AVX:
2254  return 256;
2255  case X86AVXABILevel::None:
2256  return 128;
2257  }
2258  llvm_unreachable("Unknown AVXLevel");
2259 }
2260 
2261 /// X86_64ABIInfo - The X86_64 ABI information.
2262 class X86_64ABIInfo : public ABIInfo {
2263  enum Class {
2264  Integer = 0,
2265  SSE,
2266  SSEUp,
2267  X87,
2268  X87Up,
2269  ComplexX87,
2270  NoClass,
2271  Memory
2272  };
2273 
2274  /// merge - Implement the X86_64 ABI merging algorithm.
2275  ///
2276  /// Merge an accumulating classification \arg Accum with a field
2277  /// classification \arg Field.
2278  ///
2279  /// \param Accum - The accumulating classification. This should
2280  /// always be either NoClass or the result of a previous merge
2281  /// call. In addition, this should never be Memory (the caller
2282  /// should just return Memory for the aggregate).
2283  static Class merge(Class Accum, Class Field);
2284 
2285  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2286  ///
2287  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2288  /// final MEMORY or SSE classes when necessary.
2289  ///
2290  /// \param AggregateSize - The size of the current aggregate in
2291  /// the classification process.
2292  ///
2293  /// \param Lo - The classification for the parts of the type
2294  /// residing in the low word of the containing object.
2295  ///
2296  /// \param Hi - The classification for the parts of the type
2297  /// residing in the higher words of the containing object.
2298  ///
2299  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2300 
2301  /// classify - Determine the x86_64 register classes in which the
2302  /// given type T should be passed.
2303  ///
2304  /// \param Lo - The classification for the parts of the type
2305  /// residing in the low word of the containing object.
2306  ///
2307  /// \param Hi - The classification for the parts of the type
2308  /// residing in the high word of the containing object.
2309  ///
2310  /// \param OffsetBase - The bit offset of this type in the
2311  /// containing object. Some parameters are classified different
2312  /// depending on whether they straddle an eightbyte boundary.
2313  ///
2314  /// \param isNamedArg - Whether the argument in question is a "named"
2315  /// argument, as used in AMD64-ABI 3.5.7.
2316  ///
2317  /// \param IsRegCall - Whether the calling conversion is regcall.
2318  ///
2319  /// If a word is unused its result will be NoClass; if a type should
2320  /// be passed in Memory then at least the classification of \arg Lo
2321  /// will be Memory.
2322  ///
2323  /// The \arg Lo class will be NoClass iff the argument is ignored.
2324  ///
2325  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2326  /// also be ComplexX87.
2327  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2328  bool isNamedArg, bool IsRegCall = false) const;
2329 
2330  llvm::Type *GetByteVectorType(QualType Ty) const;
2331  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2332  unsigned IROffset, QualType SourceTy,
2333  unsigned SourceOffset) const;
2334  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2335  unsigned IROffset, QualType SourceTy,
2336  unsigned SourceOffset) const;
2337 
2338  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2339  /// such that the argument will be returned in memory.
2340  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2341 
2342  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2343  /// such that the argument will be passed in memory.
2344  ///
2345  /// \param freeIntRegs - The number of free integer registers remaining
2346  /// available.
2347  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2348 
2349  ABIArgInfo classifyReturnType(QualType RetTy) const;
2350 
2351  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2352  unsigned &neededInt, unsigned &neededSSE,
2353  bool isNamedArg,
2354  bool IsRegCall = false) const;
2355 
2356  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2357  unsigned &NeededSSE,
2358  unsigned &MaxVectorWidth) const;
2359 
2360  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2361  unsigned &NeededSSE,
2362  unsigned &MaxVectorWidth) const;
2363 
2364  bool IsIllegalVectorType(QualType Ty) const;
2365 
2366  /// The 0.98 ABI revision clarified a lot of ambiguities,
2367  /// unfortunately in ways that were not always consistent with
2368  /// certain previous compilers. In particular, platforms which
2369  /// required strict binary compatibility with older versions of GCC
2370  /// may need to exempt themselves.
2371  bool honorsRevision0_98() const {
2372  return !getTarget().getTriple().isOSDarwin();
2373  }
2374 
2375  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2376  /// classify it as INTEGER (for compatibility with older clang compilers).
2377  bool classifyIntegerMMXAsSSE() const {
2378  // Clang <= 3.8 did not do this.
2379  if (getContext().getLangOpts().getClangABICompat() <=
2381  return false;
2382 
2383  const llvm::Triple &Triple = getTarget().getTriple();
2384  if (Triple.isOSDarwin() || Triple.isPS())
2385  return false;
2386  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2387  return false;
2388  return true;
2389  }
2390 
2391  // GCC classifies vectors of __int128 as memory.
2392  bool passInt128VectorsInMem() const {
2393  // Clang <= 9.0 did not do this.
2394  if (getContext().getLangOpts().getClangABICompat() <=
2396  return false;
2397 
2398  const llvm::Triple &T = getTarget().getTriple();
2399  return T.isOSLinux() || T.isOSNetBSD();
2400  }
2401 
2402  X86AVXABILevel AVXLevel;
2403  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2404  // 64-bit hardware.
2405  bool Has64BitPointers;
2406 
2407 public:
2408  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2409  : ABIInfo(CGT), AVXLevel(AVXLevel),
2410  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {}
2411 
2412  bool isPassedUsingAVXType(QualType type) const {
2413  unsigned neededInt, neededSSE;
2414  // The freeIntRegs argument doesn't matter here.
2415  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2416  /*isNamedArg*/true);
2417  if (info.isDirect()) {
2418  llvm::Type *ty = info.getCoerceToType();
2419  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2420  return vectorTy->getPrimitiveSizeInBits().getFixedSize() > 128;
2421  }
2422  return false;
2423  }
2424 
2425  void computeInfo(CGFunctionInfo &FI) const override;
2426 
2427  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2428  QualType Ty) const override;
2429  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2430  QualType Ty) const override;
2431 
2432  bool has64BitPointers() const {
2433  return Has64BitPointers;
2434  }
2435 };
2436 
2437 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2438 class WinX86_64ABIInfo : public ABIInfo {
2439 public:
2440  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2441  : ABIInfo(CGT), AVXLevel(AVXLevel),
2442  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2443 
2444  void computeInfo(CGFunctionInfo &FI) const override;
2445 
2446  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2447  QualType Ty) const override;
2448 
2449  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2450  // FIXME: Assumes vectorcall is in use.
2451  return isX86VectorTypeForVectorCall(getContext(), Ty);
2452  }
2453 
2454  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2455  uint64_t NumMembers) const override {
2456  // FIXME: Assumes vectorcall is in use.
2457  return isX86VectorCallAggregateSmallEnough(NumMembers);
2458  }
2459 
2460 private:
2461  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2462  bool IsVectorCall, bool IsRegCall) const;
2463  ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
2464  const ABIArgInfo &current) const;
2465 
2466  X86AVXABILevel AVXLevel;
2467 
2468  bool IsMingw64;
2469 };
2470 
2471 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2472 public:
2473  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2474  : TargetCodeGenInfo(std::make_unique<X86_64ABIInfo>(CGT, AVXLevel)) {
2475  SwiftInfo =
2476  std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/true);
2477  }
2478 
2479  const X86_64ABIInfo &getABIInfo() const {
2480  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2481  }
2482 
2483  /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2484  /// autoreleaseRV/retainRV and autoreleaseRV/unsafeClaimRV optimizations.
2485  bool markARCOptimizedReturnCallsAsNoTail() const override { return true; }
2486 
2487  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2488  return 7;
2489  }
2490 
2491  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2492  llvm::Value *Address) const override {
2493  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2494 
2495  // 0-15 are the 16 integer registers.
2496  // 16 is %rip.
2497  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2498  return false;
2499  }
2500 
2501  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2502  StringRef Constraint,
2503  llvm::Type* Ty) const override {
2504  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2505  }
2506 
2507  bool isNoProtoCallVariadic(const CallArgList &args,
2508  const FunctionNoProtoType *fnType) const override {
2509  // The default CC on x86-64 sets %al to the number of SSA
2510  // registers used, and GCC sets this when calling an unprototyped
2511  // function, so we override the default behavior. However, don't do
2512  // that when AVX types are involved: the ABI explicitly states it is
2513  // undefined, and it doesn't work in practice because of how the ABI
2514  // defines varargs anyway.
2515  if (fnType->getCallConv() == CC_C) {
2516  bool HasAVXType = false;
2517  for (CallArgList::const_iterator
2518  it = args.begin(), ie = args.end(); it != ie; ++it) {
2519  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2520  HasAVXType = true;
2521  break;
2522  }
2523  }
2524 
2525  if (!HasAVXType)
2526  return true;
2527  }
2528 
2529  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2530  }
2531 
2532  llvm::Constant *
2533  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2534  unsigned Sig = (0xeb << 0) | // jmp rel8
2535  (0x06 << 8) | // .+0x08
2536  ('v' << 16) |
2537  ('2' << 24);
2538  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2539  }
2540 
2541  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2542  CodeGen::CodeGenModule &CGM) const override {
2543  if (GV->isDeclaration())
2544  return;
2545  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2546  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2547  llvm::Function *Fn = cast<llvm::Function>(GV);
2548  Fn->addFnAttr("stackrealign");
2549  }
2550 
2551  addX86InterruptAttrs(FD, GV, CGM);
2552  }
2553  }
2554 
2555  void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc,
2556  const FunctionDecl *Caller,
2557  const FunctionDecl *Callee,
2558  const CallArgList &Args) const override;
2559 };
2560 
2561 static void initFeatureMaps(const ASTContext &Ctx,
2562  llvm::StringMap<bool> &CallerMap,
2563  const FunctionDecl *Caller,
2564  llvm::StringMap<bool> &CalleeMap,
2565  const FunctionDecl *Callee) {
2566  if (CalleeMap.empty() && CallerMap.empty()) {
2567  // The caller is potentially nullptr in the case where the call isn't in a
2568  // function. In this case, the getFunctionFeatureMap ensures we just get
2569  // the TU level setting (since it cannot be modified by 'target'..
2570  Ctx.getFunctionFeatureMap(CallerMap, Caller);
2571  Ctx.getFunctionFeatureMap(CalleeMap, Callee);
2572  }
2573 }
2574 
2575 static bool checkAVXParamFeature(DiagnosticsEngine &Diag,
2576  SourceLocation CallLoc,
2577  const llvm::StringMap<bool> &CallerMap,
2578  const llvm::StringMap<bool> &CalleeMap,
2579  QualType Ty, StringRef Feature,
2580  bool IsArgument) {
2581  bool CallerHasFeat = CallerMap.lookup(Feature);
2582  bool CalleeHasFeat = CalleeMap.lookup(Feature);
2583  if (!CallerHasFeat && !CalleeHasFeat)
2584  return Diag.Report(CallLoc, diag::warn_avx_calling_convention)
2585  << IsArgument << Ty << Feature;
2586 
2587  // Mixing calling conventions here is very clearly an error.
2588  if (!CallerHasFeat || !CalleeHasFeat)
2589  return Diag.Report(CallLoc, diag::err_avx_calling_convention)
2590  << IsArgument << Ty << Feature;
2591 
2592  // Else, both caller and callee have the required feature, so there is no need
2593  // to diagnose.
2594  return false;
2595 }
2596 
2597 static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx,
2598  SourceLocation CallLoc,
2599  const llvm::StringMap<bool> &CallerMap,
2600  const llvm::StringMap<bool> &CalleeMap, QualType Ty,
2601  bool IsArgument) {
2602  uint64_t Size = Ctx.getTypeSize(Ty);
2603  if (Size > 256)
2604  return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty,
2605  "avx512f", IsArgument);
2606 
2607  if (Size > 128)
2608  return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx",
2609  IsArgument);
2610 
2611  return false;
2612 }
2613 
2614 void X86_64TargetCodeGenInfo::checkFunctionCallABI(
2615  CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
2616  const FunctionDecl *Callee, const CallArgList &Args) const {
2617  llvm::StringMap<bool> CallerMap;
2618  llvm::StringMap<bool> CalleeMap;
2619  unsigned ArgIndex = 0;
2620 
2621  // We need to loop through the actual call arguments rather than the
2622  // function's parameters, in case this variadic.
2623  for (const CallArg &Arg : Args) {
2624  // The "avx" feature changes how vectors >128 in size are passed. "avx512f"
2625  // additionally changes how vectors >256 in size are passed. Like GCC, we
2626  // warn when a function is called with an argument where this will change.
2627  // Unlike GCC, we also error when it is an obvious ABI mismatch, that is,
2628  // the caller and callee features are mismatched.
2629  // Unfortunately, we cannot do this diagnostic in SEMA, since the callee can
2630  // change its ABI with attribute-target after this call.
2631  if (Arg.getType()->isVectorType() &&
2632  CGM.getContext().getTypeSize(Arg.getType()) > 128) {
2633  initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
2634  QualType Ty = Arg.getType();
2635  // The CallArg seems to have desugared the type already, so for clearer
2636  // diagnostics, replace it with the type in the FunctionDecl if possible.
2637  if (ArgIndex < Callee->getNumParams())
2638  Ty = Callee->getParamDecl(ArgIndex)->getType();
2639 
2640  if (checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
2641  CalleeMap, Ty, /*IsArgument*/ true))
2642  return;
2643  }
2644  ++ArgIndex;
2645  }
2646 
2647  // Check return always, as we don't have a good way of knowing in codegen
2648  // whether this value is used, tail-called, etc.
2649  if (Callee->getReturnType()->isVectorType() &&
2650  CGM.getContext().getTypeSize(Callee->getReturnType()) > 128) {
2651  initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
2652  checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
2653  CalleeMap, Callee->getReturnType(),
2654  /*IsArgument*/ false);
2655  }
2656 }
2657 
2658 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2659  // If the argument does not end in .lib, automatically add the suffix.
2660  // If the argument contains a space, enclose it in quotes.
2661  // This matches the behavior of MSVC.
2662  bool Quote = Lib.contains(' ');
2663  std::string ArgStr = Quote ? "\"" : "";
2664  ArgStr += Lib;
2665  if (!Lib.endswith_insensitive(".lib") && !Lib.endswith_insensitive(".a"))
2666  ArgStr += ".lib";
2667  ArgStr += Quote ? "\"" : "";
2668  return ArgStr;
2669 }
2670 
2671 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2672 public:
2673  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2674  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2675  unsigned NumRegisterParameters)
2676  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2677  Win32StructABI, NumRegisterParameters, false) {}
2678 
2679  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2680  CodeGen::CodeGenModule &CGM) const override;
2681 
2682  void getDependentLibraryOption(llvm::StringRef Lib,
2683  llvm::SmallString<24> &Opt) const override {
2684  Opt = "/DEFAULTLIB:";
2685  Opt += qualifyWindowsLibrary(Lib);
2686  }
2687 
2688  void getDetectMismatchOption(llvm::StringRef Name,
2689  llvm::StringRef Value,
2690  llvm::SmallString<32> &Opt) const override {
2691  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2692  }
2693 };
2694 
2695 static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2696  CodeGen::CodeGenModule &CGM) {
2697  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2698 
2699  if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2700  Fn->addFnAttr("stack-probe-size",
2701  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2702  if (CGM.getCodeGenOpts().NoStackArgProbe)
2703  Fn->addFnAttr("no-stack-arg-probe");
2704  }
2705 }
2706 
2707 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2708  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2709  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2710  if (GV->isDeclaration())
2711  return;
2712  addStackProbeTargetAttributes(D, GV, CGM);
2713 }
2714 
2715 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2716 public:
2717  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2718  X86AVXABILevel AVXLevel)
2719  : TargetCodeGenInfo(std::make_unique<WinX86_64ABIInfo>(CGT, AVXLevel)) {
2720  SwiftInfo =
2721  std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/true);
2722  }
2723 
2724  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2725  CodeGen::CodeGenModule &CGM) const override;
2726 
2727  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2728  return 7;
2729  }
2730 
2731  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2732  llvm::Value *Address) const override {
2733  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2734 
2735  // 0-15 are the 16 integer registers.
2736  // 16 is %rip.
2737  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2738  return false;
2739  }
2740 
2741  void getDependentLibraryOption(llvm::StringRef Lib,
2742  llvm::SmallString<24> &Opt) const override {
2743  Opt = "/DEFAULTLIB:";
2744  Opt += qualifyWindowsLibrary(Lib);
2745  }
2746 
2747  void getDetectMismatchOption(llvm::StringRef Name,
2748  llvm::StringRef Value,
2749  llvm::SmallString<32> &Opt) const override {
2750  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2751  }
2752 };
2753 
2754 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2755  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2757  if (GV->isDeclaration())
2758  return;
2759  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2760  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2761  llvm::Function *Fn = cast<llvm::Function>(GV);
2762  Fn->addFnAttr("stackrealign");
2763  }
2764 
2765  addX86InterruptAttrs(FD, GV, CGM);
2766  }
2767 
2768  addStackProbeTargetAttributes(D, GV, CGM);
2769 }
2770 }
2771 
2772 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2773  Class &Hi) const {
2774  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2775  //
2776  // (a) If one of the classes is Memory, the whole argument is passed in
2777  // memory.
2778  //
2779  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2780  // memory.
2781  //
2782  // (c) If the size of the aggregate exceeds two eightbytes and the first
2783  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2784  // argument is passed in memory. NOTE: This is necessary to keep the
2785  // ABI working for processors that don't support the __m256 type.
2786  //
2787  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2788  //
2789  // Some of these are enforced by the merging logic. Others can arise
2790  // only with unions; for example:
2791  // union { _Complex double; unsigned; }
2792  //
2793  // Note that clauses (b) and (c) were added in 0.98.
2794  //
2795  if (Hi == Memory)
2796  Lo = Memory;
2797  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2798  Lo = Memory;
2799  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2800  Lo = Memory;
2801  if (Hi == SSEUp && Lo != SSE)
2802  Hi = SSE;
2803 }
2804 
2805 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2806  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2807  // classified recursively so that always two fields are
2808  // considered. The resulting class is calculated according to
2809  // the classes of the fields in the eightbyte:
2810  //
2811  // (a) If both classes are equal, this is the resulting class.
2812  //
2813  // (b) If one of the classes is NO_CLASS, the resulting class is
2814  // the other class.
2815  //
2816  // (c) If one of the classes is MEMORY, the result is the MEMORY
2817  // class.
2818  //
2819  // (d) If one of the classes is INTEGER, the result is the
2820  // INTEGER.
2821  //
2822  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2823  // MEMORY is used as class.
2824  //
2825  // (f) Otherwise class SSE is used.
2826 
2827  // Accum should never be memory (we should have returned) or
2828  // ComplexX87 (because this cannot be passed in a structure).
2829  assert((Accum != Memory && Accum != ComplexX87) &&
2830  "Invalid accumulated classification during merge.");
2831  if (Accum == Field || Field == NoClass)
2832  return Accum;
2833  if (Field == Memory)
2834  return Memory;
2835  if (Accum == NoClass)
2836  return Field;
2837  if (Accum == Integer || Field == Integer)
2838  return Integer;
2839  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2840  Accum == X87 || Accum == X87Up)
2841  return Memory;
2842  return SSE;
2843 }
2844 
2845 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, Class &Lo,
2846  Class &Hi, bool isNamedArg, bool IsRegCall) const {
2847  // FIXME: This code can be simplified by introducing a simple value class for
2848  // Class pairs with appropriate constructor methods for the various
2849  // situations.
2850 
2851  // FIXME: Some of the split computations are wrong; unaligned vectors
2852  // shouldn't be passed in registers for example, so there is no chance they
2853  // can straddle an eightbyte. Verify & simplify.
2854 
2855  Lo = Hi = NoClass;
2856 
2857  Class &Current = OffsetBase < 64 ? Lo : Hi;
2858  Current = Memory;
2859 
2860  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2861  BuiltinType::Kind k = BT->getKind();
2862 
2863  if (k == BuiltinType::Void) {
2864  Current = NoClass;
2865  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2866  Lo = Integer;
2867  Hi = Integer;
2868  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2869  Current = Integer;
2870  } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
2871  k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
2872  Current = SSE;
2873  } else if (k == BuiltinType::LongDouble) {
2874  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2875  if (LDF == &llvm::APFloat::IEEEquad()) {
2876  Lo = SSE;
2877  Hi = SSEUp;
2878  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2879  Lo = X87;
2880  Hi = X87Up;
2881  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2882  Current = SSE;
2883  } else
2884  llvm_unreachable("unexpected long double representation!");
2885  }
2886  // FIXME: _Decimal32 and _Decimal64 are SSE.
2887  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2888  return;
2889  }
2890 
2891  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2892  // Classify the underlying integer type.
2893  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2894  return;
2895  }
2896 
2897  if (Ty->hasPointerRepresentation()) {
2898  Current = Integer;
2899  return;
2900  }
2901 
2902  if (Ty->isMemberPointerType()) {
2903  if (Ty->isMemberFunctionPointerType()) {
2904  if (Has64BitPointers) {
2905  // If Has64BitPointers, this is an {i64, i64}, so classify both
2906  // Lo and Hi now.
2907  Lo = Hi = Integer;
2908  } else {
2909  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2910  // straddles an eightbyte boundary, Hi should be classified as well.
2911  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2912  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2913  if (EB_FuncPtr != EB_ThisAdj) {
2914  Lo = Hi = Integer;
2915  } else {
2916  Current = Integer;
2917  }
2918  }
2919  } else {
2920  Current = Integer;
2921  }
2922  return;
2923  }
2924 
2925  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2926  uint64_t Size = getContext().getTypeSize(VT);
2927  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2928  // gcc passes the following as integer:
2929  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2930  // 2 bytes - <2 x char>, <1 x short>
2931  // 1 byte - <1 x char>
2932  Current = Integer;
2933 
2934  // If this type crosses an eightbyte boundary, it should be
2935  // split.
2936  uint64_t EB_Lo = (OffsetBase) / 64;
2937  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2938  if (EB_Lo != EB_Hi)
2939  Hi = Lo;
2940  } else if (Size == 64) {
2941  QualType ElementType = VT->getElementType();
2942 
2943  // gcc passes <1 x double> in memory. :(
2944  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2945  return;
2946 
2947  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2948  // pass them as integer. For platforms where clang is the de facto
2949  // platform compiler, we must continue to use integer.
2950  if (!classifyIntegerMMXAsSSE() &&
2951  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2952  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2953  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2954  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2955  Current = Integer;
2956  else
2957  Current = SSE;
2958 
2959  // If this type crosses an eightbyte boundary, it should be
2960  // split.
2961  if (OffsetBase && OffsetBase != 64)
2962  Hi = Lo;
2963  } else if (Size == 128 ||
2964  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2965  QualType ElementType = VT->getElementType();
2966 
2967  // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :(
2968  if (passInt128VectorsInMem() && Size != 128 &&
2969  (ElementType->isSpecificBuiltinType(BuiltinType::Int128) ||
2970  ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
2971  return;
2972 
2973  // Arguments of 256-bits are split into four eightbyte chunks. The
2974  // least significant one belongs to class SSE and all the others to class
2975  // SSEUP. The original Lo and Hi design considers that types can't be
2976  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2977  // This design isn't correct for 256-bits, but since there're no cases
2978  // where the upper parts would need to be inspected, avoid adding
2979  // complexity and just consider Hi to match the 64-256 part.
2980  //
2981  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2982  // registers if they are "named", i.e. not part of the "..." of a
2983  // variadic function.
2984  //
2985  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2986  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2987  Lo = SSE;
2988  Hi = SSEUp;
2989  }
2990  return;
2991  }
2992 
2993  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2994  QualType ET = getContext().getCanonicalType(CT->getElementType());
2995 
2996  uint64_t Size = getContext().getTypeSize(Ty);
2997  if (ET->isIntegralOrEnumerationType()) {
2998  if (Size <= 64)
2999  Current = Integer;
3000  else if (Size <= 128)
3001  Lo = Hi = Integer;
3002  } else if (ET->isFloat16Type() || ET == getContext().FloatTy ||
3003  ET->isBFloat16Type()) {
3004  Current = SSE;
3005  } else if (ET == getContext().DoubleTy) {
3006  Lo = Hi = SSE;
3007  } else if (ET == getContext().LongDoubleTy) {
3008  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3009  if (LDF == &llvm::APFloat::IEEEquad())
3010  Current = Memory;
3011  else if (LDF == &llvm::APFloat::x87DoubleExtended())
3012  Current = ComplexX87;
3013  else if (LDF == &llvm::APFloat::IEEEdouble())
3014  Lo = Hi = SSE;
3015  else
3016  llvm_unreachable("unexpected long double representation!");
3017  }
3018 
3019  // If this complex type crosses an eightbyte boundary then it
3020  // should be split.
3021  uint64_t EB_Real = (OffsetBase) / 64;
3022  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
3023  if (Hi == NoClass && EB_Real != EB_Imag)
3024  Hi = Lo;
3025 
3026  return;
3027  }
3028 
3029  if (const auto *EITy = Ty->getAs<BitIntType>()) {
3030  if (EITy->getNumBits() <= 64)
3031  Current = Integer;
3032  else if (EITy->getNumBits() <= 128)
3033  Lo = Hi = Integer;
3034  // Larger values need to get passed in memory.
3035  return;
3036  }
3037 
3038  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
3039  // Arrays are treated like structures.
3040 
3041  uint64_t Size = getContext().getTypeSize(Ty);
3042 
3043  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
3044  // than eight eightbytes, ..., it has class MEMORY.
3045  // regcall ABI doesn't have limitation to an object. The only limitation
3046  // is the free registers, which will be checked in computeInfo.
3047  if (!IsRegCall && Size > 512)
3048  return;
3049 
3050  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
3051  // fields, it has class MEMORY.
3052  //
3053  // Only need to check alignment of array base.
3054  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
3055  return;
3056 
3057  // Otherwise implement simplified merge. We could be smarter about
3058  // this, but it isn't worth it and would be harder to verify.
3059  Current = NoClass;
3060  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
3061  uint64_t ArraySize = AT->getSize().getZExtValue();
3062 
3063  // The only case a 256-bit wide vector could be used is when the array
3064  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
3065  // to work for sizes wider than 128, early check and fallback to memory.
3066  //
3067  if (Size > 128 &&
3068  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
3069  return;
3070 
3071  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
3072  Class FieldLo, FieldHi;
3073  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
3074  Lo = merge(Lo, FieldLo);
3075  Hi = merge(Hi, FieldHi);
3076  if (Lo == Memory || Hi == Memory)
3077  break;
3078  }
3079 
3080  postMerge(Size, Lo, Hi);
3081  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
3082  return;
3083  }
3084 
3085  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3086  uint64_t Size = getContext().getTypeSize(Ty);
3087 
3088  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
3089  // than eight eightbytes, ..., it has class MEMORY.
3090  if (Size > 512)
3091  return;
3092 
3093  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
3094  // copy constructor or a non-trivial destructor, it is passed by invisible
3095  // reference.
3096  if (getRecordArgABI(RT, getCXXABI()))
3097  return;
3098 
3099  const RecordDecl *RD = RT->getDecl();
3100 
3101  // Assume variable sized types are passed in memory.
3102  if (RD->hasFlexibleArrayMember())
3103  return;
3104 
3105  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
3106 
3107  // Reset Lo class, this will be recomputed.
3108  Current = NoClass;
3109 
3110  // If this is a C++ record, classify the bases first.
3111  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3112  for (const auto &I : CXXRD->bases()) {
3113  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3114  "Unexpected base class!");
3115  const auto *Base =
3116  cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
3117 
3118  // Classify this field.
3119  //
3120  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
3121  // single eightbyte, each is classified separately. Each eightbyte gets
3122  // initialized to class NO_CLASS.
3123  Class FieldLo, FieldHi;
3124  uint64_t Offset =
3125  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
3126  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
3127  Lo = merge(Lo, FieldLo);
3128  Hi = merge(Hi, FieldHi);
3129  if (Lo == Memory || Hi == Memory) {
3130  postMerge(Size, Lo, Hi);
3131  return;
3132  }
3133  }
3134  }
3135 
3136  // Classify the fields one at a time, merging the results.
3137  unsigned idx = 0;
3138  bool UseClang11Compat = getContext().getLangOpts().getClangABICompat() <=
3140  getContext().getTargetInfo().getTriple().isPS();
3141  bool IsUnion = RT->isUnionType() && !UseClang11Compat;
3142 
3143  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3144  i != e; ++i, ++idx) {
3145  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
3146  bool BitField = i->isBitField();
3147 
3148  // Ignore padding bit-fields.
3149  if (BitField && i->isUnnamedBitfield())
3150  continue;
3151 
3152  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
3153  // eight eightbytes, or it contains unaligned fields, it has class MEMORY.
3154  //
3155  // The only case a 256-bit or a 512-bit wide vector could be used is when
3156  // the struct contains a single 256-bit or 512-bit element. Early check
3157  // and fallback to memory.
3158  //
3159  // FIXME: Extended the Lo and Hi logic properly to work for size wider
3160  // than 128.
3161  if (Size > 128 &&
3162  ((!IsUnion && Size != getContext().getTypeSize(i->getType())) ||
3163  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
3164  Lo = Memory;
3165  postMerge(Size, Lo, Hi);
3166  return;
3167  }
3168  // Note, skip this test for bit-fields, see below.
3169  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
3170  Lo = Memory;
3171  postMerge(Size, Lo, Hi);
3172  return;
3173  }
3174 
3175  // Classify this field.
3176  //
3177  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
3178  // exceeds a single eightbyte, each is classified
3179  // separately. Each eightbyte gets initialized to class
3180  // NO_CLASS.
3181  Class FieldLo, FieldHi;
3182 
3183  // Bit-fields require special handling, they do not force the
3184  // structure to be passed in memory even if unaligned, and
3185  // therefore they can straddle an eightbyte.
3186  if (BitField) {
3187  assert(!i->isUnnamedBitfield());
3188  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
3189  uint64_t Size = i->getBitWidthValue(getContext());
3190 
3191  uint64_t EB_Lo = Offset / 64;
3192  uint64_t EB_Hi = (Offset + Size - 1) / 64;
3193 
3194  if (EB_Lo) {
3195  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
3196  FieldLo = NoClass;
3197  FieldHi = Integer;
3198  } else {
3199  FieldLo = Integer;
3200  FieldHi = EB_Hi ? Integer : NoClass;
3201  }
3202  } else
3203  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
3204  Lo = merge(Lo, FieldLo);
3205  Hi = merge(Hi, FieldHi);
3206  if (Lo == Memory || Hi == Memory)
3207  break;
3208  }
3209 
3210  postMerge(Size, Lo, Hi);
3211  }
3212 }
3213 
3214 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
3215  // If this is a scalar LLVM value then assume LLVM will pass it in the right
3216  // place naturally.
3217  if (!isAggregateTypeForABI(Ty)) {
3218  // Treat an enum type as its underlying type.
3219  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3220  Ty = EnumTy->getDecl()->getIntegerType();
3221 
3222  if (Ty->isBitIntType())
3223  return getNaturalAlignIndirect(Ty);
3224 
3225  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
3226  : ABIArgInfo::getDirect());
3227  }
3228 
3229  return getNaturalAlignIndirect(Ty);
3230 }
3231 
3232 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
3233  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
3234  uint64_t Size = getContext().getTypeSize(VecTy);
3235  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
3236  if (Size <= 64 || Size > LargestVector)
3237  return true;
3238  QualType EltTy = VecTy->getElementType();
3239  if (passInt128VectorsInMem() &&
3240  (EltTy->isSpecificBuiltinType(BuiltinType::Int128) ||
3241  EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
3242  return true;
3243  }
3244 
3245  return false;
3246 }
3247 
3248 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
3249  unsigned freeIntRegs) const {
3250  // If this is a scalar LLVM value then assume LLVM will pass it in the right
3251  // place naturally.
3252  //
3253  // This assumption is optimistic, as there could be free registers available
3254  // when we need to pass this argument in memory, and LLVM could try to pass
3255  // the argument in the free register. This does not seem to happen currently,
3256  // but this code would be much safer if we could mark the argument with
3257  // 'onstack'. See PR12193.
3258  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty) &&
3259  !Ty->isBitIntType()) {
3260  // Treat an enum type as its underlying type.
3261  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3262  Ty = EnumTy->getDecl()->getIntegerType();
3263 
3264  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
3265  : ABIArgInfo::getDirect());
3266  }
3267 
3268  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
3269  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3270 
3271  // Compute the byval alignment. We specify the alignment of the byval in all
3272  // cases so that the mid-level optimizer knows the alignment of the byval.
3273  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
3274 
3275  // Attempt to avoid passing indirect results using byval when possible. This
3276  // is important for good codegen.
3277  //
3278  // We do this by coercing the value into a scalar type which the backend can
3279  // handle naturally (i.e., without using byval).
3280  //
3281  // For simplicity, we currently only do this when we have exhausted all of the
3282  // free integer registers. Doing this when there are free integer registers
3283  // would require more care, as we would have to ensure that the coerced value
3284  // did not claim the unused register. That would require either reording the
3285  // arguments to the function (so that any subsequent inreg values came first),
3286  // or only doing this optimization when there were no following arguments that
3287  // might be inreg.
3288  //
3289  // We currently expect it to be rare (particularly in well written code) for
3290  // arguments to be passed on the stack when there are still free integer
3291  // registers available (this would typically imply large structs being passed
3292  // by value), so this seems like a fair tradeoff for now.
3293  //
3294  // We can revisit this if the backend grows support for 'onstack' parameter
3295  // attributes. See PR12193.
3296  if (freeIntRegs == 0) {
3297  uint64_t Size = getContext().getTypeSize(Ty);
3298 
3299  // If this type fits in an eightbyte, coerce it into the matching integral
3300  // type, which will end up on the stack (with alignment 8).
3301  if (Align == 8 && Size <= 64)
3302  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
3303  Size));
3304  }
3305 
3307 }
3308 
3309 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
3310 /// register. Pick an LLVM IR type that will be passed as a vector register.
3311 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
3312  // Wrapper structs/arrays that only contain vectors are passed just like
3313  // vectors; strip them off if present.
3314  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
3315  Ty = QualType(InnerTy, 0);
3316 
3317  llvm::Type *IRType = CGT.ConvertType(Ty);
3318  if (isa<llvm::VectorType>(IRType)) {
3319  // Don't pass vXi128 vectors in their native type, the backend can't
3320  // legalize them.
3321  if (passInt128VectorsInMem() &&
3322  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy(128)) {
3323  // Use a vXi64 vector.
3324  uint64_t Size = getContext().getTypeSize(Ty);
3325  return llvm::FixedVectorType::get(llvm::Type::getInt64Ty(getVMContext()),
3326  Size / 64);
3327  }
3328 
3329  return IRType;
3330  }
3331 
3332  if (IRType->getTypeID() == llvm::Type::FP128TyID)
3333  return IRType;
3334 
3335  // We couldn't find the preferred IR vector type for 'Ty'.
3336  uint64_t Size = getContext().getTypeSize(Ty);
3337  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
3338 
3339 
3340  // Return a LLVM IR vector type based on the size of 'Ty'.
3341  return llvm::FixedVectorType::get(llvm::Type::getDoubleTy(getVMContext()),
3342  Size / 64);
3343 }
3344 
3345 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
3346 /// is known to either be off the end of the specified type or being in
3347 /// alignment padding. The user type specified is known to be at most 128 bits
3348 /// in size, and have passed through X86_64ABIInfo::classify with a successful
3349 /// classification that put one of the two halves in the INTEGER class.
3350 ///
3351 /// It is conservatively correct to return false.
3352 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
3353  unsigned EndBit, ASTContext &Context) {
3354  // If the bytes being queried are off the end of the type, there is no user
3355  // data hiding here. This handles analysis of builtins, vectors and other
3356  // types that don't contain interesting padding.
3357  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3358  if (TySize <= StartBit)
3359  return true;
3360 
3361  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3362  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3363  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3364 
3365  // Check each element to see if the element overlaps with the queried range.
3366  for (unsigned i = 0; i != NumElts; ++i) {
3367  // If the element is after the span we care about, then we're done..
3368  unsigned EltOffset = i*EltSize;
3369  if (EltOffset >= EndBit) break;
3370 
3371  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
3372  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3373  EndBit-EltOffset, Context))
3374  return false;
3375  }
3376  // If it overlaps no elements, then it is safe to process as padding.
3377  return true;
3378  }
3379 
3380  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3381  const RecordDecl *RD = RT->getDecl();
3382  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3383 
3384  // If this is a C++ record, check the bases first.
3385  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3386  for (const auto &I : CXXRD->bases()) {
3387  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3388  "Unexpected base class!");
3389  const auto *Base =
3390  cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
3391 
3392  // If the base is after the span we care about, ignore it.
3393  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3394  if (BaseOffset >= EndBit) continue;
3395 
3396  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3397  if (!BitsContainNoUserData(I.getType(), BaseStart,
3398  EndBit-BaseOffset, Context))
3399  return false;
3400  }
3401  }
3402 
3403  // Verify that no field has data that overlaps the region of interest. Yes
3404  // this could be sped up a lot by being smarter about queried fields,
3405  // however we're only looking at structs up to 16 bytes, so we don't care
3406  // much.
3407  unsigned idx = 0;
3408  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3409  i != e; ++i, ++idx) {
3410  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3411 
3412  // If we found a field after the region we care about, then we're done.
3413  if (FieldOffset >= EndBit) break;
3414 
3415  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3416  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3417  Context))
3418  return false;
3419  }
3420 
3421  // If nothing in this record overlapped the area of interest, then we're
3422  // clean.
3423  return true;
3424  }
3425 
3426  return false;
3427 }
3428 
3429 /// getFPTypeAtOffset - Return a floating point type at the specified offset.
3430 static llvm::Type *getFPTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3431  const llvm::DataLayout &TD) {
3432  if (IROffset == 0 && IRType->isFloatingPointTy())
3433  return IRType;
3434 
3435  // If this is a struct, recurse into the field at the specified offset.
3436  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3437  if (!STy->getNumContainedTypes())
3438  return nullptr;
3439 
3440  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3441  unsigned Elt = SL->getElementContainingOffset(IROffset);
3442  IROffset -= SL->getElementOffset(Elt);
3443  return getFPTypeAtOffset(STy->getElementType(Elt), IROffset, TD);
3444  }
3445 
3446  // If this is an array, recurse into the field at the specified offset.
3447  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3448  llvm::Type *EltTy = ATy->getElementType();
3449  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3450  IROffset -= IROffset / EltSize * EltSize;
3451  return getFPTypeAtOffset(EltTy, IROffset, TD);
3452  }
3453 
3454  return nullptr;
3455 }
3456 
3457 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3458 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3459 llvm::Type *X86_64ABIInfo::
3460 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3461  QualType SourceTy, unsigned SourceOffset) const {
3462  const llvm::DataLayout &TD = getDataLayout();
3463  unsigned SourceSize =
3464  (unsigned)getContext().getTypeSize(SourceTy) / 8 - SourceOffset;
3465  llvm::Type *T0 = getFPTypeAtOffset(IRType, IROffset, TD);
3466  if (!T0 || T0->isDoubleTy())
3467  return llvm::Type::getDoubleTy(getVMContext());
3468 
3469  // Get the adjacent FP type.
3470  llvm::Type *T1 = nullptr;
3471  unsigned T0Size = TD.getTypeAllocSize(T0);
3472  if (SourceSize > T0Size)
3473  T1 = getFPTypeAtOffset(IRType, IROffset + T0Size, TD);
3474  if (T1 == nullptr) {
3475  // Check if IRType is a half/bfloat + float. float type will be in IROffset+4 due
3476  // to its alignment.
3477  if (T0->is16bitFPTy() && SourceSize > 4)
3478  T1 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
3479  // If we can't get a second FP type, return a simple half or float.
3480  // avx512fp16-abi.c:pr51813_2 shows it works to return float for
3481  // {float, i8} too.
3482  if (T1 == nullptr)
3483  return T0;
3484  }
3485 
3486  if (T0->isFloatTy() && T1->isFloatTy())
3487  return llvm::FixedVectorType::get(T0, 2);
3488 
3489  if (T0->is16bitFPTy() && T1->is16bitFPTy()) {
3490  llvm::Type *T2 = nullptr;
3491  if (SourceSize > 4)
3492  T2 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
3493  if (T2 == nullptr)
3494  return llvm::FixedVectorType::get(T0, 2);
3495  return llvm::FixedVectorType::get(T0, 4);
3496  }
3497 
3498  if (T0->is16bitFPTy() || T1->is16bitFPTy())
3499  return llvm::FixedVectorType::get(llvm::Type::getHalfTy(getVMContext()), 4);
3500 
3501  return llvm::Type::getDoubleTy(getVMContext());
3502 }
3503 
3504 
3505 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3506 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3507 /// about the high or low part of an up-to-16-byte struct. This routine picks
3508 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3509 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3510 /// etc).
3511 ///
3512 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3513 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3514 /// the 8-byte value references. PrefType may be null.
3515 ///
3516 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3517 /// an offset into this that we're processing (which is always either 0 or 8).
3518 ///
3519 llvm::Type *X86_64ABIInfo::
3520 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3521  QualType SourceTy, unsigned SourceOffset) const {
3522  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3523  // returning an 8-byte unit starting with it. See if we can safely use it.
3524  if (IROffset == 0) {
3525  // Pointers and int64's always fill the 8-byte unit.
3526  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3527  IRType->isIntegerTy(64))
3528  return IRType;
3529 
3530  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3531  // goodness in the source type is just tail padding. This is allowed to
3532  // kick in for struct {double,int} on the int, but not on
3533  // struct{double,int,int} because we wouldn't return the second int. We
3534  // have to do this analysis on the source type because we can't depend on
3535  // unions being lowered a specific way etc.
3536  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3537  IRType->isIntegerTy(32) ||
3538  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3539  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3540  cast<llvm::IntegerType>(IRType)->getBitWidth();
3541 
3542  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3543  SourceOffset*8+64, getContext()))
3544  return IRType;
3545  }
3546  }
3547 
3548  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3549  // If this is a struct, recurse into the field at the specified offset.
3550  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3551  if (IROffset < SL->getSizeInBytes()) {
3552  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3553  IROffset -= SL->getElementOffset(FieldIdx);
3554 
3555  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3556  SourceTy, SourceOffset);
3557  }
3558  }
3559 
3560  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3561  llvm::Type *EltTy = ATy->getElementType();
3562  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3563  unsigned EltOffset = IROffset/EltSize*EltSize;
3564  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3565  SourceOffset);
3566  }
3567 
3568  // Okay, we don't have any better idea of what to pass, so we pass this in an
3569  // integer register that isn't too big to fit the rest of the struct.
3570  unsigned TySizeInBytes =
3571  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3572 
3573  assert(TySizeInBytes != SourceOffset && "Empty field?");
3574 
3575  // It is always safe to classify this as an integer type up to i64 that
3576  // isn't larger than the structure.
3577  return llvm::IntegerType::get(getVMContext(),
3578  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3579 }
3580 
3581 
3582 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3583 /// be used as elements of a two register pair to pass or return, return a
3584 /// first class aggregate to represent them. For example, if the low part of
3585 /// a by-value argument should be passed as i32* and the high part as float,
3586 /// return {i32*, float}.
3587 static llvm::Type *
3588 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3589  const llvm::DataLayout &TD) {
3590  // In order to correctly satisfy the ABI, we need to the high part to start
3591  // at offset 8. If the high and low parts we inferred are both 4-byte types
3592  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3593  // the second element at offset 8. Check for this:
3594  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3595  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3596  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3597  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3598 
3599  // To handle this, we have to increase the size of the low part so that the
3600  // second element will start at an 8 byte offset. We can't increase the size
3601  // of the second element because it might make us access off the end of the
3602  // struct.
3603  if (HiStart != 8) {
3604  // There are usually two sorts of types the ABI generation code can produce
3605  // for the low part of a pair that aren't 8 bytes in size: half, float or
3606  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3607  // NaCl).
3608  // Promote these to a larger type.
3609  if (Lo->isHalfTy() || Lo->isFloatTy())
3610  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3611  else {
3612  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3613  && "Invalid/unknown lo type");
3614  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3615  }
3616  }
3617 
3618  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3619 
3620  // Verify that the second element is at an 8-byte offset.
3621  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3622  "Invalid x86-64 argument pair!");
3623  return Result;
3624 }
3625 
3627 classifyReturnType(QualType RetTy) const {
3628  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3629  // classification algorithm.
3630  X86_64ABIInfo::Class Lo, Hi;
3631  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3632 
3633  // Check some invariants.
3634  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3635  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3636 
3637  llvm::Type *ResType = nullptr;
3638  switch (Lo) {
3639  case NoClass:
3640  if (Hi == NoClass)
3641  return ABIArgInfo::getIgnore();
3642  // If the low part is just padding, it takes no register, leave ResType
3643  // null.
3644  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3645  "Unknown missing lo part");
3646  break;
3647 
3648  case SSEUp:
3649  case X87Up:
3650  llvm_unreachable("Invalid classification for lo word.");
3651 
3652  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3653  // hidden argument.
3654  case Memory:
3655  return getIndirectReturnResult(RetTy);
3656 
3657  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3658  // available register of the sequence %rax, %rdx is used.
3659  case Integer:
3660  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3661 
3662  // If we have a sign or zero extended integer, make sure to return Extend
3663  // so that the parameter gets the right LLVM IR attributes.
3664  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3665  // Treat an enum type as its underlying type.
3666  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3667  RetTy = EnumTy->getDecl()->getIntegerType();
3668 
3669  if (RetTy->isIntegralOrEnumerationType() &&
3670  isPromotableIntegerTypeForABI(RetTy))
3671  return ABIArgInfo::getExtend(RetTy);
3672  }
3673  break;
3674 
3675  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3676  // available SSE register of the sequence %xmm0, %xmm1 is used.
3677  case SSE:
3678  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3679  break;
3680 
3681  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3682  // returned on the X87 stack in %st0 as 80-bit x87 number.
3683  case X87:
3684  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3685  break;
3686 
3687  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3688  // part of the value is returned in %st0 and the imaginary part in
3689  // %st1.
3690  case ComplexX87:
3691  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3692  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3693  llvm::Type::getX86_FP80Ty(getVMContext()));
3694  break;
3695  }
3696 
3697  llvm::Type *HighPart = nullptr;
3698  switch (Hi) {
3699  // Memory was handled previously and X87 should
3700  // never occur as a hi class.
3701  case Memory:
3702  case X87:
3703  llvm_unreachable("Invalid classification for hi word.");
3704 
3705  case ComplexX87: // Previously handled.
3706  case NoClass:
3707  break;
3708 
3709  case Integer:
3710  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3711  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3712  return ABIArgInfo::getDirect(HighPart, 8);
3713  break;
3714  case SSE:
3715  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3716  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3717  return ABIArgInfo::getDirect(HighPart, 8);
3718  break;
3719 
3720  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3721  // is passed in the next available eightbyte chunk if the last used
3722  // vector register.
3723  //
3724  // SSEUP should always be preceded by SSE, just widen.
3725  case SSEUp:
3726  assert(Lo == SSE && "Unexpected SSEUp classification.");
3727  ResType = GetByteVectorType(RetTy);
3728  break;
3729 
3730  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3731  // returned together with the previous X87 value in %st0.
3732  case X87Up:
3733  // If X87Up is preceded by X87, we don't need to do
3734  // anything. However, in some cases with unions it may not be
3735  // preceded by X87. In such situations we follow gcc and pass the
3736  // extra bits in an SSE reg.
3737  if (Lo != X87) {
3738  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3739  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3740  return ABIArgInfo::getDirect(HighPart, 8);
3741  }
3742  break;
3743  }
3744 
3745  // If a high part was specified, merge it together with the low part. It is
3746  // known to pass in the high eightbyte of the result. We do this by forming a
3747  // first class struct aggregate with the high and low part: {low, high}
3748  if (HighPart)
3749  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3750 
3751  return ABIArgInfo::getDirect(ResType);
3752 }
3753 
3754 ABIArgInfo
3755 X86_64ABIInfo::classifyArgumentType(QualType Ty, unsigned freeIntRegs,
3756  unsigned &neededInt, unsigned &neededSSE,
3757  bool isNamedArg, bool IsRegCall) const {
3759 
3760  X86_64ABIInfo::Class Lo, Hi;
3761  classify(Ty, 0, Lo, Hi, isNamedArg, IsRegCall);
3762 
3763  // Check some invariants.
3764  // FIXME: Enforce these by construction.
3765  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3766  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3767 
3768  neededInt = 0;
3769  neededSSE = 0;
3770  llvm::Type *ResType = nullptr;
3771  switch (Lo) {
3772  case NoClass:
3773  if (Hi == NoClass)
3774  return ABIArgInfo::getIgnore();
3775  // If the low part is just padding, it takes no register, leave ResType
3776  // null.
3777  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3778  "Unknown missing lo part");
3779  break;
3780 
3781  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3782  // on the stack.
3783  case Memory:
3784 
3785  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3786  // COMPLEX_X87, it is passed in memory.
3787  case X87:
3788  case ComplexX87:
3789  if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3790  ++neededInt;
3791  return getIndirectResult(Ty, freeIntRegs);
3792 
3793  case SSEUp:
3794  case X87Up:
3795  llvm_unreachable("Invalid classification for lo word.");
3796 
3797  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3798  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3799  // and %r9 is used.
3800  case Integer:
3801  ++neededInt;
3802 
3803  // Pick an 8-byte type based on the preferred type.
3804  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3805 
3806  // If we have a sign or zero extended integer, make sure to return Extend
3807  // so that the parameter gets the right LLVM IR attributes.
3808  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3809  // Treat an enum type as its underlying type.
3810  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3811  Ty = EnumTy->getDecl()->getIntegerType();
3812 
3813  if (Ty->isIntegralOrEnumerationType() &&
3814  isPromotableIntegerTypeForABI(Ty))
3815  return ABIArgInfo::getExtend(Ty);
3816  }
3817 
3818  break;
3819 
3820  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3821  // available SSE register is used, the registers are taken in the
3822  // order from %xmm0 to %xmm7.
3823  case SSE: {
3824  llvm::Type *IRType = CGT.ConvertType(Ty);
3825  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3826  ++neededSSE;
3827  break;
3828  }
3829  }
3830 
3831  llvm::Type *HighPart = nullptr;
3832  switch (Hi) {
3833  // Memory was handled previously, ComplexX87 and X87 should
3834  // never occur as hi classes, and X87Up must be preceded by X87,
3835  // which is passed in memory.
3836  case Memory:
3837  case X87:
3838  case ComplexX87:
3839  llvm_unreachable("Invalid classification for hi word.");
3840 
3841  case NoClass: break;
3842 
3843  case Integer:
3844  ++neededInt;
3845  // Pick an 8-byte type based on the preferred type.
3846  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3847 
3848  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3849  return ABIArgInfo::getDirect(HighPart, 8);
3850  break;
3851 
3852  // X87Up generally doesn't occur here (long double is passed in
3853  // memory), except in situations involving unions.
3854  case X87Up:
3855  case SSE:
3856  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3857 
3858  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3859  return ABIArgInfo::getDirect(HighPart, 8);
3860 
3861  ++neededSSE;
3862  break;
3863 
3864  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3865  // eightbyte is passed in the upper half of the last used SSE
3866  // register. This only happens when 128-bit vectors are passed.
3867  case SSEUp:
3868  assert(Lo == SSE && "Unexpected SSEUp classification");
3869  ResType = GetByteVectorType(Ty);
3870  break;
3871  }
3872 
3873  // If a high part was specified, merge it together with the low part. It is
3874  // known to pass in the high eightbyte of the result. We do this by forming a
3875  // first class struct aggregate with the high and low part: {low, high}
3876  if (HighPart)
3877  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3878 
3879  return ABIArgInfo::getDirect(ResType);
3880 }
3881 
3882 ABIArgInfo
3883 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3884  unsigned &NeededSSE,
3885  unsigned &MaxVectorWidth) const {
3886  auto RT = Ty->getAs<RecordType>();
3887  assert(RT && "classifyRegCallStructType only valid with struct types");
3888 
3889  if (RT->getDecl()->hasFlexibleArrayMember())
3890  return getIndirectReturnResult(Ty);
3891 
3892  // Sum up bases
3893  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3894  if (CXXRD->isDynamicClass()) {
3895  NeededInt = NeededSSE = 0;
3896  return getIndirectReturnResult(Ty);
3897  }
3898 
3899  for (const auto &I : CXXRD->bases())
3900  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE,
3901  MaxVectorWidth)
3902  .isIndirect()) {
3903  NeededInt = NeededSSE = 0;
3904  return getIndirectReturnResult(Ty);
3905  }
3906  }
3907 
3908  // Sum up members
3909  for (const auto *FD : RT->getDecl()->fields()) {
3910  QualType MTy = FD->getType();
3911  if (MTy->isRecordType() && !MTy->isUnionType()) {
3912  if (classifyRegCallStructTypeImpl(MTy, NeededInt, NeededSSE,
3913  MaxVectorWidth)
3914  .isIndirect()) {
3915  NeededInt = NeededSSE = 0;
3916  return getIndirectReturnResult(Ty);
3917  }
3918  } else {
3919  unsigned LocalNeededInt, LocalNeededSSE;
3920  if (classifyArgumentType(MTy, UINT_MAX, LocalNeededInt, LocalNeededSSE,
3921  true, true)
3922  .isIndirect()) {
3923  NeededInt = NeededSSE = 0;
3924  return getIndirectReturnResult(Ty);
3925  }
3926  if (const auto *AT = getContext().getAsConstantArrayType(MTy))
3927  MTy = AT->getElementType();
3928  if (const auto *VT = MTy->getAs<VectorType>())
3929  if (getContext().getTypeSize(VT) > MaxVectorWidth)
3930  MaxVectorWidth = getContext().getTypeSize(VT);
3931  NeededInt += LocalNeededInt;
3932  NeededSSE += LocalNeededSSE;
3933  }
3934  }
3935 
3936  return ABIArgInfo::getDirect();
3937 }
3938 
3939 ABIArgInfo
3940 X86_64ABIInfo::classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
3941  unsigned &NeededSSE,
3942  unsigned &MaxVectorWidth) const {
3943 
3944  NeededInt = 0;
3945  NeededSSE = 0;
3946  MaxVectorWidth = 0;
3947 
3948  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE,
3949  MaxVectorWidth);
3950 }
3951 
3952 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3953 
3954  const unsigned CallingConv = FI.getCallingConvention();
3955  // It is possible to force Win64 calling convention on any x86_64 target by
3956  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3957  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3958  if (CallingConv == llvm::CallingConv::Win64) {
3959  WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
3960  Win64ABIInfo.computeInfo(FI);
3961  return;
3962  }
3963 
3964  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3965 
3966  // Keep track of the number of assigned registers.
3967  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3968  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3969  unsigned NeededInt = 0, NeededSSE = 0, MaxVectorWidth = 0;
3970 
3971  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3972  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3973  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3974  FI.getReturnInfo() = classifyRegCallStructType(
3975  FI.getReturnType(), NeededInt, NeededSSE, MaxVectorWidth);
3976  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3977  FreeIntRegs -= NeededInt;
3978  FreeSSERegs -= NeededSSE;
3979  } else {
3980  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3981  }
3982  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>() &&
3983  getContext().getCanonicalType(FI.getReturnType()
3984  ->getAs<ComplexType>()
3985  ->getElementType()) ==
3986  getContext().LongDoubleTy)
3987  // Complex Long Double Type is passed in Memory when Regcall
3988  // calling convention is used.
3989  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3990  else
3992  }
3993 
3994  // If the return value is indirect, then the hidden argument is consuming one
3995  // integer register.
3996  if (FI.getReturnInfo().isIndirect())
3997  --FreeIntRegs;
3998  else if (NeededSSE && MaxVectorWidth > 0)
3999  FI.setMaxVectorWidth(MaxVectorWidth);
4000 
4001  // The chain argument effectively gives us another free register.
4002  if (FI.isChainCall())
4003  ++FreeIntRegs;
4004 
4005  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
4006  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
4007  // get assigned (in left-to-right order) for passing as follows...
4008  unsigned ArgNo = 0;
4009  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
4010  it != ie; ++it, ++ArgNo) {
4011  bool IsNamedArg = ArgNo < NumRequiredArgs;
4012 
4013  if (IsRegCall && it->type->isStructureOrClassType())
4014  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE,
4015  MaxVectorWidth);
4016  else
4017  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
4018  NeededSSE, IsNamedArg);
4019 
4020  // AMD64-ABI 3.2.3p3: If there are no registers available for any
4021  // eightbyte of an argument, the whole argument is passed on the
4022  // stack. If registers have already been assigned for some
4023  // eightbytes of such an argument, the assignments get reverted.
4024  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
4025  FreeIntRegs -= NeededInt;
4026  FreeSSERegs -= NeededSSE;
4027  if (MaxVectorWidth > FI.getMaxVectorWidth())
4028  FI.setMaxVectorWidth(MaxVectorWidth);
4029  } else {
4030  it->info = getIndirectResult(it->type, FreeIntRegs);
4031  }
4032  }
4033 }
4034 
4036  Address VAListAddr, QualType Ty) {
4037  Address overflow_arg_area_p =
4038  CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
4039  llvm::Value *overflow_arg_area =
4040  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
4041 
4042  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
4043  // byte boundary if alignment needed by type exceeds 8 byte boundary.
4044  // It isn't stated explicitly in the standard, but in practice we use
4045  // alignment greater than 16 where necessary.
4046  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4047  if (Align > CharUnits::fromQuantity(8)) {
4048  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
4049  Align);
4050  }
4051 
4052  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
4053  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
4054  llvm::Value *Res =
4055  CGF.Builder.CreateBitCast(overflow_arg_area,
4056  llvm::PointerType::getUnqual(LTy));
4057 
4058  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
4059  // l->overflow_arg_area + sizeof(type).
4060  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
4061  // an 8 byte boundary.
4062 
4063  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
4064  llvm::Value *Offset =
4065  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
4066  overflow_arg_area = CGF.Builder.CreateGEP(CGF.Int8Ty, overflow_arg_area,
4067  Offset, "overflow_arg_area.next");
4068  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
4069 
4070  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
4071  return Address(Res, LTy, Align);
4072 }
4073 
4074 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4075  QualType Ty) const {
4076  // Assume that va_list type is correct; should be pointer to LLVM type:
4077  // struct {
4078  // i32 gp_offset;
4079  // i32 fp_offset;
4080  // i8* overflow_arg_area;
4081  // i8* reg_save_area;
4082  // };
4083  unsigned neededInt, neededSSE;
4084 
4085  Ty = getContext().getCanonicalType(Ty);
4086  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
4087  /*isNamedArg*/false);
4088 
4089  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
4090  // in the registers. If not go to step 7.
4091  if (!neededInt && !neededSSE)
4092  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
4093 
4094  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
4095  // general purpose registers needed to pass type and num_fp to hold
4096  // the number of floating point registers needed.
4097 
4098  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
4099  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
4100  // l->fp_offset > 304 - num_fp * 16 go to step 7.
4101  //
4102  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
4103  // register save space).
4104 
4105  llvm::Value *InRegs = nullptr;
4106  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
4107  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
4108  if (neededInt) {
4109  gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
4110  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
4111  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
4112  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
4113  }
4114 
4115  if (neededSSE) {
4116  fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
4117  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
4118  llvm::Value *FitsInFP =
4119  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
4120  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
4121  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
4122  }
4123 
4124  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4125  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
4126  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4127  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
4128 
4129  // Emit code to load the value if it was passed in registers.
4130 
4131  CGF.EmitBlock(InRegBlock);
4132 
4133  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
4134  // an offset of l->gp_offset and/or l->fp_offset. This may require
4135  // copying to a temporary location in case the parameter is passed
4136  // in different register classes or requires an alignment greater
4137  // than 8 for general purpose registers and 16 for XMM registers.
4138  //
4139  // FIXME: This really results in shameful code when we end up needing to
4140  // collect arguments from different places; often what should result in a
4141  // simple assembling of a structure from scattered addresses has many more
4142  // loads than necessary. Can we clean this up?
4143  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
4144  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
4145  CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
4146 
4147  Address RegAddr = Address::invalid();
4148  if (neededInt && neededSSE) {
4149  // FIXME: Cleanup.
4150  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
4151  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
4152  Address Tmp = CGF.CreateMemTemp(Ty);
4153  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
4154  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
4155  llvm::Type *TyLo = ST->getElementType(0);
4156  llvm::Type *TyHi = ST->getElementType(1);
4157  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
4158  "Unexpected ABI info for mixed regs");
4159  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
4160  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
4161  llvm::Value *GPAddr =
4162  CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset);
4163  llvm::Value *FPAddr =
4164  CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset);
4165  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
4166  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
4167 
4168  // Copy the first element.
4169  // FIXME: Our choice of alignment here and below is probably pessimistic.
4170  llvm::Value *V = CGF.Builder.CreateAlignedLoad(
4171  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
4172  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
4173  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
4174 
4175  // Copy the second element.
4176  V = CGF.Builder.CreateAlignedLoad(
4177  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
4178  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
4179  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
4180 
4181  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
4182  } else if (neededInt) {
4183  RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset),
4185  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
4186 
4187  // Copy to a temporary if necessary to ensure the appropriate alignment.
4188  auto TInfo = getContext().getTypeInfoInChars(Ty);
4189  uint64_t TySize = TInfo.Width.getQuantity();
4190  CharUnits TyAlign = TInfo.Align;
4191 
4192  // Copy into a temporary if the type is more aligned than the
4193  // register save area.
4194  if (TyAlign.getQuantity() > 8) {
4195  Address Tmp = CGF.CreateMemTemp(Ty);
4196  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
4197  RegAddr = Tmp;
4198  }
4199 
4200  } else if (neededSSE == 1) {
4201  RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset),
4202  CGF.Int8Ty, CharUnits::fromQuantity(16));
4203  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
4204  } else {
4205  assert(neededSSE == 2 && "Invalid number of needed registers!");
4206  // SSE registers are spaced 16 bytes apart in the register save
4207  // area, we need to collect the two eightbytes together.
4208  // The ABI isn't explicit about this, but it seems reasonable
4209  // to assume that the slots are 16-byte aligned, since the stack is
4210  // naturally 16-byte aligned and the prologue is expected to store
4211  // all the SSE registers to the RSA.
4212  Address RegAddrLo = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea,
4213  fp_offset),
4214  CGF.Int8Ty, CharUnits::fromQuantity(16));
4215  Address RegAddrHi =
4216  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
4218  llvm::Type *ST = AI.canHaveCoerceToType()
4219  ? AI.getCoerceToType()
4220  : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
4221  llvm::Value *V;
4222  Address Tmp = CGF.CreateMemTemp(Ty);
4223  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
4225  RegAddrLo, ST->getStructElementType(0)));
4226  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
4228  RegAddrHi, ST->getStructElementType(1)));
4229  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
4230 
4231  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
4232  }
4233 
4234  // AMD64-ABI 3.5.7p5: Step 5. Set:
4235  // l->gp_offset = l->gp_offset + num_gp * 8
4236  // l->fp_offset = l->fp_offset + num_fp * 16.
4237  if (neededInt) {
4238  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
4239  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
4240  gp_offset_p);
4241  }
4242  if (neededSSE) {
4243  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
4244  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
4245  fp_offset_p);
4246  }
4247  CGF.EmitBranch(ContBlock);
4248 
4249  // Emit code to load the value if it was passed in memory.
4250 
4251  CGF.EmitBlock(InMemBlock);
4252  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
4253 
4254  // Return the appropriate result.
4255 
4256  CGF.EmitBlock(ContBlock);
4257  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
4258  "vaarg.addr");
4259  return ResAddr;
4260 }
4261 
4262 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4263  QualType Ty) const {
4264  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4265  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4266  uint64_t Width = getContext().getTypeSize(Ty);
4267  bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4268 
4269  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4270  CGF.getContext().getTypeInfoInChars(Ty),
4272  /*allowHigherAlign*/ false);
4273 }
4274 
4275 ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
4276  QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo &current) const {
4277  const Type *Base = nullptr;
4278  uint64_t NumElts = 0;
4279 
4280  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
4281  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
4282  FreeSSERegs -= NumElts;
4283  return getDirectX86Hva();
4284  }
4285  return current;
4286 }
4287 
4288 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
4289  bool IsReturnType, bool IsVectorCall,
4290  bool IsRegCall) const {
4291 
4292  if (Ty->isVoidType())
4293  return ABIArgInfo::getIgnore();
4294 
4295  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4296  Ty = EnumTy->getDecl()->getIntegerType();
4297 
4298  TypeInfo Info = getContext().getTypeInfo(Ty);
4299  uint64_t Width = Info.Width;
4300  CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
4301 
4302  const RecordType *RT = Ty->getAs<RecordType>();
4303  if (RT) {
4304  if (!IsReturnType) {
4305  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
4306  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4307  }
4308 
4309  if (RT->getDecl()->hasFlexibleArrayMember())
4310  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4311 
4312  }
4313 
4314  const Type *Base = nullptr;
4315  uint64_t NumElts = 0;
4316  // vectorcall adds the concept of a homogenous vector aggregate, similar to
4317  // other targets.
4318  if ((IsVectorCall || IsRegCall) &&
4319  isHomogeneousAggregate(Ty, Base, NumElts)) {
4320  if (IsRegCall) {
4321  if (FreeSSERegs >= NumElts) {
4322  FreeSSERegs -= NumElts;
4323  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
4324  return ABIArgInfo::getDirect();
4325  return ABIArgInfo::getExpand();
4326  }
4327  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4328  } else if (IsVectorCall) {
4329  if (FreeSSERegs >= NumElts &&
4330  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
4331  FreeSSERegs -= NumElts;
4332  return ABIArgInfo::getDirect();
4333  } else if (IsReturnType) {
4334  return ABIArgInfo::getExpand();
4335  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
4336  // HVAs are delayed and reclassified in the 2nd step.
4337  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4338  }
4339  }
4340  }
4341 
4342  if (Ty->isMemberPointerType()) {
4343  // If the member pointer is represented by an LLVM int or ptr, pass it
4344  // directly.
4345  llvm::Type *LLTy = CGT.ConvertType(Ty);
4346  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
4347  return ABIArgInfo::getDirect();
4348  }
4349 
4350  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
4351  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4352  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4353  if (Width > 64 || !llvm::isPowerOf2_64(Width))
4354  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4355 
4356  // Otherwise, coerce it to a small integer.
4357  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
4358  }
4359 
4360  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4361  switch (BT->getKind()) {
4362  case BuiltinType::Bool:
4363  // Bool type is always extended to the ABI, other builtin types are not
4364  // extended.
4365  return ABIArgInfo::getExtend(Ty);
4366 
4367  case BuiltinType::LongDouble:
4368  // Mingw64 GCC uses the old 80 bit extended precision floating point
4369  // unit. It passes them indirectly through memory.
4370  if (IsMingw64) {
4371  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
4372  if (LDF == &llvm::APFloat::x87DoubleExtended())
4373  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4374  }
4375  break;
4376 
4377  case BuiltinType::Int128:
4378  case BuiltinType::UInt128:
4379  // If it's a parameter type, the normal ABI rule is that arguments larger
4380  // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
4381  // even though it isn't particularly efficient.
4382  if (!IsReturnType)
4383  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4384 
4385  // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
4386  // Clang matches them for compatibility.
4387  return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
4388  llvm::Type::getInt64Ty(getVMContext()), 2));
4389 
4390  default:
4391  break;
4392  }
4393  }
4394 
4395  if (Ty->isBitIntType()) {
4396  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4397  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4398  // However, non-power-of-two bit-precise integers will be passed as 1, 2, 4,
4399  // or 8 bytes anyway as long is it fits in them, so we don't have to check
4400  // the power of 2.
4401  if (Width <= 64)
4402  return ABIArgInfo::getDirect();
4403  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4404  }
4405 
4406  return ABIArgInfo::getDirect();
4407 }
4408 
4409 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4410  const unsigned CC = FI.getCallingConvention();
4411  bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
4412  bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
4413 
4414  // If __attribute__((sysv_abi)) is in use, use the SysV argument
4415  // classification rules.
4416  if (CC == llvm::CallingConv::X86_64_SysV) {
4417  X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
4418  SysVABIInfo.computeInfo(FI);
4419  return;
4420  }
4421 
4422  unsigned FreeSSERegs = 0;
4423  if (IsVectorCall) {
4424  // We can use up to 4 SSE return registers with vectorcall.
4425  FreeSSERegs = 4;
4426  } else if (IsRegCall) {
4427  // RegCall gives us 16 SSE registers.
4428  FreeSSERegs = 16;
4429  }
4430 
4431  if (!getCXXABI().classifyReturnType(FI))
4432  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4433  IsVectorCall, IsRegCall);
4434 
4435  if (IsVectorCall) {
4436  // We can use up to 6 SSE register parameters with vectorcall.
4437  FreeSSERegs = 6;
4438  } else if (IsRegCall) {
4439  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4440  FreeSSERegs = 16;
4441  }
4442 
4443  unsigned ArgNum = 0;
4444  unsigned ZeroSSERegs = 0;
4445  for (auto &I : FI.arguments()) {
4446  // Vectorcall in x64 only permits the first 6 arguments to be passed as
4447  // XMM/YMM registers. After the sixth argument, pretend no vector
4448  // registers are left.
4449  unsigned *MaybeFreeSSERegs =
4450  (IsVectorCall && ArgNum >= 6) ? &ZeroSSERegs : &FreeSSERegs;
4451  I.info =
4452  classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
4453  ++ArgNum;
4454  }
4455 
4456  if (IsVectorCall) {
4457  // For vectorcall, assign aggregate HVAs to any free vector registers in a
4458  // second pass.
4459  for (auto &I : FI.arguments())
4460  I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
4461  }
4462 }
4463 
4464 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4465  QualType Ty) const {
4466  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4467  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4468  uint64_t Width = getContext().getTypeSize(Ty);
4469  bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4470 
4471  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4472  CGF.getContext().getTypeInfoInChars(Ty),
4474  /*allowHigherAlign*/ false);
4475 }
4476 
4478  llvm::Value *Address, bool Is64Bit,
4479  bool IsAIX) {
4480  // This is calculated from the LLVM and GCC tables and verified
4481  // against gcc output. AFAIK all PPC ABIs use the same encoding.
4482 
4483  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4484 
4485  llvm::IntegerType *i8 = CGF.Int8Ty;
4486  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4487  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4488  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4489 
4490  // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
4491  AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 0, 31);
4492 
4493  // 32-63: fp0-31, the 8-byte floating-point registers
4494  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4495 
4496  // 64-67 are various 4-byte or 8-byte special-purpose registers:
4497  // 64: mq
4498  // 65: lr
4499  // 66: ctr
4500  // 67: ap
4501  AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 64, 67);
4502 
4503  // 68-76 are various 4-byte special-purpose registers:
4504  // 68-75 cr0-7
4505  // 76: xer
4506  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4507 
4508  // 77-108: v0-31, the 16-byte vector registers
4509  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4510 
4511  // 109: vrsave
4512  // 110: vscr
4513  AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 109, 110);
4514 
4515  // AIX does not utilize the rest of the registers.
4516  if (IsAIX)
4517  return false;
4518 
4519  // 111: spe_acc
4520  // 112: spefscr
4521  // 113: sfp
4522  AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 111, 113);
4523 
4524  if (!Is64Bit)
4525  return false;
4526 
4527  // TODO: Need to verify if these registers are used on 64 bit AIX with Power8
4528  // or above CPU.
4529  // 64-bit only registers:
4530  // 114: tfhar
4531  // 115: tfiar
4532  // 116: texasr
4533  AssignToArrayRange(Builder, Address, Eight8, 114, 116);
4534 
4535  return false;
4536 }
4537 
4538 // AIX
4539 namespace {
4540 /// AIXABIInfo - The AIX XCOFF ABI information.
4541 class AIXABIInfo : public ABIInfo {
4542  const bool Is64Bit;
4543  const unsigned PtrByteSize;
4544  CharUnits getParamTypeAlignment(QualType Ty) const;
4545 
4546 public:
4547  AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
4548  : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}
4549 
4550  bool isPromotableTypeForABI(QualType Ty) const;
4551 
4552  ABIArgInfo classifyReturnType(QualType RetTy) const;
4554 
4555  void computeInfo(CGFunctionInfo &FI) const override {
4556  if (!getCXXABI().classifyReturnType(FI))
4558 
4559  for (auto &I : FI.arguments())
4561  }
4562 
4563  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4564  QualType Ty) const override;
4565 };
4566 
4567 class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
4568  const bool Is64Bit;
4569 
4570 public:
4571  AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
4572  : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(CGT, Is64Bit)),
4573  Is64Bit(Is64Bit) {}
4574  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4575  return 1; // r1 is the dedicated stack pointer
4576  }
4577 
4578  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4579  llvm::Value *Address) const override;
4580 };
4581 } // namespace
4582 
4583 // Return true if the ABI requires Ty to be passed sign- or zero-
4584 // extended to 32/64 bits.
4585 bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
4586  // Treat an enum type as its underlying type.
4587  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4588  Ty = EnumTy->getDecl()->getIntegerType();
4589 
4590  // Promotable integer types are required to be promoted by the ABI.
4591  if (getContext().isPromotableIntegerType(Ty))
4592  return true;
4593 
4594  if (!Is64Bit)
4595  return false;
4596 
4597  // For 64 bit mode, in addition to the usual promotable integer types, we also
4598  // need to extend all 32-bit types, since the ABI requires promotion to 64
4599  // bits.
4600  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4601  switch (BT->getKind()) {
4602  case BuiltinType::Int:
4603  case BuiltinType::UInt:
4604  return true;
4605  default:
4606  break;
4607  }
4608 
4609  return false;
4610 }
4611 
4613  if (RetTy->isAnyComplexType())
4614  return ABIArgInfo::getDirect();
4615 
4616  if (RetTy->isVectorType())
4617  return ABIArgInfo::getDirect();
4618 
4619  if (RetTy->isVoidType())
4620  return ABIArgInfo::getIgnore();
4621 
4622  if (isAggregateTypeForABI(RetTy))
4623  return getNaturalAlignIndirect(RetTy);
4624 
4625  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4626  : ABIArgInfo::getDirect());
4627 }
4628 
4631 
4632  if (Ty->isAnyComplexType())
4633  return ABIArgInfo::getDirect();
4634 
4635  if (Ty->isVectorType())
4636  return ABIArgInfo::getDirect();
4637 
4638  if (isAggregateTypeForABI(Ty)) {
4639  // Records with non-trivial destructors/copy-constructors should not be
4640  // passed by value.
4641  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4642  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4643 
4644  CharUnits CCAlign = getParamTypeAlignment(Ty);
4645  CharUnits TyAlign = getContext().getTypeAlignInChars(Ty);
4646 
4647  return ABIArgInfo::getIndirect(CCAlign, /*ByVal*/ true,
4648  /*Realign*/ TyAlign > CCAlign);
4649  }
4650 
4651  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4652  : ABIArgInfo::getDirect());
4653 }
4654 
4655 CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
4656  // Complex types are passed just like their elements.
4657  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4658  Ty = CTy->getElementType();
4659 
4660  if (Ty->isVectorType())
4661  return CharUnits::fromQuantity(16);
4662 
4663  // If the structure contains a vector type, the alignment is 16.
4664  if (isRecordWithSIMDVectorType(getContext(), Ty))
4665  return CharUnits::fromQuantity(16);
4666 
4667  return CharUnits::fromQuantity(PtrByteSize);
4668 }
4669 
4670 Address AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4671  QualType Ty) const {
4672 
4673  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4674  TypeInfo.Align = getParamTypeAlignment(Ty);
4675 
4676  CharUnits SlotSize = CharUnits::fromQuantity(PtrByteSize);
4677 
4678  // If we have a complex type and the base type is smaller than the register
4679  // size, the ABI calls for the real and imaginary parts to be right-adjusted
4680  // in separate words in 32bit mode or doublewords in 64bit mode. However,
4681  // Clang expects us to produce a pointer to a structure with the two parts
4682  // packed tightly. So generate loads of the real and imaginary parts relative
4683  // to the va_list pointer, and store them to a temporary structure. We do the
4684  // same as the PPC64ABI here.
4685  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4686  CharUnits EltSize = TypeInfo.Width / 2;
4687  if (EltSize < SlotSize)
4688  return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
4689  }
4690 
4691  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,
4692  SlotSize, /*AllowHigher*/ true);
4693 }
4694 
4695 bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
4696  CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
4697  return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
4698 }
4699 
4700 // PowerPC-32
4701 namespace {
4702 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4703 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4704  bool IsSoftFloatABI;
4705  bool IsRetSmallStructInRegABI;
4706 
4707  CharUnits getParamTypeAlignment(QualType Ty) const;
4708 
4709 public:
4710  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
4711  bool RetSmallStructInRegABI)
4712  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
4713  IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
4714 
4715  ABIArgInfo classifyReturnType(QualType RetTy) const;
4716 
4717  void computeInfo(CGFunctionInfo &FI) const override {
4718  if (!getCXXABI().classifyReturnType(FI))
4720  for (auto &I : FI.arguments())
4722  }
4723 
4724  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4725  QualType Ty) const override;
4726 };
4727 
4728 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4729 public:
4730  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
4731  bool RetSmallStructInRegABI)
4732  : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
4733  CGT, SoftFloatABI, RetSmallStructInRegABI)) {}
4734 
4735  static bool isStructReturnInRegABI(const llvm::Triple &Triple,
4736  const CodeGenOptions &Opts);
4737 
4738  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4739  // This is recovered from gcc output.
4740  return 1; // r1 is the dedicated stack pointer
4741  }
4742 
4743  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4744  llvm::Value *Address) const override;
4745 };
4746 }
4747 
4748 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4749  // Complex types are passed just like their elements.
4750  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4751  Ty = CTy->getElementType();
4752 
4753  if (Ty->isVectorType())
4754  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4755  : 4);
4756 
4757  // For single-element float/vector structs, we consider the whole type
4758  // to have the same alignment requirements as its single element.
4759  const Type *AlignTy = nullptr;
4760  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4761  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4762  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4763  (BT && BT->isFloatingPoint()))
4764  AlignTy = EltType;
4765  }
4766 
4767  if (AlignTy)
4768  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4769  return CharUnits::fromQuantity(4);
4770 }
4771 
4773  uint64_t Size;
4774 
4775  // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
4776  if (isAggregateTypeForABI(RetTy) && IsRetSmallStructInRegABI &&
4777  (Size = getContext().getTypeSize(RetTy)) <= 64) {
4778  // System V ABI (1995), page 3-22, specified:
4779  // > A structure or union whose size is less than or equal to 8 bytes
4780  // > shall be returned in r3 and r4, as if it were first stored in the
4781  // > 8-byte aligned memory area and then the low addressed word were
4782  // > loaded into r3 and the high-addressed word into r4. Bits beyond
4783  // > the last member of the structure or union are not defined.
4784  //
4785  // GCC for big-endian PPC32 inserts the pad before the first member,
4786  // not "beyond the last member" of the struct. To stay compatible
4787  // with GCC, we coerce the struct to an integer of the same size.
4788  // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
4789  if (Size == 0)
4790  return ABIArgInfo::getIgnore();
4791  else {
4792  llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size);
4793  return ABIArgInfo::getDirect(CoerceTy);
4794  }
4795  }
4796 
4797  return DefaultABIInfo::classifyReturnType(RetTy);
4798 }
4799 
4800 // TODO: this implementation is now likely redundant with
4801 // DefaultABIInfo::EmitVAArg.
4802 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4803  QualType Ty) const {
4804  if (getTarget().getTriple().isOSDarwin()) {
4805  auto TI = getContext().getTypeInfoInChars(Ty);
4806  TI.Align = getParamTypeAlignment(Ty);
4807 
4808  CharUnits SlotSize = CharUnits::fromQuantity(4);
4809  return emitVoidPtrVAArg(CGF, VAList, Ty,
4810  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4811  /*AllowHigherAlign=*/true);
4812  }
4813 
4814  const unsigned OverflowLimit = 8;
4815  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4816  // TODO: Implement this. For now ignore.
4817  (void)CTy;
4818  return Address::invalid(); // FIXME?
4819  }
4820 
4821  // struct __va_list_tag {
4822  // unsigned char gpr;
4823  // unsigned char fpr;
4824  // unsigned short reserved;
4825  // void *overflow_arg_area;
4826  // void *reg_save_area;
4827  // };
4828 
4829  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4830  bool isInt = !Ty->isFloatingType();
4831  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4832 
4833  // All aggregates are passed indirectly? That doesn't seem consistent
4834  // with the argument-lowering code.
4835  bool isIndirect = isAggregateTypeForABI(Ty);
4836 
4837  CGBuilderTy &Builder = CGF.Builder;
4838 
4839  // The calling convention either uses 1-2 GPRs or 1 FPR.
4840  Address NumRegsAddr = Address::invalid();
4841  if (isInt || IsSoftFloatABI) {
4842  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4843  } else {
4844  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4845  }
4846 
4847  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4848 
4849  // "Align" the register count when TY is i64.
4850  if (isI64 || (isF64 && IsSoftFloatABI)) {
4851  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4852  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4853  }
4854 
4855  llvm::Value *CC =
4856  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4857 
4858  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4859  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4860  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4861 
4862  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4863 
4864  llvm::Type *DirectTy = CGF.ConvertType(Ty), *ElementTy = DirectTy;
4865  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4866 
4867  // Case 1: consume registers.
4868  Address RegAddr = Address::invalid();
4869  {
4870  CGF.EmitBlock(UsingRegs);
4871 
4872  Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4873  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr), CGF.Int8Ty,
4875  assert(RegAddr.getElementType() == CGF.Int8Ty);
4876 
4877  // Floating-point registers start after the general-purpose registers.
4878  if (!(isInt || IsSoftFloatABI)) {
4879  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4881  }
4882 
4883  // Get the address of the saved value by scaling the number of
4884  // registers we've used by the number of
4885  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4886  llvm::Value *RegOffset =
4887  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4888  RegAddr = Address(
4889  Builder.CreateInBoundsGEP(CGF.Int8Ty, RegAddr.getPointer(), RegOffset),
4890  CGF.Int8Ty, RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4891  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4892 
4893  // Increase the used-register count.
4894  NumRegs =
4895  Builder.CreateAdd(NumRegs,
4896  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4897  Builder.CreateStore(NumRegs, NumRegsAddr);
4898 
4899  CGF.EmitBranch(Cont);
4900  }
4901 
4902  // Case 2: consume space in the overflow area.
4903  Address MemAddr = Address::invalid();
4904  {
4905  CGF.EmitBlock(UsingOverflow);
4906 
4907  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4908 
4909  // Everything in the overflow area is rounded up to a size of at least 4.
4910  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4911 
4912  CharUnits Size;
4913  if (!isIndirect) {
4914  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4915  Size = TypeInfo.Width.alignTo(OverflowAreaAlign);
4916  } else {
4917  Size = CGF.getPointerSize();
4918  }
4919 
4920  Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4921  Address OverflowArea =
4922  Address(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"), CGF.Int8Ty,
4923  OverflowAreaAlign);
4924  // Round up address of argument to alignment
4925  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4926  if (Align > OverflowAreaAlign) {
4927  llvm::Value *Ptr = OverflowArea.getPointer();
4928  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4929  OverflowArea.getElementType(), Align);
4930  }
4931 
4932  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4933 
4934  // Increase the overflow area.
4935  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4936  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4937  CGF.EmitBranch(Cont);
4938  }
4939 
4940  CGF.EmitBlock(Cont);
4941 
4942  // Merge the cases with a phi.
4943  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4944  "vaarg.addr");
4945 
4946  // Load the pointer if the argument was passed indirectly.
4947  if (isIndirect) {
4948  Result = Address(Builder.CreateLoad(Result, "aggr"), ElementTy,
4949  getContext().getTypeAlignInChars(Ty));
4950  }
4951 
4952  return Result;
4953 }
4954 
4955 bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
4956  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
4957  assert(Triple.isPPC32());
4958 
4959  switch (Opts.getStructReturnConvention()) {
4961  break;
4962  case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
4963  return false;
4964  case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
4965  return true;
4966  }
4967 
4968  if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
4969  return true;
4970 
4971  return false;
4972 }
4973 
4974 bool
4975 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4976  llvm::Value *Address) const {
4977  return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
4978  /*IsAIX*/ false);
4979 }
4980 
4981 // PowerPC-64
4982 
4983 namespace {
4984 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4985 class PPC64_SVR4_ABIInfo : public ABIInfo {
4986 public:
4987  enum ABIKind {
4988  ELFv1 = 0,
4989  ELFv2
4990  };
4991 
4992 private:
4993  static const unsigned GPRBits = 64;
4994  ABIKind Kind;
4995  bool IsSoftFloatABI;
4996 
4997 public:
4998  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind,
4999  bool SoftFloatABI)
5000  : ABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}
5001 
5002  bool isPromotableTypeForABI(QualType Ty) const;
5003  CharUnits getParamTypeAlignment(QualType Ty) const;
5004 
5005  ABIArgInfo classifyReturnType(QualType RetTy) const;
5007 
5008  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5009  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5010  uint64_t Members) const override;
5011 
5012  // TODO: We can add more logic to computeInfo to improve performance.
5013  // Example: For aggregate arguments that fit in a register, we could
5014  // use getDirectInReg (as is done below for structs containing a single
5015  // floating-point value) to avoid pushing them to memory on function
5016  // entry. This would require changing the logic in PPCISelLowering
5017  // when lowering the parameters in the caller and args in the callee.
5018  void computeInfo(CGFunctionInfo &FI) const override {
5019  if (!getCXXABI().classifyReturnType(FI))
5021  for (auto &I : FI.arguments()) {
5022  // We rely on the default argument classification for the most part.
5023  // One exception: An aggregate containing a single floating-point
5024  // or vector item must be passed in a register if one is available.
5025  const Type *T = isSingleElementStruct(I.type, getContext());
5026  if (T) {
5027  const BuiltinType *BT = T->getAs<BuiltinType>();
5028  if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||
5029  (BT && BT->isFloatingPoint())) {
5030  QualType QT(T, 0);
5031  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
5032  continue;
5033  }
5034  }
5036  }
5037  }
5038 
5039  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5040  QualType Ty) const override;
5041 };
5042 
5043 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
5044 
5045 public:
5046  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
5047  PPC64_SVR4_ABIInfo::ABIKind Kind,
5048  bool SoftFloatABI)
5050  std::make_unique<PPC64_SVR4_ABIInfo>(CGT, Kind, SoftFloatABI)) {
5051  SwiftInfo =
5052  std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
5053  }
5054 
5055  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5056  // This is recovered from gcc output.
5057  return 1; // r1 is the dedicated stack pointer
5058  }
5059 
5060  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5061  llvm::Value *Address) const override;
5062 };
5063 
5064 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
5065 public:
5066  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
5067 
5068  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5069  // This is recovered from gcc output.
5070  return 1; // r1 is the dedicated stack pointer
5071  }
5072 
5073  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5074  llvm::Value *Address) const override;
5075 };
5076 
5077 }
5078 
5079 // Return true if the ABI requires Ty to be passed sign- or zero-
5080 // extended to 64 bits.
5081 bool
5082 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
5083  // Treat an enum type as its underlying type.
5084  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5085  Ty = EnumTy->getDecl()->getIntegerType();
5086 
5087  // Promotable integer types are required to be promoted by the ABI.
5088  if (isPromotableIntegerTypeForABI(Ty))
5089  return true;
5090 
5091  // In addition to the usual promotable integer types, we also need to
5092  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
5093  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5094  switch (BT->getKind()) {
5095  case BuiltinType::Int:
5096  case BuiltinType::UInt:
5097  return true;
5098  default:
5099  break;
5100  }
5101 
5102  if (const auto *EIT = Ty->getAs<BitIntType>())
5103  if (EIT->getNumBits() < 64)
5104  return true;
5105 
5106  return false;
5107 }
5108 
5109 /// isAlignedParamType - Determine whether a type requires 16-byte or
5110 /// higher alignment in the parameter area. Always returns at least 8.
5111 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
5112  // Complex types are passed just like their elements.
5113  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
5114  Ty = CTy->getElementType();
5115 
5116  auto FloatUsesVector = [this](QualType Ty){
5117  return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(
5118  Ty) == &llvm::APFloat::IEEEquad();
5119  };
5120 
5121  // Only vector types of size 16 bytes need alignment (larger types are
5122  // passed via reference, smaller types are not aligned).
5123  if (Ty->isVectorType()) {
5124  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
5125  } else if (FloatUsesVector(Ty)) {
5126  // According to ABI document section 'Optional Save Areas': If extended
5127  // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
5128  // format are supported, map them to a single quadword, quadword aligned.
5129  return CharUnits::fromQuantity(16);
5130  }
5131 
5132  // For single-element float/vector structs, we consider the whole type
5133  // to have the same alignment requirements as its single element.
5134  const Type *AlignAsType = nullptr;
5135  const Type *EltType = isSingleElementStruct(Ty, getContext());
5136  if (EltType) {
5137  const BuiltinType *BT = EltType->getAs<BuiltinType>();
5138  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
5139  (BT && BT->isFloatingPoint()))
5140  AlignAsType = EltType;
5141  }
5142 
5143  // Likewise for ELFv2 homogeneous aggregates.
5144  const Type *Base = nullptr;
5145  uint64_t Members = 0;
5146  if (!AlignAsType && Kind == ELFv2 &&
5147  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
5148  AlignAsType = Base;
5149 
5150  // With special case aggregates, only vector base types need alignment.
5151  if (AlignAsType) {
5152  bool UsesVector = AlignAsType->isVectorType() ||
5153  FloatUsesVector(QualType(AlignAsType, 0));
5154  return CharUnits::fromQuantity(UsesVector ? 16 : 8);
5155  }
5156 
5157  // Otherwise, we only need alignment for any aggregate type that
5158  // has an alignment requirement of >= 16 bytes.
5159  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
5160  return CharUnits::fromQuantity(16);
5161  }
5162 
5163  return CharUnits::fromQuantity(8);
5164 }
5165 
5166 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
5167 /// aggregate. Base is set to the base element type, and Members is set
5168 /// to the number of base elements.
5170  uint64_t &Members) const {
5171  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
5172  uint64_t NElements = AT->getSize().getZExtValue();
5173  if (NElements == 0)
5174  return false;
5175  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
5176  return false;
5177  Members *= NElements;
5178  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
5179  const RecordDecl *RD = RT->getDecl();
5180  if (RD->hasFlexibleArrayMember())
5181  return false;
5182 
5183  Members = 0;
5184 
5185  // If this is a C++ record, check the properties of the record such as
5186  // bases and ABI specific restrictions
5187  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
5188  if (!getCXXABI().isPermittedToBeHomogeneousAggregate(CXXRD))
5189  return false;
5190 
5191  for (const auto &I : CXXRD->bases()) {
5192  // Ignore empty records.
5193  if (isEmptyRecord(getContext(), I.getType(), true))
5194  continue;
5195 
5196  uint64_t FldMembers;
5197  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
5198  return false;
5199 
5200  Members += FldMembers;
5201  }
5202  }
5203 
5204  for (const auto *FD : RD->fields()) {
5205  // Ignore (non-zero arrays of) empty records.
5206  QualType FT = FD->getType();
5207  while (const ConstantArrayType *AT =
5208  getContext().getAsConstantArrayType(FT)) {
5209  if (AT->getSize().getZExtValue() == 0)
5210  return false;
5211  FT = AT->getElementType();
5212  }
5213  if (isEmptyRecord(getContext(), FT, true))
5214  continue;
5215 
5217  FD->isZeroLengthBitField(getContext()))
5218  continue;
5219 
5220  uint64_t FldMembers;
5221  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
5222  return false;
5223 
5224  Members = (RD->isUnion() ?
5225  std::max(Members, FldMembers) : Members + FldMembers);
5226  }
5227 
5228  if (!Base)
5229  return false;
5230 
5231  // Ensure there is no padding.
5232  if (getContext().getTypeSize(Base) * Members !=
5233  getContext().getTypeSize(Ty))
5234  return false;
5235  } else {
5236  Members = 1;
5237  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
5238  Members = 2;
5239  Ty = CT->getElementType();
5240  }
5241 
5242  // Most ABIs only support float, double, and some vector type widths.
5244  return false;
5245 
5246  // The base type must be the same for all members. Types that
5247  // agree in both total size and mode (float vs. vector) are
5248  // treated as being equivalent here.
5249  const Type *TyPtr = Ty.getTypePtr();
5250  if (!Base) {
5251  Base = TyPtr;
5252  // If it's a non-power-of-2 vector, its size is already a power-of-2,
5253  // so make sure to widen it explicitly.
5254  if (const VectorType *VT = Base->getAs<VectorType>()) {
5255  QualType EltTy = VT->getElementType();
5256  unsigned NumElements =
5257  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
5258  Base = getContext()
5259  .getVectorType(EltTy, NumElements, VT->getVectorKind())
5260  .getTypePtr();
5261  }
5262  }
5263 
5264  if (Base->isVectorType() != TyPtr->isVectorType() ||
5265  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
5266  return false;
5267  }
5268  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
5269 }
5270 
5271 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5272  // Homogeneous aggregates for ELFv2 must have base types of float,
5273  // double, long double, or 128-bit vectors.
5274  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5275  if (BT->getKind() == BuiltinType::Float ||
5276  BT->getKind() == BuiltinType::Double ||
5277  BT->getKind() == BuiltinType::LongDouble ||
5278  BT->getKind() == BuiltinType::Ibm128 ||
5279  (getContext().getTargetInfo().hasFloat128Type() &&
5280  (BT->getKind() == BuiltinType::Float128))) {
5281  if (IsSoftFloatABI)
5282  return false;
5283  return true;
5284  }
5285  }
5286  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5287  if (getContext().getTypeSize(VT) == 128)
5288  return true;
5289  }
5290  return false;
5291 }
5292 
5293 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
5294  const Type *Base, uint64_t Members) const {
5295  // Vector and fp128 types require one register, other floating point types
5296  // require one or two registers depending on their size.
5297  uint32_t NumRegs =
5298  ((getContext().getTargetInfo().hasFloat128Type() &&
5299  Base->isFloat128Type()) ||
5300  Base->isVectorType()) ? 1
5301  : (getContext().getTypeSize(Base) + 63) / 64;
5302 
5303  // Homogeneous Aggregates may occupy at most 8 registers.
5304  return Members * NumRegs <= 8;
5305 }
5306 
5307 ABIArgInfo
5310 
5311  if (Ty->isAnyComplexType())
5312  return ABIArgInfo::getDirect();
5313 
5314  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
5315  // or via reference (larger than 16 bytes).
5316  if (Ty->isVectorType()) {
5317  uint64_t Size = getContext().getTypeSize(Ty);
5318  if (Size > 128)
5319  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5320  else if (Size < 128) {
5321  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
5322  return ABIArgInfo::getDirect(CoerceTy);
5323  }
5324  }
5325 
5326  if (const auto *EIT = Ty->getAs<BitIntType>())
5327  if (EIT->getNumBits() > 128)
5328  return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
5329 
5330  if (isAggregateTypeForABI(Ty)) {
5331  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
5332  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5333 
5334  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
5335  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
5336 
5337  // ELFv2 homogeneous aggregates are passed as array types.
5338  const Type *Base = nullptr;
5339  uint64_t Members = 0;
5340  if (Kind == ELFv2 &&
5341  isHomogeneousAggregate(Ty, Base, Members)) {
5342  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
5343  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
5344  return ABIArgInfo::getDirect(CoerceTy);
5345  }
5346 
5347  // If an aggregate may end up fully in registers, we do not
5348  // use the ByVal method, but pass the aggregate as array.
5349  // This is usually beneficial since we avoid forcing the
5350  // back-end to store the argument to memory.
5351  uint64_t Bits = getContext().getTypeSize(Ty);
5352  if (Bits > 0 && Bits <= 8 * GPRBits) {
5353  llvm::Type *CoerceTy;
5354 
5355  // Types up to 8 bytes are passed as integer type (which will be
5356  // properly aligned in the argument save area doubleword).
5357  if (Bits <= GPRBits)
5358  CoerceTy =
5359  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
5360  // Larger types are passed as arrays, with the base type selected
5361  // according to the required alignment in the save area.
5362  else {
5363  uint64_t RegBits = ABIAlign * 8;
5364  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
5365  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
5366  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
5367  }
5368 
5369  return ABIArgInfo::getDirect(CoerceTy);
5370  }
5371 
5372  // All other aggregates are passed ByVal.
5374  /*ByVal=*/true,
5375  /*Realign=*/TyAlign > ABIAlign);
5376  }
5377 
5378  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
5379  : ABIArgInfo::getDirect());
5380 }
5381 
5382 ABIArgInfo
5384  if (RetTy->isVoidType())
5385  return ABIArgInfo::getIgnore();
5386 
5387  if (RetTy->isAnyComplexType())
5388  return ABIArgInfo::getDirect();
5389 
5390  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
5391  // or via reference (larger than 16 bytes).
5392  if (RetTy->isVectorType()) {
5393  uint64_t Size = getContext().getTypeSize(RetTy);
5394  if (Size > 128)
5395  return getNaturalAlignIndirect(RetTy);
5396  else if (Size < 128) {
5397  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
5398  return ABIArgInfo::getDirect(CoerceTy);
5399  }
5400  }
5401 
5402  if (const auto *EIT = RetTy->getAs<BitIntType>())
5403  if (EIT->getNumBits() > 128)
5404  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
5405 
5406  if (isAggregateTypeForABI(RetTy)) {
5407  // ELFv2 homogeneous aggregates are returned as array types.
5408  const Type *Base = nullptr;
5409  uint64_t Members = 0;
5410  if (Kind == ELFv2 &&
5411  isHomogeneousAggregate(RetTy, Base, Members)) {
5412  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
5413  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
5414  return ABIArgInfo::getDirect(CoerceTy);
5415  }
5416 
5417  // ELFv2 small aggregates are returned in up to two registers.
5418  uint64_t Bits = getContext().getTypeSize(RetTy);
5419  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
5420  if (Bits == 0)
5421  return ABIArgInfo::getIgnore();
5422 
5423  llvm::Type *CoerceTy;
5424  if (Bits > GPRBits) {
5425  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
5426  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
5427  } else
5428  CoerceTy =
5429  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
5430  return ABIArgInfo::getDirect(CoerceTy);
5431  }
5432 
5433  // All other aggregates are returned indirectly.
5434  return getNaturalAlignIndirect(RetTy);
5435  }
5436 
5437  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
5438  : ABIArgInfo::getDirect());
5439 }
5440 
5441 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
5442 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5443  QualType Ty) const {
5444  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
5445  TypeInfo.Align = getParamTypeAlignment(Ty);
5446 
5447  CharUnits SlotSize = CharUnits::fromQuantity(8);
5448 
5449  // If we have a complex type and the base type is smaller than 8 bytes,
5450  // the ABI calls for the real and imaginary parts to be right-adjusted
5451  // in separate doublewords. However, Clang expects us to produce a
5452  // pointer to a structure with the two parts packed tightly. So generate
5453  // loads of the real and imaginary parts relative to the va_list pointer,
5454  // and store them to a temporary structure.
5455  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
5456  CharUnits EltSize = TypeInfo.Width / 2;
5457  if (EltSize < SlotSize)
5458  return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
5459  }
5460 
5461  // Otherwise, just use the general rule.
5462  //
5463  // The PPC64 ABI passes some arguments in integer registers, even to variadic
5464  // functions. To allow va_list to use the simple "void*" representation,
5465  // variadic calls allocate space in the argument area for the integer argument
5466  // registers, and variadic functions spill their integer argument registers to
5467  // this area in their prologues. When aggregates smaller than a register are
5468  // passed this way, they are passed in the least significant bits of the
5469  // register, which means that after spilling on big-endian targets they will
5470  // be right-aligned in their argument slot. This is uncommon; for a variety of
5471  // reasons, other big-endian targets don't end up right-aligning aggregate
5472  // types this way, and so right-alignment only applies to fundamental types.
5473  // So on PPC64, we must force the use of right-alignment even for aggregates.
5474  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,
5475  SlotSize, /*AllowHigher*/ true,
5476  /*ForceRightAdjust*/ true);
5477 }
5478 
5479 bool
5480 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
5482  llvm::Value *Address) const {
5483  return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
5484  /*IsAIX*/ false);
5485 }
5486 
5487 bool
5488 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5489  llvm::Value *Address) const {
5490  return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
5491  /*IsAIX*/ false);
5492 }
5493 
5494 //===----------------------------------------------------------------------===//
5495 // AArch64 ABI Implementation
5496 //===----------------------------------------------------------------------===//
5497 
5498 namespace {
5499 
5500 class AArch64ABIInfo : public ABIInfo {
5501 public:
5502  enum ABIKind {
5503  AAPCS = 0,
5504  DarwinPCS,
5505  Win64
5506  };
5507 
5508 private:
5509  ABIKind Kind;
5510 
5511 public:
5512  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) : ABIInfo(CGT), Kind(Kind) {}
5513 
5514 private:
5515  ABIKind getABIKind() const { return Kind; }
5516  bool isDarwinPCS() const { return Kind == DarwinPCS; }
5517 
5518  ABIArgInfo classifyReturnType(QualType RetTy, bool IsVariadic) const;
5519  ABIArgInfo classifyArgumentType(QualType RetTy, bool IsVariadic,
5520  unsigned CallingConvention) const;
5521  ABIArgInfo coerceIllegalVector(QualType Ty) const;
5522  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5523  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5524  uint64_t Members) const override;
5525  bool isZeroLengthBitfieldPermittedInHomogeneousAggregate() const override;
5526 
5527  bool isIllegalVectorType(QualType Ty) const;
5528 
5529  void computeInfo(CGFunctionInfo &FI) const override {
5530  if (!::classifyReturnType(getCXXABI(), FI, *this))
5531  FI.getReturnInfo() =
5533 
5534  for (auto &it : FI.arguments())
5535  it.info = classifyArgumentType(it.type, FI.isVariadic(),
5536  FI.getCallingConvention());
5537  }
5538 
5539  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5540  CodeGenFunction &CGF) const;
5541 
5542  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
5543  CodeGenFunction &CGF) const;
5544 
5545  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5546  QualType Ty) const override {
5547  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5548  if (isa<llvm::ScalableVectorType>(BaseTy))
5549  llvm::report_fatal_error("Passing SVE types to variadic functions is "
5550  "currently not supported");
5551 
5552  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
5553  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
5554  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
5555  }
5556 
5557  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5558  QualType Ty) const override;
5559 
5560  bool allowBFloatArgsAndRet() const override {
5561  return getTarget().hasBFloat16Type();
5562  }
5563 };
5564 
5565 class AArch64SwiftABIInfo : public SwiftABIInfo {
5566 public:
5567  explicit AArch64SwiftABIInfo(CodeGenTypes &CGT)
5568  : SwiftABIInfo(CGT, /*SwiftErrorInRegister=*/true) {}
5569 
5570  bool isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
5571  unsigned NumElts) const override;
5572 };
5573 
5574 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
5575 public:
5576  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
5577  : TargetCodeGenInfo(std::make_unique<AArch64ABIInfo>(CGT, Kind)) {
5578  SwiftInfo = std::make_unique<AArch64SwiftABIInfo>(CGT);
5579  }
5580 
5581  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5582  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
5583  }
5584 
5585  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5586  return 31;
5587  }
5588 
5589  bool doesReturnSlotInterfereWithArgs() const override { return false; }
5590 
5591  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5592  CodeGen::CodeGenModule &CGM) const override {
5593  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5594  if (!FD)
5595  return;
5596 
5597  const auto *TA = FD->getAttr<TargetAttr>();
5598  if (TA == nullptr)
5599  return;
5600 
5602  CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
5603  if (Attr.BranchProtection.empty())
5604  return;
5605 
5607  StringRef Error;
5608  (void)CGM.getTarget().validateBranchProtection(Attr.BranchProtection,
5609  Attr.CPU, BPI, Error);
5610  assert(Error.empty());
5611 
5612  auto *Fn = cast<llvm::Function>(GV);
5613  static const char *SignReturnAddrStr[] = {"none", "non-leaf", "all"};
5614  Fn->addFnAttr("sign-return-address", SignReturnAddrStr[static_cast<int>(BPI.SignReturnAddr)]);
5615 
5617  Fn->addFnAttr("sign-return-address-key",
5619  ? "a_key"
5620  : "b_key");
5621  }
5622 
5623  Fn->addFnAttr("branch-target-enforcement",
5624  BPI.BranchTargetEnforcement ? "true" : "false");
5625  }
5626 
5627  bool isScalarizableAsmOperand(CodeGen::CodeGenFunction &CGF,
5628  llvm::Type *Ty) const override {
5629  if (CGF.getTarget().hasFeature("ls64")) {
5630  auto *ST = dyn_cast<llvm::StructType>(Ty);
5631  if (ST && ST->getNumElements() == 1) {
5632  auto *AT = dyn_cast<llvm::ArrayType>(ST->getElementType(0));
5633  if (AT && AT->getNumElements() == 8 &&
5634  AT->getElementType()->isIntegerTy(64))
5635  return true;
5636  }
5637  }
5639  }
5640 };
5641 
5642 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5643 public:
5644  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
5645  : AArch64TargetCodeGenInfo(CGT, K) {}
5646 
5647  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5648  CodeGen::CodeGenModule &CGM) const override;
5649 
5650  void getDependentLibraryOption(llvm::StringRef Lib,
5651  llvm::SmallString<24> &Opt) const override {
5652  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5653  }
5654 
5655  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5656  llvm::SmallString<32> &Opt) const override {
5657  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5658  }
5659 };
5660 
5661 void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
5662  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5663  AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5664  if (GV->isDeclaration())
5665  return;
5666  addStackProbeTargetAttributes(D, GV, CGM);
5667 }
5668 }
5669 
5670 ABIArgInfo AArch64ABIInfo::coerceIllegalVector(QualT