clang 22.0.0git
AArch64.cpp
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1//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements AArch64 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64.h"
18#include "llvm/ADT/APSInt.h"
19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/TargetParser/AArch64TargetParser.h"
22#include "llvm/TargetParser/ARMTargetParserCommon.h"
23#include <optional>
24
25using namespace clang;
26using namespace clang::targets;
27
28static constexpr int NumNeonBuiltins =
30static constexpr int NumFp16Builtins =
32static constexpr int NumSVEBuiltins =
34static constexpr int NumSVENeonBridgeBuiltins =
37static constexpr int NumAArch64Builtins =
39static constexpr int NumBuiltins =
41static_assert(NumBuiltins ==
44
45namespace clang {
46namespace NEON {
47#define GET_NEON_BUILTIN_STR_TABLE
48#include "clang/Basic/arm_neon.inc"
49#undef GET_NEON_BUILTIN_STR_TABLE
50
51static constexpr std::array<Builtin::Info, NumNeonBuiltins> BuiltinInfos = {
52#define GET_NEON_BUILTIN_INFOS
53#include "clang/Basic/arm_neon.inc"
54#undef GET_NEON_BUILTIN_INFOS
55};
56
57namespace FP16 {
58#define GET_NEON_BUILTIN_STR_TABLE
59#include "clang/Basic/arm_fp16.inc"
60#undef GET_NEON_BUILTIN_STR_TABLE
61
62static constexpr std::array<Builtin::Info, NumFp16Builtins> BuiltinInfos = {
63#define GET_NEON_BUILTIN_INFOS
64#include "clang/Basic/arm_fp16.inc"
65#undef GET_NEON_BUILTIN_INFOS
66};
67} // namespace FP16
68} // namespace NEON
69
70namespace SVE {
71#define GET_SVE_BUILTIN_STR_TABLE
72#include "clang/Basic/arm_sve_builtins.inc"
73#undef GET_SVE_BUILTIN_STR_TABLE
74
75static constexpr std::array<Builtin::Info, NumSVEBuiltins> BuiltinInfos = {
76#define GET_SVE_BUILTIN_INFOS
77#include "clang/Basic/arm_sve_builtins.inc"
78#undef GET_SVE_BUILTIN_INFOS
79};
80} // namespace SVE
81
82namespace SME {
83#define GET_SME_BUILTIN_STR_TABLE
84#include "clang/Basic/arm_sme_builtins.inc"
85#undef GET_SME_BUILTIN_STR_TABLE
86
87static constexpr std::array<Builtin::Info, NumSMEBuiltins> BuiltinInfos = {
88#define GET_SME_BUILTIN_INFOS
89#include "clang/Basic/arm_sme_builtins.inc"
90#undef GET_SME_BUILTIN_INFOS
91};
92} // namespace SME
93} // namespace clang
94
95static constexpr llvm::StringTable BuiltinSVENeonBridgeStrings =
97#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
98#define GET_SVE_BUILTINS
99#include "clang/Basic/BuiltinsAArch64NeonSVEBridge.def"
100#undef GET_SVE_BUILTINS
101#undef TARGET_BUILTIN
102 ;
103static constexpr llvm::StringTable BuiltinAArch64Strings =
105#define BUILTIN CLANG_BUILTIN_STR_TABLE
106#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
107#define TARGET_HEADER_BUILTIN CLANG_TARGET_HEADER_BUILTIN_STR_TABLE
108#include "clang/Basic/BuiltinsAArch64.def"
109 ;
110
111static constexpr auto BuiltinSVENeonBridgeInfos =
113#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
114#define GET_SVE_BUILTINS
115#include "clang/Basic/BuiltinsAArch64NeonSVEBridge.def"
116#undef GET_SVE_BUILTINS
117#undef TARGET_BUILTIN
118 });
119static constexpr auto BuiltinAArch64Infos =
121#define BUILTIN CLANG_BUILTIN_ENTRY
122#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
123#define LANGBUILTIN CLANG_LANGBUILTIN_ENTRY
124#define TARGET_HEADER_BUILTIN CLANG_TARGET_HEADER_BUILTIN_ENTRY
125#include "clang/Basic/BuiltinsAArch64.def"
126 });
127
128AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
129 const TargetOptions &Opts)
130 : TargetInfo(Triple), ABI("aapcs") {
131 if (getTriple().isOSOpenBSD()) {
134 } else {
135 if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD())
137
140 }
141
143
144 // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
145 HasFastHalfType = true;
146 HalfArgsAndReturns = true;
147 HasFloat16 = true;
148 HasStrictFP = true;
149
150 if (Triple.isArch64Bit())
152 else
154
155 BitIntMaxAlign = 128;
156 MaxVectorAlign = 128;
159
161 LongDoubleFormat = &llvm::APFloat::IEEEquad();
162
164 BFloat16Format = &llvm::APFloat::BFloat();
165
166 // Make __builtin_ms_va_list available.
167 HasBuiltinMSVaList = true;
168
169 // Make the Neon ACLE and SVE types available. Note that this deliberately
170 // doesn't depend on SveMode, since in principle it should be possible to turn
171 // SVE on and off within a translation unit. It should also be possible
172 // to compile the global declaration:
173 //
174 // __SVInt8_t *ptr;
175 //
176 // even without SVE.
177 HasAArch64ACLETypes = true;
178
179 // {} in inline assembly are neon specifiers, not assembly variant
180 // specifiers.
181 NoAsmVariants = true;
182
183 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
184 // contributes to the alignment of the containing aggregate in the same way
185 // a plain (non bit-field) member of that type would, without exception for
186 // zero-sized or anonymous bit-fields."
187 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
189
190 // AAPCS64 allows any "fundamental integer data type" to be used for
191 // over-sized bitfields, which includes 128-bit integers.
193
194 HasUnalignedAccess = true;
195
196 // AArch64 targets default to using the ARM C++ ABI.
197 TheCXXABI.set(TargetCXXABI::GenericAArch64);
198
199 if (Triple.getOS() == llvm::Triple::Linux)
200 this->MCountName = "\01_mcount";
201 else if (Triple.getOS() == llvm::Triple::UnknownOS)
202 this->MCountName =
203 Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
204}
205
206StringRef AArch64TargetInfo::getABI() const { return ABI; }
207
208bool AArch64TargetInfo::setABI(const std::string &Name) {
209 if (Name != "aapcs" && Name != "aapcs-soft" && Name != "darwinpcs" &&
210 Name != "pauthtest")
211 return false;
212
213 ABI = Name;
214 return true;
215}
216
218 if (hasFeature("fp") && ABI == "aapcs-soft") {
219 // aapcs-soft is not allowed for targets with an FPU, to avoid there being
220 // two incomatible ABIs.
221 Diags.Report(diag::err_target_unsupported_abi_with_fpu) << ABI;
222 return false;
223 }
224 if (getTriple().getEnvironment() == llvm::Triple::PAuthTest &&
225 getTriple().getOS() != llvm::Triple::Linux) {
226 Diags.Report(diag::err_target_unsupported_abi_for_triple)
227 << getTriple().getEnvironmentName() << getTriple().getTriple();
228 return false;
229 }
230 return true;
231}
232
234 StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {
235 if (RegName == "sp") {
236 HasSizeMismatch = RegSize != 64;
237 return true;
238 }
239 if (RegName.starts_with("w"))
240 HasSizeMismatch = RegSize != 32;
241 else if (RegName.starts_with("x"))
242 HasSizeMismatch = RegSize != 64;
243 else
244 return false;
245 StringRef RegNum = RegName.drop_front();
246 // Check if the register is reserved. See also
247 // AArch64TargetLowering::getRegisterByName().
248 return RegNum == "0" ||
249 (RegNum == "18" &&
250 llvm::AArch64::isX18ReservedByDefault(getTriple())) ||
251 getTargetOpts().FeatureMap.lookup(("reserve-x" + RegNum).str());
252}
253
254bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
256 const LangOptions &LO,
257 StringRef &Err) const {
258 llvm::ARM::ParsedBranchProtection PBP;
259 if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err, HasPAuthLR))
260 return false;
261
262 // GCS is currently untested with ptrauth-returns, but enabling this could be
263 // allowed in future after testing with a suitable system.
264 if (LO.PointerAuthReturns &&
265 (PBP.Scope != "none" || PBP.BranchProtectionPAuthLR ||
266 PBP.GuardedControlStack))
267 return false;
268
269 BPI.SignReturnAddr =
270 llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
274
275 if (PBP.Key == "a_key")
277 else
279
280 BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
281 BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
282 BPI.GuardedControlStack = PBP.GuardedControlStack;
283 return true;
284}
285
286bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
287 return llvm::AArch64::parseCpu(Name).has_value();
288}
289
290bool AArch64TargetInfo::setCPU(const std::string &Name) {
291 return isValidCPUName(Name);
292}
293
295 SmallVectorImpl<StringRef> &Values) const {
296 llvm::AArch64::fillValidCPUArchList(Values);
297}
298
300 MacroBuilder &Builder) const {
301 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
302}
303
305 MacroBuilder &Builder) const {
306 // Also include the ARMv8.1 defines
307 getTargetDefinesARMV81A(Opts, Builder);
308}
309
311 MacroBuilder &Builder) const {
312 Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
313 Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
314 // Also include the Armv8.2 defines
315 getTargetDefinesARMV82A(Opts, Builder);
316}
317
319 MacroBuilder &Builder) const {
320 // Also include the Armv8.3 defines
321 getTargetDefinesARMV83A(Opts, Builder);
322}
323
325 MacroBuilder &Builder) const {
326 Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
327 // Also include the Armv8.4 defines
328 getTargetDefinesARMV84A(Opts, Builder);
329}
330
332 MacroBuilder &Builder) const {
333 // Also include the Armv8.5 defines
334 // FIXME: Armv8.6 makes the following extensions mandatory:
335 // - __ARM_FEATURE_BF16
336 // - __ARM_FEATURE_MATMUL_INT8
337 // Handle them here.
338 getTargetDefinesARMV85A(Opts, Builder);
339}
340
342 MacroBuilder &Builder) const {
343 // Also include the Armv8.6 defines
344 getTargetDefinesARMV86A(Opts, Builder);
345}
346
348 MacroBuilder &Builder) const {
349 // Also include the Armv8.7 defines
350 getTargetDefinesARMV87A(Opts, Builder);
351}
352
354 MacroBuilder &Builder) const {
355 // Also include the Armv8.8 defines
356 getTargetDefinesARMV88A(Opts, Builder);
357}
358
360 MacroBuilder &Builder) const {
361 // Armv9-A maps to Armv8.5-A
362 getTargetDefinesARMV85A(Opts, Builder);
363}
364
366 MacroBuilder &Builder) const {
367 // Armv9.1-A maps to Armv8.6-A
368 getTargetDefinesARMV86A(Opts, Builder);
369}
370
372 MacroBuilder &Builder) const {
373 // Armv9.2-A maps to Armv8.7-A
374 getTargetDefinesARMV87A(Opts, Builder);
375}
376
378 MacroBuilder &Builder) const {
379 // Armv9.3-A maps to Armv8.8-A
380 getTargetDefinesARMV88A(Opts, Builder);
381}
382
384 MacroBuilder &Builder) const {
385 // Armv9.4-A maps to Armv8.9-A
386 getTargetDefinesARMV89A(Opts, Builder);
387}
388
390 MacroBuilder &Builder) const {
391 // Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A.
392 getTargetDefinesARMV94A(Opts, Builder);
393}
394
396 MacroBuilder &Builder) const {
397 // Armv9.6-A does not have a v8.* equivalent, but is a superset of v9.5-A.
398 getTargetDefinesARMV95A(Opts, Builder);
399}
400
402 MacroBuilder &Builder) const {
403 // Target identification.
404 if (getTriple().isWindowsArm64EC()) {
405 // Define the same set of macros as would be defined on x86_64 to ensure that
406 // ARM64EC datatype layouts match those of x86_64 compiled code
407 Builder.defineMacro("__amd64__");
408 Builder.defineMacro("__amd64");
409 Builder.defineMacro("__x86_64");
410 Builder.defineMacro("__x86_64__");
411 Builder.defineMacro("__arm64ec__");
412 } else {
413 Builder.defineMacro("__aarch64__");
414 }
415
416 // Inline assembly supports AArch64 flag outputs.
417 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
418
419 std::string CodeModel = getTargetOpts().CodeModel;
420 if (CodeModel == "default")
421 CodeModel = "small";
422 for (char &c : CodeModel)
423 c = toupper(c);
424 Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
425
426 // ACLE predefines. Many can only have one possible value on v8 AArch64.
427 Builder.defineMacro("__ARM_ACLE_VERSION(year, quarter, patch)",
428 "(100 * (year) + 10 * (quarter) + (patch))");
429#define ARM_ACLE_VERSION(Y, Q, P) (100 * (Y) + 10 * (Q) + (P))
430 Builder.defineMacro("__ARM_ACLE", Twine(ARM_ACLE_VERSION(2024, 2, 0)));
431 Builder.defineMacro("__FUNCTION_MULTI_VERSIONING_SUPPORT_LEVEL",
432 Twine(ARM_ACLE_VERSION(2024, 3, 0)));
433#undef ARM_ACLE_VERSION
434 Builder.defineMacro("__ARM_ARCH",
435 std::to_string(ArchInfo->Version.getMajor()));
436 Builder.defineMacro("__ARM_ARCH_PROFILE",
437 std::string("'") + (char)ArchInfo->Profile + "'");
438
439 Builder.defineMacro("__ARM_64BIT_STATE", "1");
440 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
441 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
442
443 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
444 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
445 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
446 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
447 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
448 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
449 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
450
451 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
452
453 // These macros are set when Clang can parse declarations with these
454 // attributes.
455 Builder.defineMacro("__ARM_STATE_ZA", "1");
456 Builder.defineMacro("__ARM_STATE_ZT0", "1");
457
458 // 0xe implies support for half, single and double precision operations.
459 if (FPU & FPUMode)
460 Builder.defineMacro("__ARM_FP", "0xE");
461
462 // PCS specifies this for SysV variants, which is all we support. Other ABIs
463 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
464 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
465 Builder.defineMacro("__ARM_FP16_ARGS", "1");
466
467 // Clang supports arm_neon_sve_bridge.h
468 Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
469
470 if (Opts.UnsafeFPMath)
471 Builder.defineMacro("__ARM_FP_FAST", "1");
472
473 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
474 Twine(Opts.WCharSize ? Opts.WCharSize : 4));
475
476 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
477
478 if (FPU & NeonMode) {
479 Builder.defineMacro("__ARM_NEON", "1");
480 // 64-bit NEON supports half, single and double precision operations.
481 Builder.defineMacro("__ARM_NEON_FP", "0xE");
482 }
483
484 if (FPU & SveMode)
485 Builder.defineMacro("__ARM_FEATURE_SVE", "1");
486
487 if (HasSVE2)
488 Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
489
490 if (HasSVE2p1)
491 Builder.defineMacro("__ARM_FEATURE_SVE2p1", "1");
492
493 if (HasSVE2 && HasSVEAES)
494 Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
495
496 if (HasSVE2 && HasSVEBitPerm)
497 Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
498
499 if (HasSVE2 && HasSVE2SHA3)
500 Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
501
502 if (HasSVE2 && HasSVE2SM4)
503 Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
504
505 if (HasSVEB16B16)
506 Builder.defineMacro("__ARM_FEATURE_SVE_B16B16", "1");
507
508 if (HasSME) {
509 Builder.defineMacro("__ARM_FEATURE_SME");
510 Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1");
511 }
512
513 if (HasSME2)
514 Builder.defineMacro("__ARM_FEATURE_SME2", "1");
515
516 if (HasSME2p1)
517 Builder.defineMacro("__ARM_FEATURE_SME2p1", "1");
518
519 if (HasSMEF16F16)
520 Builder.defineMacro("__ARM_FEATURE_SME_F16F16", "1");
521
522 if (HasSMEB16B16)
523 Builder.defineMacro("__ARM_FEATURE_SME_B16B16", "1");
524
525 if (HasFP8)
526 Builder.defineMacro("__ARM_FEATURE_FP8", "1");
527
528 if (HasFP8FMA)
529 Builder.defineMacro("__ARM_FEATURE_FP8FMA", "1");
530
531 if (HasFP8DOT2)
532 Builder.defineMacro("__ARM_FEATURE_FP8DOT2", "1");
533
534 if (HasFP8DOT4)
535 Builder.defineMacro("__ARM_FEATURE_FP8DOT4", "1");
536
537 if (HasSSVE_FP8DOT2)
538 Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT2", "1");
539
540 if (HasSSVE_FP8DOT4)
541 Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT4", "1");
542
543 if (HasSSVE_FP8FMA)
544 Builder.defineMacro("__ARM_FEATURE_SSVE_FP8FMA", "1");
545
546 if (HasSME_F8F32)
547 Builder.defineMacro("__ARM_FEATURE_SME_F8F32", "1");
548
549 if (HasSME_F8F16)
550 Builder.defineMacro("__ARM_FEATURE_SME_F8F16", "1");
551
552 if (HasCRC)
553 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
554
555 if (HasCSSC)
556 Builder.defineMacro("__ARM_FEATURE_CSSC", "1");
557
558 if (HasRCPC3)
559 Builder.defineMacro("__ARM_FEATURE_RCPC", "3");
560 else if (HasRCPC)
561 Builder.defineMacro("__ARM_FEATURE_RCPC", "1");
562
563 if (HasFMV)
564 Builder.defineMacro("__HAVE_FUNCTION_MULTI_VERSIONING", "1");
565
566 // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
567 // macros for AES, SHA2, SHA3 and SM4
568 if (HasAES && HasSHA2)
569 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
570
571 if (HasAES)
572 Builder.defineMacro("__ARM_FEATURE_AES", "1");
573
574 if (HasSHA2)
575 Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
576
577 if (HasSHA3) {
578 Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
579 Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
580 }
581
582 if (HasSM4) {
583 Builder.defineMacro("__ARM_FEATURE_SM3", "1");
584 Builder.defineMacro("__ARM_FEATURE_SM4", "1");
585 }
586
587 if (HasPAuth)
588 Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
589
590 if (HasPAuthLR)
591 Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
592
593 if (HasBTI)
594 Builder.defineMacro("__ARM_FEATURE_BTI", "1");
595
597 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
598
599 if ((FPU & NeonMode) && HasFullFP16)
600 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
601 if (HasFullFP16)
602 Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
603
604 if (HasDotProd)
605 Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
606
607 if (HasMTE)
608 Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
609
610 if (HasTME)
611 Builder.defineMacro("__ARM_FEATURE_TME", "1");
612
613 if (HasMatMul)
614 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
615
616 if (HasLSE)
617 Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
618
619 if (HasBFloat16) {
620 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
621 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
622 Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
623 Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
624 }
625
626 if ((FPU & SveMode) && HasBFloat16) {
627 Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
628 }
629
630 if ((FPU & SveMode) && HasMatmulFP64)
631 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
632
633 if ((FPU & SveMode) && HasMatmulFP32)
634 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
635
636 if ((FPU & SveMode) && HasMatMul)
637 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
638
639 if ((FPU & NeonMode) && HasFP16FML)
640 Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
641
642 if (Opts.hasSignReturnAddress()) {
643 // Bitmask:
644 // 0: Protection using the A key
645 // 1: Protection using the B key
646 // 2: Protection including leaf functions
647 // 3: Protection using PC as a diversifier
648 unsigned Value = 0;
649
651 Value |= (1 << 0);
652 else
653 Value |= (1 << 1);
654
656 Value |= (1 << 2);
657
658 if (Opts.BranchProtectionPAuthLR)
659 Value |= (1 << 3);
660
661 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
662 }
663
664 if (Opts.BranchTargetEnforcement)
665 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
666
667 if (Opts.GuardedControlStack)
668 Builder.defineMacro("__ARM_FEATURE_GCS_DEFAULT", "1");
669
670 if (HasLS64)
671 Builder.defineMacro("__ARM_FEATURE_LS64", "1");
672
673 if (HasRandGen)
674 Builder.defineMacro("__ARM_FEATURE_RNG", "1");
675
676 if (HasMOPS)
677 Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
678
679 if (HasD128)
680 Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
681
682 if (HasGCS)
683 Builder.defineMacro("__ARM_FEATURE_GCS", "1");
684
685 if (*ArchInfo == llvm::AArch64::ARMV8_1A)
686 getTargetDefinesARMV81A(Opts, Builder);
687 else if (*ArchInfo == llvm::AArch64::ARMV8_2A)
688 getTargetDefinesARMV82A(Opts, Builder);
689 else if (*ArchInfo == llvm::AArch64::ARMV8_3A)
690 getTargetDefinesARMV83A(Opts, Builder);
691 else if (*ArchInfo == llvm::AArch64::ARMV8_4A)
692 getTargetDefinesARMV84A(Opts, Builder);
693 else if (*ArchInfo == llvm::AArch64::ARMV8_5A)
694 getTargetDefinesARMV85A(Opts, Builder);
695 else if (*ArchInfo == llvm::AArch64::ARMV8_6A)
696 getTargetDefinesARMV86A(Opts, Builder);
697 else if (*ArchInfo == llvm::AArch64::ARMV8_7A)
698 getTargetDefinesARMV87A(Opts, Builder);
699 else if (*ArchInfo == llvm::AArch64::ARMV8_8A)
700 getTargetDefinesARMV88A(Opts, Builder);
701 else if (*ArchInfo == llvm::AArch64::ARMV8_9A)
702 getTargetDefinesARMV89A(Opts, Builder);
703 else if (*ArchInfo == llvm::AArch64::ARMV9A)
704 getTargetDefinesARMV9A(Opts, Builder);
705 else if (*ArchInfo == llvm::AArch64::ARMV9_1A)
706 getTargetDefinesARMV91A(Opts, Builder);
707 else if (*ArchInfo == llvm::AArch64::ARMV9_2A)
708 getTargetDefinesARMV92A(Opts, Builder);
709 else if (*ArchInfo == llvm::AArch64::ARMV9_3A)
710 getTargetDefinesARMV93A(Opts, Builder);
711 else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
712 getTargetDefinesARMV94A(Opts, Builder);
713 else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
714 getTargetDefinesARMV95A(Opts, Builder);
715 else if (*ArchInfo == llvm::AArch64::ARMV9_6A)
716 getTargetDefinesARMV96A(Opts, Builder);
717
718 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8|16) builtins work.
719 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
720 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
721 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
722 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
723 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
724
725 // Allow detection of fast FMA support.
726 Builder.defineMacro("__FP_FAST_FMA", "1");
727 Builder.defineMacro("__FP_FAST_FMAF", "1");
728
729 // C/C++ operators work on both VLS and VLA SVE types
730 if (FPU & SveMode)
731 Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS", "2");
732
733 if (Opts.VScaleMin && Opts.VScaleMin == Opts.VScaleMax) {
734 Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
735 }
736}
737
740 return {
741 {&NEON::BuiltinStrings, NEON::BuiltinInfos, "__builtin_neon_"},
742 {&NEON::FP16::BuiltinStrings, NEON::FP16::BuiltinInfos,
743 "__builtin_neon_"},
744 {&SVE::BuiltinStrings, SVE::BuiltinInfos, "__builtin_sve_"},
746 {&SME::BuiltinStrings, SME::BuiltinInfos, "__builtin_sme_"},
748 };
749}
750
751std::optional<std::pair<unsigned, unsigned>>
753 ArmStreamingKind Mode,
754 llvm::StringMap<bool> *FeatureMap) const {
755 if (Mode == ArmStreamingKind::NotStreaming &&
756 (LangOpts.VScaleMin || LangOpts.VScaleMax))
757 return std::pair<unsigned, unsigned>(
758 LangOpts.VScaleMin ? LangOpts.VScaleMin : 1,
759 LangOpts.VScaleMax ? LangOpts.VScaleMax : 16);
760
761 if (Mode == ArmStreamingKind::Streaming &&
762 (LangOpts.VScaleStreamingMin || LangOpts.VScaleStreamingMax))
763 return std::pair<unsigned, unsigned>(
764 LangOpts.VScaleStreamingMin ? LangOpts.VScaleStreamingMin : 1,
765 LangOpts.VScaleStreamingMax ? LangOpts.VScaleStreamingMax : 16);
766
768 ((LangOpts.VScaleMin && LangOpts.VScaleStreamingMin) ||
769 (LangOpts.VScaleMax && LangOpts.VScaleStreamingMax))) {
770 unsigned Min =
771 std::min(LangOpts.VScaleMin ? LangOpts.VScaleMin : 1,
772 LangOpts.VScaleStreamingMin ? LangOpts.VScaleStreamingMin : 1);
773 unsigned Max = std::max(
774 LangOpts.VScaleMax ? LangOpts.VScaleMax : 16,
775 LangOpts.VScaleStreamingMax ? LangOpts.VScaleStreamingMax : 16);
776 return std::pair(Min, Max);
777 }
778
779 if (hasFeature("sve") || (FeatureMap && (FeatureMap->lookup("sve"))))
780 return std::pair<unsigned, unsigned>(1, 16);
781
782 if (Mode == ArmStreamingKind::Streaming &&
783 (hasFeature("sme") || (FeatureMap && (FeatureMap->lookup("sme")))))
784 return std::pair<unsigned, unsigned>(1, 16);
785
786 return std::nullopt;
787}
788
789llvm::APInt
791 return llvm::AArch64::getFMVPriority(Features);
792}
793
795 // FMV extensions which imply no backend features do not affect codegen.
796 if (auto Ext = llvm::AArch64::parseFMVExtension(Name))
797 return Ext->ID.has_value();
798 return false;
799}
800
801bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
802 // CPU features might be separated by '+', extract them and check
804 FeatureStr.split(Features, "+");
805 for (auto &Feature : Features)
806 if (!llvm::AArch64::parseFMVExtension(Feature.trim()).has_value())
807 return false;
808 return true;
809}
810
812 return llvm::StringSwitch<bool>(Feature)
813 .Cases("aarch64", "arm64", "arm", true)
814 .Case("fmv", HasFMV)
815 .Case("fp", FPU & FPUMode)
816 .Cases("neon", "simd", FPU & NeonMode)
817 .Case("jscvt", HasJSCVT)
818 .Case("fcma", HasFCMA)
819 .Case("rng", HasRandGen)
820 .Case("flagm", HasFlagM)
821 .Case("flagm2", HasAlternativeNZCV)
822 .Case("fp16fml", HasFP16FML)
823 .Case("dotprod", HasDotProd)
824 .Case("sm4", HasSM4)
825 .Case("rdm", HasRDM)
826 .Case("lse", HasLSE)
827 .Case("crc", HasCRC)
828 .Case("cssc", HasCSSC)
829 .Case("sha2", HasSHA2)
830 .Case("sha3", HasSHA3)
831 .Cases("aes", "pmull", HasAES)
832 .Cases("fp16", "fullfp16", HasFullFP16)
833 .Case("dit", HasDIT)
834 .Case("dpb", HasCCPP)
835 .Case("dpb2", HasCCDP)
836 .Case("rcpc", HasRCPC)
837 .Case("frintts", HasFRInt3264)
838 .Case("i8mm", HasMatMul)
839 .Case("bf16", HasBFloat16)
840 .Case("sve", FPU & SveMode)
841 .Case("sve-b16b16", HasSVEB16B16)
842 .Case("f32mm", FPU & SveMode && HasMatmulFP32)
843 .Case("f64mm", FPU & SveMode && HasMatmulFP64)
844 .Case("sve2", FPU & SveMode && HasSVE2)
845 .Case("sve-aes", HasSVEAES)
846 .Case("sve-bitperm", FPU & HasSVEBitPerm)
847 .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
848 .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
849 .Case("sve2p1", FPU & SveMode && HasSVE2p1)
850 .Case("sme", HasSME)
851 .Case("sme2", HasSME2)
852 .Case("sme2p1", HasSME2p1)
853 .Case("sme-f64f64", HasSMEF64F64)
854 .Case("sme-i16i64", HasSMEI16I64)
855 .Case("sme-fa64", HasSMEFA64)
856 .Case("sme-f16f16", HasSMEF16F16)
857 .Case("sme-b16b16", HasSMEB16B16)
858 .Case("memtag", HasMTE)
859 .Case("sb", HasSB)
860 .Case("predres", HasPredRes)
861 .Cases("ssbs", "ssbs2", HasSSBS)
862 .Case("bti", HasBTI)
863 .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
864 .Case("wfxt", HasWFxT)
865 .Case("rcpc3", HasRCPC3)
866 .Case("fp8", HasFP8)
867 .Case("fp8fma", HasFP8FMA)
868 .Case("fp8dot2", HasFP8DOT2)
869 .Case("fp8dot4", HasFP8DOT4)
870 .Case("ssve-fp8dot2", HasSSVE_FP8DOT2)
871 .Case("ssve-fp8dot4", HasSSVE_FP8DOT4)
872 .Case("ssve-fp8fma", HasSSVE_FP8FMA)
873 .Case("sme-f8f32", HasSME_F8F32)
874 .Case("sme-f8f16", HasSME_F8F16)
875 .Default(false);
876}
877
878void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
879 StringRef Name, bool Enabled) const {
880 Features[Name] = Enabled;
881 // If the feature is an architecture feature (like v8.2a), add all previous
882 // architecture versions and any dependant target features.
883 const std::optional<llvm::AArch64::ArchInfo> ArchInfo =
884 llvm::AArch64::ArchInfo::findBySubArch(Name);
885
886 if (!ArchInfo)
887 return; // Not an architecture, nothing more to do.
888
889 // Disabling an architecture feature does not affect dependent features
890 if (!Enabled)
891 return;
892
893 for (const auto *OtherArch : llvm::AArch64::ArchInfos)
894 if (ArchInfo->implies(*OtherArch))
895 Features[OtherArch->getSubArch()] = true;
896
897 // Set any features implied by the architecture
898 std::vector<StringRef> CPUFeats;
899 if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) {
900 for (auto F : CPUFeats) {
901 assert(F[0] == '+' && "Expected + in target feature!");
902 Features[F.drop_front(1)] = true;
903 }
904 }
905}
906
907bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
908 DiagnosticsEngine &Diags) {
909 for (const auto &Feature : Features) {
910 if (Feature == "-fp-armv8")
911 HasNoFP = true;
912 if (Feature == "-neon")
913 HasNoNeon = true;
914 if (Feature == "-sve")
915 HasNoSVE = true;
916
917 if (Feature == "+neon" || Feature == "+fp-armv8")
918 FPU |= NeonMode;
919 if (Feature == "+jscvt") {
920 HasJSCVT = true;
921 FPU |= NeonMode;
922 }
923 if (Feature == "+fcma") {
924 HasFCMA = true;
925 FPU |= NeonMode;
926 }
927
928 if (Feature == "+sve") {
929 FPU |= NeonMode;
930 FPU |= SveMode;
931 HasFullFP16 = true;
932 }
933 if (Feature == "+sve2") {
934 FPU |= NeonMode;
935 FPU |= SveMode;
936 HasFullFP16 = true;
937 HasSVE2 = true;
938 }
939 if (Feature == "+sve2p1") {
940 FPU |= NeonMode;
941 FPU |= SveMode;
942 HasFullFP16 = true;
943 HasSVE2 = true;
944 HasSVE2p1 = true;
945 }
946 if (Feature == "+sve-aes") {
947 FPU |= NeonMode;
948 HasFullFP16 = true;
949 HasSVEAES = true;
950 }
951 if (Feature == "+sve2-sha3") {
952 FPU |= NeonMode;
953 FPU |= SveMode;
954 HasFullFP16 = true;
955 HasSVE2 = true;
956 HasSVE2SHA3 = true;
957 }
958 if (Feature == "+sve2-sm4") {
959 FPU |= NeonMode;
960 FPU |= SveMode;
961 HasFullFP16 = true;
962 HasSVE2 = true;
963 HasSVE2SM4 = true;
964 }
965 if (Feature == "+sve-b16b16")
966 HasSVEB16B16 = true;
967 if (Feature == "+sve-bitperm") {
968 FPU |= NeonMode;
969 HasFullFP16 = true;
970 HasSVEBitPerm = true;
971 }
972 if (Feature == "+f32mm") {
973 FPU |= NeonMode;
974 FPU |= SveMode;
975 HasFullFP16 = true;
976 HasMatmulFP32 = true;
977 }
978 if (Feature == "+f64mm") {
979 FPU |= NeonMode;
980 FPU |= SveMode;
981 HasFullFP16 = true;
982 HasMatmulFP64 = true;
983 }
984 if (Feature == "+sme") {
985 HasSME = true;
986 HasBFloat16 = true;
987 HasFullFP16 = true;
988 }
989 if (Feature == "+sme2") {
990 HasSME = true;
991 HasSME2 = true;
992 HasBFloat16 = true;
993 HasFullFP16 = true;
994 }
995 if (Feature == "+sme2p1") {
996 HasSME = true;
997 HasSME2 = true;
998 HasSME2p1 = true;
999 HasBFloat16 = true;
1000 HasFullFP16 = true;
1001 }
1002 if (Feature == "+sme-f64f64") {
1003 HasSME = true;
1004 HasSMEF64F64 = true;
1005 HasBFloat16 = true;
1006 HasFullFP16 = true;
1007 }
1008 if (Feature == "+sme-i16i64") {
1009 HasSME = true;
1010 HasSMEI16I64 = true;
1011 HasBFloat16 = true;
1012 HasFullFP16 = true;
1013 }
1014 if (Feature == "+sme-fa64") {
1015 FPU |= NeonMode;
1016 FPU |= SveMode;
1017 HasSME = true;
1018 HasSVE2 = true;
1019 HasSMEFA64 = true;
1020 }
1021 if (Feature == "+sme-f16f16") {
1022 HasSME = true;
1023 HasSME2 = true;
1024 HasBFloat16 = true;
1025 HasFullFP16 = true;
1026 HasSMEF16F16 = true;
1027 }
1028 if (Feature == "+sme-b16b16") {
1029 HasSME = true;
1030 HasSME2 = true;
1031 HasBFloat16 = true;
1032 HasFullFP16 = true;
1033 HasSVEB16B16 = true;
1034 HasSMEB16B16 = true;
1035 }
1036
1037 if (Feature == "+fp8")
1038 HasFP8 = true;
1039 if (Feature == "+fp8fma")
1040 HasFP8FMA = true;
1041 if (Feature == "+fp8dot2")
1042 HasFP8DOT2 = true;
1043 if (Feature == "+fp8dot4")
1044 HasFP8DOT4 = true;
1045 if (Feature == "+ssve-fp8dot2")
1046 HasSSVE_FP8DOT2 = true;
1047 if (Feature == "+ssve-fp8dot4")
1048 HasSSVE_FP8DOT4 = true;
1049 if (Feature == "+ssve-fp8fma")
1050 HasSSVE_FP8FMA = true;
1051 if (Feature == "+sme-f8f32")
1052 HasSME_F8F32 = true;
1053 if (Feature == "+sme-f8f16")
1054 HasSME_F8F16 = true;
1055 if (Feature == "+sb")
1056 HasSB = true;
1057 if (Feature == "+predres")
1058 HasPredRes = true;
1059 if (Feature == "+ssbs")
1060 HasSSBS = true;
1061 if (Feature == "+bti")
1062 HasBTI = true;
1063 if (Feature == "+wfxt")
1064 HasWFxT = true;
1065 if (Feature == "-fmv")
1066 HasFMV = false;
1067 if (Feature == "+crc")
1068 HasCRC = true;
1069 if (Feature == "+rcpc")
1070 HasRCPC = true;
1071 if (Feature == "+aes") {
1072 FPU |= NeonMode;
1073 HasAES = true;
1074 }
1075 if (Feature == "+sha2") {
1076 FPU |= NeonMode;
1077 HasSHA2 = true;
1078 }
1079 if (Feature == "+sha3") {
1080 FPU |= NeonMode;
1081 HasSHA2 = true;
1082 HasSHA3 = true;
1083 }
1084 if (Feature == "+rdm") {
1085 FPU |= NeonMode;
1086 HasRDM = true;
1087 }
1088 if (Feature == "+dit")
1089 HasDIT = true;
1090 if (Feature == "+cccp")
1091 HasCCPP = true;
1092 if (Feature == "+ccdp") {
1093 HasCCPP = true;
1094 HasCCDP = true;
1095 }
1096 if (Feature == "+fptoint")
1097 HasFRInt3264 = true;
1098 if (Feature == "+sm4") {
1099 FPU |= NeonMode;
1100 HasSM4 = true;
1101 }
1102 if (Feature == "+strict-align")
1103 HasUnalignedAccess = false;
1104
1105 // All predecessor archs are added but select the latest one for ArchKind.
1106 if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version)
1107 ArchInfo = &llvm::AArch64::ARMV8A;
1108 if (Feature == "+v8.1a" &&
1109 ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version)
1110 ArchInfo = &llvm::AArch64::ARMV8_1A;
1111 if (Feature == "+v8.2a" &&
1112 ArchInfo->Version < llvm::AArch64::ARMV8_2A.Version)
1113 ArchInfo = &llvm::AArch64::ARMV8_2A;
1114 if (Feature == "+v8.3a" &&
1115 ArchInfo->Version < llvm::AArch64::ARMV8_3A.Version)
1116 ArchInfo = &llvm::AArch64::ARMV8_3A;
1117 if (Feature == "+v8.4a" &&
1118 ArchInfo->Version < llvm::AArch64::ARMV8_4A.Version)
1119 ArchInfo = &llvm::AArch64::ARMV8_4A;
1120 if (Feature == "+v8.5a" &&
1121 ArchInfo->Version < llvm::AArch64::ARMV8_5A.Version)
1122 ArchInfo = &llvm::AArch64::ARMV8_5A;
1123 if (Feature == "+v8.6a" &&
1124 ArchInfo->Version < llvm::AArch64::ARMV8_6A.Version)
1125 ArchInfo = &llvm::AArch64::ARMV8_6A;
1126 if (Feature == "+v8.7a" &&
1127 ArchInfo->Version < llvm::AArch64::ARMV8_7A.Version)
1128 ArchInfo = &llvm::AArch64::ARMV8_7A;
1129 if (Feature == "+v8.8a" &&
1130 ArchInfo->Version < llvm::AArch64::ARMV8_8A.Version)
1131 ArchInfo = &llvm::AArch64::ARMV8_8A;
1132 if (Feature == "+v8.9a" &&
1133 ArchInfo->Version < llvm::AArch64::ARMV8_9A.Version)
1134 ArchInfo = &llvm::AArch64::ARMV8_9A;
1135 if (Feature == "+v9a" && ArchInfo->Version < llvm::AArch64::ARMV9A.Version)
1136 ArchInfo = &llvm::AArch64::ARMV9A;
1137 if (Feature == "+v9.1a" &&
1138 ArchInfo->Version < llvm::AArch64::ARMV9_1A.Version)
1139 ArchInfo = &llvm::AArch64::ARMV9_1A;
1140 if (Feature == "+v9.2a" &&
1141 ArchInfo->Version < llvm::AArch64::ARMV9_2A.Version)
1142 ArchInfo = &llvm::AArch64::ARMV9_2A;
1143 if (Feature == "+v9.3a" &&
1144 ArchInfo->Version < llvm::AArch64::ARMV9_3A.Version)
1145 ArchInfo = &llvm::AArch64::ARMV9_3A;
1146 if (Feature == "+v9.4a" &&
1147 ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
1148 ArchInfo = &llvm::AArch64::ARMV9_4A;
1149 if (Feature == "+v9.5a" &&
1150 ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
1151 ArchInfo = &llvm::AArch64::ARMV9_5A;
1152 if (Feature == "+v9.6a" &&
1153 ArchInfo->Version < llvm::AArch64::ARMV9_6A.Version)
1154 ArchInfo = &llvm::AArch64::ARMV9_6A;
1155 if (Feature == "+v8r")
1156 ArchInfo = &llvm::AArch64::ARMV8R;
1157 if (Feature == "+fullfp16") {
1158 FPU |= NeonMode;
1159 HasFullFP16 = true;
1160 }
1161 if (Feature == "+dotprod") {
1162 FPU |= NeonMode;
1163 HasDotProd = true;
1164 }
1165 if (Feature == "+fp16fml") {
1166 FPU |= NeonMode;
1167 HasFullFP16 = true;
1168 HasFP16FML = true;
1169 }
1170 if (Feature == "+mte")
1171 HasMTE = true;
1172 if (Feature == "+tme")
1173 HasTME = true;
1174 if (Feature == "+pauth")
1175 HasPAuth = true;
1176 if (Feature == "+i8mm")
1177 HasMatMul = true;
1178 if (Feature == "+bf16")
1179 HasBFloat16 = true;
1180 if (Feature == "+lse")
1181 HasLSE = true;
1182 if (Feature == "+ls64")
1183 HasLS64 = true;
1184 if (Feature == "+rand")
1185 HasRandGen = true;
1186 if (Feature == "+flagm")
1187 HasFlagM = true;
1188 if (Feature == "+altnzcv") {
1189 HasFlagM = true;
1190 HasAlternativeNZCV = true;
1191 }
1192 if (Feature == "+mops")
1193 HasMOPS = true;
1194 if (Feature == "+d128")
1195 HasD128 = true;
1196 if (Feature == "+gcs")
1197 HasGCS = true;
1198 if (Feature == "+rcpc3")
1199 HasRCPC3 = true;
1200 if (Feature == "+pauth-lr") {
1201 HasPAuthLR = true;
1202 HasPAuth = true;
1203 }
1204 if (Feature == "+cssc")
1205 HasCSSC = true;
1206 }
1207
1208 // Check features that are manually disabled by command line options.
1209 // This needs to be checked after architecture-related features are handled,
1210 // making sure they are properly disabled when required.
1211 for (const auto &Feature : Features) {
1212 if (Feature == "-d128")
1213 HasD128 = false;
1214 }
1215
1216 setDataLayout();
1217
1218 if (HasNoFP) {
1219 FPU &= ~FPUMode;
1220 FPU &= ~NeonMode;
1221 FPU &= ~SveMode;
1222 }
1223 if (HasNoNeon) {
1224 FPU &= ~NeonMode;
1225 FPU &= ~SveMode;
1226 }
1227 if (HasNoSVE)
1228 FPU &= ~SveMode;
1229
1230 return true;
1231}
1232
1233// Parse AArch64 Target attributes, which are a comma separated list of:
1234// "arch=<arch>" - parsed to features as per -march=..
1235// "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
1236// "tune=<cpu>" - TuneCPU set to <cpu>
1237// "feature", "no-feature" - Add (or remove) feature.
1238// "+feature", "+nofeature" - Add (or remove) feature.
1239//
1240// A feature may correspond to an Extension (anything with a corresponding
1241// AEK_), in which case an ExtensionSet is used to parse it and expand its
1242// dependencies. If the feature does not yield a successful parse then it
1243// is passed through.
1245 ParsedTargetAttr Ret;
1246 if (Features == "default")
1247 return Ret;
1248 SmallVector<StringRef, 1> AttrFeatures;
1249 Features.split(AttrFeatures, ",");
1250 bool FoundArch = false;
1251
1252 auto SplitAndAddFeatures = [](StringRef FeatString,
1253 std::vector<std::string> &Features,
1254 llvm::AArch64::ExtensionSet &FeatureBits) {
1255 SmallVector<StringRef, 8> SplitFeatures;
1256 FeatString.split(SplitFeatures, StringRef("+"), -1, false);
1257 for (StringRef Feature : SplitFeatures) {
1258 if (FeatureBits.parseModifier(Feature))
1259 continue;
1260 // Pass through anything that failed to parse so that we can emit
1261 // diagnostics, as well as valid internal feature names.
1262 //
1263 // FIXME: We should consider rejecting internal feature names like
1264 // neon, v8a, etc.
1265 // FIXME: We should consider emitting diagnostics here.
1266 if (Feature.starts_with("no"))
1267 Features.push_back("-" + Feature.drop_front(2).str());
1268 else
1269 Features.push_back("+" + Feature.str());
1270 }
1271 };
1272
1273 llvm::AArch64::ExtensionSet FeatureBits;
1274 // Reconstruct the bitset from the command line option features.
1275 FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten,
1276 Ret.Features);
1277
1278 for (auto &Feature : AttrFeatures) {
1279 Feature = Feature.trim();
1280 if (Feature.starts_with("fpmath="))
1281 continue;
1282
1283 if (Feature.starts_with("branch-protection=")) {
1284 Ret.BranchProtection = Feature.split('=').second.trim();
1285 continue;
1286 }
1287
1288 if (Feature.starts_with("arch=")) {
1289 if (FoundArch)
1290 Ret.Duplicate = "arch=";
1291 FoundArch = true;
1292 std::pair<StringRef, StringRef> Split =
1293 Feature.split("=").second.trim().split("+");
1294 const llvm::AArch64::ArchInfo *AI = llvm::AArch64::parseArch(Split.first);
1295
1296 // Parse the architecture version, adding the required features to
1297 // Ret.Features.
1298 if (!AI)
1299 continue;
1300 FeatureBits.addArchDefaults(*AI);
1301 // Add any extra features, after the +
1302 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits);
1303 } else if (Feature.starts_with("cpu=")) {
1304 if (!Ret.CPU.empty())
1305 Ret.Duplicate = "cpu=";
1306 else {
1307 // Split the cpu string into "cpu=", "cortex-a710" and any remaining
1308 // "+feat" features.
1309 std::pair<StringRef, StringRef> Split =
1310 Feature.split("=").second.trim().split("+");
1311 Ret.CPU = Split.first;
1312 if (auto CpuInfo = llvm::AArch64::parseCpu(Ret.CPU)) {
1313 FeatureBits.addCPUDefaults(*CpuInfo);
1314 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits);
1315 }
1316 }
1317 } else if (Feature.starts_with("tune=")) {
1318 if (!Ret.Tune.empty())
1319 Ret.Duplicate = "tune=";
1320 else
1321 Ret.Tune = Feature.split("=").second.trim();
1322 } else if (Feature.starts_with("+")) {
1323 SplitAndAddFeatures(Feature, Ret.Features, FeatureBits);
1324 } else {
1325 if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true))
1326 continue;
1327 // Pass through anything that failed to parse so that we can emit
1328 // diagnostics, as well as valid internal feature names.
1329 //
1330 // FIXME: We should consider rejecting internal feature names like
1331 // neon, v8a, etc.
1332 // FIXME: We should consider emitting diagnostics here.
1333 if (Feature.starts_with("no-"))
1334 Ret.Features.push_back("-" + Feature.drop_front(3).str());
1335 else
1336 Ret.Features.push_back("+" + Feature.str());
1337 }
1338 }
1339 FeatureBits.toLLVMFeatureList(Ret.Features);
1340 return Ret;
1341}
1342
1344 return true;
1345}
1346
1349 switch (CC) {
1350 case CC_C:
1351 case CC_Swift:
1352 case CC_SwiftAsync:
1353 case CC_PreserveMost:
1354 case CC_PreserveAll:
1355 case CC_PreserveNone:
1356 case CC_DeviceKernel:
1358 case CC_AArch64SVEPCS:
1359 case CC_Win64:
1360 return CCCR_OK;
1361 default:
1362 return CCCR_Warning;
1363 }
1364}
1365
1366bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
1367
1371
1372const char *const AArch64TargetInfo::GCCRegNames[] = {
1373 // clang-format off
1374
1375 // 32-bit Integer registers
1376 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
1377 "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
1378 "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
1379
1380 // 64-bit Integer registers
1381 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
1382 "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
1383 "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
1384
1385 // 32-bit floating point regsisters
1386 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
1387 "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
1388 "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1389
1390 // 64-bit floating point regsisters
1391 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
1392 "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
1393 "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
1394
1395 // Neon vector registers
1396 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
1397 "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
1398 "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1399
1400 // SVE vector registers
1401 "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10",
1402 "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
1403 "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
1404
1405 // SVE predicate registers
1406 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10",
1407 "p11", "p12", "p13", "p14", "p15",
1408
1409 // SVE predicate-as-counter registers
1410 "pn0", "pn1", "pn2", "pn3", "pn4", "pn5", "pn6", "pn7", "pn8",
1411 "pn9", "pn10", "pn11", "pn12", "pn13", "pn14", "pn15",
1412
1413 // SME registers
1414 "za", "zt0",
1415
1416 // clang-format on
1417};
1418
1422
1423const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
1424 {{"w31"}, "wsp"},
1425 {{"x31"}, "sp"},
1426 // GCC rN registers are aliases of xN registers.
1427 {{"r0"}, "x0"},
1428 {{"r1"}, "x1"},
1429 {{"r2"}, "x2"},
1430 {{"r3"}, "x3"},
1431 {{"r4"}, "x4"},
1432 {{"r5"}, "x5"},
1433 {{"r6"}, "x6"},
1434 {{"r7"}, "x7"},
1435 {{"r8"}, "x8"},
1436 {{"r9"}, "x9"},
1437 {{"r10"}, "x10"},
1438 {{"r11"}, "x11"},
1439 {{"r12"}, "x12"},
1440 {{"r13"}, "x13"},
1441 {{"r14"}, "x14"},
1442 {{"r15"}, "x15"},
1443 {{"r16"}, "x16"},
1444 {{"r17"}, "x17"},
1445 {{"r18"}, "x18"},
1446 {{"r19"}, "x19"},
1447 {{"r20"}, "x20"},
1448 {{"r21"}, "x21"},
1449 {{"r22"}, "x22"},
1450 {{"r23"}, "x23"},
1451 {{"r24"}, "x24"},
1452 {{"r25"}, "x25"},
1453 {{"r26"}, "x26"},
1454 {{"r27"}, "x27"},
1455 {{"r28"}, "x28"},
1456 {{"r29", "x29"}, "fp"},
1457 {{"r30", "x30"}, "lr"},
1458 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
1459 // don't want to substitute one of these for a different-sized one.
1460};
1461
1465
1466// Returns the length of cc constraint.
1467static unsigned matchAsmCCConstraint(const char *Name) {
1468 constexpr unsigned len = 5;
1469 auto RV = llvm::StringSwitch<unsigned>(Name)
1470 .Case("@cceq", len)
1471 .Case("@ccne", len)
1472 .Case("@cchs", len)
1473 .Case("@cccs", len)
1474 .Case("@cccc", len)
1475 .Case("@cclo", len)
1476 .Case("@ccmi", len)
1477 .Case("@ccpl", len)
1478 .Case("@ccvs", len)
1479 .Case("@ccvc", len)
1480 .Case("@cchi", len)
1481 .Case("@ccls", len)
1482 .Case("@ccge", len)
1483 .Case("@cclt", len)
1484 .Case("@ccgt", len)
1485 .Case("@ccle", len)
1486 .Default(0);
1487 return RV;
1488}
1489
1490std::string
1491AArch64TargetInfo::convertConstraint(const char *&Constraint) const {
1492 std::string R;
1493 switch (*Constraint) {
1494 case 'U': // Three-character constraint; add "@3" hint for later parsing.
1495 R = std::string("@3") + std::string(Constraint, 3);
1496 Constraint += 2;
1497 break;
1498 case '@':
1499 if (const unsigned Len = matchAsmCCConstraint(Constraint)) {
1500 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1501 Constraint += Len - 1;
1502 return Converted;
1503 }
1504 return std::string(1, *Constraint);
1505 default:
1506 R = TargetInfo::convertConstraint(Constraint);
1507 break;
1508 }
1509 return R;
1510}
1511
1513 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1514 switch (*Name) {
1515 default:
1516 return false;
1517 case 'w': // Floating point and SIMD registers (V0-V31)
1518 Info.setAllowsRegister();
1519 return true;
1520 case 'I': // Constant that can be used with an ADD instruction
1521 case 'J': // Constant that can be used with a SUB instruction
1522 case 'K': // Constant that can be used with a 32-bit logical instruction
1523 case 'L': // Constant that can be used with a 64-bit logical instruction
1524 case 'M': // Constant that can be used as a 32-bit MOV immediate
1525 case 'N': // Constant that can be used as a 64-bit MOV immediate
1526 case 'Y': // Floating point constant zero
1527 case 'Z': // Integer constant zero
1528 return true;
1529 case 'Q': // A memory reference with base register and no offset
1530 Info.setAllowsMemory();
1531 return true;
1532 case 'S': // A symbolic address
1533 Info.setAllowsRegister();
1534 return true;
1535 case 'U':
1536 if (Name[1] == 'p' &&
1537 (Name[2] == 'l' || Name[2] == 'a' || Name[2] == 'h')) {
1538 // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7, "Uph"=P8-P15)
1539 Info.setAllowsRegister();
1540 Name += 2;
1541 return true;
1542 }
1543 if (Name[1] == 'c' && (Name[2] == 'i' || Name[2] == 'j')) {
1544 // Gpr registers ("Uci"=w8-11, "Ucj"=w12-15)
1545 Info.setAllowsRegister();
1546 Name += 2;
1547 return true;
1548 }
1549 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
1550 // Utf: A memory address suitable for ldp/stp in TF mode.
1551 // Usa: An absolute symbolic address.
1552 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
1553
1554 // Better to return an error saying that it's an unrecognised constraint
1555 // even if this is a valid constraint in gcc.
1556 return false;
1557 case 'z': // Zero register, wzr or xzr
1558 Info.setAllowsRegister();
1559 return true;
1560 case 'x': // Floating point and SIMD registers (V0-V15)
1561 Info.setAllowsRegister();
1562 return true;
1563 case 'y': // SVE registers (V0-V7)
1564 Info.setAllowsRegister();
1565 return true;
1566 case '@':
1567 // CC condition
1568 if (const unsigned Len = matchAsmCCConstraint(Name)) {
1569 Name += Len - 1;
1570 Info.setAllowsRegister();
1571 return true;
1572 }
1573 }
1574 return false;
1575}
1576
1578 StringRef Constraint, char Modifier, unsigned Size,
1579 std::string &SuggestedModifier) const {
1580 // Strip off constraint modifiers.
1581 Constraint = Constraint.ltrim("=+&");
1582
1583 switch (Constraint[0]) {
1584 default:
1585 return true;
1586 case 'z':
1587 case 'r': {
1588 switch (Modifier) {
1589 case 'x':
1590 case 'w':
1591 // For now assume that the person knows what they're
1592 // doing with the modifier.
1593 return true;
1594 default:
1595 // By default an 'r' constraint will be in the 'x'
1596 // registers.
1597 if (Size == 64)
1598 return true;
1599
1600 if (Size == 512)
1601 return HasLS64;
1602
1603 SuggestedModifier = "w";
1604 return false;
1605 }
1606 }
1607 }
1608}
1609
1610std::string_view AArch64TargetInfo::getClobbers() const { return ""; }
1611
1613 if (RegNo == 0)
1614 return 0;
1615 if (RegNo == 1)
1616 return 1;
1617 return -1;
1618}
1619
1621 const llvm::APSInt &value) const {
1622 return 0 <= value && value <= 3;
1623}
1624
1625bool AArch64TargetInfo::hasInt128Type() const { return true; }
1626
1628 const TargetOptions &Opts)
1629 : AArch64TargetInfo(Triple, Opts) {}
1630
1631void AArch64leTargetInfo::setDataLayout() {
1632 if (getTriple().isOSBinFormatMachO()) {
1633 if(getTriple().isArch32Bit())
1634 resetDataLayout("e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-"
1635 "i128:128-n32:64-S128-Fn32",
1636 "_");
1637 else
1638 resetDataLayout("e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-"
1639 "n32:64-S128-Fn32",
1640 "_");
1641 } else
1642 resetDataLayout("e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-"
1643 "i64:64-i128:128-n32:64-S128-Fn32");
1644}
1645
1647 MacroBuilder &Builder) const {
1648 Builder.defineMacro("__AARCH64EL__");
1650}
1651
1653 const TargetOptions &Opts)
1654 : AArch64TargetInfo(Triple, Opts) {}
1655
1657 MacroBuilder &Builder) const {
1658 Builder.defineMacro("__AARCH64EB__");
1659 Builder.defineMacro("__AARCH_BIG_ENDIAN");
1660 Builder.defineMacro("__ARM_BIG_ENDIAN");
1662}
1663
1664void AArch64beTargetInfo::setDataLayout() {
1665 assert(!getTriple().isOSBinFormatMachO());
1666 resetDataLayout("E-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-"
1667 "i64:64-i128:128-n32:64-S128-Fn32");
1668}
1669
1671 const TargetOptions &Opts)
1672 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
1673
1674 // This is an LLP64 platform.
1675 // int:4, long:4, long long:8, long double:8.
1676 IntWidth = IntAlign = 32;
1677 LongWidth = LongAlign = 32;
1680 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1686}
1687
1689 resetDataLayout(Triple.isOSBinFormatMachO()
1690 ? "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:"
1691 "128-n32:64-S128-Fn32"
1692 : "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-"
1693 "i64:64-i128:128-n32:64-S128-Fn32",
1694 Triple.isOSBinFormatMachO() ? "_" : "");
1695}
1696
1701
1704 switch (CC) {
1705 case CC_X86VectorCall:
1706 if (getTriple().isWindowsArm64EC())
1707 return CCCR_OK;
1708 return CCCR_Ignore;
1709 case CC_X86StdCall:
1710 case CC_X86ThisCall:
1711 case CC_X86FastCall:
1712 return CCCR_Ignore;
1713 case CC_C:
1714 case CC_DeviceKernel:
1715 case CC_PreserveMost:
1716 case CC_PreserveAll:
1717 case CC_PreserveNone:
1718 case CC_Swift:
1719 case CC_SwiftAsync:
1720 case CC_Win64:
1721 return CCCR_OK;
1722 default:
1723 return CCCR_Warning;
1724 }
1725}
1726
1728 const TargetOptions &Opts)
1729 : WindowsARM64TargetInfo(Triple, Opts) {
1730 TheCXXABI.set(TargetCXXABI::Microsoft);
1731}
1732
1734 MacroBuilder &Builder) const {
1736 if (getTriple().isWindowsArm64EC()) {
1737 Builder.defineMacro("_M_X64", "100");
1738 Builder.defineMacro("_M_AMD64", "100");
1739 Builder.defineMacro("_M_ARM64EC", "1");
1740 } else {
1741 Builder.defineMacro("_M_ARM64", "1");
1742 }
1743}
1744
1747 return CCK_MicrosoftWin64;
1748}
1749
1751 bool HasNonWeakDef) const {
1752 unsigned Align =
1753 WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1754
1755 // MSVC does size based alignment for arm64 based on alignment section in
1756 // below document, replicate that to keep alignment consistent with object
1757 // files compiled by MSVC.
1758 // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
1759 if (TypeSize >= 512) { // TypeSize >= 64 bytes
1760 Align = std::max(Align, 128u); // align type at least 16 bytes
1761 } else if (TypeSize >= 64) { // TypeSize >= 8 bytes
1762 Align = std::max(Align, 64u); // align type at least 8 butes
1763 } else if (TypeSize >= 16) { // TypeSize >= 2 bytes
1764 Align = std::max(Align, 32u); // align type at least 4 bytes
1765 }
1766 return Align;
1767}
1768
1770 const TargetOptions &Opts)
1771 : WindowsARM64TargetInfo(Triple, Opts) {
1772 TheCXXABI.set(TargetCXXABI::GenericAArch64);
1773}
1774
1776 const llvm::Triple &Triple, const TargetOptions &Opts)
1777 : AppleMachOTargetInfo<AArch64leTargetInfo>(Triple, Opts) {}
1778
1780 const TargetOptions &Opts)
1781 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1783 if (getTriple().isArch32Bit())
1785
1788
1790 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1791
1793
1794 if (getTriple().isArch32Bit()) {
1798 TheCXXABI.set(TargetCXXABI::WatchOS);
1799 } else
1800 TheCXXABI.set(TargetCXXABI::AppleARM64);
1801}
1802
1804 const LangOptions &Opts,
1805 const llvm::Triple &Triple) {
1806 Builder.defineMacro("__AARCH64_SIMD__");
1807 if (Triple.isArch32Bit())
1808 Builder.defineMacro("__ARM64_ARCH_8_32__");
1809 else
1810 Builder.defineMacro("__ARM64_ARCH_8__");
1811 Builder.defineMacro("__ARM_NEON__");
1812 Builder.defineMacro("__REGISTER_PREFIX__", "");
1813 Builder.defineMacro("__arm64", "1");
1814 Builder.defineMacro("__arm64__", "1");
1815
1816 if (Triple.isArm64e())
1817 Builder.defineMacro("__arm64e__", "1");
1818}
1819
1821 const llvm::Triple &Triple,
1822 MacroBuilder &Builder) const {
1823 getAppleMachOAArch64Defines(Builder, Opts, Triple);
1825 Builder);
1826}
1827
1829 const llvm::Triple &Triple,
1830 MacroBuilder &Builder) const {
1831 getAppleMachOAArch64Defines(Builder, Opts, Triple);
1833}
1834
Defines the Diagnostic-related interfaces.
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1467
static constexpr int NumAArch64Builtins
Definition AArch64.cpp:37
#define ARM_ACLE_VERSION(Y, Q, P)
static constexpr int NumSVEBuiltins
Definition AArch64.cpp:32
static constexpr int NumFp16Builtins
Definition AArch64.cpp:30
static constexpr int NumSMEBuiltins
Definition AArch64.cpp:36
static constexpr auto BuiltinAArch64Infos
Definition AArch64.cpp:119
static constexpr llvm::StringTable BuiltinSVENeonBridgeStrings
Definition AArch64.cpp:95
static constexpr int NumSVENeonBridgeBuiltins
Definition AArch64.cpp:34
static constexpr int NumNeonBuiltins
Definition AArch64.cpp:28
static constexpr llvm::StringTable BuiltinAArch64Strings
Definition AArch64.cpp:103
static constexpr auto BuiltinSVENeonBridgeInfos
Definition AArch64.cpp:111
static constexpr unsigned NumBuiltins
Definition Builtins.cpp:32
#define CLANG_BUILTIN_STR_TABLE_START
Definition Builtins.h:158
Defines the clang::LangOptions interface.
Enumerates target-specific builtins in their own namespaces within namespace clang.
__device__ __2f16 float c
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:231
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
@ NonLeaf
Sign the return address of functions that spill LR.
@ All
Sign the return address of all functions,.
@ BKey
Return address signing uses APIB key.
@ AKey
Return address signing uses APIA key.
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
bool isSignReturnAddressWithAKey() const
Check if return address signing uses AKey.
bool hasSignReturnAddress() const
Check if return address signing is enabled.
bool isSignReturnAddressScopeAll() const
Check if leaf functions are also signed.
LangOptions::SignReturnAddressScopeKind SignReturnAddr
LangOptions::SignReturnAddressKeyKind SignKey
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:323
TargetInfo(const llvm::Triple &T)
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
const LangASMap * AddrSpaceMap
Definition TargetInfo.h:258
void resetDataLayout(StringRef DL, const char *UserLabelPrefix="")
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition TargetInfo.h:330
@ AArch64ABIBuiltinVaList
__builtin_va_list as defined by the AArch64 ABI http://infocenter.arm.com/help/topic/com....
Definition TargetInfo.h:339
@ CharPtrBuiltinVaList
typedef char* __builtin_va_list;
Definition TargetInfo.h:332
virtual void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const =0
===-— Other target property query methods -----------------------—===//
unsigned HasUnalignedAccess
Definition TargetInfo.h:283
unsigned char MaxAtomicPromoteWidth
Definition TargetInfo.h:251
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:754
unsigned HasAArch64ACLETypes
Definition TargetInfo.h:274
virtual std::string convertConstraint(const char *&Constraint) const
unsigned char MaxAtomicInlineWidth
Definition TargetInfo.h:251
TargetCXXABI TheCXXABI
Definition TargetInfo.h:256
unsigned HasBuiltinMSVaList
Definition TargetInfo.h:271
Options for controlling the target.
llvm::EABI EABIVersion
The EABI version to use.
llvm::StringMap< bool > FeatureMap
The map of which features have been enabled disabled based on the command line.
void getTargetDefinesARMV95A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:389
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition AArch64.cpp:1610
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition AArch64.cpp:811
std::string convertConstraint(const char *&Constraint) const override
Definition AArch64.cpp:1491
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition AArch64.cpp:1462
bool hasBFloat16Type() const override
Determine whether the _BFloat16 type is supported on this target.
Definition AArch64.cpp:1343
ParsedTargetAttr parseTargetAttr(StringRef Str) const override
Definition AArch64.cpp:1244
void getTargetDefinesARMV96A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:395
AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:128
ArrayRef< const char * > getGCCRegNames() const override
Definition AArch64.cpp:1419
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const override
Validate register name used for global register variables.
Definition AArch64.cpp:233
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features (e.g., +sse4).
Definition AArch64.cpp:907
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition AArch64.cpp:401
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const override
Enable or disable a specific target feature; the feature name must be valid.
Definition AArch64.cpp:878
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition AArch64.cpp:739
void getTargetDefinesARMV89A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:353
void getTargetDefinesARMV92A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:371
bool validateTarget(DiagnosticsEngine &Diags) const override
Check the target is valid after it is fully initialized.
Definition AArch64.cpp:217
void getTargetDefinesARMV93A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:377
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition AArch64.cpp:208
void getTargetDefinesARMV84A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:318
bool isValidCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name.
Definition AArch64.cpp:286
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition AArch64.cpp:294
StringRef getABI() const override
Get the ABI currently in use.
Definition AArch64.cpp:206
bool hasInt128Type() const override
Determine whether the __int128 type is supported on this target.
Definition AArch64.cpp:1625
void getTargetDefinesARMV88A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:347
void getTargetDefinesARMV87A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:341
void getTargetDefinesARMV9A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:359
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition AArch64.cpp:1348
void getTargetDefinesARMV91A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:365
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode, llvm::StringMap< bool > *FeatureMap=nullptr) const override
Returns target-specific min and max values VScale_Range.
Definition AArch64.cpp:752
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition AArch64.cpp:1368
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition AArch64.cpp:1612
void getTargetDefinesARMV81A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:299
bool validateBranchProtection(StringRef Spec, StringRef Arch, BranchProtectionInfo &BPI, const LangOptions &LO, StringRef &Err) const override
Determine if this TargetInfo supports the given branch protection specification.
Definition AArch64.cpp:254
void getTargetDefinesARMV86A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:331
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition AArch64.cpp:290
void getTargetDefinesARMV94A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:383
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition AArch64.cpp:790
bool validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, std::string &SuggestedModifier) const override
Definition AArch64.cpp:1577
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition AArch64.cpp:1366
void getTargetDefinesARMV82A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:304
void getTargetDefinesARMV83A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:310
bool validateCpuSupports(StringRef FeatureStr) const override
Definition AArch64.cpp:801
bool validatePointerAuthKey(const llvm::APSInt &value) const override
Determine whether the given pointer-authentication key is valid.
Definition AArch64.cpp:1620
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition AArch64.cpp:1512
bool doesFeatureAffectCodeGen(StringRef Name) const override
Returns true if feature has an impact on target code generation.
Definition AArch64.cpp:794
void getTargetDefinesARMV85A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition AArch64.cpp:324
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition AArch64.cpp:1656
AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1652
AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1627
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition AArch64.cpp:1646
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition AArch64.cpp:1820
AppleMachOAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1775
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition OSTargets.h:48
AppleMachOTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition OSTargets.h:54
DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1779
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition AArch64.cpp:1828
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition AArch64.cpp:1836
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition OSTargets.h:71
DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition OSTargets.h:78
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition AArch64.cpp:1750
MicrosoftARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1727
TargetInfo::CallingConvKind getCallingConvKind(bool ClangABICompat4) const override
Definition AArch64.cpp:1746
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition AArch64.cpp:1733
MinGWARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1769
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition AArch64.cpp:1698
WindowsARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition AArch64.cpp:1670
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition AArch64.cpp:1703
WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition OSTargets.h:864
Defines the clang::TargetInfo interface.
static constexpr std::array< Info, N > MakeInfos(std::array< Info, N > Infos)
A constexpr function to construct an infos array from X-macros.
Definition Builtins.h:107
static constexpr std::array< Builtin::Info, NumFp16Builtins > BuiltinInfos
Definition AArch64.cpp:62
static constexpr std::array< Builtin::Info, NumNeonBuiltins > BuiltinInfos
Definition AArch64.cpp:51
static constexpr std::array< Builtin::Info, NumSMEBuiltins > BuiltinInfos
Definition AArch64.cpp:87
static constexpr std::array< Builtin::Info, NumSVEBuiltins > BuiltinInfos
Definition AArch64.cpp:75
void getAppleMachOAArch64Defines(MacroBuilder &Builder, const LangOptions &Opts, const llvm::Triple &Triple)
Definition AArch64.cpp:1803
static const unsigned ARM64AddrSpaceMap[]
Definition AArch64.h:26
The JSON file list parser is used to communicate input to InstallAPI.
if(T->getSizeExpr()) TRY_TO(TraverseStmt(const_cast< Expr * >(T -> getSizeExpr())))
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition Specifiers.h:278
@ CC_Swift
Definition Specifiers.h:293
@ CC_PreserveMost
Definition Specifiers.h:295
@ CC_Win64
Definition Specifiers.h:285
@ CC_X86ThisCall
Definition Specifiers.h:282
@ CC_AArch64VectorCall
Definition Specifiers.h:297
@ CC_DeviceKernel
Definition Specifiers.h:292
@ CC_PreserveNone
Definition Specifiers.h:300
@ CC_SwiftAsync
Definition Specifiers.h:294
@ CC_X86VectorCall
Definition Specifiers.h:283
@ CC_AArch64SVEPCS
Definition Specifiers.h:298
@ CC_X86StdCall
Definition Specifiers.h:280
@ CC_PreserveAll
Definition Specifiers.h:296
@ CC_X86FastCall
Definition Specifiers.h:281
Contains information gathered from parsing the contents of TargetAttr.
Definition TargetInfo.h:60
unsigned UseZeroLengthBitfieldAlignment
Whether zero length bitfields (e.g., int : 0;) force alignment of the next bitfield.
Definition TargetInfo.h:187
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
unsigned ZeroLengthBitfieldBoundary
If non-zero, specifies a fixed alignment value for bitfields that follow zero length bitfield,...
Definition TargetInfo.h:200
std::optional< unsigned > BitIntMaxAlign
Definition TargetInfo.h:106
unsigned LargestOverSizedBitfieldContainer
The largest container size which should be used for an over-sized bitfield, in bits.
Definition TargetInfo.h:204
unsigned UseBitFieldTypeAlignment
Control whether the alignment of bit-field types is respected when laying out structures.
Definition TargetInfo.h:178
unsigned UseSignedCharForObjCBool
Whether Objective-C's built-in boolean type should be signed char.
Definition TargetInfo.h:170
const llvm::fltSemantics * BFloat16Format
Definition TargetInfo.h:142