clang  17.0.0git
AArch64.cpp
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1 //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements AArch64 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
16 #include "clang/Basic/TargetInfo.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/AArch64TargetParser.h"
21 #include "llvm/Support/ARMTargetParserCommon.h"
22 #include "llvm/TargetParser/AArch64TargetParser.h"
23 #include <optional>
24 
25 using namespace clang;
26 using namespace clang::targets;
27 
28 static constexpr Builtin::Info BuiltinInfo[] = {
29 #define BUILTIN(ID, TYPE, ATTRS) \
30  {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
31 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
32  {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
33 #include "clang/Basic/BuiltinsNEON.def"
34 
35 #define BUILTIN(ID, TYPE, ATTRS) \
36  {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38  {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
39 #include "clang/Basic/BuiltinsSVE.def"
40 
41 #define BUILTIN(ID, TYPE, ATTRS) \
42  {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
43 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
44  {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, LANG},
45 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
46  {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
47 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
48  {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
49 #include "clang/Basic/BuiltinsAArch64.def"
50 };
51 
53  if (*ArchInfo == llvm::AArch64::ARMV8R) {
54  HasDotProd = true;
55  HasDIT = true;
56  HasFlagM = true;
57  HasRCPC = true;
58  FPU |= NeonMode;
59  HasCCPP = true;
60  HasCRC = true;
61  HasLSE = true;
62  HasRDM = true;
63  } else if (ArchInfo->Version.getMajor() == 8) {
64  if (ArchInfo->Version.getMinor() >= 7u) {
65  HasWFxT = true;
66  }
67  if (ArchInfo->Version.getMinor() >= 6u) {
68  HasBFloat16 = true;
69  HasMatMul = true;
70  }
71  if (ArchInfo->Version.getMinor() >= 5u) {
72  HasAlternativeNZCV = true;
73  HasFRInt3264 = true;
74  HasSSBS = true;
75  HasSB = true;
76  HasPredRes = true;
77  HasBTI = true;
78  }
79  if (ArchInfo->Version.getMinor() >= 4u) {
80  HasDotProd = true;
81  HasDIT = true;
82  HasFlagM = true;
83  }
84  if (ArchInfo->Version.getMinor() >= 3u) {
85  HasRCPC = true;
86  FPU |= NeonMode;
87  }
88  if (ArchInfo->Version.getMinor() >= 2u) {
89  HasCCPP = true;
90  }
91  if (ArchInfo->Version.getMinor() >= 1u) {
92  HasCRC = true;
93  HasLSE = true;
94  HasRDM = true;
95  }
96  } else if (ArchInfo->Version.getMajor() == 9) {
97  if (ArchInfo->Version.getMinor() >= 2u) {
98  HasWFxT = true;
99  }
100  if (ArchInfo->Version.getMinor() >= 1u) {
101  HasBFloat16 = true;
102  HasMatMul = true;
103  }
104  FPU |= SveMode;
105  HasSVE2 = true;
106  HasFullFP16 = true;
107  HasAlternativeNZCV = true;
108  HasFRInt3264 = true;
109  HasSSBS = true;
110  HasSB = true;
111  HasPredRes = true;
112  HasBTI = true;
113  HasDotProd = true;
114  HasDIT = true;
115  HasFlagM = true;
116  HasRCPC = true;
117  FPU |= NeonMode;
118  HasCCPP = true;
119  HasCRC = true;
120  HasLSE = true;
121  HasRDM = true;
122  }
123 }
124 
125 AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
126  const TargetOptions &Opts)
127  : TargetInfo(Triple), ABI("aapcs") {
128  if (getTriple().isOSOpenBSD()) {
131  } else {
132  if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD())
134 
137  }
138 
139  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
140  HasLegalHalfType = true;
141  HalfArgsAndReturns = true;
142  HasFloat16 = true;
143  HasStrictFP = true;
144 
145  if (Triple.isArch64Bit())
147  else
149 
150  MaxVectorAlign = 128;
151  MaxAtomicInlineWidth = 128;
152  MaxAtomicPromoteWidth = 128;
153 
155  LongDoubleFormat = &llvm::APFloat::IEEEquad();
156 
158  BFloat16Format = &llvm::APFloat::BFloat();
159 
160  // Make __builtin_ms_va_list available.
161  HasBuiltinMSVaList = true;
162 
163  // Make the SVE types available. Note that this deliberately doesn't
164  // depend on SveMode, since in principle it should be possible to turn
165  // SVE on and off within a translation unit. It should also be possible
166  // to compile the global declaration:
167  //
168  // __SVInt8_t *ptr;
169  //
170  // even without SVE.
171  HasAArch64SVETypes = true;
172 
173  // {} in inline assembly are neon specifiers, not assembly variant
174  // specifiers.
175  NoAsmVariants = true;
176 
177  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
178  // contributes to the alignment of the containing aggregate in the same way
179  // a plain (non bit-field) member of that type would, without exception for
180  // zero-sized or anonymous bit-fields."
181  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
183 
184  // AArch64 targets default to using the ARM C++ ABI.
185  TheCXXABI.set(TargetCXXABI::GenericAArch64);
186 
187  if (Triple.getOS() == llvm::Triple::Linux)
188  this->MCountName = "\01_mcount";
189  else if (Triple.getOS() == llvm::Triple::UnknownOS)
190  this->MCountName =
191  Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
192 }
193 
194 StringRef AArch64TargetInfo::getABI() const { return ABI; }
195 
197  if (Name != "aapcs" && Name != "darwinpcs")
198  return false;
199 
200  ABI = Name;
201  return true;
202 }
203 
204 bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
206  StringRef &Err) const {
207  llvm::ARM::ParsedBranchProtection PBP;
208  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
209  return false;
210 
211  BPI.SignReturnAddr =
212  llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
216 
217  if (PBP.Key == "a_key")
219  else
221 
222  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
223  return true;
224 }
225 
226 bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
227  return Name == "generic" || llvm::AArch64::parseCpu(Name);
228 }
229 
231  return isValidCPUName(Name);
232 }
233 
235  SmallVectorImpl<StringRef> &Values) const {
236  llvm::AArch64::fillValidCPUArchList(Values);
237 }
238 
240  MacroBuilder &Builder) const {
241  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
242  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
243  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
244 }
245 
247  MacroBuilder &Builder) const {
248  // Also include the ARMv8.1 defines
249  getTargetDefinesARMV81A(Opts, Builder);
250 }
251 
253  MacroBuilder &Builder) const {
254  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
255  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
256  Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
257  // Also include the Armv8.2 defines
258  getTargetDefinesARMV82A(Opts, Builder);
259 }
260 
262  MacroBuilder &Builder) const {
263  // Also include the Armv8.3 defines
264  getTargetDefinesARMV83A(Opts, Builder);
265 }
266 
268  MacroBuilder &Builder) const {
269  Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
270  Builder.defineMacro("__ARM_FEATURE_BTI", "1");
271  // Also include the Armv8.4 defines
272  getTargetDefinesARMV84A(Opts, Builder);
273 }
274 
276  MacroBuilder &Builder) const {
277  // Also include the Armv8.5 defines
278  // FIXME: Armv8.6 makes the following extensions mandatory:
279  // - __ARM_FEATURE_BF16
280  // - __ARM_FEATURE_MATMUL_INT8
281  // Handle them here.
282  getTargetDefinesARMV85A(Opts, Builder);
283 }
284 
286  MacroBuilder &Builder) const {
287  // Also include the Armv8.6 defines
288  getTargetDefinesARMV86A(Opts, Builder);
289 }
290 
292  MacroBuilder &Builder) const {
293  // Also include the Armv8.7 defines
294  getTargetDefinesARMV87A(Opts, Builder);
295 }
296 
298  MacroBuilder &Builder) const {
299  // Also include the Armv8.8 defines
300  getTargetDefinesARMV88A(Opts, Builder);
301 }
302 
304  MacroBuilder &Builder) const {
305  // Armv9-A maps to Armv8.5-A
306  getTargetDefinesARMV85A(Opts, Builder);
307 }
308 
310  MacroBuilder &Builder) const {
311  // Armv9.1-A maps to Armv8.6-A
312  getTargetDefinesARMV86A(Opts, Builder);
313 }
314 
316  MacroBuilder &Builder) const {
317  // Armv9.2-A maps to Armv8.7-A
318  getTargetDefinesARMV87A(Opts, Builder);
319 }
320 
322  MacroBuilder &Builder) const {
323  // Armv9.3-A maps to Armv8.8-A
324  getTargetDefinesARMV88A(Opts, Builder);
325 }
326 
328  MacroBuilder &Builder) const {
329  // Armv9.4-A maps to Armv8.9-A
330  getTargetDefinesARMV89A(Opts, Builder);
331 }
332 
334  MacroBuilder &Builder) const {
335  // Target identification.
336  Builder.defineMacro("__aarch64__");
337  // For bare-metal.
338  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
339  getTriple().isOSBinFormatELF())
340  Builder.defineMacro("__ELF__");
341 
342  // Target properties.
343  if (!getTriple().isOSWindows() && getTriple().isArch64Bit()) {
344  Builder.defineMacro("_LP64");
345  Builder.defineMacro("__LP64__");
346  }
347 
348  std::string CodeModel = getTargetOpts().CodeModel;
349  if (CodeModel == "default")
350  CodeModel = "small";
351  for (char &c : CodeModel)
352  c = toupper(c);
353  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
354 
355  // ACLE predefines. Many can only have one possible value on v8 AArch64.
356  Builder.defineMacro("__ARM_ACLE", "200");
357  Builder.defineMacro("__ARM_ARCH",
358  std::to_string(ArchInfo->Version.getMajor()));
359  Builder.defineMacro("__ARM_ARCH_PROFILE",
360  std::string("'") + (char)ArchInfo->Profile + "'");
361 
362  Builder.defineMacro("__ARM_64BIT_STATE", "1");
363  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
364  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
365 
366  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
367  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
368  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
369  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
370  Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
371  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
372  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
373 
374  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
375 
376  // 0xe implies support for half, single and double precision operations.
377  Builder.defineMacro("__ARM_FP", "0xE");
378 
379  // PCS specifies this for SysV variants, which is all we support. Other ABIs
380  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
381  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
382  Builder.defineMacro("__ARM_FP16_ARGS", "1");
383 
384  if (Opts.UnsafeFPMath)
385  Builder.defineMacro("__ARM_FP_FAST", "1");
386 
387  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
388  Twine(Opts.WCharSize ? Opts.WCharSize : 4));
389 
390  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
391 
392  if (FPU & NeonMode) {
393  Builder.defineMacro("__ARM_NEON", "1");
394  // 64-bit NEON supports half, single and double precision operations.
395  Builder.defineMacro("__ARM_NEON_FP", "0xE");
396  }
397 
398  if (FPU & SveMode)
399  Builder.defineMacro("__ARM_FEATURE_SVE", "1");
400 
401  if ((FPU & NeonMode) && (FPU & SveMode))
402  Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
403 
404  if (HasSVE2)
405  Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
406 
407  if (HasSVE2 && HasSVE2AES)
408  Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
409 
410  if (HasSVE2 && HasSVE2BitPerm)
411  Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
412 
413  if (HasSVE2 && HasSVE2SHA3)
414  Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
415 
416  if (HasSVE2 && HasSVE2SM4)
417  Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
418 
419  if (HasCRC)
420  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
421 
422  if (HasRCPC)
423  Builder.defineMacro("__ARM_FEATURE_RCPC", "1");
424 
425  if (HasFMV)
426  Builder.defineMacro("__HAVE_FUNCTION_MULTI_VERSIONING", "1");
427 
428  // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
429  // macros for AES, SHA2, SHA3 and SM4
430  if (HasAES && HasSHA2)
431  Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
432 
433  if (HasAES)
434  Builder.defineMacro("__ARM_FEATURE_AES", "1");
435 
436  if (HasSHA2)
437  Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
438 
439  if (HasSHA3) {
440  Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
441  Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
442  }
443 
444  if (HasSM4) {
445  Builder.defineMacro("__ARM_FEATURE_SM3", "1");
446  Builder.defineMacro("__ARM_FEATURE_SM4", "1");
447  }
448 
449  if (HasPAuth)
450  Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
451 
452  if (HasUnaligned)
453  Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
454 
455  if ((FPU & NeonMode) && HasFullFP16)
456  Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
457  if (HasFullFP16)
458  Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
459 
460  if (HasDotProd)
461  Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
462 
463  if (HasMTE)
464  Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
465 
466  if (HasTME)
467  Builder.defineMacro("__ARM_FEATURE_TME", "1");
468 
469  if (HasMatMul)
470  Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
471 
472  if (HasLSE)
473  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
474 
475  if (HasBFloat16) {
476  Builder.defineMacro("__ARM_FEATURE_BF16", "1");
477  Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
478  Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
479  Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
480  }
481 
482  if ((FPU & SveMode) && HasBFloat16) {
483  Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
484  }
485 
486  if ((FPU & SveMode) && HasMatmulFP64)
487  Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
488 
489  if ((FPU & SveMode) && HasMatmulFP32)
490  Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
491 
492  if ((FPU & SveMode) && HasMatMul)
493  Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
494 
495  if ((FPU & NeonMode) && HasFP16FML)
496  Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
497 
498  if (Opts.hasSignReturnAddress()) {
499  // Bitmask:
500  // 0: Protection using the A key
501  // 1: Protection using the B key
502  // 2: Protection including leaf functions
503  unsigned Value = 0;
504 
505  if (Opts.isSignReturnAddressWithAKey())
506  Value |= (1 << 0);
507  else
508  Value |= (1 << 1);
509 
510  if (Opts.isSignReturnAddressScopeAll())
511  Value |= (1 << 2);
512 
513  Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
514  }
515 
516  if (Opts.BranchTargetEnforcement)
517  Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
518 
519  if (HasLS64)
520  Builder.defineMacro("__ARM_FEATURE_LS64", "1");
521 
522  if (HasRandGen)
523  Builder.defineMacro("__ARM_FEATURE_RNG", "1");
524 
525  if (HasMOPS)
526  Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
527 
528  if (HasD128)
529  Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
530 
531  if (*ArchInfo == llvm::AArch64::ARMV8_1A)
532  getTargetDefinesARMV81A(Opts, Builder);
533  else if (*ArchInfo == llvm::AArch64::ARMV8_2A)
534  getTargetDefinesARMV82A(Opts, Builder);
535  else if (*ArchInfo == llvm::AArch64::ARMV8_3A)
536  getTargetDefinesARMV83A(Opts, Builder);
537  else if (*ArchInfo == llvm::AArch64::ARMV8_4A)
538  getTargetDefinesARMV84A(Opts, Builder);
539  else if (*ArchInfo == llvm::AArch64::ARMV8_5A)
540  getTargetDefinesARMV85A(Opts, Builder);
541  else if (*ArchInfo == llvm::AArch64::ARMV8_6A)
542  getTargetDefinesARMV86A(Opts, Builder);
543  else if (*ArchInfo == llvm::AArch64::ARMV8_7A)
544  getTargetDefinesARMV87A(Opts, Builder);
545  else if (*ArchInfo == llvm::AArch64::ARMV8_8A)
546  getTargetDefinesARMV88A(Opts, Builder);
547  else if (*ArchInfo == llvm::AArch64::ARMV8_9A)
548  getTargetDefinesARMV89A(Opts, Builder);
549  else if (*ArchInfo == llvm::AArch64::ARMV9A)
550  getTargetDefinesARMV9A(Opts, Builder);
551  else if (*ArchInfo == llvm::AArch64::ARMV9_1A)
552  getTargetDefinesARMV91A(Opts, Builder);
553  else if (*ArchInfo == llvm::AArch64::ARMV9_2A)
554  getTargetDefinesARMV92A(Opts, Builder);
555  else if (*ArchInfo == llvm::AArch64::ARMV9_3A)
556  getTargetDefinesARMV93A(Opts, Builder);
557  else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
558  getTargetDefinesARMV94A(Opts, Builder);
559 
560  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
561  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
562  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
563  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
564  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
565 
566  // Allow detection of fast FMA support.
567  Builder.defineMacro("__FP_FAST_FMA", "1");
568  Builder.defineMacro("__FP_FAST_FMAF", "1");
569 
570  // C/C++ operators work on both VLS and VLA SVE types
571  if (FPU & SveMode)
572  Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS", "2");
573 
574  if (Opts.VScaleMin && Opts.VScaleMin == Opts.VScaleMax) {
575  Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
576  }
577 }
578 
582 }
583 
584 std::optional<std::pair<unsigned, unsigned>>
586  if (LangOpts.VScaleMin || LangOpts.VScaleMax)
587  return std::pair<unsigned, unsigned>(
588  LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
589 
590  if (hasFeature("sve"))
591  return std::pair<unsigned, unsigned>(1, 16);
592 
593  return std::nullopt;
594 }
595 
596 unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
597  if (Name == "default")
598  return 0;
599  for (const auto &E : llvm::AArch64::Extensions)
600  if (Name == E.Name)
601  return E.FmvPriority;
602  return 0;
603 }
604 
606  // Take the maximum priority as per feature cost, so more features win.
607  return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
608 }
609 
611  std::string &FeatureVec) const {
612  FeatureVec = "";
613  for (const auto &E : llvm::AArch64::Extensions) {
614  if (Name == E.Name) {
615  FeatureVec = E.DependentFeatures;
616  break;
617  }
618  }
619  return FeatureVec != "";
620 }
621 
622 bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
623  for (const auto &E : llvm::AArch64::Extensions)
624  if (FeatureStr == E.Name)
625  return true;
626  return false;
627 }
628 
629 bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
630  return llvm::StringSwitch<bool>(Feature)
631  .Cases("aarch64", "arm64", "arm", true)
632  .Case("fmv", HasFMV)
633  .Cases("neon", "fp", "simd", FPU & NeonMode)
634  .Case("jscvt", HasJSCVT)
635  .Case("fcma", HasFCMA)
636  .Case("rng", HasRandGen)
637  .Case("flagm", HasFlagM)
638  .Case("flagm2", HasAlternativeNZCV)
639  .Case("fp16fml", HasFP16FML)
640  .Case("dotprod", HasDotProd)
641  .Case("sm4", HasSM4)
642  .Case("rdm", HasRDM)
643  .Case("lse", HasLSE)
644  .Case("crc", HasCRC)
645  .Case("sha2", HasSHA2)
646  .Case("sha3", HasSHA3)
647  .Cases("aes", "pmull", HasAES)
648  .Cases("fp16", "fullfp16", HasFullFP16)
649  .Case("dit", HasDIT)
650  .Case("dpb", HasCCPP)
651  .Case("dpb2", HasCCDP)
652  .Case("rcpc", HasRCPC)
653  .Case("frintts", HasFRInt3264)
654  .Case("i8mm", HasMatMul)
655  .Case("bf16", HasBFloat16)
656  .Case("sve", FPU & SveMode)
657  .Case("sve-bf16", FPU & SveMode && HasBFloat16)
658  .Case("sve-i8mm", FPU & SveMode && HasMatMul)
659  .Case("f32mm", FPU & SveMode && HasMatmulFP32)
660  .Case("f64mm", FPU & SveMode && HasMatmulFP64)
661  .Case("sve2", FPU & SveMode && HasSVE2)
662  .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
663  .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
664  .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
665  .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
666  .Case("sme", HasSME)
667  .Case("sme-f64f64", HasSMEF64)
668  .Case("sme-i16i64", HasSMEI64)
669  .Cases("memtag", "memtag2", HasMTE)
670  .Case("sb", HasSB)
671  .Case("predres", HasPredRes)
672  .Cases("ssbs", "ssbs2", HasSSBS)
673  .Case("bti", HasBTI)
674  .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
675  .Case("wfxt", HasWFxT)
676  .Default(false);
677 }
678 
679 void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
680  StringRef Name, bool Enabled) const {
681  Features[Name] = Enabled;
682  // If the feature is an architecture feature (like v8.2a), add all previous
683  // architecture versions and any dependant target features.
684  const std::optional<llvm::AArch64::ArchInfo> ArchInfo =
685  llvm::AArch64::ArchInfo::findBySubArch(Name);
686 
687  if (!ArchInfo)
688  return; // Not an architecure, nothing more to do.
689 
690  for (const auto *OtherArch : llvm::AArch64::ArchInfos)
691  if (ArchInfo->implies(*OtherArch))
692  Features[OtherArch->getSubArch()] = Enabled;
693 
694  // Set any features implied by the architecture
695  std::vector<StringRef> CPUFeats;
696  if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) {
697  for (auto F : CPUFeats) {
698  assert(F[0] == '+' && "Expected + in target feature!");
699  Features[F.drop_front(1)] = true;
700  }
701  }
702 }
703 
704 bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
705  DiagnosticsEngine &Diags) {
706  for (const auto &Feature : Features) {
707  if (Feature == "-neon")
708  HasNoNeon = true;
709  if (Feature == "-sve")
710  HasNoSVE = true;
711 
712  if (Feature == "+neon" || Feature == "+fp-armv8")
713  FPU |= NeonMode;
714  if (Feature == "+jscvt") {
715  HasJSCVT = true;
716  FPU |= NeonMode;
717  }
718  if (Feature == "+fcma") {
719  HasFCMA = true;
720  FPU |= NeonMode;
721  }
722 
723  if (Feature == "+sve") {
724  FPU |= NeonMode;
725  FPU |= SveMode;
726  HasFullFP16 = true;
727  }
728  if (Feature == "+sve2") {
729  FPU |= NeonMode;
730  FPU |= SveMode;
731  HasFullFP16 = true;
732  HasSVE2 = true;
733  }
734  if (Feature == "+sve2-aes") {
735  FPU |= NeonMode;
736  FPU |= SveMode;
737  HasFullFP16 = true;
738  HasSVE2 = true;
739  HasSVE2AES = true;
740  }
741  if (Feature == "+sve2-sha3") {
742  FPU |= NeonMode;
743  FPU |= SveMode;
744  HasFullFP16 = true;
745  HasSVE2 = true;
746  HasSVE2SHA3 = true;
747  }
748  if (Feature == "+sve2-sm4") {
749  FPU |= NeonMode;
750  FPU |= SveMode;
751  HasFullFP16 = true;
752  HasSVE2 = true;
753  HasSVE2SM4 = true;
754  }
755  if (Feature == "+sve2-bitperm") {
756  FPU |= NeonMode;
757  FPU |= SveMode;
758  HasFullFP16 = true;
759  HasSVE2 = true;
760  HasSVE2BitPerm = true;
761  }
762  if (Feature == "+f32mm") {
763  FPU |= NeonMode;
764  FPU |= SveMode;
765  HasFullFP16 = true;
766  HasMatmulFP32 = true;
767  }
768  if (Feature == "+f64mm") {
769  FPU |= NeonMode;
770  FPU |= SveMode;
771  HasFullFP16 = true;
772  HasMatmulFP64 = true;
773  }
774  if (Feature == "+sme") {
775  HasSME = true;
776  HasBFloat16 = true;
777  }
778  if (Feature == "+sme-f64f64") {
779  HasSME = true;
780  HasSMEF64 = true;
781  HasBFloat16 = true;
782  }
783  if (Feature == "+sme-i16i64") {
784  HasSME = true;
785  HasSMEI64 = true;
786  HasBFloat16 = true;
787  }
788  if (Feature == "+sb")
789  HasSB = true;
790  if (Feature == "+predres")
791  HasPredRes = true;
792  if (Feature == "+ssbs")
793  HasSSBS = true;
794  if (Feature == "+bti")
795  HasBTI = true;
796  if (Feature == "+wfxt")
797  HasWFxT = true;
798  if (Feature == "-fmv")
799  HasFMV = false;
800  if (Feature == "+crc")
801  HasCRC = true;
802  if (Feature == "+rcpc")
803  HasRCPC = true;
804  if (Feature == "+aes") {
805  FPU |= NeonMode;
806  HasAES = true;
807  }
808  if (Feature == "+sha2") {
809  FPU |= NeonMode;
810  HasSHA2 = true;
811  }
812  if (Feature == "+sha3") {
813  FPU |= NeonMode;
814  HasSHA2 = true;
815  HasSHA3 = true;
816  }
817  if (Feature == "+rdm") {
818  FPU |= NeonMode;
819  HasRDM = true;
820  }
821  if (Feature == "+dit")
822  HasDIT = true;
823  if (Feature == "+cccp")
824  HasCCPP = true;
825  if (Feature == "+ccdp") {
826  HasCCPP = true;
827  HasCCDP = true;
828  }
829  if (Feature == "+fptoint")
830  HasFRInt3264 = true;
831  if (Feature == "+sm4") {
832  FPU |= NeonMode;
833  HasSM4 = true;
834  }
835  if (Feature == "+strict-align")
836  HasUnaligned = false;
837  // All predecessor archs are added but select the latest one for ArchKind.
838  if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version)
839  ArchInfo = &llvm::AArch64::ARMV8A;
840  if (Feature == "+v8.1a" &&
841  ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version)
842  ArchInfo = &llvm::AArch64::ARMV8_1A;
843  if (Feature == "+v8.2a" &&
844  ArchInfo->Version < llvm::AArch64::ARMV8_2A.Version)
845  ArchInfo = &llvm::AArch64::ARMV8_2A;
846  if (Feature == "+v8.3a" &&
847  ArchInfo->Version < llvm::AArch64::ARMV8_3A.Version)
848  ArchInfo = &llvm::AArch64::ARMV8_3A;
849  if (Feature == "+v8.4a" &&
850  ArchInfo->Version < llvm::AArch64::ARMV8_4A.Version)
851  ArchInfo = &llvm::AArch64::ARMV8_4A;
852  if (Feature == "+v8.5a" &&
853  ArchInfo->Version < llvm::AArch64::ARMV8_5A.Version)
854  ArchInfo = &llvm::AArch64::ARMV8_5A;
855  if (Feature == "+v8.6a" &&
856  ArchInfo->Version < llvm::AArch64::ARMV8_6A.Version)
857  ArchInfo = &llvm::AArch64::ARMV8_6A;
858  if (Feature == "+v8.7a" &&
859  ArchInfo->Version < llvm::AArch64::ARMV8_7A.Version)
860  ArchInfo = &llvm::AArch64::ARMV8_7A;
861  if (Feature == "+v8.8a" &&
862  ArchInfo->Version < llvm::AArch64::ARMV8_8A.Version)
863  ArchInfo = &llvm::AArch64::ARMV8_8A;
864  if (Feature == "+v8.9a" &&
865  ArchInfo->Version < llvm::AArch64::ARMV8_9A.Version)
866  ArchInfo = &llvm::AArch64::ARMV8_9A;
867  if (Feature == "+v9a" && ArchInfo->Version < llvm::AArch64::ARMV9A.Version)
868  ArchInfo = &llvm::AArch64::ARMV9A;
869  if (Feature == "+v9.1a" &&
870  ArchInfo->Version < llvm::AArch64::ARMV9_1A.Version)
871  ArchInfo = &llvm::AArch64::ARMV9_1A;
872  if (Feature == "+v9.2a" &&
873  ArchInfo->Version < llvm::AArch64::ARMV9_2A.Version)
874  ArchInfo = &llvm::AArch64::ARMV9_2A;
875  if (Feature == "+v9.3a" &&
876  ArchInfo->Version < llvm::AArch64::ARMV9_3A.Version)
877  ArchInfo = &llvm::AArch64::ARMV9_3A;
878  if (Feature == "+v9.4a" &&
879  ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
880  ArchInfo = &llvm::AArch64::ARMV9_4A;
881  if (Feature == "+v8r")
882  ArchInfo = &llvm::AArch64::ARMV8R;
883  if (Feature == "+fullfp16") {
884  FPU |= NeonMode;
885  HasFullFP16 = true;
886  }
887  if (Feature == "+dotprod") {
888  FPU |= NeonMode;
889  HasDotProd = true;
890  }
891  if (Feature == "+fp16fml") {
892  FPU |= NeonMode;
893  HasFullFP16 = true;
894  HasFP16FML = true;
895  }
896  if (Feature == "+mte")
897  HasMTE = true;
898  if (Feature == "+tme")
899  HasTME = true;
900  if (Feature == "+pauth")
901  HasPAuth = true;
902  if (Feature == "+i8mm")
903  HasMatMul = true;
904  if (Feature == "+bf16")
905  HasBFloat16 = true;
906  if (Feature == "+lse")
907  HasLSE = true;
908  if (Feature == "+ls64")
909  HasLS64 = true;
910  if (Feature == "+rand")
911  HasRandGen = true;
912  if (Feature == "+flagm")
913  HasFlagM = true;
914  if (Feature == "+altnzcv") {
915  HasFlagM = true;
916  HasAlternativeNZCV = true;
917  }
918  if (Feature == "+mops")
919  HasMOPS = true;
920  if (Feature == "+d128")
921  HasD128 = true;
922  }
923 
924  // Check features that are manually disabled by command line options.
925  // This needs to be checked after architecture-related features are handled,
926  // making sure they are properly disabled when required.
927  for (const auto &Feature : Features) {
928  if (Feature == "-d128")
929  HasD128 = false;
930  }
931 
932  setDataLayout();
933  setArchFeatures();
934 
935  if (HasNoNeon) {
936  FPU &= ~NeonMode;
937  FPU &= ~SveMode;
938  }
939  if (HasNoSVE)
940  FPU &= ~SveMode;
941 
942  return true;
943 }
944 
946  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
947  const std::vector<std::string> &FeaturesVec) const {
948  std::vector<std::string> UpdatedFeaturesVec;
949  // Parse the CPU and add any implied features.
950  std::optional<llvm::AArch64::CpuInfo> CpuInfo = llvm::AArch64::parseCpu(CPU);
951  if (CpuInfo) {
952  uint64_t Exts = CpuInfo->getImpliedExtensions();
953  std::vector<StringRef> CPUFeats;
954  llvm::AArch64::getExtensionFeatures(Exts, CPUFeats);
955  for (auto F : CPUFeats) {
956  assert((F[0] == '+' || F[0] == '-') && "Expected +/- in target feature!");
957  UpdatedFeaturesVec.push_back(F.str());
958  }
959  }
960 
961  // Process target and dependent features. This is done in two loops collecting
962  // them into UpdatedFeaturesVec: first to add dependent '+'features,
963  // second to add target '+/-'features that can later disable some of
964  // features added on the first loop.
965  for (const auto &Feature : FeaturesVec)
966  if ((Feature[0] == '?' || Feature[0] == '+')) {
967  std::string Options;
968  if (AArch64TargetInfo::getFeatureDepOptions(Feature.substr(1), Options)) {
969  SmallVector<StringRef, 1> AttrFeatures;
970  StringRef(Options).split(AttrFeatures, ",");
971  for (auto F : AttrFeatures)
972  UpdatedFeaturesVec.push_back(F.str());
973  }
974  }
975  for (const auto &Feature : FeaturesVec)
976  if (Feature[0] != '?') {
977  std::string UpdatedFeature = Feature;
978  if (Feature[0] == '+') {
979  std::optional<llvm::AArch64::ExtensionInfo> Extension =
980  llvm::AArch64::parseArchExtension(Feature.substr(1));
981  if (Extension)
982  UpdatedFeature = Extension->Feature.str();
983  }
984  UpdatedFeaturesVec.push_back(UpdatedFeature);
985  }
986 
987  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
988 }
989 
990 // Parse AArch64 Target attributes, which are a comma separated list of:
991 // "arch=<arch>" - parsed to features as per -march=..
992 // "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
993 // "tune=<cpu>" - TuneCPU set to <cpu>
994 // "feature", "no-feature" - Add (or remove) feature.
995 // "+feature", "+nofeature" - Add (or remove) feature.
998  if (Features == "default")
999  return Ret;
1000  SmallVector<StringRef, 1> AttrFeatures;
1001  Features.split(AttrFeatures, ",");
1002  bool FoundArch = false;
1003 
1004  auto SplitAndAddFeatures = [](StringRef FeatString,
1005  std::vector<std::string> &Features) {
1006  SmallVector<StringRef, 8> SplitFeatures;
1007  FeatString.split(SplitFeatures, StringRef("+"), -1, false);
1008  for (StringRef Feature : SplitFeatures) {
1009  StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
1010  if (!FeatureName.empty())
1011  Features.push_back(FeatureName.str());
1012  else
1013  // Pushing the original feature string to give a sema error later on
1014  // when they get checked.
1015  if (Feature.startswith("no"))
1016  Features.push_back("-" + Feature.drop_front(2).str());
1017  else
1018  Features.push_back("+" + Feature.str());
1019  }
1020  };
1021 
1022  for (auto &Feature : AttrFeatures) {
1023  Feature = Feature.trim();
1024  if (Feature.startswith("fpmath="))
1025  continue;
1026 
1027  if (Feature.startswith("branch-protection=")) {
1028  Ret.BranchProtection = Feature.split('=').second.trim();
1029  continue;
1030  }
1031 
1032  if (Feature.startswith("arch=")) {
1033  if (FoundArch)
1034  Ret.Duplicate = "arch=";
1035  FoundArch = true;
1036  std::pair<StringRef, StringRef> Split =
1037  Feature.split("=").second.trim().split("+");
1038  const std::optional<llvm::AArch64::ArchInfo> AI =
1039  llvm::AArch64::parseArch(Split.first);
1040 
1041  // Parse the architecture version, adding the required features to
1042  // Ret.Features.
1043  if (!AI)
1044  continue;
1045  Ret.Features.push_back(AI->ArchFeature.str());
1046  // Add any extra features, after the +
1047  SplitAndAddFeatures(Split.second, Ret.Features);
1048  } else if (Feature.startswith("cpu=")) {
1049  if (!Ret.CPU.empty())
1050  Ret.Duplicate = "cpu=";
1051  else {
1052  // Split the cpu string into "cpu=", "cortex-a710" and any remaining
1053  // "+feat" features.
1054  std::pair<StringRef, StringRef> Split =
1055  Feature.split("=").second.trim().split("+");
1056  Ret.CPU = Split.first;
1057  SplitAndAddFeatures(Split.second, Ret.Features);
1058  }
1059  } else if (Feature.startswith("tune=")) {
1060  if (!Ret.Tune.empty())
1061  Ret.Duplicate = "tune=";
1062  else
1063  Ret.Tune = Feature.split("=").second.trim();
1064  } else if (Feature.startswith("+")) {
1065  SplitAndAddFeatures(Feature, Ret.Features);
1066  } else if (Feature.startswith("no-")) {
1067  StringRef FeatureName =
1068  llvm::AArch64::getArchExtFeature(Feature.split("-").second);
1069  if (!FeatureName.empty())
1070  Ret.Features.push_back("-" + FeatureName.drop_front(1).str());
1071  else
1072  Ret.Features.push_back("-" + Feature.split("-").second.str());
1073  } else {
1074  // Try parsing the string to the internal target feature name. If it is
1075  // invalid, add the original string (which could already be an internal
1076  // name). These should be checked later by isValidFeatureName.
1077  StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
1078  if (!FeatureName.empty())
1079  Ret.Features.push_back(FeatureName.str());
1080  else
1081  Ret.Features.push_back("+" + Feature.str());
1082  }
1083  }
1084  return Ret;
1085 }
1086 
1088  return true;
1089 }
1090 
1093  switch (CC) {
1094  case CC_C:
1095  case CC_Swift:
1096  case CC_SwiftAsync:
1097  case CC_PreserveMost:
1098  case CC_PreserveAll:
1099  case CC_OpenCLKernel:
1100  case CC_AArch64VectorCall:
1101  case CC_AArch64SVEPCS:
1102  case CC_Win64:
1103  return CCCR_OK;
1104  default:
1105  return CCCR_Warning;
1106  }
1107 }
1108 
1109 bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
1110 
1113 }
1114 
1115 const char *const AArch64TargetInfo::GCCRegNames[] = {
1116  // 32-bit Integer registers
1117  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
1118  "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
1119  "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
1120 
1121  // 64-bit Integer registers
1122  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
1123  "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
1124  "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
1125 
1126  // 32-bit floating point regsisters
1127  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
1128  "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
1129  "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1130 
1131  // 64-bit floating point regsisters
1132  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
1133  "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
1134  "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
1135 
1136  // Neon vector registers
1137  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
1138  "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
1139  "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1140 
1141  // SVE vector registers
1142  "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10",
1143  "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
1144  "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
1145 
1146  // SVE predicate registers
1147  "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10",
1148  "p11", "p12", "p13", "p14", "p15"
1149 };
1150 
1152  return llvm::ArrayRef(GCCRegNames);
1153 }
1154 
1155 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
1156  {{"w31"}, "wsp"},
1157  {{"x31"}, "sp"},
1158  // GCC rN registers are aliases of xN registers.
1159  {{"r0"}, "x0"},
1160  {{"r1"}, "x1"},
1161  {{"r2"}, "x2"},
1162  {{"r3"}, "x3"},
1163  {{"r4"}, "x4"},
1164  {{"r5"}, "x5"},
1165  {{"r6"}, "x6"},
1166  {{"r7"}, "x7"},
1167  {{"r8"}, "x8"},
1168  {{"r9"}, "x9"},
1169  {{"r10"}, "x10"},
1170  {{"r11"}, "x11"},
1171  {{"r12"}, "x12"},
1172  {{"r13"}, "x13"},
1173  {{"r14"}, "x14"},
1174  {{"r15"}, "x15"},
1175  {{"r16"}, "x16"},
1176  {{"r17"}, "x17"},
1177  {{"r18"}, "x18"},
1178  {{"r19"}, "x19"},
1179  {{"r20"}, "x20"},
1180  {{"r21"}, "x21"},
1181  {{"r22"}, "x22"},
1182  {{"r23"}, "x23"},
1183  {{"r24"}, "x24"},
1184  {{"r25"}, "x25"},
1185  {{"r26"}, "x26"},
1186  {{"r27"}, "x27"},
1187  {{"r28"}, "x28"},
1188  {{"r29", "x29"}, "fp"},
1189  {{"r30", "x30"}, "lr"},
1190  // The S/D/Q and W/X registers overlap, but aren't really aliases; we
1191  // don't want to substitute one of these for a different-sized one.
1192 };
1193 
1195  return llvm::ArrayRef(GCCRegAliases);
1196 }
1197 
1199  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1200  switch (*Name) {
1201  default:
1202  return false;
1203  case 'w': // Floating point and SIMD registers (V0-V31)
1204  Info.setAllowsRegister();
1205  return true;
1206  case 'I': // Constant that can be used with an ADD instruction
1207  case 'J': // Constant that can be used with a SUB instruction
1208  case 'K': // Constant that can be used with a 32-bit logical instruction
1209  case 'L': // Constant that can be used with a 64-bit logical instruction
1210  case 'M': // Constant that can be used as a 32-bit MOV immediate
1211  case 'N': // Constant that can be used as a 64-bit MOV immediate
1212  case 'Y': // Floating point constant zero
1213  case 'Z': // Integer constant zero
1214  return true;
1215  case 'Q': // A memory reference with base register and no offset
1216  Info.setAllowsMemory();
1217  return true;
1218  case 'S': // A symbolic address
1219  Info.setAllowsRegister();
1220  return true;
1221  case 'U':
1222  if (Name[1] == 'p' && (Name[2] == 'l' || Name[2] == 'a')) {
1223  // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
1224  Info.setAllowsRegister();
1225  Name += 2;
1226  return true;
1227  }
1228  // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
1229  // Utf: A memory address suitable for ldp/stp in TF mode.
1230  // Usa: An absolute symbolic address.
1231  // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
1232 
1233  // Better to return an error saying that it's an unrecognised constraint
1234  // even if this is a valid constraint in gcc.
1235  return false;
1236  case 'z': // Zero register, wzr or xzr
1237  Info.setAllowsRegister();
1238  return true;
1239  case 'x': // Floating point and SIMD registers (V0-V15)
1240  Info.setAllowsRegister();
1241  return true;
1242  case 'y': // SVE registers (V0-V7)
1243  Info.setAllowsRegister();
1244  return true;
1245  }
1246  return false;
1247 }
1248 
1250  StringRef Constraint, char Modifier, unsigned Size,
1251  std::string &SuggestedModifier) const {
1252  // Strip off constraint modifiers.
1253  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1254  Constraint = Constraint.substr(1);
1255 
1256  switch (Constraint[0]) {
1257  default:
1258  return true;
1259  case 'z':
1260  case 'r': {
1261  switch (Modifier) {
1262  case 'x':
1263  case 'w':
1264  // For now assume that the person knows what they're
1265  // doing with the modifier.
1266  return true;
1267  default:
1268  // By default an 'r' constraint will be in the 'x'
1269  // registers.
1270  if (Size == 64)
1271  return true;
1272 
1273  if (Size == 512)
1274  return HasLS64;
1275 
1276  SuggestedModifier = "w";
1277  return false;
1278  }
1279  }
1280  }
1281 }
1282 
1283 const char *AArch64TargetInfo::getClobbers() const { return ""; }
1284 
1286  if (RegNo == 0)
1287  return 0;
1288  if (RegNo == 1)
1289  return 1;
1290  return -1;
1291 }
1292 
1293 bool AArch64TargetInfo::hasInt128Type() const { return true; }
1294 
1295 AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
1296  const TargetOptions &Opts)
1297  : AArch64TargetInfo(Triple, Opts) {}
1298 
1299 void AArch64leTargetInfo::setDataLayout() {
1300  if (getTriple().isOSBinFormatMachO()) {
1301  if(getTriple().isArch32Bit())
1302  resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
1303  else
1304  resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
1305  } else
1306  resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
1307 }
1308 
1310  MacroBuilder &Builder) const {
1311  Builder.defineMacro("__AARCH64EL__");
1312  AArch64TargetInfo::getTargetDefines(Opts, Builder);
1313 }
1314 
1315 AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
1316  const TargetOptions &Opts)
1317  : AArch64TargetInfo(Triple, Opts) {}
1318 
1320  MacroBuilder &Builder) const {
1321  Builder.defineMacro("__AARCH64EB__");
1322  Builder.defineMacro("__AARCH_BIG_ENDIAN");
1323  Builder.defineMacro("__ARM_BIG_ENDIAN");
1324  AArch64TargetInfo::getTargetDefines(Opts, Builder);
1325 }
1326 
1327 void AArch64beTargetInfo::setDataLayout() {
1328  assert(!getTriple().isOSBinFormatMachO());
1329  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
1330 }
1331 
1333  const TargetOptions &Opts)
1334  : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
1335 
1336  // This is an LLP64 platform.
1337  // int:4, long:4, long long:8, long double:8.
1338  IntWidth = IntAlign = 32;
1339  LongWidth = LongAlign = 32;
1340  DoubleAlign = LongLongAlign = 64;
1342  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1348 }
1349 
1351  resetDataLayout(Triple.isOSBinFormatMachO()
1352  ? "e-m:o-i64:64-i128:128-n32:64-S128"
1353  : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128",
1354  Triple.isOSBinFormatMachO() ? "_" : "");
1355 }
1356 
1360 }
1361 
1364  switch (CC) {
1365  case CC_X86StdCall:
1366  case CC_X86ThisCall:
1367  case CC_X86FastCall:
1368  case CC_X86VectorCall:
1369  return CCCR_Ignore;
1370  case CC_C:
1371  case CC_OpenCLKernel:
1372  case CC_PreserveMost:
1373  case CC_PreserveAll:
1374  case CC_Swift:
1375  case CC_SwiftAsync:
1376  case CC_Win64:
1377  return CCCR_OK;
1378  default:
1379  return CCCR_Warning;
1380  }
1381 }
1382 
1384  const TargetOptions &Opts)
1385  : WindowsARM64TargetInfo(Triple, Opts) {
1386  TheCXXABI.set(TargetCXXABI::Microsoft);
1387 }
1388 
1390  MacroBuilder &Builder) const {
1392  Builder.defineMacro("_M_ARM64", "1");
1393 }
1394 
1397  return CCK_MicrosoftWin64;
1398 }
1399 
1401  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
1402 
1403  // MSVC does size based alignment for arm64 based on alignment section in
1404  // below document, replicate that to keep alignment consistent with object
1405  // files compiled by MSVC.
1406  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
1407  if (TypeSize >= 512) { // TypeSize >= 64 bytes
1408  Align = std::max(Align, 128u); // align type at least 16 bytes
1409  } else if (TypeSize >= 64) { // TypeSize >= 8 bytes
1410  Align = std::max(Align, 64u); // align type at least 8 butes
1411  } else if (TypeSize >= 16) { // TypeSize >= 2 bytes
1412  Align = std::max(Align, 32u); // align type at least 4 bytes
1413  }
1414  return Align;
1415 }
1416 
1418  const TargetOptions &Opts)
1419  : WindowsARM64TargetInfo(Triple, Opts) {
1420  TheCXXABI.set(TargetCXXABI::GenericAArch64);
1421 }
1422 
1424  const TargetOptions &Opts)
1425  : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1427  if (getTriple().isArch32Bit())
1429 
1430  WCharType = SignedInt;
1431  UseSignedCharForObjCBool = false;
1432 
1434  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1435 
1437 
1438  if (getTriple().isArch32Bit()) {
1439  UseBitFieldTypeAlignment = false;
1442  TheCXXABI.set(TargetCXXABI::WatchOS);
1443  } else
1444  TheCXXABI.set(TargetCXXABI::AppleARM64);
1445 }
1446 
1448  const llvm::Triple &Triple,
1449  MacroBuilder &Builder) const {
1450  Builder.defineMacro("__AARCH64_SIMD__");
1451  if (Triple.isArch32Bit())
1452  Builder.defineMacro("__ARM64_ARCH_8_32__");
1453  else
1454  Builder.defineMacro("__ARM64_ARCH_8__");
1455  Builder.defineMacro("__ARM_NEON__");
1456  Builder.defineMacro("__LITTLE_ENDIAN__");
1457  Builder.defineMacro("__REGISTER_PREFIX__", "");
1458  Builder.defineMacro("__arm64", "1");
1459  Builder.defineMacro("__arm64__", "1");
1460 
1461  if (Triple.isArm64e())
1462  Builder.defineMacro("__arm64e__", "1");
1463 
1464  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1465 }
1466 
1470 }
1471 
1472 // 64-bit RenderScript is aarch64
1474  const TargetOptions &Opts)
1475  : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
1476  Triple.getOSName(),
1477  Triple.getEnvironmentName()),
1478  Opts) {
1479  IsRenderScriptTarget = true;
1480 }
1481 
1483  MacroBuilder &Builder) const {
1484  Builder.defineMacro("__RENDERSCRIPT__");
1486 }
clang::TransferrableTargetInfo::PointerAlign
unsigned char PointerAlign
Definition: TargetInfo.h:84
clang::targets::WindowsARM64TargetInfo::setDataLayout
void setDataLayout() override
Definition: AArch64.cpp:1350
clang::TransferrableTargetInfo::LongWidth
unsigned char LongWidth
Definition: TargetInfo.h:93
clang::targets::AArch64TargetInfo::getTargetDefinesARMV84A
void getTargetDefinesARMV84A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:261
clang::TargetInfo::CCCR_Ignore
@ CCCR_Ignore
Definition: TargetInfo.h:1561
clang::TargetInfo::BranchProtectionInfo::SignKey
LangOptions::SignReturnAddressKeyKind SignKey
Definition: TargetInfo.h:1345
clang::targets::AArch64TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: AArch64.cpp:629
clang::targets::OSTargetInfo< AArch64leTargetInfo >::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: OSTargets.h:30
max
__DEVICE__ int max(int __a, int __b)
Definition: __clang_cuda_math.h:196
clang::targets::AArch64TargetInfo::getTargetDefinesARMV87A
void getTargetDefinesARMV87A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:285
clang::targets::AArch64TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition: AArch64.cpp:622
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YAML serialization mapping.
Definition: Dominators.h:30
clang::CC_X86FastCall
@ CC_X86FastCall
Definition: Specifiers.h:269
clang::TargetInfo::PlatformMinVersion
VersionTuple PlatformMinVersion
Definition: TargetInfo.h:236
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo
MinGWARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1417
clang::TransferrableTargetInfo::IntPtrType
IntType IntPtrType
Definition: TargetInfo.h:150
clang::targets::AArch64TargetInfo::parseTargetAttr
ParsedTargetAttr parseTargetAttr(StringRef Str) const override
Definition: AArch64.cpp:996
clang::CC_Win64
@ CC_Win64
Definition: Specifiers.h:273
clang::TransferrableTargetInfo::IntMaxType
IntType IntMaxType
Definition: TargetInfo.h:150
clang::targets::AArch64TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: AArch64.cpp:1111
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo
MicrosoftARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1383
clang::LangOptions::isSignReturnAddressScopeAll
bool isSignReturnAddressScopeAll() const
Check if leaf functions are also signed.
Definition: LangOptions.h:602
string
string(SUBSTRING ${CMAKE_CURRENT_BINARY_DIR} 0 ${PATH_LIB_START} PATH_HEAD) string(SUBSTRING $
Definition: CMakeLists.txt:23
clang::TargetInfo::CCCR_Warning
@ CCCR_Warning
Definition: TargetInfo.h:1560
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo
WindowsARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1332
clang::targets::AArch64leTargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1309
clang::targets::AArch64TargetInfo::getTargetDefinesARMV86A
void getTargetDefinesARMV86A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:275
clang::TransferrableTargetInfo::LongLongAlign
unsigned char LongLongAlign
Definition: TargetInfo.h:94
llvm::SmallVector
Definition: LLVM.h:38
clang::targets::AArch64TargetInfo::getTargetDefinesARMV81A
void getTargetDefinesARMV81A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:239
clang::TransferrableTargetInfo::DoubleAlign
unsigned char DoubleAlign
Definition: TargetInfo.h:90
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo
AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1295
clang::TargetInfo::TheCXXABI
TargetCXXABI TheCXXABI
Definition: TargetInfo.h:232
clang::targets::AArch64TargetInfo::setABI
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: AArch64.cpp:196
TargetInfo.h
clang::ParsedTargetAttr
Contains information gathered from parsing the contents of TargetAttr.
Definition: TargetInfo.h:54
clang::TransferrableTargetInfo::UseZeroLengthBitfieldAlignment
unsigned UseZeroLengthBitfieldAlignment
Whether zero length bitfields (e.g., int : 0;) force alignment of the next bitfield.
Definition: TargetInfo.h:173
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
clang::TargetInfo
Exposes information about the current target.
Definition: TargetInfo.h:205
clang::targets::AArch64TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: AArch64.cpp:579
clang::LangOptions::SignReturnAddressScopeKind::NonLeaf
@ NonLeaf
Sign the return address of functions that spill LR.
clang::TransferrableTargetInfo::BFloat16Width
unsigned char BFloat16Width
Definition: TargetInfo.h:88
clang::LangOptions::SignReturnAddressScopeKind::None
@ None
No signing for any function.
clang::targets::AArch64TargetInfo::AArch64TargetInfo
AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:125
clang::TargetInfo::IsRenderScriptTarget
unsigned IsRenderScriptTarget
Definition: TargetInfo.h:244
clang::targets::getDarwinDefines
void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, const llvm::Triple &Triple, StringRef &PlatformName, VersionTuple &PlatformMinVersion)
Definition: OSTargets.cpp:22
clang::CC_X86ThisCall
@ CC_X86ThisCall
Definition: Specifiers.h:270
clang::TransferrableTargetInfo::LongAlign
unsigned char LongAlign
Definition: TargetInfo.h:93
clang::targets::AArch64TargetInfo::getTargetDefinesARMV82A
void getTargetDefinesARMV82A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:246
clang::targets::AArch64TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: AArch64.cpp:945
clang::TransferrableTargetInfo::UnsignedLongLong
@ UnsignedLongLong
Definition: TargetInfo.h:146
clang::TargetInfo::BuiltinVaListKind
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:287
clang::TargetInfo::MaxAtomicPromoteWidth
unsigned char MaxAtomicPromoteWidth
Definition: TargetInfo.h:227
clang::TargetInfo::ConstraintInfo::setAllowsRegister
void setAllowsRegister()
Definition: TargetInfo.h:1085
clang::TransferrableTargetInfo::BFloat16Format
const llvm::fltSemantics * BFloat16Format
Definition: TargetInfo.h:131
clang::targets::AArch64TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: AArch64.cpp:1198
clang::CC_X86StdCall
@ CC_X86StdCall
Definition: Specifiers.h:268
clang::LangOptions::SignReturnAddressKeyKind::AKey
@ AKey
Return address signing uses APIA key.
clang::targets::DarwinAArch64TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: AArch64.cpp:1468
clang::CC_OpenCLKernel
@ CC_OpenCLKernel
Definition: Specifiers.h:280
clang::TargetInfo::ConstraintInfo::setAllowsMemory
void setAllowsMemory()
Definition: TargetInfo.h:1084
clang::TargetInfo::HasLegalHalfType
bool HasLegalHalfType
Definition: TargetInfo.h:216
clang::targets::AArch64TargetInfo::getTargetDefinesARMV94A
void getTargetDefinesARMV94A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:327
clang::TargetInfo::HasAArch64SVETypes
unsigned HasAArch64SVETypes
Definition: TargetInfo.h:246
clang::targets::AArch64TargetInfo::getEHDataRegisterNumber
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: AArch64.cpp:1285
clang::CC_Swift
@ CC_Swift
Definition: Specifiers.h:281
clang::targets::AArch64TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features (e.g., +sse4).
Definition: AArch64.cpp:704
clang::targets::AArch64TargetInfo::getTargetDefinesARMV9A
void getTargetDefinesARMV9A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:303
clang::targets::WindowsTargetInfo
Definition: OSTargets.h:849
clang::targets::DarwinTargetInfo
Definition: OSTargets.h:76
hlsl::uint64_t
unsigned long uint64_t
Definition: hlsl_basic_types.h:25
clang::targets::MicrosoftARM64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition: AArch64.cpp:1400
clang::targets::AArch64TargetInfo::setArchFeatures
void setArchFeatures()
Definition: AArch64.cpp:52
LangOptions.h
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:518
clang::targets::AArch64TargetInfo
Definition: AArch64.h:24
clang::TargetInfo::CCCR_OK
@ CCCR_OK
Definition: TargetInfo.h:1559
clang::targets::AArch64TargetInfo::getVScaleRange
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts) const override
Returns target-specific min and max values VScale_Range.
Definition: AArch64.cpp:585
clang::TargetInfo::NoAsmVariants
bool NoAsmVariants
Definition: TargetInfo.h:215
clang::targets::AArch64TargetInfo::hasInt128Type
bool hasInt128Type() const override
Determine whether the __int128 type is supported on this target.
Definition: AArch64.cpp:1293
clang::CallingConv
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:266
clang::TargetInfo::resetDataLayout
void resetDataLayout(StringRef DL, const char *UserLabelPrefix="")
Definition: TargetInfo.cpp:186
clang::TargetInfo::GCCRegAlias
Definition: TargetInfo.h:1204
clang::targets::AArch64TargetInfo::getTargetDefinesARMV85A
void getTargetDefinesARMV85A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:267
clang::targets::AArch64TargetInfo::validateBranchProtection
bool validateBranchProtection(StringRef Spec, StringRef Arch, BranchProtectionInfo &BPI, StringRef &Err) const override
Determine if this TargetInfo supports the given branch protection specification.
Definition: AArch64.cpp:204
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo
RenderScript64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1473
clang::targets::MicrosoftARM64TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1389
clang::TargetInfo::HasStrictFP
bool HasStrictFP
Definition: TargetInfo.h:225
clang::TransferrableTargetInfo::BFloat16Align
unsigned char BFloat16Align
Definition: TargetInfo.h:88
clang::targets::AArch64leTargetInfo
Definition: AArch64.h:203
clang::targets::AArch64TargetInfo::isCLZForZeroUndef
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: AArch64.cpp:1109
clang::CC_C
@ CC_C
Definition: Specifiers.h:267
clang::targets::AArch64TargetInfo::checkCallingConvention
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: AArch64.cpp:1092
clang::TargetInfo::BranchProtectionInfo::BranchTargetEnforcement
bool BranchTargetEnforcement
Definition: TargetInfo.h:1347
clang::targets::AArch64TargetInfo::getABI
StringRef getABI() const override
Get the ABI currently in use.
Definition: AArch64.cpp:194
clang::targets::AArch64TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: AArch64.cpp:234
clang::targets::AArch64TargetInfo::multiVersionSortPriority
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: AArch64.cpp:596
clang::TargetCXXABI::set
void set(Kind kind)
Definition: TargetCXXABI.h:78
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1190
clang::TargetInfo::BranchProtectionInfo
Definition: TargetInfo.h:1342
clang::TransferrableTargetInfo::PtrDiffType
IntType PtrDiffType
Definition: TargetInfo.h:150
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition: TargetInfo.h:280
clang::targets::AArch64TargetInfo::hasBFloat16Type
bool hasBFloat16Type() const override
Determine whether the _BFloat16 type is supported on this target.
Definition: AArch64.cpp:1087
clang::targets::AArch64beTargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1319
clang::targets::MicrosoftARM64TargetInfo::getCallingConvKind
TargetInfo::CallingConvKind getCallingConvKind(bool ClangABICompat4) const override
Definition: AArch64.cpp:1396
clang::CC_PreserveAll
@ CC_PreserveAll
Definition: Specifiers.h:284
clang::TargetInfo::PlatformName
StringRef PlatformName
Definition: TargetInfo.h:235
clang::TargetInfo::MCountName
const char * MCountName
Definition: TargetInfo.h:230
llvm::ArrayRef
Definition: LLVM.h:34
Value
Value
Definition: UninitializedValues.cpp:102
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:132
clang::targets::AArch64TargetInfo::getClobbers
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: AArch64.cpp:1283
clang::targets::AArch64TargetInfo::isValidCPUName
bool isValidCPUName(StringRef Name) const override
brief Determine whether this TargetInfo supports the given CPU name.
Definition: AArch64.cpp:226
clang::TargetInfo::CharPtrBuiltinVaList
@ CharPtrBuiltinVaList
typedef char* __builtin_va_list;
Definition: TargetInfo.h:289
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition: TargetInfo.h:679
clang::interp::Ret
bool Ret(InterpState &S, CodePtr &PC, APValue &Result)
Definition: Interp.h:159
clang::TargetInfo::MaxAtomicInlineWidth
unsigned char MaxAtomicInlineWidth
Definition: TargetInfo.h:227
clang::AArch64::LastTSBuiltin
@ LastTSBuiltin
Definition: TargetBuiltins.h:65
TargetBuiltins.h
clang::CC_X86VectorCall
@ CC_X86VectorCall
Definition: Specifiers.h:271
clang::LangOptions::hasSignReturnAddress
bool hasSignReturnAddress() const
Check if return address signing is enabled.
Definition: LangOptions.h:592
clang::TransferrableTargetInfo::MaxVectorAlign
unsigned MaxVectorAlign
Definition: TargetInfo.h:128
clang::TransferrableTargetInfo::IntAlign
unsigned char IntAlign
Definition: TargetInfo.h:86
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:1021
clang::TransferrableTargetInfo::UseBitFieldTypeAlignment
unsigned UseBitFieldTypeAlignment
Control whether the alignment of bit-field types is respected when laying out structures.
Definition: TargetInfo.h:165
clang::targets::AArch64TargetInfo::getTargetDefinesARMV92A
void getTargetDefinesARMV92A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:315
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:82
clang::targets::AArch64TargetInfo::getTargetDefinesARMV89A
void getTargetDefinesARMV89A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:297
clang::targets::WindowsARM64TargetInfo::checkCallingConvention
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: AArch64.cpp:1363
clang::CC_AArch64SVEPCS
@ CC_AArch64SVEPCS
Definition: Specifiers.h:286
clang::targets::AArch64TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: AArch64.cpp:1151
clang::TargetInfo::HasFloat16
bool HasFloat16
Definition: TargetInfo.h:220
clang::CC_AArch64VectorCall
@ CC_AArch64VectorCall
Definition: Specifiers.h:285
clang
Definition: CalledOnceCheck.h:17
clang::targets
Definition: AArch64.h:22
clang::targets::AArch64TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:333
clang::LangOptions::isSignReturnAddressWithAKey
bool isSignReturnAddressWithAKey() const
Check if return address signing uses AKey.
Definition: LangOptions.h:597
clang::Builtin::Info
Definition: Builtins.h:71
AArch64.h
clang::LangOptions::SignReturnAddressKeyKind::BKey
@ BKey
Return address signing uses APIB key.
clang::TransferrableTargetInfo::SignedInt
@ SignedInt
Definition: TargetInfo.h:141
clang::CC_SwiftAsync
@ CC_SwiftAsync
Definition: Specifiers.h:282
clang::TransferrableTargetInfo::SignedLongLong
@ SignedLongLong
Definition: TargetInfo.h:145
clang::CC_PreserveMost
@ CC_PreserveMost
Definition: Specifiers.h:283
clang::TargetInfo::CCK_MicrosoftWin64
@ CCK_MicrosoftWin64
Definition: TargetInfo.h:1581
clang::TargetInfo::HalfArgsAndReturns
bool HalfArgsAndReturns
Definition: TargetInfo.h:218
clang::TargetOptions::EABIVersion
llvm::EABI EABIVersion
The EABI version to use.
Definition: TargetOptions.h:48
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo
AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1315
clang::Builtin::FirstTSBuiltin
@ FirstTSBuiltin
Definition: Builtins.h:68
clang::targets::AArch64TargetInfo::getGCCRegAliases
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: AArch64.cpp:1194
clang::targets::AArch64TargetInfo::getTargetDefinesARMV88A
void getTargetDefinesARMV88A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:291
c
__device__ __2f16 float c
Definition: __clang_hip_libdevice_declares.h:320
clang::TransferrableTargetInfo::SuitableAlign
unsigned short SuitableAlign
Definition: TargetInfo.h:126
clang::targets::AArch64TargetInfo::validateConstraintModifier
bool validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, std::string &SuggestedModifier) const override
Definition: AArch64.cpp:1249
clang::targets::RenderScript64TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1482
clang::LangOptions::SignReturnAddressScopeKind::All
@ All
Sign the return address of all functions,.
clang::TargetOptions
Options for controlling the target.
Definition: TargetOptions.h:26
llvm::SmallVectorImpl
Definition: Randstruct.h:18
clang::targets::AArch64TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const override
Enable or disable a specific target feature; the feature name must be valid.
Definition: AArch64.cpp:679
clang::targets::DarwinAArch64TargetInfo::getOSDefines
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition: AArch64.cpp:1447
clang::TargetInfo::AArch64ABIBuiltinVaList
@ AArch64ABIBuiltinVaList
__builtin_va_list as defined by the AArch64 ABI http://infocenter.arm.com/help/topic/com....
Definition: TargetInfo.h:296
clang::targets::AArch64TargetInfo::getTargetDefinesARMV93A
void getTargetDefinesARMV93A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:321
clang::TransferrableTargetInfo::IntWidth
unsigned char IntWidth
Definition: TargetInfo.h:86
clang::TransferrableTargetInfo::WCharType
IntType WCharType
Definition: TargetInfo.h:150
clang::TransferrableTargetInfo::PointerWidth
unsigned char PointerWidth
Definition: TargetInfo.h:84
clang::TargetInfo::CallingConvCheckResult
CallingConvCheckResult
Definition: TargetInfo.h:1558
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo
DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1423
clang::TargetInfo::CallingConvKind
CallingConvKind
Definition: TargetInfo.h:1578
clang::targets::WindowsARM64TargetInfo
Definition: AArch64.h:213
clang::targets::AArch64TargetInfo::multiVersionFeatureCost
unsigned multiVersionFeatureCost() const override
Definition: AArch64.cpp:605
clang::TargetInfo::HasBuiltinMSVaList
unsigned HasBuiltinMSVaList
Definition: TargetInfo.h:242
clang::TransferrableTargetInfo::ZeroLengthBitfieldBoundary
unsigned ZeroLengthBitfieldBoundary
If non-zero, specifies a fixed alignment value for bitfields that follow zero length bitfield,...
Definition: TargetInfo.h:184
clang::TransferrableTargetInfo::Int64Type
IntType Int64Type
Definition: TargetInfo.h:151
clang::TransferrableTargetInfo::LongDoubleWidth
unsigned char LongDoubleWidth
Definition: TargetInfo.h:91
clang::targets::AArch64TargetInfo::getFeatureDepOptions
bool getFeatureDepOptions(StringRef Feature, std::string &Options) const override
Returns true if feature has an impact on target code generation and get its dependent options in seco...
Definition: AArch64.cpp:610
clang::TransferrableTargetInfo::UnsignedInt
@ UnsignedInt
Definition: TargetInfo.h:142
clang::targets::AArch64TargetInfo::getTargetDefinesARMV91A
void getTargetDefinesARMV91A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:309
BuiltinInfo
static constexpr Builtin::Info BuiltinInfo[]
Definition: AArch64.cpp:28
clang::targets::AArch64TargetInfo::setCPU
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: AArch64.cpp:230
clang::TransferrableTargetInfo::UseSignedCharForObjCBool
unsigned UseSignedCharForObjCBool
Whether Objective-C's built-in boolean type should be signed char.
Definition: TargetInfo.h:158
clang::TransferrableTargetInfo::LongDoubleAlign
unsigned char LongDoubleAlign
Definition: TargetInfo.h:91
clang::TransferrableTargetInfo::SizeType
IntType SizeType
Definition: TargetInfo.h:150
clang::TransferrableTargetInfo::SignedLong
@ SignedLong
Definition: TargetInfo.h:143
clang::TargetInfo::BranchProtectionInfo::SignReturnAddr
LangOptions::SignReturnAddressScopeKind SignReturnAddr
Definition: TargetInfo.h:1343
clang::targets::AArch64TargetInfo::getTargetDefinesARMV83A
void getTargetDefinesARMV83A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:252
clang::TargetOptions::CodeModel
std::string CodeModel
Definition: TargetOptions.h:97
clang::targets::WindowsARM64TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: AArch64.cpp:1358