clang 24.0.0git
NVPTX.cpp
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1//===-------- NVPTX.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CGBuiltin.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsNVPTX.h"
16#include "llvm/TargetParser/AtomicScope.h"
17
18using namespace clang;
19using namespace CodeGen;
20using namespace llvm;
21
22namespace {
23// Helper classes for mapping MMA builtins to particular LLVM intrinsic variant.
24struct NVPTXMmaLdstInfo {
25 unsigned NumResults; // Number of elements to load/store
26 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
27 unsigned IID_col;
28 unsigned IID_row;
29};
30
31#define MMA_INTR(geom_op_type, layout) \
32 Intrinsic::nvvm_wmma_##geom_op_type##_##layout##_stride
33#define MMA_LDST(n, geom_op_type) \
34 { n, MMA_INTR(geom_op_type, col), MMA_INTR(geom_op_type, row) }
35
36static NVPTXMmaLdstInfo getNVPTXMmaLdstInfo(unsigned BuiltinID) {
37 switch (BuiltinID) {
38 // FP MMA loads
39 case NVPTX::BI__hmma_m16n16k16_ld_a:
40 return MMA_LDST(8, m16n16k16_load_a_f16);
41 case NVPTX::BI__hmma_m16n16k16_ld_b:
42 return MMA_LDST(8, m16n16k16_load_b_f16);
43 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
44 return MMA_LDST(4, m16n16k16_load_c_f16);
45 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
46 return MMA_LDST(8, m16n16k16_load_c_f32);
47 case NVPTX::BI__hmma_m32n8k16_ld_a:
48 return MMA_LDST(8, m32n8k16_load_a_f16);
49 case NVPTX::BI__hmma_m32n8k16_ld_b:
50 return MMA_LDST(8, m32n8k16_load_b_f16);
51 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
52 return MMA_LDST(4, m32n8k16_load_c_f16);
53 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
54 return MMA_LDST(8, m32n8k16_load_c_f32);
55 case NVPTX::BI__hmma_m8n32k16_ld_a:
56 return MMA_LDST(8, m8n32k16_load_a_f16);
57 case NVPTX::BI__hmma_m8n32k16_ld_b:
58 return MMA_LDST(8, m8n32k16_load_b_f16);
59 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
60 return MMA_LDST(4, m8n32k16_load_c_f16);
61 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
62 return MMA_LDST(8, m8n32k16_load_c_f32);
63
64 // Integer MMA loads
65 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
66 return MMA_LDST(2, m16n16k16_load_a_s8);
67 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
68 return MMA_LDST(2, m16n16k16_load_a_u8);
69 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
70 return MMA_LDST(2, m16n16k16_load_b_s8);
71 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
72 return MMA_LDST(2, m16n16k16_load_b_u8);
73 case NVPTX::BI__imma_m16n16k16_ld_c:
74 return MMA_LDST(8, m16n16k16_load_c_s32);
75 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
76 return MMA_LDST(4, m32n8k16_load_a_s8);
77 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
78 return MMA_LDST(4, m32n8k16_load_a_u8);
79 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
80 return MMA_LDST(1, m32n8k16_load_b_s8);
81 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
82 return MMA_LDST(1, m32n8k16_load_b_u8);
83 case NVPTX::BI__imma_m32n8k16_ld_c:
84 return MMA_LDST(8, m32n8k16_load_c_s32);
85 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
86 return MMA_LDST(1, m8n32k16_load_a_s8);
87 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
88 return MMA_LDST(1, m8n32k16_load_a_u8);
89 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
90 return MMA_LDST(4, m8n32k16_load_b_s8);
91 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
92 return MMA_LDST(4, m8n32k16_load_b_u8);
93 case NVPTX::BI__imma_m8n32k16_ld_c:
94 return MMA_LDST(8, m8n32k16_load_c_s32);
95
96 // Sub-integer MMA loads.
97 // Only row/col layout is supported by A/B fragments.
98 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
99 return {1, 0, MMA_INTR(m8n8k32_load_a_s4, row)};
100 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
101 return {1, 0, MMA_INTR(m8n8k32_load_a_u4, row)};
102 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
103 return {1, MMA_INTR(m8n8k32_load_b_s4, col), 0};
104 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
105 return {1, MMA_INTR(m8n8k32_load_b_u4, col), 0};
106 case NVPTX::BI__imma_m8n8k32_ld_c:
107 return MMA_LDST(2, m8n8k32_load_c_s32);
108 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
109 return {1, 0, MMA_INTR(m8n8k128_load_a_b1, row)};
110 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
111 return {1, MMA_INTR(m8n8k128_load_b_b1, col), 0};
112 case NVPTX::BI__bmma_m8n8k128_ld_c:
113 return MMA_LDST(2, m8n8k128_load_c_s32);
114
115 // Double MMA loads
116 case NVPTX::BI__dmma_m8n8k4_ld_a:
117 return MMA_LDST(1, m8n8k4_load_a_f64);
118 case NVPTX::BI__dmma_m8n8k4_ld_b:
119 return MMA_LDST(1, m8n8k4_load_b_f64);
120 case NVPTX::BI__dmma_m8n8k4_ld_c:
121 return MMA_LDST(2, m8n8k4_load_c_f64);
122
123 // Alternate float MMA loads
124 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
125 return MMA_LDST(4, m16n16k16_load_a_bf16);
126 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
127 return MMA_LDST(4, m16n16k16_load_b_bf16);
128 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
129 return MMA_LDST(2, m8n32k16_load_a_bf16);
130 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
131 return MMA_LDST(8, m8n32k16_load_b_bf16);
132 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
133 return MMA_LDST(8, m32n8k16_load_a_bf16);
134 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
135 return MMA_LDST(2, m32n8k16_load_b_bf16);
136 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
137 return MMA_LDST(4, m16n16k8_load_a_tf32);
138 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
139 return MMA_LDST(4, m16n16k8_load_b_tf32);
140 case NVPTX::BI__mma_tf32_m16n16k8_ld_c:
141 return MMA_LDST(8, m16n16k8_load_c_f32);
142
143 // NOTE: We need to follow inconsitent naming scheme used by NVCC. Unlike
144 // PTX and LLVM IR where stores always use fragment D, NVCC builtins always
145 // use fragment C for both loads and stores.
146 // FP MMA stores.
147 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
148 return MMA_LDST(4, m16n16k16_store_d_f16);
149 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
150 return MMA_LDST(8, m16n16k16_store_d_f32);
151 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
152 return MMA_LDST(4, m32n8k16_store_d_f16);
153 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
154 return MMA_LDST(8, m32n8k16_store_d_f32);
155 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
156 return MMA_LDST(4, m8n32k16_store_d_f16);
157 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
158 return MMA_LDST(8, m8n32k16_store_d_f32);
159
160 // Integer and sub-integer MMA stores.
161 // Another naming quirk. Unlike other MMA builtins that use PTX types in the
162 // name, integer loads/stores use LLVM's i32.
163 case NVPTX::BI__imma_m16n16k16_st_c_i32:
164 return MMA_LDST(8, m16n16k16_store_d_s32);
165 case NVPTX::BI__imma_m32n8k16_st_c_i32:
166 return MMA_LDST(8, m32n8k16_store_d_s32);
167 case NVPTX::BI__imma_m8n32k16_st_c_i32:
168 return MMA_LDST(8, m8n32k16_store_d_s32);
169 case NVPTX::BI__imma_m8n8k32_st_c_i32:
170 return MMA_LDST(2, m8n8k32_store_d_s32);
171 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
172 return MMA_LDST(2, m8n8k128_store_d_s32);
173
174 // Double MMA store
175 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
176 return MMA_LDST(2, m8n8k4_store_d_f64);
177
178 // Alternate float MMA store
179 case NVPTX::BI__mma_m16n16k8_st_c_f32:
180 return MMA_LDST(8, m16n16k8_store_d_f32);
181
182 default:
183 llvm_unreachable("Unknown MMA builtin");
184 }
185}
186#undef MMA_LDST
187#undef MMA_INTR
188
189
190struct NVPTXMmaInfo {
191 unsigned NumEltsA;
192 unsigned NumEltsB;
193 unsigned NumEltsC;
194 unsigned NumEltsD;
195
196 // Variants are ordered by layout-A/layout-B/satf, where 'row' has priority
197 // over 'col' for layout. The index of non-satf variants is expected to match
198 // the undocumented layout constants used by CUDA's mma.hpp.
199 std::array<unsigned, 8> Variants;
200
201 unsigned getMMAIntrinsic(int Layout, bool Satf) {
202 unsigned Index = Layout + 4 * Satf;
203 if (Index >= Variants.size())
204 return 0;
205 return Variants[Index];
206 }
207};
208
209 // Returns an intrinsic that matches Layout and Satf for valid combinations of
210 // Layout and Satf, 0 otherwise.
211static NVPTXMmaInfo getNVPTXMmaInfo(unsigned BuiltinID) {
212 // clang-format off
213#define MMA_VARIANTS(geom, type) \
214 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type, \
215 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
216 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type, \
217 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type
218#define MMA_SATF_VARIANTS(geom, type) \
219 MMA_VARIANTS(geom, type), \
220 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type##_satfinite, \
221 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
222 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type##_satfinite, \
223 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type##_satfinite
224// Sub-integer MMA only supports row.col layout.
225#define MMA_VARIANTS_I4(geom, type) \
226 0, \
227 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
228 0, \
229 0, \
230 0, \
231 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
232 0, \
233 0
234// b1 MMA does not support .satfinite.
235#define MMA_VARIANTS_B1_XOR(geom, type) \
236 0, \
237 Intrinsic::nvvm_wmma_##geom##_mma_xor_popc_row_col_##type, \
238 0, \
239 0, \
240 0, \
241 0, \
242 0, \
243 0
244#define MMA_VARIANTS_B1_AND(geom, type) \
245 0, \
246 Intrinsic::nvvm_wmma_##geom##_mma_and_popc_row_col_##type, \
247 0, \
248 0, \
249 0, \
250 0, \
251 0, \
252 0
253 // clang-format on
254 switch (BuiltinID) {
255 // FP MMA
256 // Note that 'type' argument of MMA_SATF_VARIANTS uses D_C notation, while
257 // NumEltsN of return value are ordered as A,B,C,D.
258 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
259 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f16)}}};
260 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
261 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f16)}}};
262 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
263 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f32)}}};
264 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
265 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f32)}}};
266 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
267 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f16)}}};
268 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
269 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f16)}}};
270 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
271 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f32)}}};
272 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
273 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f32)}}};
274 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
275 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f16)}}};
276 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
277 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f16)}}};
278 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
279 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f32)}}};
280 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
281 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f32)}}};
282
283 // Integer MMA
284 case NVPTX::BI__imma_m16n16k16_mma_s8:
285 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, s8)}}};
286 case NVPTX::BI__imma_m16n16k16_mma_u8:
287 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, u8)}}};
288 case NVPTX::BI__imma_m32n8k16_mma_s8:
289 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, s8)}}};
290 case NVPTX::BI__imma_m32n8k16_mma_u8:
291 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, u8)}}};
292 case NVPTX::BI__imma_m8n32k16_mma_s8:
293 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, s8)}}};
294 case NVPTX::BI__imma_m8n32k16_mma_u8:
295 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, u8)}}};
296
297 // Sub-integer MMA
298 case NVPTX::BI__imma_m8n8k32_mma_s4:
299 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, s4)}}};
300 case NVPTX::BI__imma_m8n8k32_mma_u4:
301 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, u4)}}};
302 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
303 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_XOR(m8n8k128, b1)}}};
304 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
305 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_AND(m8n8k128, b1)}}};
306
307 // Double MMA
308 case NVPTX::BI__dmma_m8n8k4_mma_f64:
309 return {1, 1, 2, 2, {{MMA_VARIANTS(m8n8k4, f64)}}};
310
311 // Alternate FP MMA
312 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
313 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k16, bf16)}}};
314 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
315 return {2, 8, 8, 8, {{MMA_VARIANTS(m8n32k16, bf16)}}};
316 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
317 return {8, 2, 8, 8, {{MMA_VARIANTS(m32n8k16, bf16)}}};
318 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32:
319 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k8, tf32)}}};
320 default:
321 llvm_unreachable("Unexpected builtin ID.");
322 }
323#undef MMA_VARIANTS
324#undef MMA_SATF_VARIANTS
325#undef MMA_VARIANTS_I4
326#undef MMA_VARIANTS_B1_AND
327#undef MMA_VARIANTS_B1_XOR
328}
329
330static Value *MakeLdu(unsigned IntrinsicID, CodeGenFunction &CGF,
331 const CallExpr *E) {
332 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
333 QualType ArgType = E->getArg(0)->getType();
334 clang::CharUnits Align = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
335 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
336 return CGF.Builder.CreateCall(
337 CGF.CGM.getIntrinsic(IntrinsicID, {ElemTy, Ptr->getType()}),
338 {Ptr, ConstantInt::get(CGF.Builder.getInt32Ty(), Align.getQuantity())});
339}
340
341static Value *MakeLdg(CodeGenFunction &CGF, const CallExpr *E) {
342 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
343 QualType ArgType = E->getArg(0)->getType();
344 clang::CharUnits AlignV = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
345 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
346
347 // Use addrspace(1) for NVPTX ADDRESS_SPACE_GLOBAL
348 auto *ASC = CGF.Builder.CreateAddrSpaceCast(Ptr, CGF.Builder.getPtrTy(1));
349 auto *LD = CGF.Builder.CreateAlignedLoad(ElemTy, ASC, AlignV.getAsAlign());
350 MDNode *MD = MDNode::get(CGF.Builder.getContext(), {});
351 LD->setMetadata(LLVMContext::MD_invariant_load, MD);
352
353 return LD;
354}
355
356// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
357// for _sys builtins.
358static Value *MakeScopedAtomicRMW(CodeGenFunction &CGF, const CallExpr *E,
359 llvm::AtomicRMWInst::BinOp Kind,
360 llvm::AtomicScope Scope) {
361 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
362 Value *Val = CGF.EmitScalarExpr(E->getArg(1));
363 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
364 *llvm::getAtomicScopeIRString(CGF.getTarget().getTriple(), Scope));
365 return CGF.Builder.CreateAtomicRMW(Kind, Ptr, Val,
366 llvm::AtomicOrdering::Monotonic, SSID);
367}
368
369// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
370// for _sys builtins.
371static Value *MakeScopedAtomicCAS(CodeGenFunction &CGF, const CallExpr *E,
372 llvm::AtomicScope Scope) {
373 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
374 Value *Cmp = CGF.EmitScalarExpr(E->getArg(1));
375 Value *New = CGF.EmitScalarExpr(E->getArg(2));
376 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
377 *llvm::getAtomicScopeIRString(CGF.getTarget().getTriple(), Scope));
378 Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
379 Ptr, Cmp, New, llvm::AtomicOrdering::Monotonic,
380 llvm::AtomicOrdering::Monotonic, SSID);
381 return CGF.Builder.CreateExtractValue(Pair, 0);
382}
383
384static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
385 CodeGenFunction &CGF, const CallExpr *E,
386 int SrcSize) {
387 return E->getNumArgs() == 3
388 ? CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicIDS),
389 {CGF.EmitScalarExpr(E->getArg(0)),
390 CGF.EmitScalarExpr(E->getArg(1)),
391 CGF.EmitScalarExpr(E->getArg(2))})
392 : CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID),
393 {CGF.EmitScalarExpr(E->getArg(0)),
394 CGF.EmitScalarExpr(E->getArg(1))});
395}
396
397static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
398 const CallExpr *E, CodeGenFunction &CGF,
399 ArrayRef<Value *> TrailingArgs = {}) {
400 SmallVector<Value *, 16> Args;
401 auto *FTy = Intrinsic->getFunctionType();
402 unsigned ICEArguments = 0;
403 ASTContext::GetBuiltinTypeError Error;
404 CGF.CGM.getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
405 assert(Error == ASTContext::GE_None && "Should not codegen an error");
406 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
407 assert((ICEArguments & (1 << i)) == 0);
408 auto *ArgValue = CGF.EmitScalarExpr(E->getArg(i));
409 auto *PTy = FTy->getParamType(i);
410 if (PTy != ArgValue->getType())
411 ArgValue = CGF.Builder.CreateBitCast(ArgValue, PTy);
412 Args.push_back(ArgValue);
413 }
414
415 llvm::append_range(Args, TrailingArgs);
416 appendDefaultIntrinsicArgs(Args, Intrinsic);
417
418 return CGF.Builder.CreateCall(Intrinsic, Args);
419}
420
421static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
422 const CallExpr *E, CodeGenFunction &CGF,
423 ArrayRef<Value *> TrailingArgs = {}) {
424 return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF,
425 TrailingArgs);
426}
427
428static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
429 const CallExpr *E, CodeGenFunction &CGF) {
430 return CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID, {Ty}),
431 {CGF.EmitScalarExpr(E->getArg(0)),
432 CGF.EmitScalarExpr(E->getArg(1)),
433 CGF.EmitScalarExpr(E->getArg(2))});
434}
435
436static Value *MakeFAdd(unsigned IntrinsicID, APFloat::roundingMode RM,
437 unsigned BuiltinID, const CallExpr *E,
438 CodeGenFunction &CGF) {
439 llvm::Type *Ty = CGF.ConvertType(E->getType());
440 return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID, Ty), BuiltinID, E, CGF,
441 {CGF.Builder.getInt32(static_cast<int>(RM))});
442}
443
444} // namespace
445
446Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
447 const CallExpr *E) {
448 switch (BuiltinID) {
449 case NVPTX::BI__nvvm_atom_add_gen_i:
450 case NVPTX::BI__nvvm_atom_add_gen_l:
451 case NVPTX::BI__nvvm_atom_add_gen_ll:
452 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Add, E,
453 AtomicOrdering::Monotonic);
454
455 case NVPTX::BI__nvvm_atom_sub_gen_i:
456 case NVPTX::BI__nvvm_atom_sub_gen_l:
457 case NVPTX::BI__nvvm_atom_sub_gen_ll:
458 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Sub, E,
459 AtomicOrdering::Monotonic);
460
461 case NVPTX::BI__nvvm_atom_and_gen_i:
462 case NVPTX::BI__nvvm_atom_and_gen_l:
463 case NVPTX::BI__nvvm_atom_and_gen_ll:
464 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::And, E,
465 AtomicOrdering::Monotonic);
466
467 case NVPTX::BI__nvvm_atom_or_gen_i:
468 case NVPTX::BI__nvvm_atom_or_gen_l:
469 case NVPTX::BI__nvvm_atom_or_gen_ll:
470 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Or, E,
471 AtomicOrdering::Monotonic);
472
473 case NVPTX::BI__nvvm_atom_xor_gen_i:
474 case NVPTX::BI__nvvm_atom_xor_gen_l:
475 case NVPTX::BI__nvvm_atom_xor_gen_ll:
476 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xor, E,
477 AtomicOrdering::Monotonic);
478
479 case NVPTX::BI__nvvm_atom_xchg_gen_i:
480 case NVPTX::BI__nvvm_atom_xchg_gen_l:
481 case NVPTX::BI__nvvm_atom_xchg_gen_ll:
482 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xchg, E,
483 AtomicOrdering::Monotonic);
484
485 case NVPTX::BI__nvvm_atom_max_gen_i:
486 case NVPTX::BI__nvvm_atom_max_gen_l:
487 case NVPTX::BI__nvvm_atom_max_gen_ll:
488 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Max, E,
489 AtomicOrdering::Monotonic);
490
491 case NVPTX::BI__nvvm_atom_max_gen_ui:
492 case NVPTX::BI__nvvm_atom_max_gen_ul:
493 case NVPTX::BI__nvvm_atom_max_gen_ull:
494 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMax, E,
495 AtomicOrdering::Monotonic);
496
497 case NVPTX::BI__nvvm_atom_min_gen_i:
498 case NVPTX::BI__nvvm_atom_min_gen_l:
499 case NVPTX::BI__nvvm_atom_min_gen_ll:
500 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Min, E,
501 AtomicOrdering::Monotonic);
502
503 case NVPTX::BI__nvvm_atom_min_gen_ui:
504 case NVPTX::BI__nvvm_atom_min_gen_ul:
505 case NVPTX::BI__nvvm_atom_min_gen_ull:
506 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMin, E,
507 AtomicOrdering::Monotonic);
508
509 case NVPTX::BI__nvvm_atom_cas_gen_us:
510 case NVPTX::BI__nvvm_atom_cas_gen_i:
511 case NVPTX::BI__nvvm_atom_cas_gen_l:
512 case NVPTX::BI__nvvm_atom_cas_gen_ll:
513 // __nvvm_atom_cas_gen_* should return the old value rather than the
514 // success flag.
515 return MakeAtomicCmpXchgValue(*this, E, /*ReturnBool=*/false,
516 AtomicOrdering::Monotonic,
517 AtomicOrdering::Monotonic);
518
519 case NVPTX::BI__nvvm_atom_add_gen_f:
520 case NVPTX::BI__nvvm_atom_add_gen_d: {
521 Address DestAddr = EmitPointerWithAlignment(E->getArg(0));
522 Value *Val = EmitScalarExpr(E->getArg(1));
523
524 return Builder.CreateAtomicRMW(llvm::AtomicRMWInst::FAdd, DestAddr, Val,
525 AtomicOrdering::Monotonic);
526 }
527
528 case NVPTX::BI__nvvm_atom_inc_gen_ui:
529 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UIncWrap, E,
530 AtomicOrdering::Monotonic);
531
532 case NVPTX::BI__nvvm_atom_dec_gen_ui:
533 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UDecWrap, E,
534 AtomicOrdering::Monotonic);
535
536 case NVPTX::BI__nvvm_ldg_c:
537 case NVPTX::BI__nvvm_ldg_sc:
538 case NVPTX::BI__nvvm_ldg_c2:
539 case NVPTX::BI__nvvm_ldg_sc2:
540 case NVPTX::BI__nvvm_ldg_c4:
541 case NVPTX::BI__nvvm_ldg_sc4:
542 case NVPTX::BI__nvvm_ldg_s:
543 case NVPTX::BI__nvvm_ldg_s2:
544 case NVPTX::BI__nvvm_ldg_s4:
545 case NVPTX::BI__nvvm_ldg_i:
546 case NVPTX::BI__nvvm_ldg_i2:
547 case NVPTX::BI__nvvm_ldg_i4:
548 case NVPTX::BI__nvvm_ldg_l:
549 case NVPTX::BI__nvvm_ldg_l2:
550 case NVPTX::BI__nvvm_ldg_ll:
551 case NVPTX::BI__nvvm_ldg_ll2:
552 case NVPTX::BI__nvvm_ldg_uc:
553 case NVPTX::BI__nvvm_ldg_uc2:
554 case NVPTX::BI__nvvm_ldg_uc4:
555 case NVPTX::BI__nvvm_ldg_us:
556 case NVPTX::BI__nvvm_ldg_us2:
557 case NVPTX::BI__nvvm_ldg_us4:
558 case NVPTX::BI__nvvm_ldg_ui:
559 case NVPTX::BI__nvvm_ldg_ui2:
560 case NVPTX::BI__nvvm_ldg_ui4:
561 case NVPTX::BI__nvvm_ldg_ul:
562 case NVPTX::BI__nvvm_ldg_ul2:
563 case NVPTX::BI__nvvm_ldg_ull:
564 case NVPTX::BI__nvvm_ldg_ull2:
565 case NVPTX::BI__nvvm_ldg_f:
566 case NVPTX::BI__nvvm_ldg_f2:
567 case NVPTX::BI__nvvm_ldg_f4:
568 case NVPTX::BI__nvvm_ldg_d:
569 case NVPTX::BI__nvvm_ldg_d2:
570 // PTX Interoperability section 2.2: "For a vector with an even number of
571 // elements, its alignment is set to number of elements times the alignment
572 // of its member: n*alignof(t)."
573 return MakeLdg(*this, E);
574
575 case NVPTX::BI__nvvm_ldu_c:
576 case NVPTX::BI__nvvm_ldu_sc:
577 case NVPTX::BI__nvvm_ldu_c2:
578 case NVPTX::BI__nvvm_ldu_sc2:
579 case NVPTX::BI__nvvm_ldu_c4:
580 case NVPTX::BI__nvvm_ldu_sc4:
581 case NVPTX::BI__nvvm_ldu_s:
582 case NVPTX::BI__nvvm_ldu_s2:
583 case NVPTX::BI__nvvm_ldu_s4:
584 case NVPTX::BI__nvvm_ldu_i:
585 case NVPTX::BI__nvvm_ldu_i2:
586 case NVPTX::BI__nvvm_ldu_i4:
587 case NVPTX::BI__nvvm_ldu_l:
588 case NVPTX::BI__nvvm_ldu_l2:
589 case NVPTX::BI__nvvm_ldu_ll:
590 case NVPTX::BI__nvvm_ldu_ll2:
591 case NVPTX::BI__nvvm_ldu_uc:
592 case NVPTX::BI__nvvm_ldu_uc2:
593 case NVPTX::BI__nvvm_ldu_uc4:
594 case NVPTX::BI__nvvm_ldu_us:
595 case NVPTX::BI__nvvm_ldu_us2:
596 case NVPTX::BI__nvvm_ldu_us4:
597 case NVPTX::BI__nvvm_ldu_ui:
598 case NVPTX::BI__nvvm_ldu_ui2:
599 case NVPTX::BI__nvvm_ldu_ui4:
600 case NVPTX::BI__nvvm_ldu_ul:
601 case NVPTX::BI__nvvm_ldu_ul2:
602 case NVPTX::BI__nvvm_ldu_ull:
603 case NVPTX::BI__nvvm_ldu_ull2:
604 return MakeLdu(Intrinsic::nvvm_ldu_global_i, *this, E);
605 case NVPTX::BI__nvvm_ldu_f:
606 case NVPTX::BI__nvvm_ldu_f2:
607 case NVPTX::BI__nvvm_ldu_f4:
608 case NVPTX::BI__nvvm_ldu_d:
609 case NVPTX::BI__nvvm_ldu_d2:
610 return MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E);
611
612 case NVPTX::BI__nvvm_atom_cta_add_gen_i:
613 case NVPTX::BI__nvvm_atom_cta_add_gen_l:
614 case NVPTX::BI__nvvm_atom_cta_add_gen_ll:
615 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add,
616 llvm::AtomicScope::Workgroup);
617 case NVPTX::BI__nvvm_atom_sys_add_gen_i:
618 case NVPTX::BI__nvvm_atom_sys_add_gen_l:
619 case NVPTX::BI__nvvm_atom_sys_add_gen_ll:
620 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add,
621 llvm::AtomicScope::System);
622 case NVPTX::BI__nvvm_atom_cta_add_gen_f:
623 case NVPTX::BI__nvvm_atom_cta_add_gen_d:
624 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd,
625 llvm::AtomicScope::Workgroup);
626 case NVPTX::BI__nvvm_atom_sys_add_gen_f:
627 case NVPTX::BI__nvvm_atom_sys_add_gen_d:
628 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd,
629 llvm::AtomicScope::System);
630 case NVPTX::BI__nvvm_atom_cta_xchg_gen_i:
631 case NVPTX::BI__nvvm_atom_cta_xchg_gen_l:
632 case NVPTX::BI__nvvm_atom_cta_xchg_gen_ll:
633 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg,
634 llvm::AtomicScope::Workgroup);
635 case NVPTX::BI__nvvm_atom_sys_xchg_gen_i:
636 case NVPTX::BI__nvvm_atom_sys_xchg_gen_l:
637 case NVPTX::BI__nvvm_atom_sys_xchg_gen_ll:
638 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg,
639 llvm::AtomicScope::System);
640 case NVPTX::BI__nvvm_atom_cta_max_gen_i:
641 case NVPTX::BI__nvvm_atom_cta_max_gen_l:
642 case NVPTX::BI__nvvm_atom_cta_max_gen_ll:
643 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max,
644 llvm::AtomicScope::Workgroup);
645 case NVPTX::BI__nvvm_atom_cta_max_gen_ui:
646 case NVPTX::BI__nvvm_atom_cta_max_gen_ul:
647 case NVPTX::BI__nvvm_atom_cta_max_gen_ull:
648 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax,
649 llvm::AtomicScope::Workgroup);
650 case NVPTX::BI__nvvm_atom_sys_max_gen_i:
651 case NVPTX::BI__nvvm_atom_sys_max_gen_l:
652 case NVPTX::BI__nvvm_atom_sys_max_gen_ll:
653 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max,
654 llvm::AtomicScope::System);
655 case NVPTX::BI__nvvm_atom_sys_max_gen_ui:
656 case NVPTX::BI__nvvm_atom_sys_max_gen_ul:
657 case NVPTX::BI__nvvm_atom_sys_max_gen_ull:
658 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax,
659 llvm::AtomicScope::System);
660 case NVPTX::BI__nvvm_atom_cta_min_gen_i:
661 case NVPTX::BI__nvvm_atom_cta_min_gen_l:
662 case NVPTX::BI__nvvm_atom_cta_min_gen_ll:
663 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min,
664 llvm::AtomicScope::Workgroup);
665 case NVPTX::BI__nvvm_atom_cta_min_gen_ui:
666 case NVPTX::BI__nvvm_atom_cta_min_gen_ul:
667 case NVPTX::BI__nvvm_atom_cta_min_gen_ull:
668 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin,
669 llvm::AtomicScope::Workgroup);
670 case NVPTX::BI__nvvm_atom_sys_min_gen_i:
671 case NVPTX::BI__nvvm_atom_sys_min_gen_l:
672 case NVPTX::BI__nvvm_atom_sys_min_gen_ll:
673 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min,
674 llvm::AtomicScope::System);
675 case NVPTX::BI__nvvm_atom_sys_min_gen_ui:
676 case NVPTX::BI__nvvm_atom_sys_min_gen_ul:
677 case NVPTX::BI__nvvm_atom_sys_min_gen_ull:
678 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin,
679 llvm::AtomicScope::System);
680 case NVPTX::BI__nvvm_atom_cta_inc_gen_ui:
681 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap,
682 llvm::AtomicScope::Workgroup);
683 case NVPTX::BI__nvvm_atom_cta_dec_gen_ui:
684 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap,
685 llvm::AtomicScope::Workgroup);
686 case NVPTX::BI__nvvm_atom_sys_inc_gen_ui:
687 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap,
688 llvm::AtomicScope::System);
689 case NVPTX::BI__nvvm_atom_sys_dec_gen_ui:
690 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap,
691 llvm::AtomicScope::System);
692 case NVPTX::BI__nvvm_atom_cta_and_gen_i:
693 case NVPTX::BI__nvvm_atom_cta_and_gen_l:
694 case NVPTX::BI__nvvm_atom_cta_and_gen_ll:
695 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And,
696 llvm::AtomicScope::Workgroup);
697 case NVPTX::BI__nvvm_atom_sys_and_gen_i:
698 case NVPTX::BI__nvvm_atom_sys_and_gen_l:
699 case NVPTX::BI__nvvm_atom_sys_and_gen_ll:
700 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And,
701 llvm::AtomicScope::System);
702 case NVPTX::BI__nvvm_atom_cta_or_gen_i:
703 case NVPTX::BI__nvvm_atom_cta_or_gen_l:
704 case NVPTX::BI__nvvm_atom_cta_or_gen_ll:
705 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or,
706 llvm::AtomicScope::Workgroup);
707 case NVPTX::BI__nvvm_atom_sys_or_gen_i:
708 case NVPTX::BI__nvvm_atom_sys_or_gen_l:
709 case NVPTX::BI__nvvm_atom_sys_or_gen_ll:
710 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or,
711 llvm::AtomicScope::System);
712 case NVPTX::BI__nvvm_atom_cta_xor_gen_i:
713 case NVPTX::BI__nvvm_atom_cta_xor_gen_l:
714 case NVPTX::BI__nvvm_atom_cta_xor_gen_ll:
715 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor,
716 llvm::AtomicScope::Workgroup);
717 case NVPTX::BI__nvvm_atom_sys_xor_gen_i:
718 case NVPTX::BI__nvvm_atom_sys_xor_gen_l:
719 case NVPTX::BI__nvvm_atom_sys_xor_gen_ll:
720 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor,
721 llvm::AtomicScope::System);
722 case NVPTX::BI__nvvm_atom_cta_cas_gen_us:
723 case NVPTX::BI__nvvm_atom_cta_cas_gen_i:
724 case NVPTX::BI__nvvm_atom_cta_cas_gen_l:
725 case NVPTX::BI__nvvm_atom_cta_cas_gen_ll:
726 return MakeScopedAtomicCAS(*this, E, llvm::AtomicScope::Workgroup);
727 case NVPTX::BI__nvvm_atom_sys_cas_gen_us:
728 case NVPTX::BI__nvvm_atom_sys_cas_gen_i:
729 case NVPTX::BI__nvvm_atom_sys_cas_gen_l:
730 case NVPTX::BI__nvvm_atom_sys_cas_gen_ll:
731 return MakeScopedAtomicCAS(*this, E, llvm::AtomicScope::System);
732 case NVPTX::BI__nvvm_match_all_sync_i32p:
733 case NVPTX::BI__nvvm_match_all_sync_i64p: {
734 Value *Mask = EmitScalarExpr(E->getArg(0));
735 Value *Val = EmitScalarExpr(E->getArg(1));
736 Address PredOutPtr = EmitPointerWithAlignment(E->getArg(2));
737 Value *ResultPair = Builder.CreateCall(
738 CGM.getIntrinsic(BuiltinID == NVPTX::BI__nvvm_match_all_sync_i32p
739 ? Intrinsic::nvvm_match_all_sync_i32p
740 : Intrinsic::nvvm_match_all_sync_i64p),
741 {Mask, Val});
742 Value *Pred = Builder.CreateZExt(Builder.CreateExtractValue(ResultPair, 1),
743 PredOutPtr.getElementType());
744 Builder.CreateStore(Pred, PredOutPtr);
745 return Builder.CreateExtractValue(ResultPair, 0);
746 }
747
748 // FP MMA loads
749 case NVPTX::BI__hmma_m16n16k16_ld_a:
750 case NVPTX::BI__hmma_m16n16k16_ld_b:
751 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
752 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
753 case NVPTX::BI__hmma_m32n8k16_ld_a:
754 case NVPTX::BI__hmma_m32n8k16_ld_b:
755 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
756 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
757 case NVPTX::BI__hmma_m8n32k16_ld_a:
758 case NVPTX::BI__hmma_m8n32k16_ld_b:
759 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
760 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
761 // Integer MMA loads.
762 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
763 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
764 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
765 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
766 case NVPTX::BI__imma_m16n16k16_ld_c:
767 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
768 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
769 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
770 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
771 case NVPTX::BI__imma_m32n8k16_ld_c:
772 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
773 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
774 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
775 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
776 case NVPTX::BI__imma_m8n32k16_ld_c:
777 // Sub-integer MMA loads.
778 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
779 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
780 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
781 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
782 case NVPTX::BI__imma_m8n8k32_ld_c:
783 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
784 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
785 case NVPTX::BI__bmma_m8n8k128_ld_c:
786 // Double MMA loads.
787 case NVPTX::BI__dmma_m8n8k4_ld_a:
788 case NVPTX::BI__dmma_m8n8k4_ld_b:
789 case NVPTX::BI__dmma_m8n8k4_ld_c:
790 // Alternate float MMA loads.
791 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
792 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
793 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
794 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
795 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
796 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
797 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
798 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
799 case NVPTX::BI__mma_tf32_m16n16k8_ld_c: {
800 Address Dst = EmitPointerWithAlignment(E->getArg(0));
801 Value *Src = EmitScalarExpr(E->getArg(1));
802 Value *Ldm = EmitScalarExpr(E->getArg(2));
803 std::optional<llvm::APSInt> isColMajorArg =
804 E->getArg(3)->getIntegerConstantExpr(getContext());
805 if (!isColMajorArg)
806 return nullptr;
807 bool isColMajor = isColMajorArg->getSExtValue();
808 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
809 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
810 if (IID == 0)
811 return nullptr;
812
813 Value *Result =
814 Builder.CreateCall(CGM.getIntrinsic(IID, Src->getType()), {Src, Ldm});
815
816 // Save returned values.
817 assert(II.NumResults);
818 if (II.NumResults == 1) {
819 Builder.CreateAlignedStore(Result, Dst.emitRawPointer(*this),
820 CharUnits::fromQuantity(4));
821 } else {
822 for (unsigned i = 0; i < II.NumResults; ++i) {
823 Builder.CreateAlignedStore(
824 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i),
825 Dst.getElementType()),
826 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
827 llvm::ConstantInt::get(IntTy, i)),
828 CharUnits::fromQuantity(4));
829 }
830 }
831 return Result;
832 }
833
834 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
835 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
836 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
837 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
838 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
839 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
840 case NVPTX::BI__imma_m16n16k16_st_c_i32:
841 case NVPTX::BI__imma_m32n8k16_st_c_i32:
842 case NVPTX::BI__imma_m8n32k16_st_c_i32:
843 case NVPTX::BI__imma_m8n8k32_st_c_i32:
844 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
845 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
846 case NVPTX::BI__mma_m16n16k8_st_c_f32: {
847 Value *Dst = EmitScalarExpr(E->getArg(0));
848 Address Src = EmitPointerWithAlignment(E->getArg(1));
849 Value *Ldm = EmitScalarExpr(E->getArg(2));
850 std::optional<llvm::APSInt> isColMajorArg =
851 E->getArg(3)->getIntegerConstantExpr(getContext());
852 if (!isColMajorArg)
853 return nullptr;
854 bool isColMajor = isColMajorArg->getSExtValue();
855 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
856 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
857 if (IID == 0)
858 return nullptr;
859 Function *Intrinsic =
860 CGM.getIntrinsic(IID, Dst->getType());
861 llvm::Type *ParamType = Intrinsic->getFunctionType()->getParamType(1);
862 SmallVector<Value *, 10> Values = {Dst};
863 for (unsigned i = 0; i < II.NumResults; ++i) {
864 Value *V = Builder.CreateAlignedLoad(
865 Src.getElementType(),
866 Builder.CreateGEP(Src.getElementType(), Src.emitRawPointer(*this),
867 llvm::ConstantInt::get(IntTy, i)),
868 CharUnits::fromQuantity(4));
869 Values.push_back(Builder.CreateBitCast(V, ParamType));
870 }
871 Values.push_back(Ldm);
872 Value *Result = Builder.CreateCall(Intrinsic, Values);
873 return Result;
874 }
875
876 // BI__hmma_m16n16k16_mma_<Dtype><CType>(d, a, b, c, layout, satf) -->
877 // Intrinsic::nvvm_wmma_m16n16k16_mma_sync<layout A,B><DType><CType><Satf>
878 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
879 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
880 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
881 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
882 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
883 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
884 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
885 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
886 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
887 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
888 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
889 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
890 case NVPTX::BI__imma_m16n16k16_mma_s8:
891 case NVPTX::BI__imma_m16n16k16_mma_u8:
892 case NVPTX::BI__imma_m32n8k16_mma_s8:
893 case NVPTX::BI__imma_m32n8k16_mma_u8:
894 case NVPTX::BI__imma_m8n32k16_mma_s8:
895 case NVPTX::BI__imma_m8n32k16_mma_u8:
896 case NVPTX::BI__imma_m8n8k32_mma_s4:
897 case NVPTX::BI__imma_m8n8k32_mma_u4:
898 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
899 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
900 case NVPTX::BI__dmma_m8n8k4_mma_f64:
901 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
902 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
903 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
904 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32: {
905 Address Dst = EmitPointerWithAlignment(E->getArg(0));
906 Address SrcA = EmitPointerWithAlignment(E->getArg(1));
907 Address SrcB = EmitPointerWithAlignment(E->getArg(2));
908 Address SrcC = EmitPointerWithAlignment(E->getArg(3));
909 std::optional<llvm::APSInt> LayoutArg =
910 E->getArg(4)->getIntegerConstantExpr(getContext());
911 if (!LayoutArg)
912 return nullptr;
913 int Layout = LayoutArg->getSExtValue();
914 if (Layout < 0 || Layout > 3)
915 return nullptr;
916 llvm::APSInt SatfArg;
917 if (BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1 ||
918 BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1)
919 SatfArg = 0; // .b1 does not have satf argument.
920 else if (std::optional<llvm::APSInt> OptSatfArg =
921 E->getArg(5)->getIntegerConstantExpr(getContext()))
922 SatfArg = *OptSatfArg;
923 else
924 return nullptr;
925 bool Satf = SatfArg.getSExtValue();
926 NVPTXMmaInfo MI = getNVPTXMmaInfo(BuiltinID);
927 unsigned IID = MI.getMMAIntrinsic(Layout, Satf);
928 if (IID == 0) // Unsupported combination of Layout/Satf.
929 return nullptr;
930
931 SmallVector<Value *, 24> Values;
932 Function *Intrinsic = CGM.getIntrinsic(IID);
933 llvm::Type *AType = Intrinsic->getFunctionType()->getParamType(0);
934 // Load A
935 for (unsigned i = 0; i < MI.NumEltsA; ++i) {
936 Value *V = Builder.CreateAlignedLoad(
937 SrcA.getElementType(),
938 Builder.CreateGEP(SrcA.getElementType(), SrcA.emitRawPointer(*this),
939 llvm::ConstantInt::get(IntTy, i)),
940 CharUnits::fromQuantity(4));
941 Values.push_back(Builder.CreateBitCast(V, AType));
942 }
943 // Load B
944 llvm::Type *BType = Intrinsic->getFunctionType()->getParamType(MI.NumEltsA);
945 for (unsigned i = 0; i < MI.NumEltsB; ++i) {
946 Value *V = Builder.CreateAlignedLoad(
947 SrcB.getElementType(),
948 Builder.CreateGEP(SrcB.getElementType(), SrcB.emitRawPointer(*this),
949 llvm::ConstantInt::get(IntTy, i)),
950 CharUnits::fromQuantity(4));
951 Values.push_back(Builder.CreateBitCast(V, BType));
952 }
953 // Load C
954 llvm::Type *CType =
955 Intrinsic->getFunctionType()->getParamType(MI.NumEltsA + MI.NumEltsB);
956 for (unsigned i = 0; i < MI.NumEltsC; ++i) {
957 Value *V = Builder.CreateAlignedLoad(
958 SrcC.getElementType(),
959 Builder.CreateGEP(SrcC.getElementType(), SrcC.emitRawPointer(*this),
960 llvm::ConstantInt::get(IntTy, i)),
961 CharUnits::fromQuantity(4));
962 Values.push_back(Builder.CreateBitCast(V, CType));
963 }
964 Value *Result = Builder.CreateCall(Intrinsic, Values);
965 llvm::Type *DType = Dst.getElementType();
966 for (unsigned i = 0; i < MI.NumEltsD; ++i)
967 Builder.CreateAlignedStore(
968 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i), DType),
969 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
970 llvm::ConstantInt::get(IntTy, i)),
971 CharUnits::fromQuantity(4));
972 return Result;
973 }
974 // The following builtins require half type support
975 case NVPTX::BI__nvvm_ex2_approx_f16:
976 return MakeHalfType(
977 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx, Builder.getHalfTy()),
978 BuiltinID, E, *this);
979 case NVPTX::BI__nvvm_ex2_approx_f16x2:
980 return MakeHalfType(
981 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx,
982 FixedVectorType::get(Builder.getHalfTy(), 2)),
983 BuiltinID, E, *this);
984 case NVPTX::BI__nvvm_ff2f16x2_rn:
985 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, *this);
986 case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
987 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn_relu, BuiltinID, E, *this);
988 case NVPTX::BI__nvvm_ff2f16x2_rz:
989 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz, BuiltinID, E, *this);
990 case NVPTX::BI__nvvm_ff2f16x2_rz_relu:
991 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz_relu, BuiltinID, E, *this);
992
993#define PZO_CVT(cvt) \
994 case NVPTX::BI__nvvm_##cvt##_pzo: \
995 return MakeHalfType(Intrinsic::nvvm_##cvt, BuiltinID, E, *this, \
996 {Builder.getTrue()})
997
998 PZO_CVT(ff2f16x2_rn);
999 PZO_CVT(ff2f16x2_rn_relu);
1000 PZO_CVT(ff2f16x2_rz);
1001 PZO_CVT(ff2f16x2_rz_relu);
1002 PZO_CVT(ff2f16x2_rn_satfinite);
1003 PZO_CVT(ff2f16x2_rn_relu_satfinite);
1004 PZO_CVT(ff2f16x2_rz_satfinite);
1005 PZO_CVT(ff2f16x2_rz_relu_satfinite);
1006 PZO_CVT(ff2bf16x2_rn);
1007 PZO_CVT(ff2bf16x2_rn_relu);
1008 PZO_CVT(ff2bf16x2_rz);
1009 PZO_CVT(ff2bf16x2_rz_relu);
1010 PZO_CVT(ff2bf16x2_rn_satfinite);
1011 PZO_CVT(ff2bf16x2_rn_relu_satfinite);
1012 PZO_CVT(ff2bf16x2_rz_satfinite);
1013 PZO_CVT(ff2bf16x2_rz_relu_satfinite);
1014 PZO_CVT(f2f16_rn);
1015 PZO_CVT(f2f16_rn_relu);
1016 PZO_CVT(f2f16_rz);
1017 PZO_CVT(f2f16_rz_relu);
1018 PZO_CVT(f2f16_rn_satfinite);
1019 PZO_CVT(f2f16_rn_relu_satfinite);
1020 PZO_CVT(f2f16_rz_satfinite);
1021 PZO_CVT(f2f16_rz_relu_satfinite);
1022 PZO_CVT(f2bf16_rn);
1023 PZO_CVT(f2bf16_rn_relu);
1024 PZO_CVT(f2bf16_rz);
1025 PZO_CVT(f2bf16_rz_relu);
1026 PZO_CVT(f2bf16_rn_satfinite);
1027 PZO_CVT(f2bf16_rn_relu_satfinite);
1028 PZO_CVT(f2bf16_rz_satfinite);
1029 PZO_CVT(f2bf16_rz_relu_satfinite);
1030
1031#undef PZO_CVT
1032
1033 case NVPTX::BI__nvvm_fma_rn_f16:
1034 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16, BuiltinID, E, *this);
1035 case NVPTX::BI__nvvm_fma_rn_f16x2:
1036 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16x2, BuiltinID, E, *this);
1037 case NVPTX::BI__nvvm_fma_rn_ftz_f16:
1038 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16, BuiltinID, E, *this);
1039 case NVPTX::BI__nvvm_fma_rn_ftz_f16x2:
1040 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16x2, BuiltinID, E, *this);
1041 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16:
1042 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16, BuiltinID, E,
1043 *this);
1044 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16x2:
1045 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16x2, BuiltinID, E,
1046 *this);
1047 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16:
1048 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16, BuiltinID, E,
1049 *this);
1050 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16x2:
1051 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16x2, BuiltinID, E,
1052 *this);
1053 case NVPTX::BI__nvvm_fma_rn_relu_f16:
1054 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16, BuiltinID, E, *this);
1055 case NVPTX::BI__nvvm_fma_rn_relu_f16x2:
1056 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16x2, BuiltinID, E, *this);
1057 case NVPTX::BI__nvvm_fma_rn_sat_f16:
1058 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16, BuiltinID, E, *this);
1059 case NVPTX::BI__nvvm_fma_rn_sat_f16x2:
1060 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16x2, BuiltinID, E, *this);
1061 case NVPTX::BI__nvvm_fma_rn_oob_f16:
1062 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getHalfTy(), E,
1063 *this);
1064 case NVPTX::BI__nvvm_fma_rn_oob_f16x2:
1065 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1066 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1067 *this);
1068 case NVPTX::BI__nvvm_fma_rn_oob_bf16:
1069 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getBFloatTy(), E,
1070 *this);
1071 case NVPTX::BI__nvvm_fma_rn_oob_bf16x2:
1072 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1073 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1074 *this);
1075 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16:
1076 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getHalfTy(), E,
1077 *this);
1078 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16x2:
1079 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1080 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1081 *this);
1082 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16:
1083 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getBFloatTy(), E,
1084 *this);
1085 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16x2:
1086 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1087 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1088 *this);
1089 case NVPTX::BI__nvvm_fmax_f16:
1090 return MakeHalfType(Intrinsic::nvvm_fmax_f16, BuiltinID, E, *this);
1091 case NVPTX::BI__nvvm_fmax_f16x2:
1092 return MakeHalfType(Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, *this);
1093 case NVPTX::BI__nvvm_fmax_ftz_f16:
1094 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, *this);
1095 case NVPTX::BI__nvvm_fmax_ftz_f16x2:
1096 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, *this);
1097 case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
1098 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, *this);
1099 case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
1100 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
1101 *this);
1102 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
1103 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
1104 E, *this);
1105 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
1106 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
1107 BuiltinID, E, *this);
1108 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
1109 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
1110 *this);
1111 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
1112 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
1113 E, *this);
1114 case NVPTX::BI__nvvm_fmax_nan_f16:
1115 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, *this);
1116 case NVPTX::BI__nvvm_fmax_nan_f16x2:
1117 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, *this);
1118 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
1119 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
1120 *this);
1121 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
1122 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
1123 E, *this);
1124 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
1125 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
1126 *this);
1127 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
1128 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
1129 *this);
1130 case NVPTX::BI__nvvm_fmin_f16:
1131 return MakeHalfType(Intrinsic::nvvm_fmin_f16, BuiltinID, E, *this);
1132 case NVPTX::BI__nvvm_fmin_f16x2:
1133 return MakeHalfType(Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, *this);
1134 case NVPTX::BI__nvvm_fmin_ftz_f16:
1135 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, *this);
1136 case NVPTX::BI__nvvm_fmin_ftz_f16x2:
1137 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, *this);
1138 case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
1139 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, *this);
1140 case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
1141 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
1142 *this);
1143 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
1144 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
1145 E, *this);
1146 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
1147 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
1148 BuiltinID, E, *this);
1149 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
1150 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
1151 *this);
1152 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
1153 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
1154 E, *this);
1155 case NVPTX::BI__nvvm_fmin_nan_f16:
1156 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, *this);
1157 case NVPTX::BI__nvvm_fmin_nan_f16x2:
1158 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, *this);
1159 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
1160 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
1161 *this);
1162 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
1163 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
1164 E, *this);
1165 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
1166 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
1167 *this);
1168 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
1169 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
1170 *this);
1171 case NVPTX::BI__nvvm_fabs_f:
1172 case NVPTX::BI__nvvm_abs_bf16:
1173 case NVPTX::BI__nvvm_abs_bf16x2:
1174 case NVPTX::BI__nvvm_fabs_f16:
1175 case NVPTX::BI__nvvm_fabs_f16x2:
1176 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs,
1177 EmitScalarExpr(E->getArg(0)));
1178 case NVPTX::BI__nvvm_fabs_ftz_f:
1179 case NVPTX::BI__nvvm_fabs_ftz_f16:
1180 case NVPTX::BI__nvvm_fabs_ftz_f16x2:
1181 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs_ftz,
1182 EmitScalarExpr(E->getArg(0)));
1183 case NVPTX::BI__nvvm_fabs_d:
1184 return Builder.CreateFAbs(EmitScalarExpr(E->getArg(0)));
1185 case NVPTX::BI__nvvm_ex2_approx_d:
1186 case NVPTX::BI__nvvm_ex2_approx_f:
1187 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx,
1188 EmitScalarExpr(E->getArg(0)));
1189 case NVPTX::BI__nvvm_ex2_approx_ftz_f:
1190 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx_ftz,
1191 EmitScalarExpr(E->getArg(0)));
1192 case NVPTX::BI__nvvm_add_rn_f:
1193 case NVPTX::BI__nvvm_add_rn_d:
1194 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmNearestTiesToEven,
1195 BuiltinID, E, *this);
1196 case NVPTX::BI__nvvm_add_rz_f:
1197 case NVPTX::BI__nvvm_add_rz_d:
1198 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardZero, BuiltinID, E,
1199 *this);
1200 case NVPTX::BI__nvvm_add_rm_f:
1201 case NVPTX::BI__nvvm_add_rm_d:
1202 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardNegative, BuiltinID,
1203 E, *this);
1204 case NVPTX::BI__nvvm_add_rp_f:
1205 case NVPTX::BI__nvvm_add_rp_d:
1206 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardPositive, BuiltinID,
1207 E, *this);
1208 case NVPTX::BI__nvvm_add_rn_ftz_f:
1209 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmNearestTiesToEven,
1210 BuiltinID, E, *this);
1211 case NVPTX::BI__nvvm_add_rz_ftz_f:
1212 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardZero, BuiltinID,
1213 E, *this);
1214 case NVPTX::BI__nvvm_add_rm_ftz_f:
1215 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardNegative,
1216 BuiltinID, E, *this);
1217 case NVPTX::BI__nvvm_add_rp_ftz_f:
1218 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardPositive,
1219 BuiltinID, E, *this);
1220 case NVPTX::BI__nvvm_add_rn_sat_f:
1221 case NVPTX::BI__nvvm_add_rn_sat_f16:
1222 case NVPTX::BI__nvvm_add_rn_sat_v2f16:
1223 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmNearestTiesToEven,
1224 BuiltinID, E, *this);
1225 case NVPTX::BI__nvvm_add_rz_sat_f:
1226 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardZero, BuiltinID,
1227 E, *this);
1228 case NVPTX::BI__nvvm_add_rm_sat_f:
1229 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardNegative,
1230 BuiltinID, E, *this);
1231 case NVPTX::BI__nvvm_add_rp_sat_f:
1232 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardPositive,
1233 BuiltinID, E, *this);
1234 case NVPTX::BI__nvvm_add_rn_ftz_sat_f:
1235 case NVPTX::BI__nvvm_add_rn_ftz_sat_f16:
1236 case NVPTX::BI__nvvm_add_rn_ftz_sat_v2f16:
1237 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmNearestTiesToEven,
1238 BuiltinID, E, *this);
1239 case NVPTX::BI__nvvm_add_rz_ftz_sat_f:
1240 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardZero,
1241 BuiltinID, E, *this);
1242 case NVPTX::BI__nvvm_add_rm_ftz_sat_f:
1243 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardNegative,
1244 BuiltinID, E, *this);
1245 case NVPTX::BI__nvvm_add_rp_ftz_sat_f:
1246 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardPositive,
1247 BuiltinID, E, *this);
1248 case NVPTX::BI__nvvm_ldg_h:
1249 case NVPTX::BI__nvvm_ldg_h2:
1250 return MakeLdg(*this, E);
1251 case NVPTX::BI__nvvm_ldu_h:
1252 case NVPTX::BI__nvvm_ldu_h2:
1253 return MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E);
1254 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
1255 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_4,
1256 Intrinsic::nvvm_cp_async_ca_shared_global_4_s, *this, E,
1257 4);
1258 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8:
1259 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_8,
1260 Intrinsic::nvvm_cp_async_ca_shared_global_8_s, *this, E,
1261 8);
1262 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
1263 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_16,
1264 Intrinsic::nvvm_cp_async_ca_shared_global_16_s, *this, E,
1265 16);
1266 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
1267 return MakeCpAsync(Intrinsic::nvvm_cp_async_cg_shared_global_16,
1268 Intrinsic::nvvm_cp_async_cg_shared_global_16_s, *this, E,
1269 16);
1270 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_x:
1271 return Builder.CreateCall(
1272 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_x));
1273 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_y:
1274 return Builder.CreateCall(
1275 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_y));
1276 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_z:
1277 return Builder.CreateCall(
1278 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_z));
1279 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_w:
1280 return Builder.CreateCall(
1281 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_w));
1282 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_x:
1283 return Builder.CreateCall(
1284 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_x));
1285 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_y:
1286 return Builder.CreateCall(
1287 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_y));
1288 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_z:
1289 return Builder.CreateCall(
1290 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_z));
1291 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_w:
1292 return Builder.CreateCall(
1293 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_w));
1294 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_x:
1295 return Builder.CreateCall(
1296 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_x));
1297 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_y:
1298 return Builder.CreateCall(
1299 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_y));
1300 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_z:
1301 return Builder.CreateCall(
1302 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_z));
1303 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_w:
1304 return Builder.CreateCall(
1305 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_w));
1306 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_x:
1307 return Builder.CreateCall(
1308 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_x));
1309 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_y:
1310 return Builder.CreateCall(
1311 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_y));
1312 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_z:
1313 return Builder.CreateCall(
1314 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_z));
1315 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_w:
1316 return Builder.CreateCall(
1317 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_w));
1318 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctarank:
1319 return Builder.CreateCall(
1320 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctarank));
1321 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctarank:
1322 return Builder.CreateCall(
1323 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctarank));
1324 case NVPTX::BI__nvvm_is_explicit_cluster:
1325 return Builder.CreateCall(
1326 CGM.getIntrinsic(Intrinsic::nvvm_is_explicit_cluster));
1327 case NVPTX::BI__nvvm_isspacep_shared_cluster:
1328 return Builder.CreateCall(
1329 CGM.getIntrinsic(Intrinsic::nvvm_isspacep_shared_cluster),
1330 EmitScalarExpr(E->getArg(0)));
1331 case NVPTX::BI__nvvm_mapa:
1332 return Builder.CreateCall(
1333 CGM.getIntrinsic(Intrinsic::nvvm_mapa),
1334 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1335 case NVPTX::BI__nvvm_mapa_shared_cluster:
1336 return Builder.CreateCall(
1337 CGM.getIntrinsic(Intrinsic::nvvm_mapa_shared_cluster),
1338 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1339 case NVPTX::BI__nvvm_getctarank:
1340 return Builder.CreateCall(
1341 CGM.getIntrinsic(Intrinsic::nvvm_getctarank),
1342 EmitScalarExpr(E->getArg(0)));
1343 case NVPTX::BI__nvvm_getctarank_shared_cluster:
1344 return Builder.CreateCall(
1345 CGM.getIntrinsic(Intrinsic::nvvm_getctarank_shared_cluster),
1346 EmitScalarExpr(E->getArg(0)));
1347 case NVPTX::BI__nvvm_barrier_cluster_arrive:
1348 return Builder.CreateCall(
1349 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive));
1350 case NVPTX::BI__nvvm_barrier_cluster_arrive_relaxed:
1351 return Builder.CreateCall(
1352 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive_relaxed));
1353 case NVPTX::BI__nvvm_barrier_cluster_wait:
1354 return Builder.CreateCall(
1355 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_wait));
1356 case NVPTX::BI__nvvm_fence_sc_cluster:
1357 return Builder.CreateCall(
1358 CGM.getIntrinsic(Intrinsic::nvvm_fence_sc_cluster));
1359 case NVPTX::BI__nvvm_bar_sync:
1360 return Builder.CreateCall(
1361 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1362 EmitScalarExpr(E->getArg(0)));
1363 case NVPTX::BI__syncthreads:
1364 return Builder.CreateCall(
1365 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1366 Builder.getInt32(0));
1367 case NVPTX::BI__nvvm_barrier_sync:
1368 return Builder.CreateCall(
1369 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_all),
1370 EmitScalarExpr(E->getArg(0)));
1371 case NVPTX::BI__nvvm_barrier_sync_cnt:
1372 return Builder.CreateCall(
1373 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_count),
1374 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1375 case NVPTX::BI__nvvm_bar0_and:
1376 return Builder.CreateZExt(
1377 Builder.CreateIntrinsic(
1378 Intrinsic::nvvm_barrier_cta_red_and_aligned_all, {},
1379 {Builder.getInt32(0),
1380 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1381 Builder.getInt32(0))}),
1382 Builder.getInt32Ty());
1383 case NVPTX::BI__nvvm_bar0_or:
1384 return Builder.CreateZExt(
1385 Builder.CreateIntrinsic(
1386 Intrinsic::nvvm_barrier_cta_red_or_aligned_all, {},
1387 {Builder.getInt32(0),
1388 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1389 Builder.getInt32(0))}),
1390 Builder.getInt32Ty());
1391 case NVPTX::BI__nvvm_bar0_popc:
1392 return Builder.CreateIntrinsic(
1393 Intrinsic::nvvm_barrier_cta_red_popc_aligned_all, {},
1394 {Builder.getInt32(0), Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1395 Builder.getInt32(0))});
1396 case NVPTX::BI__nvvm_mbarrier_init:
1397 case NVPTX::BI__nvvm_mbarrier_init_shared: {
1398 // The intrinsic is overloaded on the pointer, so the two builtins differ
1399 // only in the address space of their first argument.
1400 Value *Ptr = EmitScalarExpr(E->getArg(0));
1401 return Builder.CreateIntrinsic(
1402 Intrinsic::nvvm_mbarrier_init, {Ptr->getType()},
1403 {Ptr, EmitScalarExpr(E->getArg(1)), Builder.getInt32(0)});
1404 }
1405 default:
1406 return nullptr;
1407 }
1408}
V
#define V(N, I)
Definition ASTContext.h:3825
MakeAtomicCmpXchgValue
Value * MakeAtomicCmpXchgValue(CodeGenFunction &CGF, const CallExpr *E, bool ReturnBool, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering)
Utility to insert an atomic cmpxchg instruction.
Definition CGBuiltin.cpp:420
appendDefaultIntrinsicArgs
void appendDefaultIntrinsicArgs(SmallVectorImpl< llvm::Value * > &Args, llvm::Function *F)
Definition CGBuiltin.cpp:256
MakeBinaryAtomicValue
Value * MakeBinaryAtomicValue(CodeGenFunction &CGF, llvm::AtomicRMWInst::BinOp Kind, const CallExpr *E, AtomicOrdering Ordering)
Utility to insert an atomic instruction based on Intrinsic::ID and the expression node.
Definition CGBuiltin.cpp:320
MMA_VARIANTS_B1_AND
#define MMA_VARIANTS_B1_AND(geom, type)
PZO_CVT
#define PZO_CVT(cvt)
MMA_INTR
#define MMA_INTR(geom_op_type, layout)
Definition NVPTX.cpp:31
MMA_VARIANTS
#define MMA_VARIANTS(geom, type)
MMA_SATF_VARIANTS
#define MMA_SATF_VARIANTS(geom, type)
MMA_LDST
#define MMA_LDST(n, geom_op_type)
Definition NVPTX.cpp:33
MMA_VARIANTS_B1_XOR
#define MMA_VARIANTS_B1_XOR(geom, type)
MMA_VARIANTS_I4
#define MMA_VARIANTS_I4(geom, type)
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
ASTContext::GE_None
@ GE_None
No error.
Definition ASTContext.h:2719
clang::ASTContext::GetBuiltinType
QualType GetBuiltinType(unsigned ID, GetBuiltinTypeError &Error, unsigned *IntegerConstantArgs=nullptr) const
Return the type for the specified builtin.
Definition ASTContext.cpp:12982
clang::CallExpr
CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).
Definition Expr.h:2987
clang::CallExpr::getArg
Expr * getArg(unsigned Arg)
getArg - Return the specified argument.
Definition Expr.h:3191
clang::CallExpr::getNumArgs
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this call.
Definition Expr.h:3178
clang::CharUnits
CharUnits - This is an opaque type for sizes expressed in character units.
Definition CharUnits.h:38
clang::CharUnits::getAsAlign
llvm::Align getAsAlign() const
getAsAlign - Returns Quantity as a valid llvm::Align, Beware llvm::Align assumes power of two 8-bit b...
Definition CharUnits.h:189
clang::CharUnits::fromQuantity
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition CharUnits.h:63
clang::CodeGen::Address
Like RawAddress, an abstract representation of an aligned address, but the pointer contained in this ...
Definition Address.h:128
clang::CodeGen::Address::emitRawPointer
llvm::Value * emitRawPointer(CodeGenFunction &CGF) const
Return the pointer contained in this class after authenticating it and adding offset to it if necessa...
Definition Address.h:253
clang::CodeGen::Address::getElementType
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition Address.h:209
clang::CodeGen::CGBuilderTy::CreateAtomicRMW
llvm::AtomicRMWInst * CreateAtomicRMW(llvm::AtomicRMWInst::BinOp Op, Address Addr, llvm::Value *Val, llvm::AtomicOrdering Ordering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:190
clang::CodeGen::CGBuilderTy::CreateAtomicCmpXchg
llvm::AtomicCmpXchgInst * CreateAtomicCmpXchg(Address Addr, llvm::Value *Cmp, llvm::Value *New, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:179
clang::CodeGen::CGBuilderTy::CreateAlignedLoad
llvm::LoadInst * CreateAlignedLoad(llvm::Type *Ty, llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition CGBuilder.h:138
clang::CodeGen::CGBuilderTy::CreateAddrSpaceCast
Address CreateAddrSpaceCast(Address Addr, llvm::Type *Ty, llvm::Type *ElementTy, const llvm::Twine &Name="")
Definition CGBuilder.h:199
clang::CodeGen::CodeGenFunction
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
Definition CodeGenFunction.h:259
clang::CodeGen::CodeGenFunction::ConvertType
llvm::Type * ConvertType(QualType T)
Definition CodeGenFunction.cpp:245
clang::CodeGen::CodeGenFunction::getTarget
const TargetInfo & getTarget() const
Definition CodeGenFunction.h:2247
clang::CodeGen::CodeGenFunction::ConvertTypeForMem
llvm::Type * ConvertTypeForMem(QualType T)
Definition CodeGenFunction.cpp:241
clang::CodeGen::CodeGenFunction::EmitPointerWithAlignment
Address EmitPointerWithAlignment(const Expr *Addr, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr, KnownNonNull_t IsKnownNonNull=NotKnownNonNull)
EmitPointerWithAlignment - Given an expression with a pointer type, emit the value and compute our be...
Definition CGExpr.cpp:1617
clang::CodeGen::CodeGenFunction::EmitScalarExpr
llvm::Value * EmitScalarExpr(const Expr *E, bool IgnoreResultAssign=false)
EmitScalarExpr - Emit the computation of the specified expression of LLVM scalar type,...
Definition CGExprScalar.cpp:6239
clang::CodeGen::CodeGenFunction::EmitNVPTXBuiltinExpr
llvm::Value * EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E)
Definition NVPTX.cpp:446
clang::CodeGen::CodeGenFunction::getLLVMContext
llvm::LLVMContext & getLLVMContext()
Definition CodeGenFunction.h:2248
clang::CodeGen::CodeGenModule::getContext
ASTContext & getContext() const
Definition CodeGenModule.h:900
clang::CodeGen::CodeGenModule::getNaturalPointeeTypeAlignment
CharUnits getNaturalPointeeTypeAlignment(QualType T, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr)
Definition CodeGenModule.cpp:8837
clang::CodeGen::CodeGenModule::getIntrinsic
llvm::Function * getIntrinsic(unsigned IID, ArrayRef< llvm::Type * > Tys={})
Definition CodeGenModule.cpp:7352
clang::Expr::getIntegerConstantExpr
std::optional< llvm::APSInt > getIntegerConstantExpr(const ASTContext &Ctx, bool AllowRelaxedEval=false) const
isIntegerConstantExpr - Return the value if this expression is a valid integer constant expression.
Definition ExprConstant.cpp:22861
clang::Expr::getType
QualType getType() const
Definition Expr.h:145
clang::QualType
A (possibly-)qualified type.
Definition TypeBase.h:938
clang::Scope
Scope - A scope is a transient data structure that is used while parsing the program.
Definition Scope.h:41
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1314
clang::Value::getType
QualType getType() const
Definition Value.cpp:238
clang
Top level wrappers for InstallAPI frontend operations.
Definition CalledOnceCheck.h:17
clang::OpenACCClauseKind::DType
@ DType
'dtype' clause, an alias for 'device_type', stored separately for diagnostic purposes.
Definition OpenACCKinds.h:274
clang::ObjCSubstitutionContext::Result
@ Result
The result type of a method or function.
Definition TypeBase.h:906
llvm
Diagnostic wrappers for TextAPI types for error reporting.
Definition Dominators.h:30
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