clang 24.0.0git
NVPTX.cpp
Go to the documentation of this file.
1//===-------- NVPTX.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CGBuiltin.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsNVPTX.h"
16#include "llvm/TargetParser/AtomicScope.h"
17
18using namespace clang;
19using namespace CodeGen;
20using namespace llvm;
21
22namespace {
23// Helper classes for mapping MMA builtins to particular LLVM intrinsic variant.
24struct NVPTXMmaLdstInfo {
25 unsigned NumResults; // Number of elements to load/store
26 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
27 unsigned IID_col;
28 unsigned IID_row;
29};
30
31#define MMA_INTR(geom_op_type, layout) \
32 Intrinsic::nvvm_wmma_##geom_op_type##_##layout##_stride
33#define MMA_LDST(n, geom_op_type) \
34 { n, MMA_INTR(geom_op_type, col), MMA_INTR(geom_op_type, row) }
35
36static NVPTXMmaLdstInfo getNVPTXMmaLdstInfo(unsigned BuiltinID) {
37 switch (BuiltinID) {
38 // FP MMA loads
39 case NVPTX::BI__hmma_m16n16k16_ld_a:
40 return MMA_LDST(8, m16n16k16_load_a_f16);
41 case NVPTX::BI__hmma_m16n16k16_ld_b:
42 return MMA_LDST(8, m16n16k16_load_b_f16);
43 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
44 return MMA_LDST(4, m16n16k16_load_c_f16);
45 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
46 return MMA_LDST(8, m16n16k16_load_c_f32);
47 case NVPTX::BI__hmma_m32n8k16_ld_a:
48 return MMA_LDST(8, m32n8k16_load_a_f16);
49 case NVPTX::BI__hmma_m32n8k16_ld_b:
50 return MMA_LDST(8, m32n8k16_load_b_f16);
51 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
52 return MMA_LDST(4, m32n8k16_load_c_f16);
53 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
54 return MMA_LDST(8, m32n8k16_load_c_f32);
55 case NVPTX::BI__hmma_m8n32k16_ld_a:
56 return MMA_LDST(8, m8n32k16_load_a_f16);
57 case NVPTX::BI__hmma_m8n32k16_ld_b:
58 return MMA_LDST(8, m8n32k16_load_b_f16);
59 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
60 return MMA_LDST(4, m8n32k16_load_c_f16);
61 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
62 return MMA_LDST(8, m8n32k16_load_c_f32);
63
64 // Integer MMA loads
65 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
66 return MMA_LDST(2, m16n16k16_load_a_s8);
67 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
68 return MMA_LDST(2, m16n16k16_load_a_u8);
69 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
70 return MMA_LDST(2, m16n16k16_load_b_s8);
71 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
72 return MMA_LDST(2, m16n16k16_load_b_u8);
73 case NVPTX::BI__imma_m16n16k16_ld_c:
74 return MMA_LDST(8, m16n16k16_load_c_s32);
75 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
76 return MMA_LDST(4, m32n8k16_load_a_s8);
77 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
78 return MMA_LDST(4, m32n8k16_load_a_u8);
79 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
80 return MMA_LDST(1, m32n8k16_load_b_s8);
81 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
82 return MMA_LDST(1, m32n8k16_load_b_u8);
83 case NVPTX::BI__imma_m32n8k16_ld_c:
84 return MMA_LDST(8, m32n8k16_load_c_s32);
85 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
86 return MMA_LDST(1, m8n32k16_load_a_s8);
87 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
88 return MMA_LDST(1, m8n32k16_load_a_u8);
89 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
90 return MMA_LDST(4, m8n32k16_load_b_s8);
91 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
92 return MMA_LDST(4, m8n32k16_load_b_u8);
93 case NVPTX::BI__imma_m8n32k16_ld_c:
94 return MMA_LDST(8, m8n32k16_load_c_s32);
95
96 // Sub-integer MMA loads.
97 // Only row/col layout is supported by A/B fragments.
98 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
99 return {1, 0, MMA_INTR(m8n8k32_load_a_s4, row)};
100 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
101 return {1, 0, MMA_INTR(m8n8k32_load_a_u4, row)};
102 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
103 return {1, MMA_INTR(m8n8k32_load_b_s4, col), 0};
104 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
105 return {1, MMA_INTR(m8n8k32_load_b_u4, col), 0};
106 case NVPTX::BI__imma_m8n8k32_ld_c:
107 return MMA_LDST(2, m8n8k32_load_c_s32);
108 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
109 return {1, 0, MMA_INTR(m8n8k128_load_a_b1, row)};
110 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
111 return {1, MMA_INTR(m8n8k128_load_b_b1, col), 0};
112 case NVPTX::BI__bmma_m8n8k128_ld_c:
113 return MMA_LDST(2, m8n8k128_load_c_s32);
114
115 // Double MMA loads
116 case NVPTX::BI__dmma_m8n8k4_ld_a:
117 return MMA_LDST(1, m8n8k4_load_a_f64);
118 case NVPTX::BI__dmma_m8n8k4_ld_b:
119 return MMA_LDST(1, m8n8k4_load_b_f64);
120 case NVPTX::BI__dmma_m8n8k4_ld_c:
121 return MMA_LDST(2, m8n8k4_load_c_f64);
122
123 // Alternate float MMA loads
124 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
125 return MMA_LDST(4, m16n16k16_load_a_bf16);
126 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
127 return MMA_LDST(4, m16n16k16_load_b_bf16);
128 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
129 return MMA_LDST(2, m8n32k16_load_a_bf16);
130 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
131 return MMA_LDST(8, m8n32k16_load_b_bf16);
132 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
133 return MMA_LDST(8, m32n8k16_load_a_bf16);
134 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
135 return MMA_LDST(2, m32n8k16_load_b_bf16);
136 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
137 return MMA_LDST(4, m16n16k8_load_a_tf32);
138 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
139 return MMA_LDST(4, m16n16k8_load_b_tf32);
140 case NVPTX::BI__mma_tf32_m16n16k8_ld_c:
141 return MMA_LDST(8, m16n16k8_load_c_f32);
142
143 // NOTE: We need to follow inconsitent naming scheme used by NVCC. Unlike
144 // PTX and LLVM IR where stores always use fragment D, NVCC builtins always
145 // use fragment C for both loads and stores.
146 // FP MMA stores.
147 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
148 return MMA_LDST(4, m16n16k16_store_d_f16);
149 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
150 return MMA_LDST(8, m16n16k16_store_d_f32);
151 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
152 return MMA_LDST(4, m32n8k16_store_d_f16);
153 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
154 return MMA_LDST(8, m32n8k16_store_d_f32);
155 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
156 return MMA_LDST(4, m8n32k16_store_d_f16);
157 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
158 return MMA_LDST(8, m8n32k16_store_d_f32);
159
160 // Integer and sub-integer MMA stores.
161 // Another naming quirk. Unlike other MMA builtins that use PTX types in the
162 // name, integer loads/stores use LLVM's i32.
163 case NVPTX::BI__imma_m16n16k16_st_c_i32:
164 return MMA_LDST(8, m16n16k16_store_d_s32);
165 case NVPTX::BI__imma_m32n8k16_st_c_i32:
166 return MMA_LDST(8, m32n8k16_store_d_s32);
167 case NVPTX::BI__imma_m8n32k16_st_c_i32:
168 return MMA_LDST(8, m8n32k16_store_d_s32);
169 case NVPTX::BI__imma_m8n8k32_st_c_i32:
170 return MMA_LDST(2, m8n8k32_store_d_s32);
171 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
172 return MMA_LDST(2, m8n8k128_store_d_s32);
173
174 // Double MMA store
175 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
176 return MMA_LDST(2, m8n8k4_store_d_f64);
177
178 // Alternate float MMA store
179 case NVPTX::BI__mma_m16n16k8_st_c_f32:
180 return MMA_LDST(8, m16n16k8_store_d_f32);
181
182 default:
183 llvm_unreachable("Unknown MMA builtin");
184 }
185}
186#undef MMA_LDST
187#undef MMA_INTR
188
189
190struct NVPTXMmaInfo {
191 unsigned NumEltsA;
192 unsigned NumEltsB;
193 unsigned NumEltsC;
194 unsigned NumEltsD;
195
196 // Variants are ordered by layout-A/layout-B/satf, where 'row' has priority
197 // over 'col' for layout. The index of non-satf variants is expected to match
198 // the undocumented layout constants used by CUDA's mma.hpp.
199 std::array<unsigned, 8> Variants;
200
201 unsigned getMMAIntrinsic(int Layout, bool Satf) {
202 unsigned Index = Layout + 4 * Satf;
203 if (Index >= Variants.size())
204 return 0;
205 return Variants[Index];
206 }
207};
208
209 // Returns an intrinsic that matches Layout and Satf for valid combinations of
210 // Layout and Satf, 0 otherwise.
211static NVPTXMmaInfo getNVPTXMmaInfo(unsigned BuiltinID) {
212 // clang-format off
213#define MMA_VARIANTS(geom, type) \
214 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type, \
215 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
216 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type, \
217 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type
218#define MMA_SATF_VARIANTS(geom, type) \
219 MMA_VARIANTS(geom, type), \
220 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type##_satfinite, \
221 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
222 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type##_satfinite, \
223 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type##_satfinite
224// Sub-integer MMA only supports row.col layout.
225#define MMA_VARIANTS_I4(geom, type) \
226 0, \
227 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
228 0, \
229 0, \
230 0, \
231 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
232 0, \
233 0
234// b1 MMA does not support .satfinite.
235#define MMA_VARIANTS_B1_XOR(geom, type) \
236 0, \
237 Intrinsic::nvvm_wmma_##geom##_mma_xor_popc_row_col_##type, \
238 0, \
239 0, \
240 0, \
241 0, \
242 0, \
243 0
244#define MMA_VARIANTS_B1_AND(geom, type) \
245 0, \
246 Intrinsic::nvvm_wmma_##geom##_mma_and_popc_row_col_##type, \
247 0, \
248 0, \
249 0, \
250 0, \
251 0, \
252 0
253 // clang-format on
254 switch (BuiltinID) {
255 // FP MMA
256 // Note that 'type' argument of MMA_SATF_VARIANTS uses D_C notation, while
257 // NumEltsN of return value are ordered as A,B,C,D.
258 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
259 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f16)}}};
260 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
261 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f16)}}};
262 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
263 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f32)}}};
264 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
265 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f32)}}};
266 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
267 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f16)}}};
268 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
269 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f16)}}};
270 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
271 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f32)}}};
272 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
273 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f32)}}};
274 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
275 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f16)}}};
276 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
277 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f16)}}};
278 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
279 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f32)}}};
280 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
281 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f32)}}};
282
283 // Integer MMA
284 case NVPTX::BI__imma_m16n16k16_mma_s8:
285 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, s8)}}};
286 case NVPTX::BI__imma_m16n16k16_mma_u8:
287 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, u8)}}};
288 case NVPTX::BI__imma_m32n8k16_mma_s8:
289 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, s8)}}};
290 case NVPTX::BI__imma_m32n8k16_mma_u8:
291 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, u8)}}};
292 case NVPTX::BI__imma_m8n32k16_mma_s8:
293 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, s8)}}};
294 case NVPTX::BI__imma_m8n32k16_mma_u8:
295 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, u8)}}};
296
297 // Sub-integer MMA
298 case NVPTX::BI__imma_m8n8k32_mma_s4:
299 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, s4)}}};
300 case NVPTX::BI__imma_m8n8k32_mma_u4:
301 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, u4)}}};
302 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
303 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_XOR(m8n8k128, b1)}}};
304 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
305 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_AND(m8n8k128, b1)}}};
306
307 // Double MMA
308 case NVPTX::BI__dmma_m8n8k4_mma_f64:
309 return {1, 1, 2, 2, {{MMA_VARIANTS(m8n8k4, f64)}}};
310
311 // Alternate FP MMA
312 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
313 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k16, bf16)}}};
314 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
315 return {2, 8, 8, 8, {{MMA_VARIANTS(m8n32k16, bf16)}}};
316 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
317 return {8, 2, 8, 8, {{MMA_VARIANTS(m32n8k16, bf16)}}};
318 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32:
319 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k8, tf32)}}};
320 default:
321 llvm_unreachable("Unexpected builtin ID.");
322 }
323#undef MMA_VARIANTS
324#undef MMA_SATF_VARIANTS
325#undef MMA_VARIANTS_I4
326#undef MMA_VARIANTS_B1_AND
327#undef MMA_VARIANTS_B1_XOR
328}
329
330static Value *MakeLdu(unsigned IntrinsicID, CodeGenFunction &CGF,
331 const CallExpr *E) {
332 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
333 QualType ArgType = E->getArg(0)->getType();
334 clang::CharUnits Align = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
335 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
336 return CGF.Builder.CreateCall(
337 CGF.CGM.getIntrinsic(IntrinsicID, {ElemTy, Ptr->getType()}),
338 {Ptr, ConstantInt::get(CGF.Builder.getInt32Ty(), Align.getQuantity())});
339}
340
341static Value *MakeLdg(CodeGenFunction &CGF, const CallExpr *E) {
342 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
343 QualType ArgType = E->getArg(0)->getType();
344 clang::CharUnits AlignV = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
345 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
346
347 // Use addrspace(1) for NVPTX ADDRESS_SPACE_GLOBAL
348 auto *ASC = CGF.Builder.CreateAddrSpaceCast(Ptr, CGF.Builder.getPtrTy(1));
349 auto *LD = CGF.Builder.CreateAlignedLoad(ElemTy, ASC, AlignV.getAsAlign());
350 MDNode *MD = MDNode::get(CGF.Builder.getContext(), {});
351 LD->setMetadata(LLVMContext::MD_invariant_load, MD);
352
353 return LD;
354}
355
356// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
357// for _sys builtins.
358static Value *MakeScopedAtomicRMW(CodeGenFunction &CGF, const CallExpr *E,
359 llvm::AtomicRMWInst::BinOp Kind,
360 llvm::AtomicScope Scope) {
361 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
362 Value *Val = CGF.EmitScalarExpr(E->getArg(1));
363 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
364 *llvm::getAtomicScopeIRString(CGF.getTarget().getTriple(), Scope));
365 return CGF.Builder.CreateAtomicRMW(Kind, Ptr, Val,
366 llvm::AtomicOrdering::Monotonic, SSID);
367}
368
369// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
370// for _sys builtins.
371static Value *MakeScopedAtomicCAS(CodeGenFunction &CGF, const CallExpr *E,
372 llvm::AtomicScope Scope) {
373 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
374 Value *Cmp = CGF.EmitScalarExpr(E->getArg(1));
375 Value *New = CGF.EmitScalarExpr(E->getArg(2));
376 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
377 *llvm::getAtomicScopeIRString(CGF.getTarget().getTriple(), Scope));
378 Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
379 Ptr, Cmp, New, llvm::AtomicOrdering::Monotonic,
380 llvm::AtomicOrdering::Monotonic, SSID);
381 return CGF.Builder.CreateExtractValue(Pair, 0);
382}
383
384static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
385 CodeGenFunction &CGF, const CallExpr *E,
386 int SrcSize) {
387 return E->getNumArgs() == 3
388 ? CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicIDS),
389 {CGF.EmitScalarExpr(E->getArg(0)),
390 CGF.EmitScalarExpr(E->getArg(1)),
391 CGF.EmitScalarExpr(E->getArg(2))})
392 : CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID),
393 {CGF.EmitScalarExpr(E->getArg(0)),
394 CGF.EmitScalarExpr(E->getArg(1))});
395}
396
397static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
398 const CallExpr *E, CodeGenFunction &CGF,
399 ArrayRef<Value *> TrailingArgs = {}) {
400 SmallVector<Value *, 16> Args;
401 auto *FTy = Intrinsic->getFunctionType();
402 unsigned ICEArguments = 0;
403 ASTContext::GetBuiltinTypeError Error;
404 CGF.CGM.getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
405 assert(Error == ASTContext::GE_None && "Should not codegen an error");
406 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
407 assert((ICEArguments & (1 << i)) == 0);
408 auto *ArgValue = CGF.EmitScalarExpr(E->getArg(i));
409 auto *PTy = FTy->getParamType(i);
410 if (PTy != ArgValue->getType())
411 ArgValue = CGF.Builder.CreateBitCast(ArgValue, PTy);
412 Args.push_back(ArgValue);
413 }
414
415 llvm::append_range(Args, TrailingArgs);
416 appendDefaultIntrinsicArgs(Args, Intrinsic);
417
418 return CGF.Builder.CreateCall(Intrinsic, Args);
419}
420
421static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
422 const CallExpr *E, CodeGenFunction &CGF,
423 ArrayRef<Value *> TrailingArgs = {}) {
424 return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF,
425 TrailingArgs);
426}
427
428static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
429 const CallExpr *E, CodeGenFunction &CGF) {
430 return CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID, {Ty}),
431 {CGF.EmitScalarExpr(E->getArg(0)),
432 CGF.EmitScalarExpr(E->getArg(1)),
433 CGF.EmitScalarExpr(E->getArg(2))});
434}
435
436static Value *MakeFAdd(unsigned IntrinsicID, APFloat::roundingMode RM,
437 unsigned BuiltinID, const CallExpr *E,
438 CodeGenFunction &CGF) {
439 llvm::Type *Ty = CGF.ConvertType(E->getType());
440 return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID, Ty), BuiltinID, E, CGF,
441 {CGF.Builder.getInt32(static_cast<int>(RM))});
442}
443
444} // namespace
445
446Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
447 const CallExpr *E) {
448 switch (BuiltinID) {
449 case NVPTX::BI__nvvm_mulhi_i:
450 case NVPTX::BI__nvvm_mulhi_ui:
451 case NVPTX::BI__nvvm_mulhi_ll:
452 case NVPTX::BI__nvvm_mulhi_ull:
453 return Builder.CreateBinaryIntrinsic(
454 E->getType()->hasSignedIntegerRepresentation() ? Intrinsic::smulh
455 : Intrinsic::umulh,
456 EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)));
457 case NVPTX::BI__nvvm_atom_add_gen_i:
458 case NVPTX::BI__nvvm_atom_add_gen_l:
459 case NVPTX::BI__nvvm_atom_add_gen_ll:
460 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Add, E,
461 AtomicOrdering::Monotonic);
462
463 case NVPTX::BI__nvvm_atom_sub_gen_i:
464 case NVPTX::BI__nvvm_atom_sub_gen_l:
465 case NVPTX::BI__nvvm_atom_sub_gen_ll:
466 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Sub, E,
467 AtomicOrdering::Monotonic);
468
469 case NVPTX::BI__nvvm_atom_and_gen_i:
470 case NVPTX::BI__nvvm_atom_and_gen_l:
471 case NVPTX::BI__nvvm_atom_and_gen_ll:
472 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::And, E,
473 AtomicOrdering::Monotonic);
474
475 case NVPTX::BI__nvvm_atom_or_gen_i:
476 case NVPTX::BI__nvvm_atom_or_gen_l:
477 case NVPTX::BI__nvvm_atom_or_gen_ll:
478 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Or, E,
479 AtomicOrdering::Monotonic);
480
481 case NVPTX::BI__nvvm_atom_xor_gen_i:
482 case NVPTX::BI__nvvm_atom_xor_gen_l:
483 case NVPTX::BI__nvvm_atom_xor_gen_ll:
484 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xor, E,
485 AtomicOrdering::Monotonic);
486
487 case NVPTX::BI__nvvm_atom_xchg_gen_i:
488 case NVPTX::BI__nvvm_atom_xchg_gen_l:
489 case NVPTX::BI__nvvm_atom_xchg_gen_ll:
490 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xchg, E,
491 AtomicOrdering::Monotonic);
492
493 case NVPTX::BI__nvvm_atom_max_gen_i:
494 case NVPTX::BI__nvvm_atom_max_gen_l:
495 case NVPTX::BI__nvvm_atom_max_gen_ll:
496 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Max, E,
497 AtomicOrdering::Monotonic);
498
499 case NVPTX::BI__nvvm_atom_max_gen_ui:
500 case NVPTX::BI__nvvm_atom_max_gen_ul:
501 case NVPTX::BI__nvvm_atom_max_gen_ull:
502 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMax, E,
503 AtomicOrdering::Monotonic);
504
505 case NVPTX::BI__nvvm_atom_min_gen_i:
506 case NVPTX::BI__nvvm_atom_min_gen_l:
507 case NVPTX::BI__nvvm_atom_min_gen_ll:
508 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Min, E,
509 AtomicOrdering::Monotonic);
510
511 case NVPTX::BI__nvvm_atom_min_gen_ui:
512 case NVPTX::BI__nvvm_atom_min_gen_ul:
513 case NVPTX::BI__nvvm_atom_min_gen_ull:
514 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMin, E,
515 AtomicOrdering::Monotonic);
516
517 case NVPTX::BI__nvvm_atom_cas_gen_us:
518 case NVPTX::BI__nvvm_atom_cas_gen_i:
519 case NVPTX::BI__nvvm_atom_cas_gen_l:
520 case NVPTX::BI__nvvm_atom_cas_gen_ll:
521 // __nvvm_atom_cas_gen_* should return the old value rather than the
522 // success flag.
523 return MakeAtomicCmpXchgValue(*this, E, /*ReturnBool=*/false,
524 AtomicOrdering::Monotonic,
525 AtomicOrdering::Monotonic);
526
527 case NVPTX::BI__nvvm_atom_add_gen_f:
528 case NVPTX::BI__nvvm_atom_add_gen_d: {
529 Address DestAddr = EmitPointerWithAlignment(E->getArg(0));
530 Value *Val = EmitScalarExpr(E->getArg(1));
531
532 return Builder.CreateAtomicRMW(llvm::AtomicRMWInst::FAdd, DestAddr, Val,
533 AtomicOrdering::Monotonic);
534 }
535
536 case NVPTX::BI__nvvm_atom_inc_gen_ui:
537 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UIncWrap, E,
538 AtomicOrdering::Monotonic);
539
540 case NVPTX::BI__nvvm_atom_dec_gen_ui:
541 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UDecWrap, E,
542 AtomicOrdering::Monotonic);
543
544 case NVPTX::BI__nvvm_ldg_c:
545 case NVPTX::BI__nvvm_ldg_sc:
546 case NVPTX::BI__nvvm_ldg_c2:
547 case NVPTX::BI__nvvm_ldg_sc2:
548 case NVPTX::BI__nvvm_ldg_c4:
549 case NVPTX::BI__nvvm_ldg_sc4:
550 case NVPTX::BI__nvvm_ldg_s:
551 case NVPTX::BI__nvvm_ldg_s2:
552 case NVPTX::BI__nvvm_ldg_s4:
553 case NVPTX::BI__nvvm_ldg_i:
554 case NVPTX::BI__nvvm_ldg_i2:
555 case NVPTX::BI__nvvm_ldg_i4:
556 case NVPTX::BI__nvvm_ldg_l:
557 case NVPTX::BI__nvvm_ldg_l2:
558 case NVPTX::BI__nvvm_ldg_ll:
559 case NVPTX::BI__nvvm_ldg_ll2:
560 case NVPTX::BI__nvvm_ldg_uc:
561 case NVPTX::BI__nvvm_ldg_uc2:
562 case NVPTX::BI__nvvm_ldg_uc4:
563 case NVPTX::BI__nvvm_ldg_us:
564 case NVPTX::BI__nvvm_ldg_us2:
565 case NVPTX::BI__nvvm_ldg_us4:
566 case NVPTX::BI__nvvm_ldg_ui:
567 case NVPTX::BI__nvvm_ldg_ui2:
568 case NVPTX::BI__nvvm_ldg_ui4:
569 case NVPTX::BI__nvvm_ldg_ul:
570 case NVPTX::BI__nvvm_ldg_ul2:
571 case NVPTX::BI__nvvm_ldg_ull:
572 case NVPTX::BI__nvvm_ldg_ull2:
573 case NVPTX::BI__nvvm_ldg_f:
574 case NVPTX::BI__nvvm_ldg_f2:
575 case NVPTX::BI__nvvm_ldg_f4:
576 case NVPTX::BI__nvvm_ldg_d:
577 case NVPTX::BI__nvvm_ldg_d2:
578 // PTX Interoperability section 2.2: "For a vector with an even number of
579 // elements, its alignment is set to number of elements times the alignment
580 // of its member: n*alignof(t)."
581 return MakeLdg(*this, E);
582
583 case NVPTX::BI__nvvm_ldu_c:
584 case NVPTX::BI__nvvm_ldu_sc:
585 case NVPTX::BI__nvvm_ldu_c2:
586 case NVPTX::BI__nvvm_ldu_sc2:
587 case NVPTX::BI__nvvm_ldu_c4:
588 case NVPTX::BI__nvvm_ldu_sc4:
589 case NVPTX::BI__nvvm_ldu_s:
590 case NVPTX::BI__nvvm_ldu_s2:
591 case NVPTX::BI__nvvm_ldu_s4:
592 case NVPTX::BI__nvvm_ldu_i:
593 case NVPTX::BI__nvvm_ldu_i2:
594 case NVPTX::BI__nvvm_ldu_i4:
595 case NVPTX::BI__nvvm_ldu_l:
596 case NVPTX::BI__nvvm_ldu_l2:
597 case NVPTX::BI__nvvm_ldu_ll:
598 case NVPTX::BI__nvvm_ldu_ll2:
599 case NVPTX::BI__nvvm_ldu_uc:
600 case NVPTX::BI__nvvm_ldu_uc2:
601 case NVPTX::BI__nvvm_ldu_uc4:
602 case NVPTX::BI__nvvm_ldu_us:
603 case NVPTX::BI__nvvm_ldu_us2:
604 case NVPTX::BI__nvvm_ldu_us4:
605 case NVPTX::BI__nvvm_ldu_ui:
606 case NVPTX::BI__nvvm_ldu_ui2:
607 case NVPTX::BI__nvvm_ldu_ui4:
608 case NVPTX::BI__nvvm_ldu_ul:
609 case NVPTX::BI__nvvm_ldu_ul2:
610 case NVPTX::BI__nvvm_ldu_ull:
611 case NVPTX::BI__nvvm_ldu_ull2:
612 return MakeLdu(Intrinsic::nvvm_ldu_global_i, *this, E);
613 case NVPTX::BI__nvvm_ldu_f:
614 case NVPTX::BI__nvvm_ldu_f2:
615 case NVPTX::BI__nvvm_ldu_f4:
616 case NVPTX::BI__nvvm_ldu_d:
617 case NVPTX::BI__nvvm_ldu_d2:
618 return MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E);
619
620 case NVPTX::BI__nvvm_atom_cta_add_gen_i:
621 case NVPTX::BI__nvvm_atom_cta_add_gen_l:
622 case NVPTX::BI__nvvm_atom_cta_add_gen_ll:
623 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add,
624 llvm::AtomicScope::Workgroup);
625 case NVPTX::BI__nvvm_atom_sys_add_gen_i:
626 case NVPTX::BI__nvvm_atom_sys_add_gen_l:
627 case NVPTX::BI__nvvm_atom_sys_add_gen_ll:
628 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add,
629 llvm::AtomicScope::System);
630 case NVPTX::BI__nvvm_atom_cta_add_gen_f:
631 case NVPTX::BI__nvvm_atom_cta_add_gen_d:
632 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd,
633 llvm::AtomicScope::Workgroup);
634 case NVPTX::BI__nvvm_atom_sys_add_gen_f:
635 case NVPTX::BI__nvvm_atom_sys_add_gen_d:
636 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd,
637 llvm::AtomicScope::System);
638 case NVPTX::BI__nvvm_atom_cta_xchg_gen_i:
639 case NVPTX::BI__nvvm_atom_cta_xchg_gen_l:
640 case NVPTX::BI__nvvm_atom_cta_xchg_gen_ll:
641 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg,
642 llvm::AtomicScope::Workgroup);
643 case NVPTX::BI__nvvm_atom_sys_xchg_gen_i:
644 case NVPTX::BI__nvvm_atom_sys_xchg_gen_l:
645 case NVPTX::BI__nvvm_atom_sys_xchg_gen_ll:
646 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg,
647 llvm::AtomicScope::System);
648 case NVPTX::BI__nvvm_atom_cta_max_gen_i:
649 case NVPTX::BI__nvvm_atom_cta_max_gen_l:
650 case NVPTX::BI__nvvm_atom_cta_max_gen_ll:
651 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max,
652 llvm::AtomicScope::Workgroup);
653 case NVPTX::BI__nvvm_atom_cta_max_gen_ui:
654 case NVPTX::BI__nvvm_atom_cta_max_gen_ul:
655 case NVPTX::BI__nvvm_atom_cta_max_gen_ull:
656 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax,
657 llvm::AtomicScope::Workgroup);
658 case NVPTX::BI__nvvm_atom_sys_max_gen_i:
659 case NVPTX::BI__nvvm_atom_sys_max_gen_l:
660 case NVPTX::BI__nvvm_atom_sys_max_gen_ll:
661 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max,
662 llvm::AtomicScope::System);
663 case NVPTX::BI__nvvm_atom_sys_max_gen_ui:
664 case NVPTX::BI__nvvm_atom_sys_max_gen_ul:
665 case NVPTX::BI__nvvm_atom_sys_max_gen_ull:
666 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax,
667 llvm::AtomicScope::System);
668 case NVPTX::BI__nvvm_atom_cta_min_gen_i:
669 case NVPTX::BI__nvvm_atom_cta_min_gen_l:
670 case NVPTX::BI__nvvm_atom_cta_min_gen_ll:
671 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min,
672 llvm::AtomicScope::Workgroup);
673 case NVPTX::BI__nvvm_atom_cta_min_gen_ui:
674 case NVPTX::BI__nvvm_atom_cta_min_gen_ul:
675 case NVPTX::BI__nvvm_atom_cta_min_gen_ull:
676 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin,
677 llvm::AtomicScope::Workgroup);
678 case NVPTX::BI__nvvm_atom_sys_min_gen_i:
679 case NVPTX::BI__nvvm_atom_sys_min_gen_l:
680 case NVPTX::BI__nvvm_atom_sys_min_gen_ll:
681 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min,
682 llvm::AtomicScope::System);
683 case NVPTX::BI__nvvm_atom_sys_min_gen_ui:
684 case NVPTX::BI__nvvm_atom_sys_min_gen_ul:
685 case NVPTX::BI__nvvm_atom_sys_min_gen_ull:
686 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin,
687 llvm::AtomicScope::System);
688 case NVPTX::BI__nvvm_atom_cta_inc_gen_ui:
689 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap,
690 llvm::AtomicScope::Workgroup);
691 case NVPTX::BI__nvvm_atom_cta_dec_gen_ui:
692 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap,
693 llvm::AtomicScope::Workgroup);
694 case NVPTX::BI__nvvm_atom_sys_inc_gen_ui:
695 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap,
696 llvm::AtomicScope::System);
697 case NVPTX::BI__nvvm_atom_sys_dec_gen_ui:
698 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap,
699 llvm::AtomicScope::System);
700 case NVPTX::BI__nvvm_atom_cta_and_gen_i:
701 case NVPTX::BI__nvvm_atom_cta_and_gen_l:
702 case NVPTX::BI__nvvm_atom_cta_and_gen_ll:
703 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And,
704 llvm::AtomicScope::Workgroup);
705 case NVPTX::BI__nvvm_atom_sys_and_gen_i:
706 case NVPTX::BI__nvvm_atom_sys_and_gen_l:
707 case NVPTX::BI__nvvm_atom_sys_and_gen_ll:
708 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And,
709 llvm::AtomicScope::System);
710 case NVPTX::BI__nvvm_atom_cta_or_gen_i:
711 case NVPTX::BI__nvvm_atom_cta_or_gen_l:
712 case NVPTX::BI__nvvm_atom_cta_or_gen_ll:
713 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or,
714 llvm::AtomicScope::Workgroup);
715 case NVPTX::BI__nvvm_atom_sys_or_gen_i:
716 case NVPTX::BI__nvvm_atom_sys_or_gen_l:
717 case NVPTX::BI__nvvm_atom_sys_or_gen_ll:
718 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or,
719 llvm::AtomicScope::System);
720 case NVPTX::BI__nvvm_atom_cta_xor_gen_i:
721 case NVPTX::BI__nvvm_atom_cta_xor_gen_l:
722 case NVPTX::BI__nvvm_atom_cta_xor_gen_ll:
723 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor,
724 llvm::AtomicScope::Workgroup);
725 case NVPTX::BI__nvvm_atom_sys_xor_gen_i:
726 case NVPTX::BI__nvvm_atom_sys_xor_gen_l:
727 case NVPTX::BI__nvvm_atom_sys_xor_gen_ll:
728 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor,
729 llvm::AtomicScope::System);
730 case NVPTX::BI__nvvm_atom_cta_cas_gen_us:
731 case NVPTX::BI__nvvm_atom_cta_cas_gen_i:
732 case NVPTX::BI__nvvm_atom_cta_cas_gen_l:
733 case NVPTX::BI__nvvm_atom_cta_cas_gen_ll:
734 return MakeScopedAtomicCAS(*this, E, llvm::AtomicScope::Workgroup);
735 case NVPTX::BI__nvvm_atom_sys_cas_gen_us:
736 case NVPTX::BI__nvvm_atom_sys_cas_gen_i:
737 case NVPTX::BI__nvvm_atom_sys_cas_gen_l:
738 case NVPTX::BI__nvvm_atom_sys_cas_gen_ll:
739 return MakeScopedAtomicCAS(*this, E, llvm::AtomicScope::System);
740 case NVPTX::BI__nvvm_match_all_sync_i32p:
741 case NVPTX::BI__nvvm_match_all_sync_i64p: {
742 Value *Mask = EmitScalarExpr(E->getArg(0));
743 Value *Val = EmitScalarExpr(E->getArg(1));
744 Address PredOutPtr = EmitPointerWithAlignment(E->getArg(2));
745 Value *ResultPair = Builder.CreateCall(
746 CGM.getIntrinsic(BuiltinID == NVPTX::BI__nvvm_match_all_sync_i32p
747 ? Intrinsic::nvvm_match_all_sync_i32p
748 : Intrinsic::nvvm_match_all_sync_i64p),
749 {Mask, Val});
750 Value *Pred = Builder.CreateZExt(Builder.CreateExtractValue(ResultPair, 1),
751 PredOutPtr.getElementType());
752 Builder.CreateStore(Pred, PredOutPtr);
753 return Builder.CreateExtractValue(ResultPair, 0);
754 }
755
756 // FP MMA loads
757 case NVPTX::BI__hmma_m16n16k16_ld_a:
758 case NVPTX::BI__hmma_m16n16k16_ld_b:
759 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
760 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
761 case NVPTX::BI__hmma_m32n8k16_ld_a:
762 case NVPTX::BI__hmma_m32n8k16_ld_b:
763 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
764 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
765 case NVPTX::BI__hmma_m8n32k16_ld_a:
766 case NVPTX::BI__hmma_m8n32k16_ld_b:
767 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
768 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
769 // Integer MMA loads.
770 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
771 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
772 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
773 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
774 case NVPTX::BI__imma_m16n16k16_ld_c:
775 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
776 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
777 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
778 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
779 case NVPTX::BI__imma_m32n8k16_ld_c:
780 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
781 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
782 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
783 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
784 case NVPTX::BI__imma_m8n32k16_ld_c:
785 // Sub-integer MMA loads.
786 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
787 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
788 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
789 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
790 case NVPTX::BI__imma_m8n8k32_ld_c:
791 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
792 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
793 case NVPTX::BI__bmma_m8n8k128_ld_c:
794 // Double MMA loads.
795 case NVPTX::BI__dmma_m8n8k4_ld_a:
796 case NVPTX::BI__dmma_m8n8k4_ld_b:
797 case NVPTX::BI__dmma_m8n8k4_ld_c:
798 // Alternate float MMA loads.
799 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
800 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
801 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
802 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
803 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
804 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
805 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
806 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
807 case NVPTX::BI__mma_tf32_m16n16k8_ld_c: {
808 Address Dst = EmitPointerWithAlignment(E->getArg(0));
809 Value *Src = EmitScalarExpr(E->getArg(1));
810 Value *Ldm = EmitScalarExpr(E->getArg(2));
811 std::optional<llvm::APSInt> isColMajorArg =
812 E->getArg(3)->getIntegerConstantExpr(getContext());
813 if (!isColMajorArg)
814 return nullptr;
815 bool isColMajor = isColMajorArg->getSExtValue();
816 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
817 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
818 if (IID == 0)
819 return nullptr;
820
821 Value *Result =
822 Builder.CreateCall(CGM.getIntrinsic(IID, Src->getType()), {Src, Ldm});
823
824 // Save returned values.
825 assert(II.NumResults);
826 if (II.NumResults == 1) {
827 Builder.CreateAlignedStore(Result, Dst.emitRawPointer(*this),
828 CharUnits::fromQuantity(4));
829 } else {
830 for (unsigned i = 0; i < II.NumResults; ++i) {
831 Builder.CreateAlignedStore(
832 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i),
833 Dst.getElementType()),
834 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
835 llvm::ConstantInt::get(IntTy, i)),
836 CharUnits::fromQuantity(4));
837 }
838 }
839 return Result;
840 }
841
842 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
843 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
844 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
845 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
846 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
847 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
848 case NVPTX::BI__imma_m16n16k16_st_c_i32:
849 case NVPTX::BI__imma_m32n8k16_st_c_i32:
850 case NVPTX::BI__imma_m8n32k16_st_c_i32:
851 case NVPTX::BI__imma_m8n8k32_st_c_i32:
852 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
853 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
854 case NVPTX::BI__mma_m16n16k8_st_c_f32: {
855 Value *Dst = EmitScalarExpr(E->getArg(0));
856 Address Src = EmitPointerWithAlignment(E->getArg(1));
857 Value *Ldm = EmitScalarExpr(E->getArg(2));
858 std::optional<llvm::APSInt> isColMajorArg =
859 E->getArg(3)->getIntegerConstantExpr(getContext());
860 if (!isColMajorArg)
861 return nullptr;
862 bool isColMajor = isColMajorArg->getSExtValue();
863 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
864 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
865 if (IID == 0)
866 return nullptr;
867 Function *Intrinsic =
868 CGM.getIntrinsic(IID, Dst->getType());
869 llvm::Type *ParamType = Intrinsic->getFunctionType()->getParamType(1);
870 SmallVector<Value *, 10> Values = {Dst};
871 for (unsigned i = 0; i < II.NumResults; ++i) {
872 Value *V = Builder.CreateAlignedLoad(
873 Src.getElementType(),
874 Builder.CreateGEP(Src.getElementType(), Src.emitRawPointer(*this),
875 llvm::ConstantInt::get(IntTy, i)),
876 CharUnits::fromQuantity(4));
877 Values.push_back(Builder.CreateBitCast(V, ParamType));
878 }
879 Values.push_back(Ldm);
880 Value *Result = Builder.CreateCall(Intrinsic, Values);
881 return Result;
882 }
883
884 // BI__hmma_m16n16k16_mma_<Dtype><CType>(d, a, b, c, layout, satf) -->
885 // Intrinsic::nvvm_wmma_m16n16k16_mma_sync<layout A,B><DType><CType><Satf>
886 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
887 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
888 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
889 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
890 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
891 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
892 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
893 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
894 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
895 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
896 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
897 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
898 case NVPTX::BI__imma_m16n16k16_mma_s8:
899 case NVPTX::BI__imma_m16n16k16_mma_u8:
900 case NVPTX::BI__imma_m32n8k16_mma_s8:
901 case NVPTX::BI__imma_m32n8k16_mma_u8:
902 case NVPTX::BI__imma_m8n32k16_mma_s8:
903 case NVPTX::BI__imma_m8n32k16_mma_u8:
904 case NVPTX::BI__imma_m8n8k32_mma_s4:
905 case NVPTX::BI__imma_m8n8k32_mma_u4:
906 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
907 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
908 case NVPTX::BI__dmma_m8n8k4_mma_f64:
909 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
910 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
911 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
912 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32: {
913 Address Dst = EmitPointerWithAlignment(E->getArg(0));
914 Address SrcA = EmitPointerWithAlignment(E->getArg(1));
915 Address SrcB = EmitPointerWithAlignment(E->getArg(2));
916 Address SrcC = EmitPointerWithAlignment(E->getArg(3));
917 std::optional<llvm::APSInt> LayoutArg =
918 E->getArg(4)->getIntegerConstantExpr(getContext());
919 if (!LayoutArg)
920 return nullptr;
921 int Layout = LayoutArg->getSExtValue();
922 if (Layout < 0 || Layout > 3)
923 return nullptr;
924 llvm::APSInt SatfArg;
925 if (BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1 ||
926 BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1)
927 SatfArg = 0; // .b1 does not have satf argument.
928 else if (std::optional<llvm::APSInt> OptSatfArg =
929 E->getArg(5)->getIntegerConstantExpr(getContext()))
930 SatfArg = *OptSatfArg;
931 else
932 return nullptr;
933 bool Satf = SatfArg.getSExtValue();
934 NVPTXMmaInfo MI = getNVPTXMmaInfo(BuiltinID);
935 unsigned IID = MI.getMMAIntrinsic(Layout, Satf);
936 if (IID == 0) // Unsupported combination of Layout/Satf.
937 return nullptr;
938
939 SmallVector<Value *, 24> Values;
940 Function *Intrinsic = CGM.getIntrinsic(IID);
941 llvm::Type *AType = Intrinsic->getFunctionType()->getParamType(0);
942 // Load A
943 for (unsigned i = 0; i < MI.NumEltsA; ++i) {
944 Value *V = Builder.CreateAlignedLoad(
945 SrcA.getElementType(),
946 Builder.CreateGEP(SrcA.getElementType(), SrcA.emitRawPointer(*this),
947 llvm::ConstantInt::get(IntTy, i)),
948 CharUnits::fromQuantity(4));
949 Values.push_back(Builder.CreateBitCast(V, AType));
950 }
951 // Load B
952 llvm::Type *BType = Intrinsic->getFunctionType()->getParamType(MI.NumEltsA);
953 for (unsigned i = 0; i < MI.NumEltsB; ++i) {
954 Value *V = Builder.CreateAlignedLoad(
955 SrcB.getElementType(),
956 Builder.CreateGEP(SrcB.getElementType(), SrcB.emitRawPointer(*this),
957 llvm::ConstantInt::get(IntTy, i)),
958 CharUnits::fromQuantity(4));
959 Values.push_back(Builder.CreateBitCast(V, BType));
960 }
961 // Load C
962 llvm::Type *CType =
963 Intrinsic->getFunctionType()->getParamType(MI.NumEltsA + MI.NumEltsB);
964 for (unsigned i = 0; i < MI.NumEltsC; ++i) {
965 Value *V = Builder.CreateAlignedLoad(
966 SrcC.getElementType(),
967 Builder.CreateGEP(SrcC.getElementType(), SrcC.emitRawPointer(*this),
968 llvm::ConstantInt::get(IntTy, i)),
969 CharUnits::fromQuantity(4));
970 Values.push_back(Builder.CreateBitCast(V, CType));
971 }
972 Value *Result = Builder.CreateCall(Intrinsic, Values);
973 llvm::Type *DType = Dst.getElementType();
974 for (unsigned i = 0; i < MI.NumEltsD; ++i)
975 Builder.CreateAlignedStore(
976 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i), DType),
977 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
978 llvm::ConstantInt::get(IntTy, i)),
979 CharUnits::fromQuantity(4));
980 return Result;
981 }
982 // The following builtins require half type support
983 case NVPTX::BI__nvvm_ex2_approx_f16:
984 return MakeHalfType(
985 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx, Builder.getHalfTy()),
986 BuiltinID, E, *this);
987 case NVPTX::BI__nvvm_ex2_approx_f16x2:
988 return MakeHalfType(
989 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx,
990 FixedVectorType::get(Builder.getHalfTy(), 2)),
991 BuiltinID, E, *this);
992 case NVPTX::BI__nvvm_ff2f16x2_rn:
993 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, *this);
994 case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
995 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn_relu, BuiltinID, E, *this);
996 case NVPTX::BI__nvvm_ff2f16x2_rz:
997 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz, BuiltinID, E, *this);
998 case NVPTX::BI__nvvm_ff2f16x2_rz_relu:
999 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz_relu, BuiltinID, E, *this);
1000
1001#define PZO_CVT(cvt) \
1002 case NVPTX::BI__nvvm_##cvt##_pzo: \
1003 return MakeHalfType(Intrinsic::nvvm_##cvt, BuiltinID, E, *this, \
1004 {Builder.getTrue()})
1005
1006 PZO_CVT(ff2f16x2_rn);
1007 PZO_CVT(ff2f16x2_rn_relu);
1008 PZO_CVT(ff2f16x2_rz);
1009 PZO_CVT(ff2f16x2_rz_relu);
1010 PZO_CVT(ff2f16x2_rn_satfinite);
1011 PZO_CVT(ff2f16x2_rn_relu_satfinite);
1012 PZO_CVT(ff2f16x2_rz_satfinite);
1013 PZO_CVT(ff2f16x2_rz_relu_satfinite);
1014 PZO_CVT(ff2bf16x2_rn);
1015 PZO_CVT(ff2bf16x2_rn_relu);
1016 PZO_CVT(ff2bf16x2_rz);
1017 PZO_CVT(ff2bf16x2_rz_relu);
1018 PZO_CVT(ff2bf16x2_rn_satfinite);
1019 PZO_CVT(ff2bf16x2_rn_relu_satfinite);
1020 PZO_CVT(ff2bf16x2_rz_satfinite);
1021 PZO_CVT(ff2bf16x2_rz_relu_satfinite);
1022 PZO_CVT(f2f16_rn);
1023 PZO_CVT(f2f16_rn_relu);
1024 PZO_CVT(f2f16_rz);
1025 PZO_CVT(f2f16_rz_relu);
1026 PZO_CVT(f2f16_rn_satfinite);
1027 PZO_CVT(f2f16_rn_relu_satfinite);
1028 PZO_CVT(f2f16_rz_satfinite);
1029 PZO_CVT(f2f16_rz_relu_satfinite);
1030 PZO_CVT(f2bf16_rn);
1031 PZO_CVT(f2bf16_rn_relu);
1032 PZO_CVT(f2bf16_rz);
1033 PZO_CVT(f2bf16_rz_relu);
1034 PZO_CVT(f2bf16_rn_satfinite);
1035 PZO_CVT(f2bf16_rn_relu_satfinite);
1036 PZO_CVT(f2bf16_rz_satfinite);
1037 PZO_CVT(f2bf16_rz_relu_satfinite);
1038
1039 PZO_CVT(ff_to_e4m3x2_rn);
1040 PZO_CVT(ff_to_e4m3x2_rn_relu);
1041 PZO_CVT(ff_to_e4m3x2_rz);
1042 PZO_CVT(ff_to_e4m3x2_rz_relu);
1043 PZO_CVT(ff_to_e5m2x2_rn);
1044 PZO_CVT(ff_to_e5m2x2_rn_relu);
1045 PZO_CVT(ff_to_e5m2x2_rz);
1046 PZO_CVT(ff_to_e5m2x2_rz_relu);
1047 PZO_CVT(f16x2_to_e4m3x2_rn);
1048 PZO_CVT(f16x2_to_e4m3x2_rn_relu);
1049 PZO_CVT(f16x2_to_e4m3x2_rz);
1050 PZO_CVT(f16x2_to_e4m3x2_rz_relu);
1051 PZO_CVT(f16x2_to_e5m2x2_rn);
1052 PZO_CVT(f16x2_to_e5m2x2_rn_relu);
1053 PZO_CVT(f16x2_to_e5m2x2_rz);
1054 PZO_CVT(f16x2_to_e5m2x2_rz_relu);
1055 PZO_CVT(bf16x2_to_e4m3x2_rn_satfinite);
1056 PZO_CVT(bf16x2_to_e4m3x2_rn_relu_satfinite);
1057 PZO_CVT(bf16x2_to_e4m3x2_rz_satfinite);
1058 PZO_CVT(bf16x2_to_e4m3x2_rz_relu_satfinite);
1059 PZO_CVT(bf16x2_to_e5m2x2_rn_satfinite);
1060 PZO_CVT(bf16x2_to_e5m2x2_rn_relu_satfinite);
1061 PZO_CVT(bf16x2_to_e5m2x2_rz_satfinite);
1062 PZO_CVT(bf16x2_to_e5m2x2_rz_relu_satfinite);
1063
1064 PZO_CVT(ff_to_e2m3x2_rn_satfinite);
1065 PZO_CVT(ff_to_e2m3x2_rn_relu_satfinite);
1066 PZO_CVT(ff_to_e2m3x2_rz_satfinite);
1067 PZO_CVT(ff_to_e2m3x2_rz_relu_satfinite);
1068 PZO_CVT(ff_to_e3m2x2_rn_satfinite);
1069 PZO_CVT(ff_to_e3m2x2_rn_relu_satfinite);
1070 PZO_CVT(ff_to_e3m2x2_rz_satfinite);
1071 PZO_CVT(ff_to_e3m2x2_rz_relu_satfinite);
1072 PZO_CVT(f16x2_to_e2m3x2_rn_satfinite);
1073 PZO_CVT(f16x2_to_e2m3x2_rn_relu_satfinite);
1074 PZO_CVT(f16x2_to_e2m3x2_rz_satfinite);
1075 PZO_CVT(f16x2_to_e2m3x2_rz_relu_satfinite);
1076 PZO_CVT(f16x2_to_e3m2x2_rn_satfinite);
1077 PZO_CVT(f16x2_to_e3m2x2_rn_relu_satfinite);
1078 PZO_CVT(f16x2_to_e3m2x2_rz_satfinite);
1079 PZO_CVT(f16x2_to_e3m2x2_rz_relu_satfinite);
1080 PZO_CVT(bf16x2_to_e2m3x2_rn_satfinite);
1081 PZO_CVT(bf16x2_to_e2m3x2_rn_relu_satfinite);
1082 PZO_CVT(bf16x2_to_e2m3x2_rz_satfinite);
1083 PZO_CVT(bf16x2_to_e2m3x2_rz_relu_satfinite);
1084 PZO_CVT(bf16x2_to_e3m2x2_rn_satfinite);
1085 PZO_CVT(bf16x2_to_e3m2x2_rn_relu_satfinite);
1086 PZO_CVT(bf16x2_to_e3m2x2_rz_satfinite);
1087 PZO_CVT(bf16x2_to_e3m2x2_rz_relu_satfinite);
1088
1089 PZO_CVT(ff_to_e2m1x2_rn_satfinite);
1090 PZO_CVT(ff_to_e2m1x2_rn_relu_satfinite);
1091 PZO_CVT(ff_to_e2m1x2_rz_satfinite);
1092 PZO_CVT(ff_to_e2m1x2_rz_relu_satfinite);
1093 PZO_CVT(f16x2_to_e2m1x2_rn_satfinite);
1094 PZO_CVT(f16x2_to_e2m1x2_rn_relu_satfinite);
1095 PZO_CVT(f16x2_to_e2m1x2_rz_satfinite);
1096 PZO_CVT(f16x2_to_e2m1x2_rz_relu_satfinite);
1097 PZO_CVT(bf16x2_to_e2m1x2_rn_satfinite);
1098 PZO_CVT(bf16x2_to_e2m1x2_rn_relu_satfinite);
1099 PZO_CVT(bf16x2_to_e2m1x2_rz_satfinite);
1100 PZO_CVT(bf16x2_to_e2m1x2_rz_relu_satfinite);
1101
1102#undef PZO_CVT
1103
1104 case NVPTX::BI__nvvm_fma_rn_f16:
1105 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16, BuiltinID, E, *this);
1106 case NVPTX::BI__nvvm_fma_rn_f16x2:
1107 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16x2, BuiltinID, E, *this);
1108 case NVPTX::BI__nvvm_fma_rn_ftz_f16:
1109 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16, BuiltinID, E, *this);
1110 case NVPTX::BI__nvvm_fma_rn_ftz_f16x2:
1111 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16x2, BuiltinID, E, *this);
1112 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16:
1113 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16, BuiltinID, E,
1114 *this);
1115 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16x2:
1116 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16x2, BuiltinID, E,
1117 *this);
1118 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16:
1119 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16, BuiltinID, E,
1120 *this);
1121 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16x2:
1122 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16x2, BuiltinID, E,
1123 *this);
1124 case NVPTX::BI__nvvm_fma_rn_relu_f16:
1125 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16, BuiltinID, E, *this);
1126 case NVPTX::BI__nvvm_fma_rn_relu_f16x2:
1127 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16x2, BuiltinID, E, *this);
1128 case NVPTX::BI__nvvm_fma_rn_sat_f16:
1129 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16, BuiltinID, E, *this);
1130 case NVPTX::BI__nvvm_fma_rn_sat_f16x2:
1131 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16x2, BuiltinID, E, *this);
1132 case NVPTX::BI__nvvm_fma_rn_oob_f16:
1133 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getHalfTy(), E,
1134 *this);
1135 case NVPTX::BI__nvvm_fma_rn_oob_f16x2:
1136 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1137 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1138 *this);
1139 case NVPTX::BI__nvvm_fma_rn_oob_bf16:
1140 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getBFloatTy(), E,
1141 *this);
1142 case NVPTX::BI__nvvm_fma_rn_oob_bf16x2:
1143 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1144 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1145 *this);
1146 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16:
1147 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getHalfTy(), E,
1148 *this);
1149 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16x2:
1150 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1151 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1152 *this);
1153 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16:
1154 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getBFloatTy(), E,
1155 *this);
1156 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16x2:
1157 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1158 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1159 *this);
1160 case NVPTX::BI__nvvm_fmax_f16:
1161 return MakeHalfType(Intrinsic::nvvm_fmax_f16, BuiltinID, E, *this);
1162 case NVPTX::BI__nvvm_fmax_f16x2:
1163 return MakeHalfType(Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, *this);
1164 case NVPTX::BI__nvvm_fmax_ftz_f16:
1165 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, *this);
1166 case NVPTX::BI__nvvm_fmax_ftz_f16x2:
1167 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, *this);
1168 case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
1169 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, *this);
1170 case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
1171 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
1172 *this);
1173 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
1174 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
1175 E, *this);
1176 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
1177 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
1178 BuiltinID, E, *this);
1179 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
1180 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
1181 *this);
1182 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
1183 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
1184 E, *this);
1185 case NVPTX::BI__nvvm_fmax_nan_f16:
1186 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, *this);
1187 case NVPTX::BI__nvvm_fmax_nan_f16x2:
1188 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, *this);
1189 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
1190 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
1191 *this);
1192 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
1193 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
1194 E, *this);
1195 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
1196 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
1197 *this);
1198 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
1199 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
1200 *this);
1201 case NVPTX::BI__nvvm_fmin_f16:
1202 return MakeHalfType(Intrinsic::nvvm_fmin_f16, BuiltinID, E, *this);
1203 case NVPTX::BI__nvvm_fmin_f16x2:
1204 return MakeHalfType(Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, *this);
1205 case NVPTX::BI__nvvm_fmin_ftz_f16:
1206 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, *this);
1207 case NVPTX::BI__nvvm_fmin_ftz_f16x2:
1208 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, *this);
1209 case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
1210 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, *this);
1211 case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
1212 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
1213 *this);
1214 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
1215 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
1216 E, *this);
1217 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
1218 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
1219 BuiltinID, E, *this);
1220 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
1221 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
1222 *this);
1223 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
1224 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
1225 E, *this);
1226 case NVPTX::BI__nvvm_fmin_nan_f16:
1227 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, *this);
1228 case NVPTX::BI__nvvm_fmin_nan_f16x2:
1229 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, *this);
1230 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
1231 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
1232 *this);
1233 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
1234 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
1235 E, *this);
1236 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
1237 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
1238 *this);
1239 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
1240 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
1241 *this);
1242 case NVPTX::BI__nvvm_fabs_f:
1243 case NVPTX::BI__nvvm_abs_bf16:
1244 case NVPTX::BI__nvvm_abs_bf16x2:
1245 case NVPTX::BI__nvvm_fabs_f16:
1246 case NVPTX::BI__nvvm_fabs_f16x2:
1247 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs,
1248 EmitScalarExpr(E->getArg(0)));
1249 case NVPTX::BI__nvvm_fabs_ftz_f:
1250 case NVPTX::BI__nvvm_fabs_ftz_f16:
1251 case NVPTX::BI__nvvm_fabs_ftz_f16x2:
1252 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs_ftz,
1253 EmitScalarExpr(E->getArg(0)));
1254 case NVPTX::BI__nvvm_fabs_d:
1255 return Builder.CreateFAbs(EmitScalarExpr(E->getArg(0)));
1256 case NVPTX::BI__nvvm_ex2_approx_d:
1257 case NVPTX::BI__nvvm_ex2_approx_f:
1258 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx,
1259 EmitScalarExpr(E->getArg(0)));
1260 case NVPTX::BI__nvvm_ex2_approx_ftz_f:
1261 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx_ftz,
1262 EmitScalarExpr(E->getArg(0)));
1263 case NVPTX::BI__nvvm_add_rn_f:
1264 case NVPTX::BI__nvvm_add_rn_d:
1265 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmNearestTiesToEven,
1266 BuiltinID, E, *this);
1267 case NVPTX::BI__nvvm_add_rz_f:
1268 case NVPTX::BI__nvvm_add_rz_d:
1269 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardZero, BuiltinID, E,
1270 *this);
1271 case NVPTX::BI__nvvm_add_rm_f:
1272 case NVPTX::BI__nvvm_add_rm_d:
1273 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardNegative, BuiltinID,
1274 E, *this);
1275 case NVPTX::BI__nvvm_add_rp_f:
1276 case NVPTX::BI__nvvm_add_rp_d:
1277 return MakeFAdd(Intrinsic::nvvm_fadd, APFloat::rmTowardPositive, BuiltinID,
1278 E, *this);
1279 case NVPTX::BI__nvvm_add_rn_ftz_f:
1280 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmNearestTiesToEven,
1281 BuiltinID, E, *this);
1282 case NVPTX::BI__nvvm_add_rz_ftz_f:
1283 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardZero, BuiltinID,
1284 E, *this);
1285 case NVPTX::BI__nvvm_add_rm_ftz_f:
1286 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardNegative,
1287 BuiltinID, E, *this);
1288 case NVPTX::BI__nvvm_add_rp_ftz_f:
1289 return MakeFAdd(Intrinsic::nvvm_fadd_ftz, APFloat::rmTowardPositive,
1290 BuiltinID, E, *this);
1291 case NVPTX::BI__nvvm_add_rn_sat_f:
1292 case NVPTX::BI__nvvm_add_rn_sat_f16:
1293 case NVPTX::BI__nvvm_add_rn_sat_v2f16:
1294 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmNearestTiesToEven,
1295 BuiltinID, E, *this);
1296 case NVPTX::BI__nvvm_add_rz_sat_f:
1297 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardZero, BuiltinID,
1298 E, *this);
1299 case NVPTX::BI__nvvm_add_rm_sat_f:
1300 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardNegative,
1301 BuiltinID, E, *this);
1302 case NVPTX::BI__nvvm_add_rp_sat_f:
1303 return MakeFAdd(Intrinsic::nvvm_fadd_sat, APFloat::rmTowardPositive,
1304 BuiltinID, E, *this);
1305 case NVPTX::BI__nvvm_add_rn_ftz_sat_f:
1306 case NVPTX::BI__nvvm_add_rn_ftz_sat_f16:
1307 case NVPTX::BI__nvvm_add_rn_ftz_sat_v2f16:
1308 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmNearestTiesToEven,
1309 BuiltinID, E, *this);
1310 case NVPTX::BI__nvvm_add_rz_ftz_sat_f:
1311 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardZero,
1312 BuiltinID, E, *this);
1313 case NVPTX::BI__nvvm_add_rm_ftz_sat_f:
1314 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardNegative,
1315 BuiltinID, E, *this);
1316 case NVPTX::BI__nvvm_add_rp_ftz_sat_f:
1317 return MakeFAdd(Intrinsic::nvvm_fadd_ftz_sat, APFloat::rmTowardPositive,
1318 BuiltinID, E, *this);
1319 case NVPTX::BI__nvvm_ldg_h:
1320 case NVPTX::BI__nvvm_ldg_h2:
1321 return MakeLdg(*this, E);
1322 case NVPTX::BI__nvvm_ldu_h:
1323 case NVPTX::BI__nvvm_ldu_h2:
1324 return MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E);
1325 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
1326 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_4,
1327 Intrinsic::nvvm_cp_async_ca_shared_global_4_s, *this, E,
1328 4);
1329 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8:
1330 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_8,
1331 Intrinsic::nvvm_cp_async_ca_shared_global_8_s, *this, E,
1332 8);
1333 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
1334 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_16,
1335 Intrinsic::nvvm_cp_async_ca_shared_global_16_s, *this, E,
1336 16);
1337 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
1338 return MakeCpAsync(Intrinsic::nvvm_cp_async_cg_shared_global_16,
1339 Intrinsic::nvvm_cp_async_cg_shared_global_16_s, *this, E,
1340 16);
1341 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_x:
1342 return Builder.CreateCall(
1343 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_x));
1344 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_y:
1345 return Builder.CreateCall(
1346 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_y));
1347 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_z:
1348 return Builder.CreateCall(
1349 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_z));
1350 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_w:
1351 return Builder.CreateCall(
1352 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_w));
1353 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_x:
1354 return Builder.CreateCall(
1355 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_x));
1356 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_y:
1357 return Builder.CreateCall(
1358 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_y));
1359 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_z:
1360 return Builder.CreateCall(
1361 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_z));
1362 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_w:
1363 return Builder.CreateCall(
1364 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_w));
1365 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_x:
1366 return Builder.CreateCall(
1367 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_x));
1368 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_y:
1369 return Builder.CreateCall(
1370 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_y));
1371 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_z:
1372 return Builder.CreateCall(
1373 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_z));
1374 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_w:
1375 return Builder.CreateCall(
1376 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_w));
1377 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_x:
1378 return Builder.CreateCall(
1379 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_x));
1380 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_y:
1381 return Builder.CreateCall(
1382 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_y));
1383 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_z:
1384 return Builder.CreateCall(
1385 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_z));
1386 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_w:
1387 return Builder.CreateCall(
1388 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_w));
1389 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctarank:
1390 return Builder.CreateCall(
1391 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctarank));
1392 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctarank:
1393 return Builder.CreateCall(
1394 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctarank));
1395 case NVPTX::BI__nvvm_is_explicit_cluster:
1396 return Builder.CreateCall(
1397 CGM.getIntrinsic(Intrinsic::nvvm_is_explicit_cluster));
1398 case NVPTX::BI__nvvm_isspacep_shared_cluster:
1399 return Builder.CreateCall(
1400 CGM.getIntrinsic(Intrinsic::nvvm_isspacep_shared_cluster),
1401 EmitScalarExpr(E->getArg(0)));
1402 case NVPTX::BI__nvvm_mapa:
1403 return Builder.CreateCall(
1404 CGM.getIntrinsic(Intrinsic::nvvm_mapa),
1405 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1406 case NVPTX::BI__nvvm_mapa_shared_cluster:
1407 return Builder.CreateCall(
1408 CGM.getIntrinsic(Intrinsic::nvvm_mapa_shared_cluster),
1409 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1410 case NVPTX::BI__nvvm_getctarank:
1411 return Builder.CreateCall(
1412 CGM.getIntrinsic(Intrinsic::nvvm_getctarank),
1413 EmitScalarExpr(E->getArg(0)));
1414 case NVPTX::BI__nvvm_getctarank_shared_cluster:
1415 return Builder.CreateCall(
1416 CGM.getIntrinsic(Intrinsic::nvvm_getctarank_shared_cluster),
1417 EmitScalarExpr(E->getArg(0)));
1418 case NVPTX::BI__nvvm_barrier_cluster_arrive:
1419 return Builder.CreateCall(
1420 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive));
1421 case NVPTX::BI__nvvm_barrier_cluster_arrive_relaxed:
1422 return Builder.CreateCall(
1423 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive_relaxed));
1424 case NVPTX::BI__nvvm_barrier_cluster_wait:
1425 return Builder.CreateCall(
1426 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_wait));
1427 case NVPTX::BI__nvvm_fence_sc_cluster:
1428 return Builder.CreateCall(
1429 CGM.getIntrinsic(Intrinsic::nvvm_fence_sc_cluster));
1430 case NVPTX::BI__nvvm_bar_sync:
1431 return Builder.CreateCall(
1432 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1433 EmitScalarExpr(E->getArg(0)));
1434 case NVPTX::BI__syncthreads:
1435 return Builder.CreateCall(
1436 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1437 Builder.getInt32(0));
1438 case NVPTX::BI__nvvm_barrier_sync:
1439 return Builder.CreateCall(
1440 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_all),
1441 EmitScalarExpr(E->getArg(0)));
1442 case NVPTX::BI__nvvm_barrier_sync_cnt:
1443 return Builder.CreateCall(
1444 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_count),
1445 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1446 case NVPTX::BI__nvvm_bar0_and:
1447 return Builder.CreateZExt(
1448 Builder.CreateIntrinsic(
1449 Intrinsic::nvvm_barrier_cta_red_and_aligned_all, {},
1450 {Builder.getInt32(0),
1451 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1452 Builder.getInt32(0))}),
1453 Builder.getInt32Ty());
1454 case NVPTX::BI__nvvm_bar0_or:
1455 return Builder.CreateZExt(
1456 Builder.CreateIntrinsic(
1457 Intrinsic::nvvm_barrier_cta_red_or_aligned_all, {},
1458 {Builder.getInt32(0),
1459 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1460 Builder.getInt32(0))}),
1461 Builder.getInt32Ty());
1462 case NVPTX::BI__nvvm_bar0_popc:
1463 return Builder.CreateIntrinsic(
1464 Intrinsic::nvvm_barrier_cta_red_popc_aligned_all, {},
1465 {Builder.getInt32(0), Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1466 Builder.getInt32(0))});
1467 case NVPTX::BI__nvvm_mbarrier_init:
1468 case NVPTX::BI__nvvm_mbarrier_init_shared: {
1469 // The intrinsic is overloaded on the pointer, so the two builtins differ
1470 // only in the address space of their first argument.
1471 Value *Ptr = EmitScalarExpr(E->getArg(0));
1472 return Builder.CreateIntrinsic(
1473 Intrinsic::nvvm_mbarrier_init, {Ptr->getType()},
1474 {Ptr, EmitScalarExpr(E->getArg(1)), Builder.getInt32(0)});
1475 }
1476 default:
1477 return nullptr;
1478 }
1479}
V
#define V(N, I)
Definition ASTContext.h:3855
MakeAtomicCmpXchgValue
Value * MakeAtomicCmpXchgValue(CodeGenFunction &CGF, const CallExpr *E, bool ReturnBool, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering)
Utility to insert an atomic cmpxchg instruction.
Definition CGBuiltin.cpp:420
appendDefaultIntrinsicArgs
void appendDefaultIntrinsicArgs(SmallVectorImpl< llvm::Value * > &Args, llvm::Function *F)
Definition CGBuiltin.cpp:256
MakeBinaryAtomicValue
Value * MakeBinaryAtomicValue(CodeGenFunction &CGF, llvm::AtomicRMWInst::BinOp Kind, const CallExpr *E, AtomicOrdering Ordering)
Utility to insert an atomic instruction based on Intrinsic::ID and the expression node.
Definition CGBuiltin.cpp:320
MMA_VARIANTS_B1_AND
#define MMA_VARIANTS_B1_AND(geom, type)
PZO_CVT
#define PZO_CVT(cvt)
MMA_INTR
#define MMA_INTR(geom_op_type, layout)
Definition NVPTX.cpp:31
MMA_VARIANTS
#define MMA_VARIANTS(geom, type)
MMA_SATF_VARIANTS
#define MMA_SATF_VARIANTS(geom, type)
MMA_LDST
#define MMA_LDST(n, geom_op_type)
Definition NVPTX.cpp:33
MMA_VARIANTS_B1_XOR
#define MMA_VARIANTS_B1_XOR(geom, type)
MMA_VARIANTS_I4
#define MMA_VARIANTS_I4(geom, type)
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
ASTContext::GE_None
@ GE_None
No error.
Definition ASTContext.h:2746
clang::ASTContext::GetBuiltinType
QualType GetBuiltinType(unsigned ID, GetBuiltinTypeError &Error, unsigned *IntegerConstantArgs=nullptr) const
Return the type for the specified builtin.
Definition ASTContext.cpp:13087
clang::CallExpr
CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).
Definition Expr.h:2987
clang::CallExpr::getArg
Expr * getArg(unsigned Arg)
getArg - Return the specified argument.
Definition Expr.h:3191
clang::CallExpr::getNumArgs
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this call.
Definition Expr.h:3178
clang::CharUnits
This is an opaque type for sizes expressed in character units.
Definition CharUnits.h:38
clang::CharUnits::getAsAlign
llvm::Align getAsAlign() const
Returns Quantity as a valid llvm::Align, Beware llvm::Align assumes power of two 8-bit bytes.
Definition CharUnits.h:157
clang::CharUnits::fromQuantity
static CharUnits fromQuantity(QuantityType Quantity)
Construct a CharUnits quantity from a raw integer type.
Definition CharUnits.h:58
clang::CodeGen::Address
Like RawAddress, an abstract representation of an aligned address, but the pointer contained in this ...
Definition Address.h:128
clang::CodeGen::Address::emitRawPointer
llvm::Value * emitRawPointer(CodeGenFunction &CGF) const
Return the pointer contained in this class after authenticating it and adding offset to it if necessa...
Definition Address.h:253
clang::CodeGen::Address::getElementType
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition Address.h:209
clang::CodeGen::CGBuilderTy::CreateAtomicRMW
llvm::AtomicRMWInst * CreateAtomicRMW(llvm::AtomicRMWInst::BinOp Op, Address Addr, llvm::Value *Val, llvm::AtomicOrdering Ordering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:190
clang::CodeGen::CGBuilderTy::CreateAtomicCmpXchg
llvm::AtomicCmpXchgInst * CreateAtomicCmpXchg(Address Addr, llvm::Value *Cmp, llvm::Value *New, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:179
clang::CodeGen::CGBuilderTy::CreateAlignedLoad
llvm::LoadInst * CreateAlignedLoad(llvm::Type *Ty, llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition CGBuilder.h:138
clang::CodeGen::CGBuilderTy::CreateAddrSpaceCast
Address CreateAddrSpaceCast(Address Addr, llvm::Type *Ty, llvm::Type *ElementTy, const llvm::Twine &Name="")
Definition CGBuilder.h:199
clang::CodeGen::CodeGenFunction
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
Definition CodeGenFunction.h:259
clang::CodeGen::CodeGenFunction::ConvertType
llvm::Type * ConvertType(QualType T)
Definition CodeGenFunction.cpp:230
clang::CodeGen::CodeGenFunction::getTarget
const TargetInfo & getTarget() const
Definition CodeGenFunction.h:2284
clang::CodeGen::CodeGenFunction::ConvertTypeForMem
llvm::Type * ConvertTypeForMem(QualType T)
Definition CodeGenFunction.cpp:226
clang::CodeGen::CodeGenFunction::EmitPointerWithAlignment
Address EmitPointerWithAlignment(const Expr *Addr, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr, KnownNonNull_t IsKnownNonNull=NotKnownNonNull)
EmitPointerWithAlignment - Given an expression with a pointer type, emit the value and compute our be...
Definition CGExpr.cpp:1624
clang::CodeGen::CodeGenFunction::EmitScalarExpr
llvm::Value * EmitScalarExpr(const Expr *E, bool IgnoreResultAssign=false)
EmitScalarExpr - Emit the computation of the specified expression of LLVM scalar type,...
Definition CGExprScalar.cpp:6199
clang::CodeGen::CodeGenFunction::EmitNVPTXBuiltinExpr
llvm::Value * EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E)
Definition NVPTX.cpp:446
clang::CodeGen::CodeGenFunction::getLLVMContext
llvm::LLVMContext & getLLVMContext()
Definition CodeGenFunction.h:2285
clang::CodeGen::CodeGenModule::getContext
ASTContext & getContext() const
Definition CodeGenModule.h:900
clang::CodeGen::CodeGenModule::getNaturalPointeeTypeAlignment
CharUnits getNaturalPointeeTypeAlignment(QualType T, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr)
Definition CodeGenModule.cpp:8817
clang::CodeGen::CodeGenModule::getIntrinsic
llvm::Function * getIntrinsic(unsigned IID, ArrayRef< llvm::Type * > Tys={})
Definition CodeGenModule.cpp:7299
clang::Expr::getIntegerConstantExpr
std::optional< llvm::APSInt > getIntegerConstantExpr(const ASTContext &Ctx, bool AllowRelaxedEval=false) const
isIntegerConstantExpr - Return the value if this expression is a valid integer constant expression.
Definition ExprConstant.cpp:23076
clang::Expr::getType
QualType getType() const
Definition Expr.h:145
clang::QualType
A (possibly-)qualified type.
Definition TypeBase.h:938
clang::Scope
Scope - A scope is a transient data structure that is used while parsing the program.
Definition Scope.h:41
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1314
clang::Type::hasSignedIntegerRepresentation
bool hasSignedIntegerRepresentation() const
Determine whether this type has an signed integer representation of some sort, e.g....
Definition Type.cpp:2434
clang::Value::getType
QualType getType() const
Definition Value.cpp:238
clang
Top level wrappers for InstallAPI frontend operations.
Definition CalledOnceCheck.h:17
clang::OpenACCClauseKind::DType
@ DType
'dtype' clause, an alias for 'device_type', stored separately for diagnostic purposes.
Definition OpenACCKinds.h:274
clang::ObjCSubstitutionContext::Result
@ Result
The result type of a method or function.
Definition TypeBase.h:906
llvm
Diagnostic wrappers for TextAPI types for error reporting.
Definition Dominators.h:30
Generated on for clang by doxygen 1.14.0