clang 23.0.0git
NVPTX.cpp
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1//===-------- NVPTX.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CGBuiltin.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsNVPTX.h"
16
17using namespace clang;
18using namespace CodeGen;
19using namespace llvm;
20
21namespace {
22// Helper classes for mapping MMA builtins to particular LLVM intrinsic variant.
23struct NVPTXMmaLdstInfo {
24 unsigned NumResults; // Number of elements to load/store
25 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
26 unsigned IID_col;
27 unsigned IID_row;
28};
29
30#define MMA_INTR(geom_op_type, layout) \
31 Intrinsic::nvvm_wmma_##geom_op_type##_##layout##_stride
32#define MMA_LDST(n, geom_op_type) \
33 { n, MMA_INTR(geom_op_type, col), MMA_INTR(geom_op_type, row) }
34
35static NVPTXMmaLdstInfo getNVPTXMmaLdstInfo(unsigned BuiltinID) {
36 switch (BuiltinID) {
37 // FP MMA loads
38 case NVPTX::BI__hmma_m16n16k16_ld_a:
39 return MMA_LDST(8, m16n16k16_load_a_f16);
40 case NVPTX::BI__hmma_m16n16k16_ld_b:
41 return MMA_LDST(8, m16n16k16_load_b_f16);
42 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
43 return MMA_LDST(4, m16n16k16_load_c_f16);
44 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
45 return MMA_LDST(8, m16n16k16_load_c_f32);
46 case NVPTX::BI__hmma_m32n8k16_ld_a:
47 return MMA_LDST(8, m32n8k16_load_a_f16);
48 case NVPTX::BI__hmma_m32n8k16_ld_b:
49 return MMA_LDST(8, m32n8k16_load_b_f16);
50 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
51 return MMA_LDST(4, m32n8k16_load_c_f16);
52 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
53 return MMA_LDST(8, m32n8k16_load_c_f32);
54 case NVPTX::BI__hmma_m8n32k16_ld_a:
55 return MMA_LDST(8, m8n32k16_load_a_f16);
56 case NVPTX::BI__hmma_m8n32k16_ld_b:
57 return MMA_LDST(8, m8n32k16_load_b_f16);
58 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
59 return MMA_LDST(4, m8n32k16_load_c_f16);
60 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
61 return MMA_LDST(8, m8n32k16_load_c_f32);
62
63 // Integer MMA loads
64 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
65 return MMA_LDST(2, m16n16k16_load_a_s8);
66 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
67 return MMA_LDST(2, m16n16k16_load_a_u8);
68 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
69 return MMA_LDST(2, m16n16k16_load_b_s8);
70 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
71 return MMA_LDST(2, m16n16k16_load_b_u8);
72 case NVPTX::BI__imma_m16n16k16_ld_c:
73 return MMA_LDST(8, m16n16k16_load_c_s32);
74 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
75 return MMA_LDST(4, m32n8k16_load_a_s8);
76 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
77 return MMA_LDST(4, m32n8k16_load_a_u8);
78 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
79 return MMA_LDST(1, m32n8k16_load_b_s8);
80 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
81 return MMA_LDST(1, m32n8k16_load_b_u8);
82 case NVPTX::BI__imma_m32n8k16_ld_c:
83 return MMA_LDST(8, m32n8k16_load_c_s32);
84 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
85 return MMA_LDST(1, m8n32k16_load_a_s8);
86 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
87 return MMA_LDST(1, m8n32k16_load_a_u8);
88 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
89 return MMA_LDST(4, m8n32k16_load_b_s8);
90 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
91 return MMA_LDST(4, m8n32k16_load_b_u8);
92 case NVPTX::BI__imma_m8n32k16_ld_c:
93 return MMA_LDST(8, m8n32k16_load_c_s32);
94
95 // Sub-integer MMA loads.
96 // Only row/col layout is supported by A/B fragments.
97 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
98 return {1, 0, MMA_INTR(m8n8k32_load_a_s4, row)};
99 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
100 return {1, 0, MMA_INTR(m8n8k32_load_a_u4, row)};
101 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
102 return {1, MMA_INTR(m8n8k32_load_b_s4, col), 0};
103 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
104 return {1, MMA_INTR(m8n8k32_load_b_u4, col), 0};
105 case NVPTX::BI__imma_m8n8k32_ld_c:
106 return MMA_LDST(2, m8n8k32_load_c_s32);
107 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
108 return {1, 0, MMA_INTR(m8n8k128_load_a_b1, row)};
109 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
110 return {1, MMA_INTR(m8n8k128_load_b_b1, col), 0};
111 case NVPTX::BI__bmma_m8n8k128_ld_c:
112 return MMA_LDST(2, m8n8k128_load_c_s32);
113
114 // Double MMA loads
115 case NVPTX::BI__dmma_m8n8k4_ld_a:
116 return MMA_LDST(1, m8n8k4_load_a_f64);
117 case NVPTX::BI__dmma_m8n8k4_ld_b:
118 return MMA_LDST(1, m8n8k4_load_b_f64);
119 case NVPTX::BI__dmma_m8n8k4_ld_c:
120 return MMA_LDST(2, m8n8k4_load_c_f64);
121
122 // Alternate float MMA loads
123 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
124 return MMA_LDST(4, m16n16k16_load_a_bf16);
125 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
126 return MMA_LDST(4, m16n16k16_load_b_bf16);
127 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
128 return MMA_LDST(2, m8n32k16_load_a_bf16);
129 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
130 return MMA_LDST(8, m8n32k16_load_b_bf16);
131 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
132 return MMA_LDST(8, m32n8k16_load_a_bf16);
133 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
134 return MMA_LDST(2, m32n8k16_load_b_bf16);
135 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
136 return MMA_LDST(4, m16n16k8_load_a_tf32);
137 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
138 return MMA_LDST(4, m16n16k8_load_b_tf32);
139 case NVPTX::BI__mma_tf32_m16n16k8_ld_c:
140 return MMA_LDST(8, m16n16k8_load_c_f32);
141
142 // NOTE: We need to follow inconsitent naming scheme used by NVCC. Unlike
143 // PTX and LLVM IR where stores always use fragment D, NVCC builtins always
144 // use fragment C for both loads and stores.
145 // FP MMA stores.
146 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
147 return MMA_LDST(4, m16n16k16_store_d_f16);
148 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
149 return MMA_LDST(8, m16n16k16_store_d_f32);
150 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
151 return MMA_LDST(4, m32n8k16_store_d_f16);
152 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
153 return MMA_LDST(8, m32n8k16_store_d_f32);
154 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
155 return MMA_LDST(4, m8n32k16_store_d_f16);
156 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
157 return MMA_LDST(8, m8n32k16_store_d_f32);
158
159 // Integer and sub-integer MMA stores.
160 // Another naming quirk. Unlike other MMA builtins that use PTX types in the
161 // name, integer loads/stores use LLVM's i32.
162 case NVPTX::BI__imma_m16n16k16_st_c_i32:
163 return MMA_LDST(8, m16n16k16_store_d_s32);
164 case NVPTX::BI__imma_m32n8k16_st_c_i32:
165 return MMA_LDST(8, m32n8k16_store_d_s32);
166 case NVPTX::BI__imma_m8n32k16_st_c_i32:
167 return MMA_LDST(8, m8n32k16_store_d_s32);
168 case NVPTX::BI__imma_m8n8k32_st_c_i32:
169 return MMA_LDST(2, m8n8k32_store_d_s32);
170 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
171 return MMA_LDST(2, m8n8k128_store_d_s32);
172
173 // Double MMA store
174 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
175 return MMA_LDST(2, m8n8k4_store_d_f64);
176
177 // Alternate float MMA store
178 case NVPTX::BI__mma_m16n16k8_st_c_f32:
179 return MMA_LDST(8, m16n16k8_store_d_f32);
180
181 default:
182 llvm_unreachable("Unknown MMA builtin");
183 }
184}
185#undef MMA_LDST
186#undef MMA_INTR
187
188
189struct NVPTXMmaInfo {
190 unsigned NumEltsA;
191 unsigned NumEltsB;
192 unsigned NumEltsC;
193 unsigned NumEltsD;
194
195 // Variants are ordered by layout-A/layout-B/satf, where 'row' has priority
196 // over 'col' for layout. The index of non-satf variants is expected to match
197 // the undocumented layout constants used by CUDA's mma.hpp.
198 std::array<unsigned, 8> Variants;
199
200 unsigned getMMAIntrinsic(int Layout, bool Satf) {
201 unsigned Index = Layout + 4 * Satf;
202 if (Index >= Variants.size())
203 return 0;
204 return Variants[Index];
205 }
206};
207
208 // Returns an intrinsic that matches Layout and Satf for valid combinations of
209 // Layout and Satf, 0 otherwise.
210static NVPTXMmaInfo getNVPTXMmaInfo(unsigned BuiltinID) {
211 // clang-format off
212#define MMA_VARIANTS(geom, type) \
213 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type, \
214 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
215 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type, \
216 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type
217#define MMA_SATF_VARIANTS(geom, type) \
218 MMA_VARIANTS(geom, type), \
219 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type##_satfinite, \
220 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
221 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type##_satfinite, \
222 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type##_satfinite
223// Sub-integer MMA only supports row.col layout.
224#define MMA_VARIANTS_I4(geom, type) \
225 0, \
226 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
227 0, \
228 0, \
229 0, \
230 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
231 0, \
232 0
233// b1 MMA does not support .satfinite.
234#define MMA_VARIANTS_B1_XOR(geom, type) \
235 0, \
236 Intrinsic::nvvm_wmma_##geom##_mma_xor_popc_row_col_##type, \
237 0, \
238 0, \
239 0, \
240 0, \
241 0, \
242 0
243#define MMA_VARIANTS_B1_AND(geom, type) \
244 0, \
245 Intrinsic::nvvm_wmma_##geom##_mma_and_popc_row_col_##type, \
246 0, \
247 0, \
248 0, \
249 0, \
250 0, \
251 0
252 // clang-format on
253 switch (BuiltinID) {
254 // FP MMA
255 // Note that 'type' argument of MMA_SATF_VARIANTS uses D_C notation, while
256 // NumEltsN of return value are ordered as A,B,C,D.
257 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
258 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f16)}}};
259 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
260 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f16)}}};
261 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
262 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m16n16k16, f16_f32)}}};
263 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
264 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, f32_f32)}}};
265 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
266 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f16)}}};
267 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
268 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f16)}}};
269 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
270 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m32n8k16, f16_f32)}}};
271 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
272 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, f32_f32)}}};
273 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
274 return {8, 8, 4, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f16)}}};
275 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
276 return {8, 8, 4, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f16)}}};
277 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
278 return {8, 8, 8, 4, {{MMA_SATF_VARIANTS(m8n32k16, f16_f32)}}};
279 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
280 return {8, 8, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, f32_f32)}}};
281
282 // Integer MMA
283 case NVPTX::BI__imma_m16n16k16_mma_s8:
284 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, s8)}}};
285 case NVPTX::BI__imma_m16n16k16_mma_u8:
286 return {2, 2, 8, 8, {{MMA_SATF_VARIANTS(m16n16k16, u8)}}};
287 case NVPTX::BI__imma_m32n8k16_mma_s8:
288 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, s8)}}};
289 case NVPTX::BI__imma_m32n8k16_mma_u8:
290 return {4, 1, 8, 8, {{MMA_SATF_VARIANTS(m32n8k16, u8)}}};
291 case NVPTX::BI__imma_m8n32k16_mma_s8:
292 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, s8)}}};
293 case NVPTX::BI__imma_m8n32k16_mma_u8:
294 return {1, 4, 8, 8, {{MMA_SATF_VARIANTS(m8n32k16, u8)}}};
295
296 // Sub-integer MMA
297 case NVPTX::BI__imma_m8n8k32_mma_s4:
298 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, s4)}}};
299 case NVPTX::BI__imma_m8n8k32_mma_u4:
300 return {1, 1, 2, 2, {{MMA_VARIANTS_I4(m8n8k32, u4)}}};
301 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
302 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_XOR(m8n8k128, b1)}}};
303 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
304 return {1, 1, 2, 2, {{MMA_VARIANTS_B1_AND(m8n8k128, b1)}}};
305
306 // Double MMA
307 case NVPTX::BI__dmma_m8n8k4_mma_f64:
308 return {1, 1, 2, 2, {{MMA_VARIANTS(m8n8k4, f64)}}};
309
310 // Alternate FP MMA
311 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
312 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k16, bf16)}}};
313 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
314 return {2, 8, 8, 8, {{MMA_VARIANTS(m8n32k16, bf16)}}};
315 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
316 return {8, 2, 8, 8, {{MMA_VARIANTS(m32n8k16, bf16)}}};
317 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32:
318 return {4, 4, 8, 8, {{MMA_VARIANTS(m16n16k8, tf32)}}};
319 default:
320 llvm_unreachable("Unexpected builtin ID.");
321 }
322#undef MMA_VARIANTS
323#undef MMA_SATF_VARIANTS
324#undef MMA_VARIANTS_I4
325#undef MMA_VARIANTS_B1_AND
326#undef MMA_VARIANTS_B1_XOR
327}
328
329static Value *MakeLdu(unsigned IntrinsicID, CodeGenFunction &CGF,
330 const CallExpr *E) {
331 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
332 QualType ArgType = E->getArg(0)->getType();
333 clang::CharUnits Align = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
334 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
335 return CGF.Builder.CreateCall(
336 CGF.CGM.getIntrinsic(IntrinsicID, {ElemTy, Ptr->getType()}),
337 {Ptr, ConstantInt::get(CGF.Builder.getInt32Ty(), Align.getQuantity())});
338}
339
340static Value *MakeLdg(CodeGenFunction &CGF, const CallExpr *E) {
341 Value *Ptr = CGF.EmitScalarExpr(E->getArg(0));
342 QualType ArgType = E->getArg(0)->getType();
343 clang::CharUnits AlignV = CGF.CGM.getNaturalPointeeTypeAlignment(ArgType);
344 llvm::Type *ElemTy = CGF.ConvertTypeForMem(ArgType->getPointeeType());
345
346 // Use addrspace(1) for NVPTX ADDRESS_SPACE_GLOBAL
347 auto *ASC = CGF.Builder.CreateAddrSpaceCast(Ptr, CGF.Builder.getPtrTy(1));
348 auto *LD = CGF.Builder.CreateAlignedLoad(ElemTy, ASC, AlignV.getAsAlign());
349 MDNode *MD = MDNode::get(CGF.Builder.getContext(), {});
350 LD->setMetadata(LLVMContext::MD_invariant_load, MD);
351
352 return LD;
353}
354
355// Set `Scope` to:
356// - "block" for _cta builtins, and
357// - "" for _sys builtins.
358static Value *MakeScopedAtomicRMW(CodeGenFunction &CGF, const CallExpr *E,
359 llvm::AtomicRMWInst::BinOp Kind,
360 StringRef Scope) {
361 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
362 Value *Val = CGF.EmitScalarExpr(E->getArg(1));
363 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(Scope);
364 return CGF.Builder.CreateAtomicRMW(Kind, Ptr, Val,
365 llvm::AtomicOrdering::Monotonic, SSID);
366}
367
368// Set `Scope` to:
369// - "block" for _cta builtins, and
370// - "" for _sys builtins.
371static Value *MakeScopedAtomicCAS(CodeGenFunction &CGF, const CallExpr *E,
372 StringRef Scope) {
373 Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0));
374 Value *Cmp = CGF.EmitScalarExpr(E->getArg(1));
375 Value *New = CGF.EmitScalarExpr(E->getArg(2));
376 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(Scope);
377 Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
378 Ptr, Cmp, New, llvm::AtomicOrdering::Monotonic,
379 llvm::AtomicOrdering::Monotonic, SSID);
380 return CGF.Builder.CreateExtractValue(Pair, 0);
381}
382
383static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
384 CodeGenFunction &CGF, const CallExpr *E,
385 int SrcSize) {
386 return E->getNumArgs() == 3
387 ? CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicIDS),
388 {CGF.EmitScalarExpr(E->getArg(0)),
389 CGF.EmitScalarExpr(E->getArg(1)),
390 CGF.EmitScalarExpr(E->getArg(2))})
391 : CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID),
392 {CGF.EmitScalarExpr(E->getArg(0)),
393 CGF.EmitScalarExpr(E->getArg(1))});
394}
395
396static bool EnsureNativeHalfSupport(unsigned BuiltinID, const CallExpr *E,
397 CodeGenFunction &CGF) {
398 auto &C = CGF.CGM.getContext();
399 if (!C.getLangOpts().NativeHalfType &&
400 C.getTargetInfo().useFP16ConversionIntrinsics()) {
401 CGF.CGM.Error(E->getExprLoc(), C.BuiltinInfo.getQuotedName(BuiltinID) +
402 " requires native half type support.");
403 return false;
404 }
405 return true;
406}
407
408static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
409 const CallExpr *E, CodeGenFunction &CGF) {
410 if (!EnsureNativeHalfSupport(BuiltinID, E, CGF))
411 return nullptr;
412
413 SmallVector<Value *, 16> Args;
414 auto *FTy = Intrinsic->getFunctionType();
415 unsigned ICEArguments = 0;
416 ASTContext::GetBuiltinTypeError Error;
417 CGF.CGM.getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
418 assert(Error == ASTContext::GE_None && "Should not codegen an error");
419 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
420 assert((ICEArguments & (1 << i)) == 0);
421 auto *ArgValue = CGF.EmitScalarExpr(E->getArg(i));
422 auto *PTy = FTy->getParamType(i);
423 if (PTy != ArgValue->getType())
424 ArgValue = CGF.Builder.CreateBitCast(ArgValue, PTy);
425 Args.push_back(ArgValue);
426 }
427
428 return CGF.Builder.CreateCall(Intrinsic, Args);
429}
430
431static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
432 const CallExpr *E, CodeGenFunction &CGF) {
433 return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF);
434}
435
436static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
437 const CallExpr *E, CodeGenFunction &CGF) {
438 return CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID, {Ty}),
439 {CGF.EmitScalarExpr(E->getArg(0)),
440 CGF.EmitScalarExpr(E->getArg(1)),
441 CGF.EmitScalarExpr(E->getArg(2))});
442}
443
444} // namespace
445
446Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
447 const CallExpr *E) {
448 switch (BuiltinID) {
449 case NVPTX::BI__nvvm_atom_add_gen_i:
450 case NVPTX::BI__nvvm_atom_add_gen_l:
451 case NVPTX::BI__nvvm_atom_add_gen_ll:
452 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Add, E,
453 AtomicOrdering::Monotonic);
454
455 case NVPTX::BI__nvvm_atom_sub_gen_i:
456 case NVPTX::BI__nvvm_atom_sub_gen_l:
457 case NVPTX::BI__nvvm_atom_sub_gen_ll:
458 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Sub, E,
459 AtomicOrdering::Monotonic);
460
461 case NVPTX::BI__nvvm_atom_and_gen_i:
462 case NVPTX::BI__nvvm_atom_and_gen_l:
463 case NVPTX::BI__nvvm_atom_and_gen_ll:
464 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::And, E,
465 AtomicOrdering::Monotonic);
466
467 case NVPTX::BI__nvvm_atom_or_gen_i:
468 case NVPTX::BI__nvvm_atom_or_gen_l:
469 case NVPTX::BI__nvvm_atom_or_gen_ll:
470 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Or, E,
471 AtomicOrdering::Monotonic);
472
473 case NVPTX::BI__nvvm_atom_xor_gen_i:
474 case NVPTX::BI__nvvm_atom_xor_gen_l:
475 case NVPTX::BI__nvvm_atom_xor_gen_ll:
476 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xor, E,
477 AtomicOrdering::Monotonic);
478
479 case NVPTX::BI__nvvm_atom_xchg_gen_i:
480 case NVPTX::BI__nvvm_atom_xchg_gen_l:
481 case NVPTX::BI__nvvm_atom_xchg_gen_ll:
482 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Xchg, E,
483 AtomicOrdering::Monotonic);
484
485 case NVPTX::BI__nvvm_atom_max_gen_i:
486 case NVPTX::BI__nvvm_atom_max_gen_l:
487 case NVPTX::BI__nvvm_atom_max_gen_ll:
488 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Max, E,
489 AtomicOrdering::Monotonic);
490
491 case NVPTX::BI__nvvm_atom_max_gen_ui:
492 case NVPTX::BI__nvvm_atom_max_gen_ul:
493 case NVPTX::BI__nvvm_atom_max_gen_ull:
494 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMax, E,
495 AtomicOrdering::Monotonic);
496
497 case NVPTX::BI__nvvm_atom_min_gen_i:
498 case NVPTX::BI__nvvm_atom_min_gen_l:
499 case NVPTX::BI__nvvm_atom_min_gen_ll:
500 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::Min, E,
501 AtomicOrdering::Monotonic);
502
503 case NVPTX::BI__nvvm_atom_min_gen_ui:
504 case NVPTX::BI__nvvm_atom_min_gen_ul:
505 case NVPTX::BI__nvvm_atom_min_gen_ull:
506 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UMin, E,
507 AtomicOrdering::Monotonic);
508
509 case NVPTX::BI__nvvm_atom_cas_gen_us:
510 case NVPTX::BI__nvvm_atom_cas_gen_i:
511 case NVPTX::BI__nvvm_atom_cas_gen_l:
512 case NVPTX::BI__nvvm_atom_cas_gen_ll:
513 // __nvvm_atom_cas_gen_* should return the old value rather than the
514 // success flag.
515 return MakeAtomicCmpXchgValue(*this, E, /*ReturnBool=*/false,
516 AtomicOrdering::Monotonic,
517 AtomicOrdering::Monotonic);
518
519 case NVPTX::BI__nvvm_atom_add_gen_f:
520 case NVPTX::BI__nvvm_atom_add_gen_d: {
521 Address DestAddr = EmitPointerWithAlignment(E->getArg(0));
522 Value *Val = EmitScalarExpr(E->getArg(1));
523
524 return Builder.CreateAtomicRMW(llvm::AtomicRMWInst::FAdd, DestAddr, Val,
525 AtomicOrdering::Monotonic);
526 }
527
528 case NVPTX::BI__nvvm_atom_inc_gen_ui:
529 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UIncWrap, E,
530 AtomicOrdering::Monotonic);
531
532 case NVPTX::BI__nvvm_atom_dec_gen_ui:
533 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::UDecWrap, E,
534 AtomicOrdering::Monotonic);
535
536 case NVPTX::BI__nvvm_ldg_c:
537 case NVPTX::BI__nvvm_ldg_sc:
538 case NVPTX::BI__nvvm_ldg_c2:
539 case NVPTX::BI__nvvm_ldg_sc2:
540 case NVPTX::BI__nvvm_ldg_c4:
541 case NVPTX::BI__nvvm_ldg_sc4:
542 case NVPTX::BI__nvvm_ldg_s:
543 case NVPTX::BI__nvvm_ldg_s2:
544 case NVPTX::BI__nvvm_ldg_s4:
545 case NVPTX::BI__nvvm_ldg_i:
546 case NVPTX::BI__nvvm_ldg_i2:
547 case NVPTX::BI__nvvm_ldg_i4:
548 case NVPTX::BI__nvvm_ldg_l:
549 case NVPTX::BI__nvvm_ldg_l2:
550 case NVPTX::BI__nvvm_ldg_ll:
551 case NVPTX::BI__nvvm_ldg_ll2:
552 case NVPTX::BI__nvvm_ldg_uc:
553 case NVPTX::BI__nvvm_ldg_uc2:
554 case NVPTX::BI__nvvm_ldg_uc4:
555 case NVPTX::BI__nvvm_ldg_us:
556 case NVPTX::BI__nvvm_ldg_us2:
557 case NVPTX::BI__nvvm_ldg_us4:
558 case NVPTX::BI__nvvm_ldg_ui:
559 case NVPTX::BI__nvvm_ldg_ui2:
560 case NVPTX::BI__nvvm_ldg_ui4:
561 case NVPTX::BI__nvvm_ldg_ul:
562 case NVPTX::BI__nvvm_ldg_ul2:
563 case NVPTX::BI__nvvm_ldg_ull:
564 case NVPTX::BI__nvvm_ldg_ull2:
565 case NVPTX::BI__nvvm_ldg_f:
566 case NVPTX::BI__nvvm_ldg_f2:
567 case NVPTX::BI__nvvm_ldg_f4:
568 case NVPTX::BI__nvvm_ldg_d:
569 case NVPTX::BI__nvvm_ldg_d2:
570 // PTX Interoperability section 2.2: "For a vector with an even number of
571 // elements, its alignment is set to number of elements times the alignment
572 // of its member: n*alignof(t)."
573 return MakeLdg(*this, E);
574
575 case NVPTX::BI__nvvm_ldu_c:
576 case NVPTX::BI__nvvm_ldu_sc:
577 case NVPTX::BI__nvvm_ldu_c2:
578 case NVPTX::BI__nvvm_ldu_sc2:
579 case NVPTX::BI__nvvm_ldu_c4:
580 case NVPTX::BI__nvvm_ldu_sc4:
581 case NVPTX::BI__nvvm_ldu_s:
582 case NVPTX::BI__nvvm_ldu_s2:
583 case NVPTX::BI__nvvm_ldu_s4:
584 case NVPTX::BI__nvvm_ldu_i:
585 case NVPTX::BI__nvvm_ldu_i2:
586 case NVPTX::BI__nvvm_ldu_i4:
587 case NVPTX::BI__nvvm_ldu_l:
588 case NVPTX::BI__nvvm_ldu_l2:
589 case NVPTX::BI__nvvm_ldu_ll:
590 case NVPTX::BI__nvvm_ldu_ll2:
591 case NVPTX::BI__nvvm_ldu_uc:
592 case NVPTX::BI__nvvm_ldu_uc2:
593 case NVPTX::BI__nvvm_ldu_uc4:
594 case NVPTX::BI__nvvm_ldu_us:
595 case NVPTX::BI__nvvm_ldu_us2:
596 case NVPTX::BI__nvvm_ldu_us4:
597 case NVPTX::BI__nvvm_ldu_ui:
598 case NVPTX::BI__nvvm_ldu_ui2:
599 case NVPTX::BI__nvvm_ldu_ui4:
600 case NVPTX::BI__nvvm_ldu_ul:
601 case NVPTX::BI__nvvm_ldu_ul2:
602 case NVPTX::BI__nvvm_ldu_ull:
603 case NVPTX::BI__nvvm_ldu_ull2:
604 return MakeLdu(Intrinsic::nvvm_ldu_global_i, *this, E);
605 case NVPTX::BI__nvvm_ldu_f:
606 case NVPTX::BI__nvvm_ldu_f2:
607 case NVPTX::BI__nvvm_ldu_f4:
608 case NVPTX::BI__nvvm_ldu_d:
609 case NVPTX::BI__nvvm_ldu_d2:
610 return MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E);
611
612 case NVPTX::BI__nvvm_atom_cta_add_gen_i:
613 case NVPTX::BI__nvvm_atom_cta_add_gen_l:
614 case NVPTX::BI__nvvm_atom_cta_add_gen_ll:
615 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add, "block");
616 case NVPTX::BI__nvvm_atom_sys_add_gen_i:
617 case NVPTX::BI__nvvm_atom_sys_add_gen_l:
618 case NVPTX::BI__nvvm_atom_sys_add_gen_ll:
619 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Add, "");
620 case NVPTX::BI__nvvm_atom_cta_add_gen_f:
621 case NVPTX::BI__nvvm_atom_cta_add_gen_d:
622 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd, "block");
623 case NVPTX::BI__nvvm_atom_sys_add_gen_f:
624 case NVPTX::BI__nvvm_atom_sys_add_gen_d:
625 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::FAdd, "");
626 case NVPTX::BI__nvvm_atom_cta_xchg_gen_i:
627 case NVPTX::BI__nvvm_atom_cta_xchg_gen_l:
628 case NVPTX::BI__nvvm_atom_cta_xchg_gen_ll:
629 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg, "block");
630 case NVPTX::BI__nvvm_atom_sys_xchg_gen_i:
631 case NVPTX::BI__nvvm_atom_sys_xchg_gen_l:
632 case NVPTX::BI__nvvm_atom_sys_xchg_gen_ll:
633 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xchg, "");
634 case NVPTX::BI__nvvm_atom_cta_max_gen_i:
635 case NVPTX::BI__nvvm_atom_cta_max_gen_l:
636 case NVPTX::BI__nvvm_atom_cta_max_gen_ll:
637 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max, "block");
638 case NVPTX::BI__nvvm_atom_cta_max_gen_ui:
639 case NVPTX::BI__nvvm_atom_cta_max_gen_ul:
640 case NVPTX::BI__nvvm_atom_cta_max_gen_ull:
641 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax, "block");
642 case NVPTX::BI__nvvm_atom_sys_max_gen_i:
643 case NVPTX::BI__nvvm_atom_sys_max_gen_l:
644 case NVPTX::BI__nvvm_atom_sys_max_gen_ll:
645 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Max, "");
646 case NVPTX::BI__nvvm_atom_sys_max_gen_ui:
647 case NVPTX::BI__nvvm_atom_sys_max_gen_ul:
648 case NVPTX::BI__nvvm_atom_sys_max_gen_ull:
649 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMax, "");
650 case NVPTX::BI__nvvm_atom_cta_min_gen_i:
651 case NVPTX::BI__nvvm_atom_cta_min_gen_l:
652 case NVPTX::BI__nvvm_atom_cta_min_gen_ll:
653 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min, "block");
654 case NVPTX::BI__nvvm_atom_cta_min_gen_ui:
655 case NVPTX::BI__nvvm_atom_cta_min_gen_ul:
656 case NVPTX::BI__nvvm_atom_cta_min_gen_ull:
657 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin, "block");
658 case NVPTX::BI__nvvm_atom_sys_min_gen_i:
659 case NVPTX::BI__nvvm_atom_sys_min_gen_l:
660 case NVPTX::BI__nvvm_atom_sys_min_gen_ll:
661 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Min, "");
662 case NVPTX::BI__nvvm_atom_sys_min_gen_ui:
663 case NVPTX::BI__nvvm_atom_sys_min_gen_ul:
664 case NVPTX::BI__nvvm_atom_sys_min_gen_ull:
665 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UMin, "");
666 case NVPTX::BI__nvvm_atom_cta_inc_gen_ui:
667 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap,
668 "block");
669 case NVPTX::BI__nvvm_atom_cta_dec_gen_ui:
670 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap,
671 "block");
672 case NVPTX::BI__nvvm_atom_sys_inc_gen_ui:
673 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UIncWrap, "");
674 case NVPTX::BI__nvvm_atom_sys_dec_gen_ui:
675 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::UDecWrap, "");
676 case NVPTX::BI__nvvm_atom_cta_and_gen_i:
677 case NVPTX::BI__nvvm_atom_cta_and_gen_l:
678 case NVPTX::BI__nvvm_atom_cta_and_gen_ll:
679 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And, "block");
680 case NVPTX::BI__nvvm_atom_sys_and_gen_i:
681 case NVPTX::BI__nvvm_atom_sys_and_gen_l:
682 case NVPTX::BI__nvvm_atom_sys_and_gen_ll:
683 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::And, "");
684 case NVPTX::BI__nvvm_atom_cta_or_gen_i:
685 case NVPTX::BI__nvvm_atom_cta_or_gen_l:
686 case NVPTX::BI__nvvm_atom_cta_or_gen_ll:
687 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or, "block");
688 case NVPTX::BI__nvvm_atom_sys_or_gen_i:
689 case NVPTX::BI__nvvm_atom_sys_or_gen_l:
690 case NVPTX::BI__nvvm_atom_sys_or_gen_ll:
691 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Or, "");
692 case NVPTX::BI__nvvm_atom_cta_xor_gen_i:
693 case NVPTX::BI__nvvm_atom_cta_xor_gen_l:
694 case NVPTX::BI__nvvm_atom_cta_xor_gen_ll:
695 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor, "block");
696 case NVPTX::BI__nvvm_atom_sys_xor_gen_i:
697 case NVPTX::BI__nvvm_atom_sys_xor_gen_l:
698 case NVPTX::BI__nvvm_atom_sys_xor_gen_ll:
699 return MakeScopedAtomicRMW(*this, E, llvm::AtomicRMWInst::Xor, "");
700 case NVPTX::BI__nvvm_atom_cta_cas_gen_us:
701 case NVPTX::BI__nvvm_atom_cta_cas_gen_i:
702 case NVPTX::BI__nvvm_atom_cta_cas_gen_l:
703 case NVPTX::BI__nvvm_atom_cta_cas_gen_ll:
704 return MakeScopedAtomicCAS(*this, E, "block");
705 case NVPTX::BI__nvvm_atom_sys_cas_gen_us:
706 case NVPTX::BI__nvvm_atom_sys_cas_gen_i:
707 case NVPTX::BI__nvvm_atom_sys_cas_gen_l:
708 case NVPTX::BI__nvvm_atom_sys_cas_gen_ll:
709 return MakeScopedAtomicCAS(*this, E, "");
710 case NVPTX::BI__nvvm_match_all_sync_i32p:
711 case NVPTX::BI__nvvm_match_all_sync_i64p: {
712 Value *Mask = EmitScalarExpr(E->getArg(0));
713 Value *Val = EmitScalarExpr(E->getArg(1));
714 Address PredOutPtr = EmitPointerWithAlignment(E->getArg(2));
715 Value *ResultPair = Builder.CreateCall(
716 CGM.getIntrinsic(BuiltinID == NVPTX::BI__nvvm_match_all_sync_i32p
717 ? Intrinsic::nvvm_match_all_sync_i32p
718 : Intrinsic::nvvm_match_all_sync_i64p),
719 {Mask, Val});
720 Value *Pred = Builder.CreateZExt(Builder.CreateExtractValue(ResultPair, 1),
721 PredOutPtr.getElementType());
722 Builder.CreateStore(Pred, PredOutPtr);
723 return Builder.CreateExtractValue(ResultPair, 0);
724 }
725
726 // FP MMA loads
727 case NVPTX::BI__hmma_m16n16k16_ld_a:
728 case NVPTX::BI__hmma_m16n16k16_ld_b:
729 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
730 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
731 case NVPTX::BI__hmma_m32n8k16_ld_a:
732 case NVPTX::BI__hmma_m32n8k16_ld_b:
733 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
734 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
735 case NVPTX::BI__hmma_m8n32k16_ld_a:
736 case NVPTX::BI__hmma_m8n32k16_ld_b:
737 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
738 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
739 // Integer MMA loads.
740 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
741 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
742 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
743 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
744 case NVPTX::BI__imma_m16n16k16_ld_c:
745 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
746 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
747 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
748 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
749 case NVPTX::BI__imma_m32n8k16_ld_c:
750 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
751 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
752 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
753 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
754 case NVPTX::BI__imma_m8n32k16_ld_c:
755 // Sub-integer MMA loads.
756 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
757 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
758 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
759 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
760 case NVPTX::BI__imma_m8n8k32_ld_c:
761 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
762 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
763 case NVPTX::BI__bmma_m8n8k128_ld_c:
764 // Double MMA loads.
765 case NVPTX::BI__dmma_m8n8k4_ld_a:
766 case NVPTX::BI__dmma_m8n8k4_ld_b:
767 case NVPTX::BI__dmma_m8n8k4_ld_c:
768 // Alternate float MMA loads.
769 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
770 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
771 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
772 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
773 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
774 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
775 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
776 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
777 case NVPTX::BI__mma_tf32_m16n16k8_ld_c: {
778 Address Dst = EmitPointerWithAlignment(E->getArg(0));
779 Value *Src = EmitScalarExpr(E->getArg(1));
780 Value *Ldm = EmitScalarExpr(E->getArg(2));
781 std::optional<llvm::APSInt> isColMajorArg =
782 E->getArg(3)->getIntegerConstantExpr(getContext());
783 if (!isColMajorArg)
784 return nullptr;
785 bool isColMajor = isColMajorArg->getSExtValue();
786 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
787 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
788 if (IID == 0)
789 return nullptr;
790
791 Value *Result =
792 Builder.CreateCall(CGM.getIntrinsic(IID, Src->getType()), {Src, Ldm});
793
794 // Save returned values.
795 assert(II.NumResults);
796 if (II.NumResults == 1) {
797 Builder.CreateAlignedStore(Result, Dst.emitRawPointer(*this),
798 CharUnits::fromQuantity(4));
799 } else {
800 for (unsigned i = 0; i < II.NumResults; ++i) {
801 Builder.CreateAlignedStore(
802 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i),
803 Dst.getElementType()),
804 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
805 llvm::ConstantInt::get(IntTy, i)),
806 CharUnits::fromQuantity(4));
807 }
808 }
809 return Result;
810 }
811
812 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
813 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
814 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
815 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
816 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
817 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
818 case NVPTX::BI__imma_m16n16k16_st_c_i32:
819 case NVPTX::BI__imma_m32n8k16_st_c_i32:
820 case NVPTX::BI__imma_m8n32k16_st_c_i32:
821 case NVPTX::BI__imma_m8n8k32_st_c_i32:
822 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
823 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
824 case NVPTX::BI__mma_m16n16k8_st_c_f32: {
825 Value *Dst = EmitScalarExpr(E->getArg(0));
826 Address Src = EmitPointerWithAlignment(E->getArg(1));
827 Value *Ldm = EmitScalarExpr(E->getArg(2));
828 std::optional<llvm::APSInt> isColMajorArg =
829 E->getArg(3)->getIntegerConstantExpr(getContext());
830 if (!isColMajorArg)
831 return nullptr;
832 bool isColMajor = isColMajorArg->getSExtValue();
833 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
834 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
835 if (IID == 0)
836 return nullptr;
837 Function *Intrinsic =
838 CGM.getIntrinsic(IID, Dst->getType());
839 llvm::Type *ParamType = Intrinsic->getFunctionType()->getParamType(1);
840 SmallVector<Value *, 10> Values = {Dst};
841 for (unsigned i = 0; i < II.NumResults; ++i) {
842 Value *V = Builder.CreateAlignedLoad(
843 Src.getElementType(),
844 Builder.CreateGEP(Src.getElementType(), Src.emitRawPointer(*this),
845 llvm::ConstantInt::get(IntTy, i)),
846 CharUnits::fromQuantity(4));
847 Values.push_back(Builder.CreateBitCast(V, ParamType));
848 }
849 Values.push_back(Ldm);
850 Value *Result = Builder.CreateCall(Intrinsic, Values);
851 return Result;
852 }
853
854 // BI__hmma_m16n16k16_mma_<Dtype><CType>(d, a, b, c, layout, satf) -->
855 // Intrinsic::nvvm_wmma_m16n16k16_mma_sync<layout A,B><DType><CType><Satf>
856 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
857 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
858 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
859 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
860 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
861 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
862 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
863 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
864 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
865 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
866 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
867 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
868 case NVPTX::BI__imma_m16n16k16_mma_s8:
869 case NVPTX::BI__imma_m16n16k16_mma_u8:
870 case NVPTX::BI__imma_m32n8k16_mma_s8:
871 case NVPTX::BI__imma_m32n8k16_mma_u8:
872 case NVPTX::BI__imma_m8n32k16_mma_s8:
873 case NVPTX::BI__imma_m8n32k16_mma_u8:
874 case NVPTX::BI__imma_m8n8k32_mma_s4:
875 case NVPTX::BI__imma_m8n8k32_mma_u4:
876 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
877 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
878 case NVPTX::BI__dmma_m8n8k4_mma_f64:
879 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
880 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
881 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
882 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32: {
883 Address Dst = EmitPointerWithAlignment(E->getArg(0));
884 Address SrcA = EmitPointerWithAlignment(E->getArg(1));
885 Address SrcB = EmitPointerWithAlignment(E->getArg(2));
886 Address SrcC = EmitPointerWithAlignment(E->getArg(3));
887 std::optional<llvm::APSInt> LayoutArg =
888 E->getArg(4)->getIntegerConstantExpr(getContext());
889 if (!LayoutArg)
890 return nullptr;
891 int Layout = LayoutArg->getSExtValue();
892 if (Layout < 0 || Layout > 3)
893 return nullptr;
894 llvm::APSInt SatfArg;
895 if (BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1 ||
896 BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1)
897 SatfArg = 0; // .b1 does not have satf argument.
898 else if (std::optional<llvm::APSInt> OptSatfArg =
899 E->getArg(5)->getIntegerConstantExpr(getContext()))
900 SatfArg = *OptSatfArg;
901 else
902 return nullptr;
903 bool Satf = SatfArg.getSExtValue();
904 NVPTXMmaInfo MI = getNVPTXMmaInfo(BuiltinID);
905 unsigned IID = MI.getMMAIntrinsic(Layout, Satf);
906 if (IID == 0) // Unsupported combination of Layout/Satf.
907 return nullptr;
908
909 SmallVector<Value *, 24> Values;
910 Function *Intrinsic = CGM.getIntrinsic(IID);
911 llvm::Type *AType = Intrinsic->getFunctionType()->getParamType(0);
912 // Load A
913 for (unsigned i = 0; i < MI.NumEltsA; ++i) {
914 Value *V = Builder.CreateAlignedLoad(
915 SrcA.getElementType(),
916 Builder.CreateGEP(SrcA.getElementType(), SrcA.emitRawPointer(*this),
917 llvm::ConstantInt::get(IntTy, i)),
918 CharUnits::fromQuantity(4));
919 Values.push_back(Builder.CreateBitCast(V, AType));
920 }
921 // Load B
922 llvm::Type *BType = Intrinsic->getFunctionType()->getParamType(MI.NumEltsA);
923 for (unsigned i = 0; i < MI.NumEltsB; ++i) {
924 Value *V = Builder.CreateAlignedLoad(
925 SrcB.getElementType(),
926 Builder.CreateGEP(SrcB.getElementType(), SrcB.emitRawPointer(*this),
927 llvm::ConstantInt::get(IntTy, i)),
928 CharUnits::fromQuantity(4));
929 Values.push_back(Builder.CreateBitCast(V, BType));
930 }
931 // Load C
932 llvm::Type *CType =
933 Intrinsic->getFunctionType()->getParamType(MI.NumEltsA + MI.NumEltsB);
934 for (unsigned i = 0; i < MI.NumEltsC; ++i) {
935 Value *V = Builder.CreateAlignedLoad(
936 SrcC.getElementType(),
937 Builder.CreateGEP(SrcC.getElementType(), SrcC.emitRawPointer(*this),
938 llvm::ConstantInt::get(IntTy, i)),
939 CharUnits::fromQuantity(4));
940 Values.push_back(Builder.CreateBitCast(V, CType));
941 }
942 Value *Result = Builder.CreateCall(Intrinsic, Values);
943 llvm::Type *DType = Dst.getElementType();
944 for (unsigned i = 0; i < MI.NumEltsD; ++i)
945 Builder.CreateAlignedStore(
946 Builder.CreateBitCast(Builder.CreateExtractValue(Result, i), DType),
947 Builder.CreateGEP(Dst.getElementType(), Dst.emitRawPointer(*this),
948 llvm::ConstantInt::get(IntTy, i)),
949 CharUnits::fromQuantity(4));
950 return Result;
951 }
952 // The following builtins require half type support
953 case NVPTX::BI__nvvm_ex2_approx_f16:
954 return MakeHalfType(
955 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx, Builder.getHalfTy()),
956 BuiltinID, E, *this);
957 case NVPTX::BI__nvvm_ex2_approx_f16x2:
958 return MakeHalfType(
959 CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx,
960 FixedVectorType::get(Builder.getHalfTy(), 2)),
961 BuiltinID, E, *this);
962 case NVPTX::BI__nvvm_ff2f16x2_rn:
963 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, *this);
964 case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
965 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn_relu, BuiltinID, E, *this);
966 case NVPTX::BI__nvvm_ff2f16x2_rz:
967 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz, BuiltinID, E, *this);
968 case NVPTX::BI__nvvm_ff2f16x2_rz_relu:
969 return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rz_relu, BuiltinID, E, *this);
970 case NVPTX::BI__nvvm_fma_rn_f16:
971 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16, BuiltinID, E, *this);
972 case NVPTX::BI__nvvm_fma_rn_f16x2:
973 return MakeHalfType(Intrinsic::nvvm_fma_rn_f16x2, BuiltinID, E, *this);
974 case NVPTX::BI__nvvm_fma_rn_ftz_f16:
975 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16, BuiltinID, E, *this);
976 case NVPTX::BI__nvvm_fma_rn_ftz_f16x2:
977 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_f16x2, BuiltinID, E, *this);
978 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16:
979 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16, BuiltinID, E,
980 *this);
981 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16x2:
982 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_relu_f16x2, BuiltinID, E,
983 *this);
984 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16:
985 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16, BuiltinID, E,
986 *this);
987 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16x2:
988 return MakeHalfType(Intrinsic::nvvm_fma_rn_ftz_sat_f16x2, BuiltinID, E,
989 *this);
990 case NVPTX::BI__nvvm_fma_rn_relu_f16:
991 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16, BuiltinID, E, *this);
992 case NVPTX::BI__nvvm_fma_rn_relu_f16x2:
993 return MakeHalfType(Intrinsic::nvvm_fma_rn_relu_f16x2, BuiltinID, E, *this);
994 case NVPTX::BI__nvvm_fma_rn_sat_f16:
995 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16, BuiltinID, E, *this);
996 case NVPTX::BI__nvvm_fma_rn_sat_f16x2:
997 return MakeHalfType(Intrinsic::nvvm_fma_rn_sat_f16x2, BuiltinID, E, *this);
998 case NVPTX::BI__nvvm_fma_rn_oob_f16:
999 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getHalfTy(), E,
1000 *this);
1001 case NVPTX::BI__nvvm_fma_rn_oob_f16x2:
1002 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1003 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1004 *this);
1005 case NVPTX::BI__nvvm_fma_rn_oob_bf16:
1006 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob, Builder.getBFloatTy(), E,
1007 *this);
1008 case NVPTX::BI__nvvm_fma_rn_oob_bf16x2:
1009 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob,
1010 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1011 *this);
1012 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16:
1013 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getHalfTy(), E,
1014 *this);
1015 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16x2:
1016 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1017 llvm::FixedVectorType::get(Builder.getHalfTy(), 2), E,
1018 *this);
1019 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16:
1020 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu, Builder.getBFloatTy(), E,
1021 *this);
1022 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16x2:
1023 return MakeFMAOOB(Intrinsic::nvvm_fma_rn_oob_relu,
1024 llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
1025 *this);
1026 case NVPTX::BI__nvvm_fmax_f16:
1027 return MakeHalfType(Intrinsic::nvvm_fmax_f16, BuiltinID, E, *this);
1028 case NVPTX::BI__nvvm_fmax_f16x2:
1029 return MakeHalfType(Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, *this);
1030 case NVPTX::BI__nvvm_fmax_ftz_f16:
1031 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, *this);
1032 case NVPTX::BI__nvvm_fmax_ftz_f16x2:
1033 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, *this);
1034 case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
1035 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, *this);
1036 case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
1037 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
1038 *this);
1039 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
1040 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
1041 E, *this);
1042 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
1043 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
1044 BuiltinID, E, *this);
1045 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
1046 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
1047 *this);
1048 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
1049 return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
1050 E, *this);
1051 case NVPTX::BI__nvvm_fmax_nan_f16:
1052 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, *this);
1053 case NVPTX::BI__nvvm_fmax_nan_f16x2:
1054 return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, *this);
1055 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
1056 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
1057 *this);
1058 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
1059 return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
1060 E, *this);
1061 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
1062 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
1063 *this);
1064 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
1065 return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
1066 *this);
1067 case NVPTX::BI__nvvm_fmin_f16:
1068 return MakeHalfType(Intrinsic::nvvm_fmin_f16, BuiltinID, E, *this);
1069 case NVPTX::BI__nvvm_fmin_f16x2:
1070 return MakeHalfType(Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, *this);
1071 case NVPTX::BI__nvvm_fmin_ftz_f16:
1072 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, *this);
1073 case NVPTX::BI__nvvm_fmin_ftz_f16x2:
1074 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, *this);
1075 case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
1076 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, *this);
1077 case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
1078 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
1079 *this);
1080 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
1081 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
1082 E, *this);
1083 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
1084 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
1085 BuiltinID, E, *this);
1086 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
1087 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
1088 *this);
1089 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
1090 return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
1091 E, *this);
1092 case NVPTX::BI__nvvm_fmin_nan_f16:
1093 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, *this);
1094 case NVPTX::BI__nvvm_fmin_nan_f16x2:
1095 return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, *this);
1096 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
1097 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
1098 *this);
1099 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
1100 return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
1101 E, *this);
1102 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
1103 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
1104 *this);
1105 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
1106 return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
1107 *this);
1108 case NVPTX::BI__nvvm_fabs_f:
1109 case NVPTX::BI__nvvm_abs_bf16:
1110 case NVPTX::BI__nvvm_abs_bf16x2:
1111 case NVPTX::BI__nvvm_fabs_f16:
1112 case NVPTX::BI__nvvm_fabs_f16x2:
1113 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs,
1114 EmitScalarExpr(E->getArg(0)));
1115 case NVPTX::BI__nvvm_fabs_ftz_f:
1116 case NVPTX::BI__nvvm_fabs_ftz_f16:
1117 case NVPTX::BI__nvvm_fabs_ftz_f16x2:
1118 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_fabs_ftz,
1119 EmitScalarExpr(E->getArg(0)));
1120 case NVPTX::BI__nvvm_fabs_d:
1121 return Builder.CreateFAbs(EmitScalarExpr(E->getArg(0)));
1122 case NVPTX::BI__nvvm_ex2_approx_d:
1123 case NVPTX::BI__nvvm_ex2_approx_f:
1124 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx,
1125 EmitScalarExpr(E->getArg(0)));
1126 case NVPTX::BI__nvvm_ex2_approx_ftz_f:
1127 return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx_ftz,
1128 EmitScalarExpr(E->getArg(0)));
1129 case NVPTX::BI__nvvm_ldg_h:
1130 case NVPTX::BI__nvvm_ldg_h2:
1131 return EnsureNativeHalfSupport(BuiltinID, E, *this) ? MakeLdg(*this, E)
1132 : nullptr;
1133 case NVPTX::BI__nvvm_ldu_h:
1134 case NVPTX::BI__nvvm_ldu_h2:
1135 return EnsureNativeHalfSupport(BuiltinID, E, *this)
1136 ? MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E)
1137 : nullptr;
1138 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
1139 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_4,
1140 Intrinsic::nvvm_cp_async_ca_shared_global_4_s, *this, E,
1141 4);
1142 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8:
1143 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_8,
1144 Intrinsic::nvvm_cp_async_ca_shared_global_8_s, *this, E,
1145 8);
1146 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
1147 return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_16,
1148 Intrinsic::nvvm_cp_async_ca_shared_global_16_s, *this, E,
1149 16);
1150 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
1151 return MakeCpAsync(Intrinsic::nvvm_cp_async_cg_shared_global_16,
1152 Intrinsic::nvvm_cp_async_cg_shared_global_16_s, *this, E,
1153 16);
1154 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_x:
1155 return Builder.CreateCall(
1156 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_x));
1157 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_y:
1158 return Builder.CreateCall(
1159 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_y));
1160 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_z:
1161 return Builder.CreateCall(
1162 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_z));
1163 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_w:
1164 return Builder.CreateCall(
1165 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_clusterid_w));
1166 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_x:
1167 return Builder.CreateCall(
1168 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_x));
1169 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_y:
1170 return Builder.CreateCall(
1171 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_y));
1172 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_z:
1173 return Builder.CreateCall(
1174 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_z));
1175 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_w:
1176 return Builder.CreateCall(
1177 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_nclusterid_w));
1178 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_x:
1179 return Builder.CreateCall(
1180 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_x));
1181 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_y:
1182 return Builder.CreateCall(
1183 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_y));
1184 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_z:
1185 return Builder.CreateCall(
1186 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_z));
1187 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_w:
1188 return Builder.CreateCall(
1189 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_w));
1190 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_x:
1191 return Builder.CreateCall(
1192 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_x));
1193 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_y:
1194 return Builder.CreateCall(
1195 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_y));
1196 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_z:
1197 return Builder.CreateCall(
1198 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_z));
1199 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_w:
1200 return Builder.CreateCall(
1201 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_w));
1202 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctarank:
1203 return Builder.CreateCall(
1204 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_ctarank));
1205 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctarank:
1206 return Builder.CreateCall(
1207 CGM.getIntrinsic(Intrinsic::nvvm_read_ptx_sreg_cluster_nctarank));
1208 case NVPTX::BI__nvvm_is_explicit_cluster:
1209 return Builder.CreateCall(
1210 CGM.getIntrinsic(Intrinsic::nvvm_is_explicit_cluster));
1211 case NVPTX::BI__nvvm_isspacep_shared_cluster:
1212 return Builder.CreateCall(
1213 CGM.getIntrinsic(Intrinsic::nvvm_isspacep_shared_cluster),
1214 EmitScalarExpr(E->getArg(0)));
1215 case NVPTX::BI__nvvm_mapa:
1216 return Builder.CreateCall(
1217 CGM.getIntrinsic(Intrinsic::nvvm_mapa),
1218 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1219 case NVPTX::BI__nvvm_mapa_shared_cluster:
1220 return Builder.CreateCall(
1221 CGM.getIntrinsic(Intrinsic::nvvm_mapa_shared_cluster),
1222 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1223 case NVPTX::BI__nvvm_getctarank:
1224 return Builder.CreateCall(
1225 CGM.getIntrinsic(Intrinsic::nvvm_getctarank),
1226 EmitScalarExpr(E->getArg(0)));
1227 case NVPTX::BI__nvvm_getctarank_shared_cluster:
1228 return Builder.CreateCall(
1229 CGM.getIntrinsic(Intrinsic::nvvm_getctarank_shared_cluster),
1230 EmitScalarExpr(E->getArg(0)));
1231 case NVPTX::BI__nvvm_barrier_cluster_arrive:
1232 return Builder.CreateCall(
1233 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive));
1234 case NVPTX::BI__nvvm_barrier_cluster_arrive_relaxed:
1235 return Builder.CreateCall(
1236 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_arrive_relaxed));
1237 case NVPTX::BI__nvvm_barrier_cluster_wait:
1238 return Builder.CreateCall(
1239 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cluster_wait));
1240 case NVPTX::BI__nvvm_fence_sc_cluster:
1241 return Builder.CreateCall(
1242 CGM.getIntrinsic(Intrinsic::nvvm_fence_sc_cluster));
1243 case NVPTX::BI__nvvm_bar_sync:
1244 return Builder.CreateCall(
1245 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1246 EmitScalarExpr(E->getArg(0)));
1247 case NVPTX::BI__syncthreads:
1248 return Builder.CreateCall(
1249 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1250 Builder.getInt32(0));
1251 case NVPTX::BI__nvvm_barrier_sync:
1252 return Builder.CreateCall(
1253 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_all),
1254 EmitScalarExpr(E->getArg(0)));
1255 case NVPTX::BI__nvvm_barrier_sync_cnt:
1256 return Builder.CreateCall(
1257 CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_count),
1258 {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1259 case NVPTX::BI__nvvm_bar0_and:
1260 return Builder.CreateZExt(
1261 Builder.CreateIntrinsic(
1262 Intrinsic::nvvm_barrier_cta_red_and_aligned_all, {},
1263 {Builder.getInt32(0),
1264 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1265 Builder.getInt32(0))}),
1266 Builder.getInt32Ty());
1267 case NVPTX::BI__nvvm_bar0_or:
1268 return Builder.CreateZExt(
1269 Builder.CreateIntrinsic(
1270 Intrinsic::nvvm_barrier_cta_red_or_aligned_all, {},
1271 {Builder.getInt32(0),
1272 Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1273 Builder.getInt32(0))}),
1274 Builder.getInt32Ty());
1275 case NVPTX::BI__nvvm_bar0_popc:
1276 return Builder.CreateIntrinsic(
1277 Intrinsic::nvvm_barrier_cta_red_popc_aligned_all, {},
1278 {Builder.getInt32(0), Builder.CreateICmpNE(EmitScalarExpr(E->getArg(0)),
1279 Builder.getInt32(0))});
1280 default:
1281 return nullptr;
1282 }
1283}
V
#define V(N, I)
Definition ASTContext.h:3728
MakeAtomicCmpXchgValue
Value * MakeAtomicCmpXchgValue(CodeGenFunction &CGF, const CallExpr *E, bool ReturnBool, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering)
Utility to insert an atomic cmpxchg instruction.
Definition CGBuiltin.cpp:397
MakeBinaryAtomicValue
Value * MakeBinaryAtomicValue(CodeGenFunction &CGF, llvm::AtomicRMWInst::BinOp Kind, const CallExpr *E, AtomicOrdering Ordering)
Utility to insert an atomic instruction based on Intrinsic::ID and the expression node.
Definition CGBuiltin.cpp:297
MMA_VARIANTS_B1_AND
#define MMA_VARIANTS_B1_AND(geom, type)
MMA_INTR
#define MMA_INTR(geom_op_type, layout)
Definition NVPTX.cpp:30
MMA_VARIANTS
#define MMA_VARIANTS(geom, type)
MMA_SATF_VARIANTS
#define MMA_SATF_VARIANTS(geom, type)
MMA_LDST
#define MMA_LDST(n, geom_op_type)
Definition NVPTX.cpp:32
MMA_VARIANTS_B1_XOR
#define MMA_VARIANTS_B1_XOR(geom, type)
MMA_VARIANTS_I4
#define MMA_VARIANTS_I4(geom, type)
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
ASTContext::GE_None
@ GE_None
No error.
Definition ASTContext.h:2631
clang::ASTContext::GetBuiltinType
QualType GetBuiltinType(unsigned ID, GetBuiltinTypeError &Error, unsigned *IntegerConstantArgs=nullptr) const
Return the type for the specified builtin.
Definition ASTContext.cpp:12956
clang::CallExpr
CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).
Definition Expr.h:2946
clang::CallExpr::getArg
Expr * getArg(unsigned Arg)
getArg - Return the specified argument.
Definition Expr.h:3150
clang::CallExpr::getNumArgs
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this call.
Definition Expr.h:3137
clang::CharUnits
CharUnits - This is an opaque type for sizes expressed in character units.
Definition CharUnits.h:38
clang::CharUnits::getAsAlign
llvm::Align getAsAlign() const
getAsAlign - Returns Quantity as a valid llvm::Align, Beware llvm::Align assumes power of two 8-bit b...
Definition CharUnits.h:189
clang::CharUnits::fromQuantity
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition CharUnits.h:63
clang::CodeGen::Address
Like RawAddress, an abstract representation of an aligned address, but the pointer contained in this ...
Definition Address.h:128
clang::CodeGen::Address::emitRawPointer
llvm::Value * emitRawPointer(CodeGenFunction &CGF) const
Return the pointer contained in this class after authenticating it and adding offset to it if necessa...
Definition Address.h:253
clang::CodeGen::Address::getElementType
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition Address.h:209
clang::CodeGen::CGBuilderTy::CreateAtomicRMW
llvm::AtomicRMWInst * CreateAtomicRMW(llvm::AtomicRMWInst::BinOp Op, Address Addr, llvm::Value *Val, llvm::AtomicOrdering Ordering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:190
clang::CodeGen::CGBuilderTy::CreateAtomicCmpXchg
llvm::AtomicCmpXchgInst * CreateAtomicCmpXchg(Address Addr, llvm::Value *Cmp, llvm::Value *New, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering, llvm::SyncScope::ID SSID=llvm::SyncScope::System)
Definition CGBuilder.h:179
clang::CodeGen::CGBuilderTy::CreateAlignedLoad
llvm::LoadInst * CreateAlignedLoad(llvm::Type *Ty, llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition CGBuilder.h:138
clang::CodeGen::CGBuilderTy::CreateAddrSpaceCast
Address CreateAddrSpaceCast(Address Addr, llvm::Type *Ty, llvm::Type *ElementTy, const llvm::Twine &Name="")
Definition CGBuilder.h:199
clang::CodeGen::CodeGenFunction
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
Definition CodeGenFunction.h:258
clang::CodeGen::CodeGenFunction::ConvertTypeForMem
llvm::Type * ConvertTypeForMem(QualType T)
Definition CodeGenFunction.cpp:233
clang::CodeGen::CodeGenFunction::EmitPointerWithAlignment
Address EmitPointerWithAlignment(const Expr *Addr, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr, KnownNonNull_t IsKnownNonNull=NotKnownNonNull)
EmitPointerWithAlignment - Given an expression with a pointer type, emit the value and compute our be...
Definition CGExpr.cpp:1598
clang::CodeGen::CodeGenFunction::EmitScalarExpr
llvm::Value * EmitScalarExpr(const Expr *E, bool IgnoreResultAssign=false)
EmitScalarExpr - Emit the computation of the specified expression of LLVM scalar type,...
Definition CGExprScalar.cpp:6166
clang::CodeGen::CodeGenFunction::EmitNVPTXBuiltinExpr
llvm::Value * EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E)
Definition NVPTX.cpp:446
clang::CodeGen::CodeGenFunction::getLLVMContext
llvm::LLVMContext & getLLVMContext()
Definition CodeGenFunction.h:2235
clang::CodeGen::CodeGenModule::Error
void Error(SourceLocation loc, StringRef error)
Emit a general error that something can't be done.
Definition CodeGenModule.cpp:1949
clang::CodeGen::CodeGenModule::getContext
ASTContext & getContext() const
Definition CodeGenModule.h:886
clang::CodeGen::CodeGenModule::getNaturalPointeeTypeAlignment
CharUnits getNaturalPointeeTypeAlignment(QualType T, LValueBaseInfo *BaseInfo=nullptr, TBAAAccessInfo *TBAAInfo=nullptr)
Definition CodeGenModule.cpp:8566
clang::CodeGen::CodeGenModule::getIntrinsic
llvm::Function * getIntrinsic(unsigned IID, ArrayRef< llvm::Type * > Tys={})
Definition CodeGenModule.cpp:7095
clang::Expr::getIntegerConstantExpr
std::optional< llvm::APSInt > getIntegerConstantExpr(const ASTContext &Ctx) const
isIntegerConstantExpr - Return the value if this expression is a valid integer constant expression.
Definition ExprConstant.cpp:22215
clang::Expr::getExprLoc
SourceLocation getExprLoc() const LLVM_READONLY
getExprLoc - Return the preferred location for the arrow when diagnosing a problem with a generic exp...
Definition Expr.cpp:282
clang::Expr::getType
QualType getType() const
Definition Expr.h:144
clang::QualType
A (possibly-)qualified type.
Definition TypeBase.h:937
clang::Scope
Scope - A scope is a transient data structure that is used while parsing the program.
Definition Scope.h:41
clang::Value::getType
QualType getType() const
Definition Value.cpp:237
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::OpenACCClauseKind::DType
@ DType
'dtype' clause, an alias for 'device_type', stored separately for diagnostic purposes.
Definition OpenACCKinds.h:274
clang::ObjCSubstitutionContext::Result
@ Result
The result type of a method or function.
Definition TypeBase.h:905
llvm
Diagnostic wrappers for TextAPI types for error reporting.
Definition Dominators.h:30
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