clang  16.0.0git
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/X86TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65  "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabled(Features, "sse2", true);
112 
113  using namespace llvm::X86;
114 
115  SmallVector<StringRef, 16> CPUFeatures;
116  getFeaturesForCPU(CPU, CPUFeatures);
117  for (auto &F : CPUFeatures)
118  setFeatureEnabled(Features, F, true);
119 
120  std::vector<std::string> UpdatedFeaturesVec;
121  for (const auto &Feature : FeaturesVec) {
122  // Expand general-regs-only to -x86, -mmx and -sse
123  if (Feature == "+general-regs-only") {
124  UpdatedFeaturesVec.push_back("-x87");
125  UpdatedFeaturesVec.push_back("-mmx");
126  UpdatedFeaturesVec.push_back("-sse");
127  continue;
128  }
129 
130  UpdatedFeaturesVec.push_back(Feature);
131  }
132 
133  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134  return false;
135 
136  // Can't do this earlier because we need to be able to explicitly enable
137  // or disable these features and the things that they depend upon.
138 
139  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140  auto I = Features.find("sse4.2");
141  if (I != Features.end() && I->getValue() &&
142  !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
143  Features["popcnt"] = true;
144 
145  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146  // then enable MMX.
147  I = Features.find("sse");
148  if (I != Features.end() && I->getValue() &&
149  !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
150  Features["mmx"] = true;
151 
152  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153  I = Features.find("avx");
154  if (I != Features.end() && I->getValue() &&
155  !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
156  Features["xsave"] = true;
157 
158  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
159  I = Features.find("sse4.2");
160  if (I != Features.end() && I->getValue() &&
161  !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
162  Features["crc32"] = true;
163 
164  return true;
165 }
166 
167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
168  StringRef Name, bool Enabled) const {
169  if (Name == "sse4") {
170  // We can get here via the __target__ attribute since that's not controlled
171  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
172  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
173  // disabled.
174  if (Enabled)
175  Name = "sse4.2";
176  else
177  Name = "sse4.1";
178  }
179 
180  Features[Name] = Enabled;
181  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
182 }
183 
184 /// handleTargetFeatures - Perform initialization based on the user
185 /// configured set of features.
186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
187  DiagnosticsEngine &Diags) {
188  for (const auto &Feature : Features) {
189  if (Feature[0] != '+')
190  continue;
191 
192  if (Feature == "+aes") {
193  HasAES = true;
194  } else if (Feature == "+vaes") {
195  HasVAES = true;
196  } else if (Feature == "+pclmul") {
197  HasPCLMUL = true;
198  } else if (Feature == "+vpclmulqdq") {
199  HasVPCLMULQDQ = true;
200  } else if (Feature == "+lzcnt") {
201  HasLZCNT = true;
202  } else if (Feature == "+rdrnd") {
203  HasRDRND = true;
204  } else if (Feature == "+fsgsbase") {
205  HasFSGSBASE = true;
206  } else if (Feature == "+bmi") {
207  HasBMI = true;
208  } else if (Feature == "+bmi2") {
209  HasBMI2 = true;
210  } else if (Feature == "+popcnt") {
211  HasPOPCNT = true;
212  } else if (Feature == "+rtm") {
213  HasRTM = true;
214  } else if (Feature == "+prfchw") {
215  HasPRFCHW = true;
216  } else if (Feature == "+rdseed") {
217  HasRDSEED = true;
218  } else if (Feature == "+adx") {
219  HasADX = true;
220  } else if (Feature == "+tbm") {
221  HasTBM = true;
222  } else if (Feature == "+lwp") {
223  HasLWP = true;
224  } else if (Feature == "+fma") {
225  HasFMA = true;
226  } else if (Feature == "+f16c") {
227  HasF16C = true;
228  } else if (Feature == "+gfni") {
229  HasGFNI = true;
230  } else if (Feature == "+avx512cd") {
231  HasAVX512CD = true;
232  } else if (Feature == "+avx512vpopcntdq") {
233  HasAVX512VPOPCNTDQ = true;
234  } else if (Feature == "+avx512vnni") {
235  HasAVX512VNNI = true;
236  } else if (Feature == "+avx512bf16") {
237  HasAVX512BF16 = true;
238  } else if (Feature == "+avx512er") {
239  HasAVX512ER = true;
240  } else if (Feature == "+avx512fp16") {
241  HasAVX512FP16 = true;
242  HasLegalHalfType = true;
243  } else if (Feature == "+avx512pf") {
244  HasAVX512PF = true;
245  } else if (Feature == "+avx512dq") {
246  HasAVX512DQ = true;
247  } else if (Feature == "+avx512bitalg") {
248  HasAVX512BITALG = true;
249  } else if (Feature == "+avx512bw") {
250  HasAVX512BW = true;
251  } else if (Feature == "+avx512vl") {
252  HasAVX512VL = true;
253  } else if (Feature == "+avx512vbmi") {
254  HasAVX512VBMI = true;
255  } else if (Feature == "+avx512vbmi2") {
256  HasAVX512VBMI2 = true;
257  } else if (Feature == "+avx512ifma") {
258  HasAVX512IFMA = true;
259  } else if (Feature == "+avx512vp2intersect") {
260  HasAVX512VP2INTERSECT = true;
261  } else if (Feature == "+sha") {
262  HasSHA = true;
263  } else if (Feature == "+shstk") {
264  HasSHSTK = true;
265  } else if (Feature == "+movbe") {
266  HasMOVBE = true;
267  } else if (Feature == "+sgx") {
268  HasSGX = true;
269  } else if (Feature == "+cx8") {
270  HasCX8 = true;
271  } else if (Feature == "+cx16") {
272  HasCX16 = true;
273  } else if (Feature == "+fxsr") {
274  HasFXSR = true;
275  } else if (Feature == "+xsave") {
276  HasXSAVE = true;
277  } else if (Feature == "+xsaveopt") {
278  HasXSAVEOPT = true;
279  } else if (Feature == "+xsavec") {
280  HasXSAVEC = true;
281  } else if (Feature == "+xsaves") {
282  HasXSAVES = true;
283  } else if (Feature == "+mwaitx") {
284  HasMWAITX = true;
285  } else if (Feature == "+pku") {
286  HasPKU = true;
287  } else if (Feature == "+clflushopt") {
288  HasCLFLUSHOPT = true;
289  } else if (Feature == "+clwb") {
290  HasCLWB = true;
291  } else if (Feature == "+wbnoinvd") {
292  HasWBNOINVD = true;
293  } else if (Feature == "+prefetchi") {
294  HasPREFETCHI = true;
295  } else if (Feature == "+prefetchwt1") {
296  HasPREFETCHWT1 = true;
297  } else if (Feature == "+clzero") {
298  HasCLZERO = true;
299  } else if (Feature == "+cldemote") {
300  HasCLDEMOTE = true;
301  } else if (Feature == "+rdpid") {
302  HasRDPID = true;
303  } else if (Feature == "+rdpru") {
304  HasRDPRU = true;
305  } else if (Feature == "+kl") {
306  HasKL = true;
307  } else if (Feature == "+widekl") {
308  HasWIDEKL = true;
309  } else if (Feature == "+retpoline-external-thunk") {
310  HasRetpolineExternalThunk = true;
311  } else if (Feature == "+sahf") {
312  HasLAHFSAHF = true;
313  } else if (Feature == "+waitpkg") {
314  HasWAITPKG = true;
315  } else if (Feature == "+movdiri") {
316  HasMOVDIRI = true;
317  } else if (Feature == "+movdir64b") {
318  HasMOVDIR64B = true;
319  } else if (Feature == "+pconfig") {
320  HasPCONFIG = true;
321  } else if (Feature == "+ptwrite") {
322  HasPTWRITE = true;
323  } else if (Feature == "+invpcid") {
324  HasINVPCID = true;
325  } else if (Feature == "+enqcmd") {
326  HasENQCMD = true;
327  } else if (Feature == "+hreset") {
328  HasHRESET = true;
329  } else if (Feature == "+amx-bf16") {
330  HasAMXBF16 = true;
331  } else if (Feature == "+amx-fp16") {
332  HasAMXFP16 = true;
333  } else if (Feature == "+amx-int8") {
334  HasAMXINT8 = true;
335  } else if (Feature == "+amx-tile") {
336  HasAMXTILE = true;
337  } else if (Feature == "+cmpccxadd") {
338  HasCMPCCXADD = true;
339  } else if (Feature == "+raoint") {
340  HasRAOINT = true;
341  } else if (Feature == "+avxifma") {
342  HasAVXIFMA = true;
343  } else if (Feature == "+avxneconvert") {
344  HasAVXNECONVERT= true;
345  } else if (Feature == "+avxvnni") {
346  HasAVXVNNI = true;
347  } else if (Feature == "+avxvnniint8") {
348  HasAVXVNNIINT8 = true;
349  } else if (Feature == "+serialize") {
350  HasSERIALIZE = true;
351  } else if (Feature == "+tsxldtrk") {
352  HasTSXLDTRK = true;
353  } else if (Feature == "+uintr") {
354  HasUINTR = true;
355  } else if (Feature == "+crc32") {
356  HasCRC32 = true;
357  } else if (Feature == "+x87") {
358  HasX87 = true;
359  }
360 
361  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
362  .Case("+avx512f", AVX512F)
363  .Case("+avx2", AVX2)
364  .Case("+avx", AVX)
365  .Case("+sse4.2", SSE42)
366  .Case("+sse4.1", SSE41)
367  .Case("+ssse3", SSSE3)
368  .Case("+sse3", SSE3)
369  .Case("+sse2", SSE2)
370  .Case("+sse", SSE1)
371  .Default(NoSSE);
372  SSELevel = std::max(SSELevel, Level);
373 
374  HasFloat16 = SSELevel >= SSE2;
375 
376  HasBFloat16 = SSELevel >= SSE2;
377 
378  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
379  .Case("+3dnowa", AMD3DNowAthlon)
380  .Case("+3dnow", AMD3DNow)
381  .Case("+mmx", MMX)
382  .Default(NoMMX3DNow);
383  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
384 
385  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
386  .Case("+xop", XOP)
387  .Case("+fma4", FMA4)
388  .Case("+sse4a", SSE4A)
389  .Default(NoXOP);
390  XOPLevel = std::max(XOPLevel, XLevel);
391  }
392 
393  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
394  // matches the selected sse level.
395  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
396  (FPMath == FP_387 && SSELevel >= SSE1)) {
397  Diags.Report(diag::err_target_unsupported_fpmath)
398  << (FPMath == FP_SSE ? "sse" : "387");
399  return false;
400  }
401 
403  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
404 
405  // FIXME: We should allow long double type on 32-bits to match with GCC.
406  // This requires backend to be able to lower f80 without x87 first.
407  if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
408  HasLongDouble = false;
409 
410  return true;
411 }
412 
413 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
414 /// definitions for this particular subtarget.
416  MacroBuilder &Builder) const {
417  // Inline assembly supports X86 flag outputs.
418  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
419 
420  std::string CodeModel = getTargetOpts().CodeModel;
421  if (CodeModel == "default")
422  CodeModel = "small";
423  Builder.defineMacro("__code_model_" + CodeModel + "__");
424 
425  // Target identification.
426  if (getTriple().getArch() == llvm::Triple::x86_64) {
427  Builder.defineMacro("__amd64__");
428  Builder.defineMacro("__amd64");
429  Builder.defineMacro("__x86_64");
430  Builder.defineMacro("__x86_64__");
431  if (getTriple().getArchName() == "x86_64h") {
432  Builder.defineMacro("__x86_64h");
433  Builder.defineMacro("__x86_64h__");
434  }
435  } else {
436  DefineStd(Builder, "i386", Opts);
437  }
438 
439  Builder.defineMacro("__SEG_GS");
440  Builder.defineMacro("__SEG_FS");
441  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
442  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
443 
444  // Subtarget options.
445  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
446  // truly should be based on -mtune options.
447  using namespace llvm::X86;
448  switch (CPU) {
449  case CK_None:
450  break;
451  case CK_i386:
452  // The rest are coming from the i386 define above.
453  Builder.defineMacro("__tune_i386__");
454  break;
455  case CK_i486:
456  case CK_WinChipC6:
457  case CK_WinChip2:
458  case CK_C3:
459  defineCPUMacros(Builder, "i486");
460  break;
461  case CK_PentiumMMX:
462  Builder.defineMacro("__pentium_mmx__");
463  Builder.defineMacro("__tune_pentium_mmx__");
464  [[fallthrough]];
465  case CK_i586:
466  case CK_Pentium:
467  defineCPUMacros(Builder, "i586");
468  defineCPUMacros(Builder, "pentium");
469  break;
470  case CK_Pentium3:
471  case CK_PentiumM:
472  Builder.defineMacro("__tune_pentium3__");
473  [[fallthrough]];
474  case CK_Pentium2:
475  case CK_C3_2:
476  Builder.defineMacro("__tune_pentium2__");
477  [[fallthrough]];
478  case CK_PentiumPro:
479  case CK_i686:
480  defineCPUMacros(Builder, "i686");
481  defineCPUMacros(Builder, "pentiumpro");
482  break;
483  case CK_Pentium4:
484  defineCPUMacros(Builder, "pentium4");
485  break;
486  case CK_Yonah:
487  case CK_Prescott:
488  case CK_Nocona:
489  defineCPUMacros(Builder, "nocona");
490  break;
491  case CK_Core2:
492  case CK_Penryn:
493  defineCPUMacros(Builder, "core2");
494  break;
495  case CK_Bonnell:
496  defineCPUMacros(Builder, "atom");
497  break;
498  case CK_Silvermont:
499  defineCPUMacros(Builder, "slm");
500  break;
501  case CK_Goldmont:
502  defineCPUMacros(Builder, "goldmont");
503  break;
504  case CK_GoldmontPlus:
505  defineCPUMacros(Builder, "goldmont_plus");
506  break;
507  case CK_Tremont:
508  defineCPUMacros(Builder, "tremont");
509  break;
510  case CK_Nehalem:
511  case CK_Westmere:
512  case CK_SandyBridge:
513  case CK_IvyBridge:
514  case CK_Haswell:
515  case CK_Broadwell:
516  case CK_SkylakeClient:
517  case CK_SkylakeServer:
518  case CK_Cascadelake:
519  case CK_Cooperlake:
520  case CK_Cannonlake:
521  case CK_IcelakeClient:
522  case CK_Rocketlake:
523  case CK_IcelakeServer:
524  case CK_Tigerlake:
525  case CK_SapphireRapids:
526  case CK_Alderlake:
527  case CK_Raptorlake:
528  case CK_Meteorlake:
529  case CK_Sierraforest:
530  case CK_Grandridge:
531  case CK_Graniterapids:
532  // FIXME: Historically, we defined this legacy name, it would be nice to
533  // remove it at some point. We've never exposed fine-grained names for
534  // recent primary x86 CPUs, and we should keep it that way.
535  defineCPUMacros(Builder, "corei7");
536  break;
537  case CK_KNL:
538  defineCPUMacros(Builder, "knl");
539  break;
540  case CK_KNM:
541  break;
542  case CK_Lakemont:
543  defineCPUMacros(Builder, "i586", /*Tuning*/false);
544  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
545  Builder.defineMacro("__tune_lakemont__");
546  break;
547  case CK_K6_2:
548  Builder.defineMacro("__k6_2__");
549  Builder.defineMacro("__tune_k6_2__");
550  [[fallthrough]];
551  case CK_K6_3:
552  if (CPU != CK_K6_2) { // In case of fallthrough
553  // FIXME: GCC may be enabling these in cases where some other k6
554  // architecture is specified but -m3dnow is explicitly provided. The
555  // exact semantics need to be determined and emulated here.
556  Builder.defineMacro("__k6_3__");
557  Builder.defineMacro("__tune_k6_3__");
558  }
559  [[fallthrough]];
560  case CK_K6:
561  defineCPUMacros(Builder, "k6");
562  break;
563  case CK_Athlon:
564  case CK_AthlonXP:
565  defineCPUMacros(Builder, "athlon");
566  if (SSELevel != NoSSE) {
567  Builder.defineMacro("__athlon_sse__");
568  Builder.defineMacro("__tune_athlon_sse__");
569  }
570  break;
571  case CK_K8:
572  case CK_K8SSE3:
573  case CK_x86_64:
574  defineCPUMacros(Builder, "k8");
575  break;
576  case CK_x86_64_v2:
577  case CK_x86_64_v3:
578  case CK_x86_64_v4:
579  break;
580  case CK_AMDFAM10:
581  defineCPUMacros(Builder, "amdfam10");
582  break;
583  case CK_BTVER1:
584  defineCPUMacros(Builder, "btver1");
585  break;
586  case CK_BTVER2:
587  defineCPUMacros(Builder, "btver2");
588  break;
589  case CK_BDVER1:
590  defineCPUMacros(Builder, "bdver1");
591  break;
592  case CK_BDVER2:
593  defineCPUMacros(Builder, "bdver2");
594  break;
595  case CK_BDVER3:
596  defineCPUMacros(Builder, "bdver3");
597  break;
598  case CK_BDVER4:
599  defineCPUMacros(Builder, "bdver4");
600  break;
601  case CK_ZNVER1:
602  defineCPUMacros(Builder, "znver1");
603  break;
604  case CK_ZNVER2:
605  defineCPUMacros(Builder, "znver2");
606  break;
607  case CK_ZNVER3:
608  defineCPUMacros(Builder, "znver3");
609  break;
610  case CK_Geode:
611  defineCPUMacros(Builder, "geode");
612  break;
613  }
614 
615  // Target properties.
616  Builder.defineMacro("__REGISTER_PREFIX__", "");
617 
618  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
619  // functions in glibc header files that use FP Stack inline asm which the
620  // backend can't deal with (PR879).
621  Builder.defineMacro("__NO_MATH_INLINES");
622 
623  if (HasAES)
624  Builder.defineMacro("__AES__");
625 
626  if (HasVAES)
627  Builder.defineMacro("__VAES__");
628 
629  if (HasPCLMUL)
630  Builder.defineMacro("__PCLMUL__");
631 
632  if (HasVPCLMULQDQ)
633  Builder.defineMacro("__VPCLMULQDQ__");
634 
635  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
636  // the feature flag only applies to 64-bit mode.
637  if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
638  Builder.defineMacro("__LAHF_SAHF__");
639 
640  if (HasLZCNT)
641  Builder.defineMacro("__LZCNT__");
642 
643  if (HasRDRND)
644  Builder.defineMacro("__RDRND__");
645 
646  if (HasFSGSBASE)
647  Builder.defineMacro("__FSGSBASE__");
648 
649  if (HasBMI)
650  Builder.defineMacro("__BMI__");
651 
652  if (HasBMI2)
653  Builder.defineMacro("__BMI2__");
654 
655  if (HasPOPCNT)
656  Builder.defineMacro("__POPCNT__");
657 
658  if (HasRTM)
659  Builder.defineMacro("__RTM__");
660 
661  if (HasPRFCHW)
662  Builder.defineMacro("__PRFCHW__");
663 
664  if (HasRDSEED)
665  Builder.defineMacro("__RDSEED__");
666 
667  if (HasADX)
668  Builder.defineMacro("__ADX__");
669 
670  if (HasTBM)
671  Builder.defineMacro("__TBM__");
672 
673  if (HasLWP)
674  Builder.defineMacro("__LWP__");
675 
676  if (HasMWAITX)
677  Builder.defineMacro("__MWAITX__");
678 
679  if (HasMOVBE)
680  Builder.defineMacro("__MOVBE__");
681 
682  switch (XOPLevel) {
683  case XOP:
684  Builder.defineMacro("__XOP__");
685  [[fallthrough]];
686  case FMA4:
687  Builder.defineMacro("__FMA4__");
688  [[fallthrough]];
689  case SSE4A:
690  Builder.defineMacro("__SSE4A__");
691  [[fallthrough]];
692  case NoXOP:
693  break;
694  }
695 
696  if (HasFMA)
697  Builder.defineMacro("__FMA__");
698 
699  if (HasF16C)
700  Builder.defineMacro("__F16C__");
701 
702  if (HasGFNI)
703  Builder.defineMacro("__GFNI__");
704 
705  if (HasAVX512CD)
706  Builder.defineMacro("__AVX512CD__");
707  if (HasAVX512VPOPCNTDQ)
708  Builder.defineMacro("__AVX512VPOPCNTDQ__");
709  if (HasAVX512VNNI)
710  Builder.defineMacro("__AVX512VNNI__");
711  if (HasAVX512BF16)
712  Builder.defineMacro("__AVX512BF16__");
713  if (HasAVX512ER)
714  Builder.defineMacro("__AVX512ER__");
715  if (HasAVX512FP16)
716  Builder.defineMacro("__AVX512FP16__");
717  if (HasAVX512PF)
718  Builder.defineMacro("__AVX512PF__");
719  if (HasAVX512DQ)
720  Builder.defineMacro("__AVX512DQ__");
721  if (HasAVX512BITALG)
722  Builder.defineMacro("__AVX512BITALG__");
723  if (HasAVX512BW)
724  Builder.defineMacro("__AVX512BW__");
725  if (HasAVX512VL)
726  Builder.defineMacro("__AVX512VL__");
727  if (HasAVX512VBMI)
728  Builder.defineMacro("__AVX512VBMI__");
729  if (HasAVX512VBMI2)
730  Builder.defineMacro("__AVX512VBMI2__");
731  if (HasAVX512IFMA)
732  Builder.defineMacro("__AVX512IFMA__");
733  if (HasAVX512VP2INTERSECT)
734  Builder.defineMacro("__AVX512VP2INTERSECT__");
735  if (HasSHA)
736  Builder.defineMacro("__SHA__");
737 
738  if (HasFXSR)
739  Builder.defineMacro("__FXSR__");
740  if (HasXSAVE)
741  Builder.defineMacro("__XSAVE__");
742  if (HasXSAVEOPT)
743  Builder.defineMacro("__XSAVEOPT__");
744  if (HasXSAVEC)
745  Builder.defineMacro("__XSAVEC__");
746  if (HasXSAVES)
747  Builder.defineMacro("__XSAVES__");
748  if (HasPKU)
749  Builder.defineMacro("__PKU__");
750  if (HasCLFLUSHOPT)
751  Builder.defineMacro("__CLFLUSHOPT__");
752  if (HasCLWB)
753  Builder.defineMacro("__CLWB__");
754  if (HasWBNOINVD)
755  Builder.defineMacro("__WBNOINVD__");
756  if (HasSHSTK)
757  Builder.defineMacro("__SHSTK__");
758  if (HasSGX)
759  Builder.defineMacro("__SGX__");
760  if (HasPREFETCHI)
761  Builder.defineMacro("__PREFETCHI__");
762  if (HasPREFETCHWT1)
763  Builder.defineMacro("__PREFETCHWT1__");
764  if (HasCLZERO)
765  Builder.defineMacro("__CLZERO__");
766  if (HasKL)
767  Builder.defineMacro("__KL__");
768  if (HasWIDEKL)
769  Builder.defineMacro("__WIDEKL__");
770  if (HasRDPID)
771  Builder.defineMacro("__RDPID__");
772  if (HasRDPRU)
773  Builder.defineMacro("__RDPRU__");
774  if (HasCLDEMOTE)
775  Builder.defineMacro("__CLDEMOTE__");
776  if (HasWAITPKG)
777  Builder.defineMacro("__WAITPKG__");
778  if (HasMOVDIRI)
779  Builder.defineMacro("__MOVDIRI__");
780  if (HasMOVDIR64B)
781  Builder.defineMacro("__MOVDIR64B__");
782  if (HasPCONFIG)
783  Builder.defineMacro("__PCONFIG__");
784  if (HasPTWRITE)
785  Builder.defineMacro("__PTWRITE__");
786  if (HasINVPCID)
787  Builder.defineMacro("__INVPCID__");
788  if (HasENQCMD)
789  Builder.defineMacro("__ENQCMD__");
790  if (HasHRESET)
791  Builder.defineMacro("__HRESET__");
792  if (HasAMXTILE)
793  Builder.defineMacro("__AMXTILE__");
794  if (HasAMXINT8)
795  Builder.defineMacro("__AMXINT8__");
796  if (HasAMXBF16)
797  Builder.defineMacro("__AMXBF16__");
798  if (HasAMXFP16)
799  Builder.defineMacro("__AMXFP16__");
800  if (HasCMPCCXADD)
801  Builder.defineMacro("__CMPCCXADD__");
802  if (HasRAOINT)
803  Builder.defineMacro("__RAOINT__");
804  if (HasAVXIFMA)
805  Builder.defineMacro("__AVXIFMA__");
806  if (HasAVXNECONVERT)
807  Builder.defineMacro("__AVXNECONVERT__");
808  if (HasAVXVNNI)
809  Builder.defineMacro("__AVXVNNI__");
810  if (HasAVXVNNIINT8)
811  Builder.defineMacro("__AVXVNNIINT8__");
812  if (HasSERIALIZE)
813  Builder.defineMacro("__SERIALIZE__");
814  if (HasTSXLDTRK)
815  Builder.defineMacro("__TSXLDTRK__");
816  if (HasUINTR)
817  Builder.defineMacro("__UINTR__");
818  if (HasCRC32)
819  Builder.defineMacro("__CRC32__");
820 
821  // Each case falls through to the previous one here.
822  switch (SSELevel) {
823  case AVX512F:
824  Builder.defineMacro("__AVX512F__");
825  [[fallthrough]];
826  case AVX2:
827  Builder.defineMacro("__AVX2__");
828  [[fallthrough]];
829  case AVX:
830  Builder.defineMacro("__AVX__");
831  [[fallthrough]];
832  case SSE42:
833  Builder.defineMacro("__SSE4_2__");
834  [[fallthrough]];
835  case SSE41:
836  Builder.defineMacro("__SSE4_1__");
837  [[fallthrough]];
838  case SSSE3:
839  Builder.defineMacro("__SSSE3__");
840  [[fallthrough]];
841  case SSE3:
842  Builder.defineMacro("__SSE3__");
843  [[fallthrough]];
844  case SSE2:
845  Builder.defineMacro("__SSE2__");
846  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
847  [[fallthrough]];
848  case SSE1:
849  Builder.defineMacro("__SSE__");
850  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
851  [[fallthrough]];
852  case NoSSE:
853  break;
854  }
855 
856  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
857  switch (SSELevel) {
858  case AVX512F:
859  case AVX2:
860  case AVX:
861  case SSE42:
862  case SSE41:
863  case SSSE3:
864  case SSE3:
865  case SSE2:
866  Builder.defineMacro("_M_IX86_FP", Twine(2));
867  break;
868  case SSE1:
869  Builder.defineMacro("_M_IX86_FP", Twine(1));
870  break;
871  default:
872  Builder.defineMacro("_M_IX86_FP", Twine(0));
873  break;
874  }
875  }
876 
877  // Each case falls through to the previous one here.
878  switch (MMX3DNowLevel) {
879  case AMD3DNowAthlon:
880  Builder.defineMacro("__3dNOW_A__");
881  [[fallthrough]];
882  case AMD3DNow:
883  Builder.defineMacro("__3dNOW__");
884  [[fallthrough]];
885  case MMX:
886  Builder.defineMacro("__MMX__");
887  [[fallthrough]];
888  case NoMMX3DNow:
889  break;
890  }
891 
892  if (CPU >= CK_i486 || CPU == CK_None) {
893  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
894  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
895  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
896  }
897  if (HasCX8)
898  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
899  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
900  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
901 
902  if (HasFloat128)
903  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
904 }
905 
906 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
907  return llvm::StringSwitch<bool>(Name)
908  .Case("3dnow", true)
909  .Case("3dnowa", true)
910  .Case("adx", true)
911  .Case("aes", true)
912  .Case("amx-bf16", true)
913  .Case("amx-fp16", true)
914  .Case("amx-int8", true)
915  .Case("amx-tile", true)
916  .Case("avx", true)
917  .Case("avx2", true)
918  .Case("avx512f", true)
919  .Case("avx512cd", true)
920  .Case("avx512vpopcntdq", true)
921  .Case("avx512vnni", true)
922  .Case("avx512bf16", true)
923  .Case("avx512er", true)
924  .Case("avx512fp16", true)
925  .Case("avx512pf", true)
926  .Case("avx512dq", true)
927  .Case("avx512bitalg", true)
928  .Case("avx512bw", true)
929  .Case("avx512vl", true)
930  .Case("avx512vbmi", true)
931  .Case("avx512vbmi2", true)
932  .Case("avx512ifma", true)
933  .Case("avx512vp2intersect", true)
934  .Case("avxifma", true)
935  .Case("avxneconvert", true)
936  .Case("avxvnni", true)
937  .Case("avxvnniint8", true)
938  .Case("bmi", true)
939  .Case("bmi2", true)
940  .Case("cldemote", true)
941  .Case("clflushopt", true)
942  .Case("clwb", true)
943  .Case("clzero", true)
944  .Case("cmpccxadd", true)
945  .Case("crc32", true)
946  .Case("cx16", true)
947  .Case("enqcmd", true)
948  .Case("f16c", true)
949  .Case("fma", true)
950  .Case("fma4", true)
951  .Case("fsgsbase", true)
952  .Case("fxsr", true)
953  .Case("general-regs-only", true)
954  .Case("gfni", true)
955  .Case("hreset", true)
956  .Case("invpcid", true)
957  .Case("kl", true)
958  .Case("widekl", true)
959  .Case("lwp", true)
960  .Case("lzcnt", true)
961  .Case("mmx", true)
962  .Case("movbe", true)
963  .Case("movdiri", true)
964  .Case("movdir64b", true)
965  .Case("mwaitx", true)
966  .Case("pclmul", true)
967  .Case("pconfig", true)
968  .Case("pku", true)
969  .Case("popcnt", true)
970  .Case("prefetchi", true)
971  .Case("prefetchwt1", true)
972  .Case("prfchw", true)
973  .Case("ptwrite", true)
974  .Case("raoint", true)
975  .Case("rdpid", true)
976  .Case("rdpru", true)
977  .Case("rdrnd", true)
978  .Case("rdseed", true)
979  .Case("rtm", true)
980  .Case("sahf", true)
981  .Case("serialize", true)
982  .Case("sgx", true)
983  .Case("sha", true)
984  .Case("shstk", true)
985  .Case("sse", true)
986  .Case("sse2", true)
987  .Case("sse3", true)
988  .Case("ssse3", true)
989  .Case("sse4", true)
990  .Case("sse4.1", true)
991  .Case("sse4.2", true)
992  .Case("sse4a", true)
993  .Case("tbm", true)
994  .Case("tsxldtrk", true)
995  .Case("uintr", true)
996  .Case("vaes", true)
997  .Case("vpclmulqdq", true)
998  .Case("wbnoinvd", true)
999  .Case("waitpkg", true)
1000  .Case("x87", true)
1001  .Case("xop", true)
1002  .Case("xsave", true)
1003  .Case("xsavec", true)
1004  .Case("xsaves", true)
1005  .Case("xsaveopt", true)
1006  .Default(false);
1007 }
1008 
1009 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1010  return llvm::StringSwitch<bool>(Feature)
1011  .Case("adx", HasADX)
1012  .Case("aes", HasAES)
1013  .Case("amx-bf16", HasAMXBF16)
1014  .Case("amx-fp16", HasAMXFP16)
1015  .Case("amx-int8", HasAMXINT8)
1016  .Case("amx-tile", HasAMXTILE)
1017  .Case("avx", SSELevel >= AVX)
1018  .Case("avx2", SSELevel >= AVX2)
1019  .Case("avx512f", SSELevel >= AVX512F)
1020  .Case("avx512cd", HasAVX512CD)
1021  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1022  .Case("avx512vnni", HasAVX512VNNI)
1023  .Case("avx512bf16", HasAVX512BF16)
1024  .Case("avx512er", HasAVX512ER)
1025  .Case("avx512fp16", HasAVX512FP16)
1026  .Case("avx512pf", HasAVX512PF)
1027  .Case("avx512dq", HasAVX512DQ)
1028  .Case("avx512bitalg", HasAVX512BITALG)
1029  .Case("avx512bw", HasAVX512BW)
1030  .Case("avx512vl", HasAVX512VL)
1031  .Case("avx512vbmi", HasAVX512VBMI)
1032  .Case("avx512vbmi2", HasAVX512VBMI2)
1033  .Case("avx512ifma", HasAVX512IFMA)
1034  .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1035  .Case("avxifma", HasAVXIFMA)
1036  .Case("avxneconvert", HasAVXNECONVERT)
1037  .Case("avxvnni", HasAVXVNNI)
1038  .Case("avxvnniint8", HasAVXVNNIINT8)
1039  .Case("bmi", HasBMI)
1040  .Case("bmi2", HasBMI2)
1041  .Case("cldemote", HasCLDEMOTE)
1042  .Case("clflushopt", HasCLFLUSHOPT)
1043  .Case("clwb", HasCLWB)
1044  .Case("clzero", HasCLZERO)
1045  .Case("cmpccxadd", HasCMPCCXADD)
1046  .Case("crc32", HasCRC32)
1047  .Case("cx8", HasCX8)
1048  .Case("cx16", HasCX16)
1049  .Case("enqcmd", HasENQCMD)
1050  .Case("f16c", HasF16C)
1051  .Case("fma", HasFMA)
1052  .Case("fma4", XOPLevel >= FMA4)
1053  .Case("fsgsbase", HasFSGSBASE)
1054  .Case("fxsr", HasFXSR)
1055  .Case("gfni", HasGFNI)
1056  .Case("hreset", HasHRESET)
1057  .Case("invpcid", HasINVPCID)
1058  .Case("kl", HasKL)
1059  .Case("widekl", HasWIDEKL)
1060  .Case("lwp", HasLWP)
1061  .Case("lzcnt", HasLZCNT)
1062  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1063  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1064  .Case("mmx", MMX3DNowLevel >= MMX)
1065  .Case("movbe", HasMOVBE)
1066  .Case("movdiri", HasMOVDIRI)
1067  .Case("movdir64b", HasMOVDIR64B)
1068  .Case("mwaitx", HasMWAITX)
1069  .Case("pclmul", HasPCLMUL)
1070  .Case("pconfig", HasPCONFIG)
1071  .Case("pku", HasPKU)
1072  .Case("popcnt", HasPOPCNT)
1073  .Case("prefetchi", HasPREFETCHI)
1074  .Case("prefetchwt1", HasPREFETCHWT1)
1075  .Case("prfchw", HasPRFCHW)
1076  .Case("ptwrite", HasPTWRITE)
1077  .Case("raoint", HasRAOINT)
1078  .Case("rdpid", HasRDPID)
1079  .Case("rdpru", HasRDPRU)
1080  .Case("rdrnd", HasRDRND)
1081  .Case("rdseed", HasRDSEED)
1082  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1083  .Case("rtm", HasRTM)
1084  .Case("sahf", HasLAHFSAHF)
1085  .Case("serialize", HasSERIALIZE)
1086  .Case("sgx", HasSGX)
1087  .Case("sha", HasSHA)
1088  .Case("shstk", HasSHSTK)
1089  .Case("sse", SSELevel >= SSE1)
1090  .Case("sse2", SSELevel >= SSE2)
1091  .Case("sse3", SSELevel >= SSE3)
1092  .Case("ssse3", SSELevel >= SSSE3)
1093  .Case("sse4.1", SSELevel >= SSE41)
1094  .Case("sse4.2", SSELevel >= SSE42)
1095  .Case("sse4a", XOPLevel >= SSE4A)
1096  .Case("tbm", HasTBM)
1097  .Case("tsxldtrk", HasTSXLDTRK)
1098  .Case("uintr", HasUINTR)
1099  .Case("vaes", HasVAES)
1100  .Case("vpclmulqdq", HasVPCLMULQDQ)
1101  .Case("wbnoinvd", HasWBNOINVD)
1102  .Case("waitpkg", HasWAITPKG)
1103  .Case("x86", true)
1104  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1105  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1106  .Case("x87", HasX87)
1107  .Case("xop", XOPLevel >= XOP)
1108  .Case("xsave", HasXSAVE)
1109  .Case("xsavec", HasXSAVEC)
1110  .Case("xsaves", HasXSAVES)
1111  .Case("xsaveopt", HasXSAVEOPT)
1112  .Default(false);
1113 }
1114 
1115 // We can't use a generic validation scheme for the features accepted here
1116 // versus subtarget features accepted in the target attribute because the
1117 // bitfield structure that's initialized in the runtime only supports the
1118 // below currently rather than the full range of subtarget features. (See
1119 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1120 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1121  return llvm::StringSwitch<bool>(FeatureStr)
1122 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1123 #include "llvm/Support/X86TargetParser.def"
1124  .Default(false);
1125 }
1126 
1127 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1128  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1129 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1130  .Case(STR, llvm::X86::FEATURE_##ENUM)
1131 
1132 #include "llvm/Support/X86TargetParser.def"
1133  ;
1134  // Note, this function should only be used after ensuring the value is
1135  // correct, so it asserts if the value is out of range.
1136 }
1137 
1138 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1139  // Valid CPUs have a 'key feature' that compares just better than its key
1140  // feature.
1141  using namespace llvm::X86;
1142  CPUKind Kind = parseArchX86(Name);
1143  if (Kind != CK_None) {
1144  ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1145  return (getFeaturePriority(KeyFeature) << 1) + 1;
1146  }
1147 
1148  // Now we know we have a feature, so get its priority and shift it a few so
1149  // that we have sufficient room for the CPUs (above).
1150  return getFeaturePriority(getFeature(Name)) << 1;
1151 }
1152 
1154  return llvm::StringSwitch<bool>(Name)
1155 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1156 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1157 #include "llvm/Support/X86TargetParser.def"
1158  .Default(false);
1159 }
1160 
1161 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1162  return llvm::StringSwitch<StringRef>(Name)
1163 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1164 #include "llvm/Support/X86TargetParser.def"
1165  .Default(Name);
1166 }
1167 
1169  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1170 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1171 #include "llvm/Support/X86TargetParser.def"
1172  .Default(0);
1173 }
1174 
1176  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1177  StringRef WholeList =
1178  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1179 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1180 #include "llvm/Support/X86TargetParser.def"
1181  .Default("");
1182  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1183 }
1184 
1185 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const {
1186  return llvm::StringSwitch<StringRef>(Name)
1187 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1188 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1189 #include "llvm/Support/X86TargetParser.def"
1190  .Default("");
1191 }
1192 
1193 // We can't use a generic validation scheme for the cpus accepted here
1194 // versus subtarget cpus accepted in the target attribute because the
1195 // variables intitialized by the runtime only support the below currently
1196 // rather than the full range of cpus.
1197 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1198  return llvm::StringSwitch<bool>(FeatureStr)
1199 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1200 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1201 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1202 #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1203 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1204 #include "llvm/Support/X86TargetParser.def"
1205  .Default(false);
1206 }
1207 
1208 static unsigned matchAsmCCConstraint(const char *&Name) {
1209  auto RV = llvm::StringSwitch<unsigned>(Name)
1210  .Case("@cca", 4)
1211  .Case("@ccae", 5)
1212  .Case("@ccb", 4)
1213  .Case("@ccbe", 5)
1214  .Case("@ccc", 4)
1215  .Case("@cce", 4)
1216  .Case("@ccz", 4)
1217  .Case("@ccg", 4)
1218  .Case("@ccge", 5)
1219  .Case("@ccl", 4)
1220  .Case("@ccle", 5)
1221  .Case("@ccna", 5)
1222  .Case("@ccnae", 6)
1223  .Case("@ccnb", 5)
1224  .Case("@ccnbe", 6)
1225  .Case("@ccnc", 5)
1226  .Case("@ccne", 5)
1227  .Case("@ccnz", 5)
1228  .Case("@ccng", 5)
1229  .Case("@ccnge", 6)
1230  .Case("@ccnl", 5)
1231  .Case("@ccnle", 6)
1232  .Case("@ccno", 5)
1233  .Case("@ccnp", 5)
1234  .Case("@ccns", 5)
1235  .Case("@cco", 4)
1236  .Case("@ccp", 4)
1237  .Case("@ccs", 4)
1238  .Default(0);
1239  return RV;
1240 }
1241 
1243  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1244  switch (*Name) {
1245  default:
1246  return false;
1247  // Constant constraints.
1248  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1249  // instructions.
1250  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1251  // x86_64 instructions.
1252  case 's':
1253  Info.setRequiresImmediate();
1254  return true;
1255  case 'I':
1256  Info.setRequiresImmediate(0, 31);
1257  return true;
1258  case 'J':
1259  Info.setRequiresImmediate(0, 63);
1260  return true;
1261  case 'K':
1262  Info.setRequiresImmediate(-128, 127);
1263  return true;
1264  case 'L':
1265  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1266  return true;
1267  case 'M':
1268  Info.setRequiresImmediate(0, 3);
1269  return true;
1270  case 'N':
1271  Info.setRequiresImmediate(0, 255);
1272  return true;
1273  case 'O':
1274  Info.setRequiresImmediate(0, 127);
1275  return true;
1276  // Register constraints.
1277  case 'Y': // 'Y' is the first character for several 2-character constraints.
1278  // Shift the pointer to the second character of the constraint.
1279  Name++;
1280  switch (*Name) {
1281  default:
1282  return false;
1283  case 'z': // First SSE register.
1284  case '2':
1285  case 't': // Any SSE register, when SSE2 is enabled.
1286  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1287  case 'm': // Any MMX register, when inter-unit moves enabled.
1288  case 'k': // AVX512 arch mask registers: k1-k7.
1289  Info.setAllowsRegister();
1290  return true;
1291  }
1292  case 'f': // Any x87 floating point stack register.
1293  // Constraint 'f' cannot be used for output operands.
1294  if (Info.ConstraintStr[0] == '=')
1295  return false;
1296  Info.setAllowsRegister();
1297  return true;
1298  case 'a': // eax.
1299  case 'b': // ebx.
1300  case 'c': // ecx.
1301  case 'd': // edx.
1302  case 'S': // esi.
1303  case 'D': // edi.
1304  case 'A': // edx:eax.
1305  case 't': // Top of floating point stack.
1306  case 'u': // Second from top of floating point stack.
1307  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1308  case 'y': // Any MMX register.
1309  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1310  case 'x': // Any SSE register.
1311  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1312  // for intermideate k reg operations).
1313  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1314  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1315  case 'l': // "Index" registers: any general register that can be used as an
1316  // index in a base+index memory access.
1317  Info.setAllowsRegister();
1318  return true;
1319  // Floating point constant constraints.
1320  case 'C': // SSE floating point constant.
1321  case 'G': // x87 floating point constant.
1322  return true;
1323  case '@':
1324  // CC condition changes.
1325  if (auto Len = matchAsmCCConstraint(Name)) {
1326  Name += Len - 1;
1327  Info.setAllowsRegister();
1328  return true;
1329  }
1330  return false;
1331  }
1332 }
1333 
1334 // Below is based on the following information:
1335 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1336 // | Processor Name | Cache Line Size (Bytes) | Source |
1337 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1338 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1339 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1340 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1341 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1342 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1343 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1344 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1345 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1346 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1347 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1348 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1349 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1350 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1351 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1352 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1353 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1354 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1355 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1357  using namespace llvm::X86;
1358  switch (CPU) {
1359  // i386
1360  case CK_i386:
1361  // i486
1362  case CK_i486:
1363  case CK_WinChipC6:
1364  case CK_WinChip2:
1365  case CK_C3:
1366  // Lakemont
1367  case CK_Lakemont:
1368  return 16;
1369 
1370  // i586
1371  case CK_i586:
1372  case CK_Pentium:
1373  case CK_PentiumMMX:
1374  // i686
1375  case CK_PentiumPro:
1376  case CK_i686:
1377  case CK_Pentium2:
1378  case CK_Pentium3:
1379  case CK_PentiumM:
1380  case CK_C3_2:
1381  // K6
1382  case CK_K6:
1383  case CK_K6_2:
1384  case CK_K6_3:
1385  // Geode
1386  case CK_Geode:
1387  return 32;
1388 
1389  // Netburst
1390  case CK_Pentium4:
1391  case CK_Prescott:
1392  case CK_Nocona:
1393  // Atom
1394  case CK_Bonnell:
1395  case CK_Silvermont:
1396  case CK_Goldmont:
1397  case CK_GoldmontPlus:
1398  case CK_Tremont:
1399 
1400  case CK_Westmere:
1401  case CK_SandyBridge:
1402  case CK_IvyBridge:
1403  case CK_Haswell:
1404  case CK_Broadwell:
1405  case CK_SkylakeClient:
1406  case CK_SkylakeServer:
1407  case CK_Cascadelake:
1408  case CK_Nehalem:
1409  case CK_Cooperlake:
1410  case CK_Cannonlake:
1411  case CK_Tigerlake:
1412  case CK_SapphireRapids:
1413  case CK_IcelakeClient:
1414  case CK_Rocketlake:
1415  case CK_IcelakeServer:
1416  case CK_Alderlake:
1417  case CK_Raptorlake:
1418  case CK_Meteorlake:
1419  case CK_Sierraforest:
1420  case CK_Grandridge:
1421  case CK_Graniterapids:
1422  case CK_KNL:
1423  case CK_KNM:
1424  // K7
1425  case CK_Athlon:
1426  case CK_AthlonXP:
1427  // K8
1428  case CK_K8:
1429  case CK_K8SSE3:
1430  case CK_AMDFAM10:
1431  // Bobcat
1432  case CK_BTVER1:
1433  case CK_BTVER2:
1434  // Bulldozer
1435  case CK_BDVER1:
1436  case CK_BDVER2:
1437  case CK_BDVER3:
1438  case CK_BDVER4:
1439  // Zen
1440  case CK_ZNVER1:
1441  case CK_ZNVER2:
1442  case CK_ZNVER3:
1443  // Deprecated
1444  case CK_x86_64:
1445  case CK_x86_64_v2:
1446  case CK_x86_64_v3:
1447  case CK_x86_64_v4:
1448  case CK_Yonah:
1449  case CK_Penryn:
1450  case CK_Core2:
1451  return 64;
1452 
1453  // The following currently have unknown cache line sizes (but they are probably all 64):
1454  // Core
1455  case CK_None:
1456  return None;
1457  }
1458  llvm_unreachable("Unknown CPU kind");
1459 }
1460 
1461 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1462  StringRef Constraint,
1463  unsigned Size) const {
1464  // Strip off constraint modifiers.
1465  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1466  Constraint = Constraint.substr(1);
1467 
1468  return validateOperandSize(FeatureMap, Constraint, Size);
1469 }
1470 
1471 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1472  StringRef Constraint,
1473  unsigned Size) const {
1474  return validateOperandSize(FeatureMap, Constraint, Size);
1475 }
1476 
1477 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1478  StringRef Constraint,
1479  unsigned Size) const {
1480  switch (Constraint[0]) {
1481  default:
1482  break;
1483  case 'k':
1484  // Registers k0-k7 (AVX512) size limit is 64 bit.
1485  case 'y':
1486  return Size <= 64;
1487  case 'f':
1488  case 't':
1489  case 'u':
1490  return Size <= 128;
1491  case 'Y':
1492  // 'Y' is the first character for several 2-character constraints.
1493  switch (Constraint[1]) {
1494  default:
1495  return false;
1496  case 'm':
1497  // 'Ym' is synonymous with 'y'.
1498  case 'k':
1499  return Size <= 64;
1500  case 'z':
1501  // XMM0/YMM/ZMM0
1502  if (hasFeatureEnabled(FeatureMap, "avx512f"))
1503  // ZMM0 can be used if target supports AVX512F.
1504  return Size <= 512U;
1505  else if (hasFeatureEnabled(FeatureMap, "avx"))
1506  // YMM0 can be used if target supports AVX.
1507  return Size <= 256U;
1508  else if (hasFeatureEnabled(FeatureMap, "sse"))
1509  return Size <= 128U;
1510  return false;
1511  case 'i':
1512  case 't':
1513  case '2':
1514  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1515  if (SSELevel < SSE2)
1516  return false;
1517  break;
1518  }
1519  break;
1520  case 'v':
1521  case 'x':
1522  if (hasFeatureEnabled(FeatureMap, "avx512f"))
1523  // 512-bit zmm registers can be used if target supports AVX512F.
1524  return Size <= 512U;
1525  else if (hasFeatureEnabled(FeatureMap, "avx"))
1526  // 256-bit ymm registers can be used if target supports AVX.
1527  return Size <= 256U;
1528  return Size <= 128U;
1529 
1530  }
1531 
1532  return true;
1533 }
1534 
1535 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1536  switch (*Constraint) {
1537  case '@':
1538  if (auto Len = matchAsmCCConstraint(Constraint)) {
1539  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1540  Constraint += Len - 1;
1541  return Converted;
1542  }
1543  return std::string(1, *Constraint);
1544  case 'a':
1545  return std::string("{ax}");
1546  case 'b':
1547  return std::string("{bx}");
1548  case 'c':
1549  return std::string("{cx}");
1550  case 'd':
1551  return std::string("{dx}");
1552  case 'S':
1553  return std::string("{si}");
1554  case 'D':
1555  return std::string("{di}");
1556  case 'p': // Keep 'p' constraint (address).
1557  return std::string("p");
1558  case 't': // top of floating point stack.
1559  return std::string("{st}");
1560  case 'u': // second from top of floating point stack.
1561  return std::string("{st(1)}"); // second from top of floating point stack.
1562  case 'Y':
1563  switch (Constraint[1]) {
1564  default:
1565  // Break from inner switch and fall through (copy single char),
1566  // continue parsing after copying the current constraint into
1567  // the return string.
1568  break;
1569  case 'k':
1570  case 'm':
1571  case 'i':
1572  case 't':
1573  case 'z':
1574  case '2':
1575  // "^" hints llvm that this is a 2 letter constraint.
1576  // "Constraint++" is used to promote the string iterator
1577  // to the next constraint.
1578  return std::string("^") + std::string(Constraint++, 2);
1579  }
1580  [[fallthrough]];
1581  default:
1582  return std::string(1, *Constraint);
1583  }
1584 }
1585 
1587  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1588  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1589 }
1590 
1592  llvm::X86::fillValidTuneCPUList(Values);
1593 }
1594 
1596  return llvm::makeArrayRef(GCCRegNames);
1597 }
1598 
1600  return llvm::makeArrayRef(AddlRegNames);
1601 }
1602 
1604  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1606 }
1607 
1609  return llvm::makeArrayRef(BuiltinInfoX86,
1611 }
Builtins.h
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Definition: X86.cpp:1599
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Definition: X86.cpp:1208
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Definition: CMakeLists.txt:22
clang::targets::X86TargetInfo::isValidFeatureName
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Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:906
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void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1175
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Definition: Diagnostic.h:192
int
__device__ int
Definition: __clang_hip_libdevice_declares.h:63
llvm::Optional< unsigned >
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bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1471
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Definition: TargetInfo.h:221
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Definition: TargetInfo.h:1092
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@ FP_387
Definition: X86.h:162
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bool HasLegalHalfType
Definition: TargetInfo.h:216
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bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1197
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llvm::X86::CPUKind CPU
Definition: X86.h:160
U
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1586
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:1094
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ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1603
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Definition: TargetBuiltins.h:116
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Definition: TargetBuiltins.h:119
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unsigned short SimdDefaultAlign
Definition: TargetInfo.h:228
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: X86.cpp:1591
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition: X86.cpp:167
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
Diagnostic.h
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virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:492
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Definition: X86.cpp:43
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DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:59
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unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1138
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@ FP_SSE
Definition: X86.h:162
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Definition: X86.cpp:1153
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Definition: TargetInfo.h:219
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Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105
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Definition: TargetInfo.h:1047
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Returns the target triple of the primary target.
Definition: TargetInfo.h:1197
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Determine whether the given target has the given feature.
Definition: X86.cpp:1009
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Definition: TargetInfo.h:1214
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bool HasLongDouble
Definition: TargetInfo.h:223
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition: TargetInfo.h:281
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition: X86.cpp:186
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1127
llvm::ArrayRef< const char * >
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:132
clang::targets::X86_64TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1608
clang::targets::X86TargetInfo::getCPUSpecificTuneName
StringRef getCPUSpecificTuneName(StringRef Name) const override
Definition: X86.cpp:1185
TargetBuiltins.h
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1120
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1461
X86.h
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:1028
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:81
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
clang::ObjCPropertyAttribute::Kind
Kind
Definition: DeclObjCCommon.h:22
clang::TargetInfo::HasFloat16
bool HasFloat16
Definition: TargetInfo.h:220
clang
Definition: CalledOnceCheck.h:17
clang::targets
Definition: AArch64.h:21
clang::Builtin::Info
Definition: Builtins.h:59
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1535
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition: TargetInfo.h:1322
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1168
clang::prec::Level
Level
Definition: OperatorPrecedence.h:26
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1477
clang::Builtin::FirstTSBuiltin
@ FirstTSBuiltin
Definition: Builtins.h:56
clang::targets::BuiltinInfoX86
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
llvm::SmallVectorImpl
Definition: Randstruct.h:18
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::defineCPUMacros
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:75
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1242
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1595
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:415
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1537
clang::TargetOptions::CodeModel
std::string CodeModel
Definition: TargetOptions.h:97
CPUSpecificCPUDispatchNameDealias
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1161