clang 23.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 UpdatedFeaturesVec.push_back(Feature);
178 }
179
180 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
181 return false;
182
183 // Can't do this earlier because we need to be able to explicitly enable
184 // or disable these features and the things that they depend upon.
185
186 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
187 auto I = Features.find("sse4.2");
188 if (I != Features.end() && I->getValue() &&
189 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
190 Features["popcnt"] = true;
191
192 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
193 // then enable MMX.
194 I = Features.find("sse");
195 if (I != Features.end() && I->getValue() &&
196 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
197 Features["mmx"] = true;
198
199 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
200 I = Features.find("avx");
201 if (I != Features.end() && I->getValue() &&
202 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
203 Features["xsave"] = true;
204
205 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
206 I = Features.find("sse4.2");
207 if (I != Features.end() && I->getValue() &&
208 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
209 Features["crc32"] = true;
210
211 return true;
212}
213
214void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
215 StringRef Name, bool Enabled) const {
216 if (Name == "sse4") {
217 // We can get here via the __target__ attribute since that's not controlled
218 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
219 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
220 // disabled.
221 if (Enabled)
222 Name = "sse4.2";
223 else
224 Name = "sse4.1";
225 }
226
227 Features[Name] = Enabled;
228 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
229}
230
231/// handleTargetFeatures - Perform initialization based on the user
232/// configured set of features.
233bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
234 DiagnosticsEngine &Diags) {
235 for (const auto &Feature : Features) {
236 if (Feature[0] != '+')
237 continue;
238
239 if (Feature == "+mmx") {
240 HasMMX = true;
241 } else if (Feature == "+aes") {
242 HasAES = true;
243 } else if (Feature == "+vaes") {
244 HasVAES = true;
245 } else if (Feature == "+pclmul") {
246 HasPCLMUL = true;
247 } else if (Feature == "+vpclmulqdq") {
248 HasVPCLMULQDQ = true;
249 } else if (Feature == "+lzcnt") {
250 HasLZCNT = true;
251 } else if (Feature == "+rdrnd") {
252 HasRDRND = true;
253 } else if (Feature == "+fsgsbase") {
254 HasFSGSBASE = true;
255 } else if (Feature == "+bmi") {
256 HasBMI = true;
257 } else if (Feature == "+bmi2") {
258 HasBMI2 = true;
259 } else if (Feature == "+popcnt") {
260 HasPOPCNT = true;
261 } else if (Feature == "+rtm") {
262 HasRTM = true;
263 } else if (Feature == "+prfchw") {
264 HasPRFCHW = true;
265 } else if (Feature == "+rdseed") {
266 HasRDSEED = true;
267 } else if (Feature == "+adx") {
268 HasADX = true;
269 } else if (Feature == "+tbm") {
270 HasTBM = true;
271 } else if (Feature == "+lwp") {
272 HasLWP = true;
273 } else if (Feature == "+fma") {
274 HasFMA = true;
275 } else if (Feature == "+f16c") {
276 HasF16C = true;
277 } else if (Feature == "+gfni") {
278 HasGFNI = true;
279 } else if (Feature == "+avx10.1") {
280 HasAVX10_1 = true;
281 } else if (Feature == "+avx10.2") {
282 HasAVX10_2 = true;
283 HasFullBFloat16 = true;
284 } else if (Feature == "+avx512cd") {
285 HasAVX512CD = true;
286 } else if (Feature == "+avx512vpopcntdq") {
287 HasAVX512VPOPCNTDQ = true;
288 } else if (Feature == "+avx512vnni") {
289 HasAVX512VNNI = true;
290 } else if (Feature == "+avx512bf16") {
291 HasAVX512BF16 = true;
292 } else if (Feature == "+avx512fp16") {
293 HasAVX512FP16 = true;
294 HasFastHalfType = true;
295 } else if (Feature == "+avx512dq") {
296 HasAVX512DQ = true;
297 } else if (Feature == "+avx512bitalg") {
298 HasAVX512BITALG = true;
299 } else if (Feature == "+avx512bw") {
300 HasAVX512BW = true;
301 } else if (Feature == "+avx512vl") {
302 HasAVX512VL = true;
303 } else if (Feature == "+avx512vbmi") {
304 HasAVX512VBMI = true;
305 } else if (Feature == "+avx512vbmi2") {
306 HasAVX512VBMI2 = true;
307 } else if (Feature == "+avx512ifma") {
308 HasAVX512IFMA = true;
309 } else if (Feature == "+avx512vp2intersect") {
310 HasAVX512VP2INTERSECT = true;
311 } else if (Feature == "+sha") {
312 HasSHA = true;
313 } else if (Feature == "+sha512") {
314 HasSHA512 = true;
315 } else if (Feature == "+shstk") {
316 HasSHSTK = true;
317 } else if (Feature == "+sm3") {
318 HasSM3 = true;
319 } else if (Feature == "+sm4") {
320 HasSM4 = true;
321 } else if (Feature == "+movbe") {
322 HasMOVBE = true;
323 } else if (Feature == "+movrs") {
324 HasMOVRS = true;
325 } else if (Feature == "+sgx") {
326 HasSGX = true;
327 } else if (Feature == "+cx8") {
328 HasCX8 = true;
329 } else if (Feature == "+cx16") {
330 HasCX16 = true;
331 } else if (Feature == "+fxsr") {
332 HasFXSR = true;
333 } else if (Feature == "+xsave") {
334 HasXSAVE = true;
335 } else if (Feature == "+xsaveopt") {
336 HasXSAVEOPT = true;
337 } else if (Feature == "+xsavec") {
338 HasXSAVEC = true;
339 } else if (Feature == "+xsaves") {
340 HasXSAVES = true;
341 } else if (Feature == "+mwaitx") {
342 HasMWAITX = true;
343 } else if (Feature == "+pku") {
344 HasPKU = true;
345 } else if (Feature == "+clflushopt") {
346 HasCLFLUSHOPT = true;
347 } else if (Feature == "+clwb") {
348 HasCLWB = true;
349 } else if (Feature == "+wbnoinvd") {
350 HasWBNOINVD = true;
351 } else if (Feature == "+prefetchi") {
352 HasPREFETCHI = true;
353 } else if (Feature == "+clzero") {
354 HasCLZERO = true;
355 } else if (Feature == "+cldemote") {
356 HasCLDEMOTE = true;
357 } else if (Feature == "+rdpid") {
358 HasRDPID = true;
359 } else if (Feature == "+rdpru") {
360 HasRDPRU = true;
361 } else if (Feature == "+kl") {
362 HasKL = true;
363 } else if (Feature == "+widekl") {
364 HasWIDEKL = true;
365 } else if (Feature == "+retpoline-external-thunk") {
366 HasRetpolineExternalThunk = true;
367 } else if (Feature == "+sahf") {
368 HasLAHFSAHF = true;
369 } else if (Feature == "+waitpkg") {
370 HasWAITPKG = true;
371 } else if (Feature == "+movdiri") {
372 HasMOVDIRI = true;
373 } else if (Feature == "+movdir64b") {
374 HasMOVDIR64B = true;
375 } else if (Feature == "+pconfig") {
376 HasPCONFIG = true;
377 } else if (Feature == "+ptwrite") {
378 HasPTWRITE = true;
379 } else if (Feature == "+invpcid") {
380 HasINVPCID = true;
381 } else if (Feature == "+enqcmd") {
382 HasENQCMD = true;
383 } else if (Feature == "+hreset") {
384 HasHRESET = true;
385 } else if (Feature == "+amx-bf16") {
386 HasAMXBF16 = true;
387 } else if (Feature == "+amx-fp16") {
388 HasAMXFP16 = true;
389 } else if (Feature == "+amx-int8") {
390 HasAMXINT8 = true;
391 } else if (Feature == "+amx-tile") {
392 HasAMXTILE = true;
393 } else if (Feature == "+amx-complex") {
394 HasAMXCOMPLEX = true;
395 } else if (Feature == "+amx-fp8") {
396 HasAMXFP8 = true;
397 } else if (Feature == "+amx-movrs") {
398 HasAMXMOVRS = true;
399 } else if (Feature == "+amx-avx512") {
400 HasAMXAVX512 = true;
401 } else if (Feature == "+amx-tf32") {
402 HasAMXTF32 = true;
403 } else if (Feature == "+cmpccxadd") {
404 HasCMPCCXADD = true;
405 } else if (Feature == "+raoint") {
406 HasRAOINT = true;
407 } else if (Feature == "+avxifma") {
408 HasAVXIFMA = true;
409 } else if (Feature == "+avxneconvert") {
410 HasAVXNECONVERT= true;
411 } else if (Feature == "+avxvnni") {
412 HasAVXVNNI = true;
413 } else if (Feature == "+avxvnniint16") {
414 HasAVXVNNIINT16 = true;
415 } else if (Feature == "+avxvnniint8") {
416 HasAVXVNNIINT8 = true;
417 } else if (Feature == "+serialize") {
418 HasSERIALIZE = true;
419 } else if (Feature == "+tsxldtrk") {
420 HasTSXLDTRK = true;
421 } else if (Feature == "+uintr") {
422 HasUINTR = true;
423 } else if (Feature == "+usermsr") {
424 HasUSERMSR = true;
425 } else if (Feature == "+crc32") {
426 HasCRC32 = true;
427 } else if (Feature == "+x87") {
428 HasX87 = true;
429 } else if (Feature == "+fullbf16") {
430 HasFullBFloat16 = true;
431 } else if (Feature == "+egpr") {
432 HasEGPR = true;
433 } else if (Feature == "+inline-asm-use-gpr32") {
434 HasInlineAsmUseGPR32 = true;
435 } else if (Feature == "+push2pop2") {
436 HasPush2Pop2 = true;
437 } else if (Feature == "+ppx") {
438 HasPPX = true;
439 } else if (Feature == "+ndd") {
440 HasNDD = true;
441 } else if (Feature == "+ccmp") {
442 HasCCMP = true;
443 } else if (Feature == "+nf") {
444 HasNF = true;
445 } else if (Feature == "+cf") {
446 HasCF = true;
447 } else if (Feature == "+zu") {
448 HasZU = true;
449 } else if (Feature == "+jmpabs") {
450 HasJMPABS = true;
451 } else if (Feature == "+branch-hint") {
452 HasBranchHint = true;
453 }
454
455 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
456 .Case("+avx512f", AVX512F)
457 .Case("+avx2", AVX2)
458 .Case("+avx", AVX)
459 .Case("+sse4.2", SSE42)
460 .Case("+sse4.1", SSE41)
461 .Case("+ssse3", SSSE3)
462 .Case("+sse3", SSE3)
463 .Case("+sse2", SSE2)
464 .Case("+sse", SSE1)
465 .Default(NoSSE);
466 SSELevel = std::max(SSELevel, Level);
467
468 HasFloat16 = SSELevel >= SSE2;
469
470 // X86 target has bfloat16 emulation support in the backend, where
471 // bfloat16 is treated as a 32-bit float, arithmetic operations are
472 // performed in 32-bit, and the result is converted back to bfloat16.
473 // Truncation and extension between bfloat16 and 32-bit float are supported
474 // by the compiler-rt library. However, native bfloat16 support is currently
475 // not available in the X86 target. Hence, HasFullBFloat16 will be false
476 // until native bfloat16 support is available. HasFullBFloat16 is used to
477 // determine whether to automatically use excess floating point precision
478 // for bfloat16 arithmetic operations in the front-end.
479 HasBFloat16 = SSELevel >= SSE2;
480
481 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
482 .Case("+xop", XOP)
483 .Case("+fma4", FMA4)
484 .Case("+sse4a", SSE4A)
485 .Default(NoXOP);
486 XOPLevel = std::max(XOPLevel, XLevel);
487 }
488
489 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
490 // matches the selected sse level.
491 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
492 (FPMath == FP_387 && SSELevel >= SSE1)) {
493 Diags.Report(diag::err_target_unsupported_fpmath)
494 << (FPMath == FP_SSE ? "sse" : "387");
495 return false;
496 }
497
498 // FIXME: We should allow long double type on 32-bits to match with GCC.
499 // This requires backend to be able to lower f80 without x87 first.
500 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
501 HasLongDouble = false;
502
503 return true;
504}
505
506/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
507/// definitions for this particular subtarget.
508void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
509 MacroBuilder &Builder) const {
510 // Inline assembly supports X86 flag outputs.
511 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
512
513 std::string CodeModel = getTargetOpts().CodeModel;
514 if (CodeModel == "default")
515 CodeModel = "small";
516 Builder.defineMacro("__code_model_" + CodeModel + "__");
517
518 // Target identification.
519 if (getTriple().getArch() == llvm::Triple::x86_64) {
520 Builder.defineMacro("__amd64__");
521 Builder.defineMacro("__amd64");
522 Builder.defineMacro("__x86_64");
523 Builder.defineMacro("__x86_64__");
524 if (getTriple().getArchName() == "x86_64h") {
525 Builder.defineMacro("__x86_64h");
526 Builder.defineMacro("__x86_64h__");
527 }
528 } else {
529 DefineStd(Builder, "i386", Opts);
530 }
531
532 Builder.defineMacro("__SEG_GS");
533 Builder.defineMacro("__SEG_FS");
534 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
535 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
536
537 // Subtarget options.
538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
539 // truly should be based on -mtune options.
540 using namespace llvm::X86;
541 switch (CPU) {
542 case CK_None:
543 break;
544 case CK_i386:
545 // The rest are coming from the i386 define above.
546 Builder.defineMacro("__tune_i386__");
547 break;
548 case CK_i486:
549 case CK_WinChipC6:
550 case CK_WinChip2:
551 case CK_C3:
552 defineCPUMacros(Builder, "i486");
553 break;
554 case CK_PentiumMMX:
555 Builder.defineMacro("__pentium_mmx__");
556 Builder.defineMacro("__tune_pentium_mmx__");
557 [[fallthrough]];
558 case CK_i586:
559 case CK_Pentium:
560 defineCPUMacros(Builder, "i586");
561 defineCPUMacros(Builder, "pentium");
562 break;
563 case CK_Pentium3:
564 case CK_PentiumM:
565 Builder.defineMacro("__tune_pentium3__");
566 [[fallthrough]];
567 case CK_Pentium2:
568 case CK_C3_2:
569 Builder.defineMacro("__tune_pentium2__");
570 [[fallthrough]];
571 case CK_PentiumPro:
572 case CK_i686:
573 defineCPUMacros(Builder, "i686");
574 defineCPUMacros(Builder, "pentiumpro");
575 break;
576 case CK_Pentium4:
577 defineCPUMacros(Builder, "pentium4");
578 break;
579 case CK_Yonah:
580 case CK_Prescott:
581 case CK_Nocona:
582 defineCPUMacros(Builder, "nocona");
583 break;
584 case CK_Core2:
585 case CK_Penryn:
586 defineCPUMacros(Builder, "core2");
587 break;
588 case CK_Bonnell:
589 defineCPUMacros(Builder, "atom");
590 break;
591 case CK_Silvermont:
592 defineCPUMacros(Builder, "slm");
593 break;
594 case CK_Goldmont:
595 defineCPUMacros(Builder, "goldmont");
596 break;
597 case CK_GoldmontPlus:
598 defineCPUMacros(Builder, "goldmont_plus");
599 break;
600 case CK_Tremont:
601 defineCPUMacros(Builder, "tremont");
602 break;
603 // Gracemont and later atom-cores use P-core cpu macros.
604 case CK_Gracemont:
605 case CK_Nehalem:
606 case CK_Westmere:
607 case CK_SandyBridge:
608 case CK_IvyBridge:
609 case CK_Haswell:
610 case CK_Broadwell:
611 case CK_SkylakeClient:
612 case CK_SkylakeServer:
613 case CK_Cascadelake:
614 case CK_Cooperlake:
615 case CK_Cannonlake:
616 case CK_IcelakeClient:
617 case CK_Rocketlake:
618 case CK_IcelakeServer:
619 case CK_Tigerlake:
620 case CK_SapphireRapids:
621 case CK_Alderlake:
622 case CK_Raptorlake:
623 case CK_Meteorlake:
624 case CK_Arrowlake:
625 case CK_ArrowlakeS:
626 case CK_Lunarlake:
627 case CK_Pantherlake:
628 case CK_Wildcatlake:
629 case CK_Novalake:
630 case CK_Sierraforest:
631 case CK_Grandridge:
632 case CK_Graniterapids:
633 case CK_GraniterapidsD:
634 case CK_Emeraldrapids:
635 case CK_Clearwaterforest:
636 case CK_Diamondrapids:
637 // FIXME: Historically, we defined this legacy name, it would be nice to
638 // remove it at some point. We've never exposed fine-grained names for
639 // recent primary x86 CPUs, and we should keep it that way.
640 defineCPUMacros(Builder, "corei7");
641 break;
642 case CK_KNL:
643 defineCPUMacros(Builder, "knl");
644 break;
645 case CK_KNM:
646 break;
647 case CK_Lakemont:
648 defineCPUMacros(Builder, "i586", /*Tuning*/false);
649 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
650 Builder.defineMacro("__tune_lakemont__");
651 break;
652 case CK_K6_2:
653 Builder.defineMacro("__k6_2__");
654 Builder.defineMacro("__tune_k6_2__");
655 [[fallthrough]];
656 case CK_K6_3:
657 if (CPU != CK_K6_2) { // In case of fallthrough
658 // FIXME: GCC may be enabling these in cases where some other k6
659 // architecture is specified but -m3dnow is explicitly provided. The
660 // exact semantics need to be determined and emulated here.
661 Builder.defineMacro("__k6_3__");
662 Builder.defineMacro("__tune_k6_3__");
663 }
664 [[fallthrough]];
665 case CK_K6:
666 defineCPUMacros(Builder, "k6");
667 break;
668 case CK_Athlon:
669 case CK_AthlonXP:
670 defineCPUMacros(Builder, "athlon");
671 if (SSELevel != NoSSE) {
672 Builder.defineMacro("__athlon_sse__");
673 Builder.defineMacro("__tune_athlon_sse__");
674 }
675 break;
676 case CK_K8:
677 case CK_K8SSE3:
678 case CK_x86_64:
679 defineCPUMacros(Builder, "k8");
680 break;
681 case CK_x86_64_v2:
682 case CK_x86_64_v3:
683 case CK_x86_64_v4:
684 break;
685 case CK_AMDFAM10:
686 defineCPUMacros(Builder, "amdfam10");
687 break;
688 case CK_BTVER1:
689 defineCPUMacros(Builder, "btver1");
690 break;
691 case CK_BTVER2:
692 defineCPUMacros(Builder, "btver2");
693 break;
694 case CK_BDVER1:
695 defineCPUMacros(Builder, "bdver1");
696 break;
697 case CK_BDVER2:
698 defineCPUMacros(Builder, "bdver2");
699 break;
700 case CK_BDVER3:
701 defineCPUMacros(Builder, "bdver3");
702 break;
703 case CK_BDVER4:
704 defineCPUMacros(Builder, "bdver4");
705 break;
706 case CK_ZNVER1:
707 defineCPUMacros(Builder, "znver1");
708 break;
709 case CK_ZNVER2:
710 defineCPUMacros(Builder, "znver2");
711 break;
712 case CK_ZNVER3:
713 defineCPUMacros(Builder, "znver3");
714 break;
715 case CK_ZNVER4:
716 defineCPUMacros(Builder, "znver4");
717 break;
718 case CK_ZNVER5:
719 defineCPUMacros(Builder, "znver5");
720 break;
721 case CK_ZNVER6:
722 defineCPUMacros(Builder, "znver6");
723 break;
724 case CK_Geode:
725 defineCPUMacros(Builder, "geode");
726 break;
727 case CK_C86_4G_M4:
728 defineCPUMacros(Builder, "c86_4g_m4");
729 break;
730 case CK_C86_4G_M6:
731 defineCPUMacros(Builder, "c86_4g_m6");
732 break;
733 case CK_C86_4G_M7:
734 defineCPUMacros(Builder, "c86_4g_m7");
735 break;
736 }
737
738 // Target properties.
739 Builder.defineMacro("__REGISTER_PREFIX__", "");
740
741 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
742 // functions in glibc header files that use FP Stack inline asm which the
743 // backend can't deal with (PR879).
744 Builder.defineMacro("__NO_MATH_INLINES");
745
746 if (HasAES)
747 Builder.defineMacro("__AES__");
748
749 if (HasVAES)
750 Builder.defineMacro("__VAES__");
751
752 if (HasPCLMUL)
753 Builder.defineMacro("__PCLMUL__");
754
755 if (HasVPCLMULQDQ)
756 Builder.defineMacro("__VPCLMULQDQ__");
757
758 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
759 // the feature flag only applies to 64-bit mode.
760 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
761 Builder.defineMacro("__LAHF_SAHF__");
762
763 if (HasLZCNT)
764 Builder.defineMacro("__LZCNT__");
765
766 if (HasRDRND)
767 Builder.defineMacro("__RDRND__");
768
769 if (HasFSGSBASE)
770 Builder.defineMacro("__FSGSBASE__");
771
772 if (HasBMI)
773 Builder.defineMacro("__BMI__");
774
775 if (HasBMI2)
776 Builder.defineMacro("__BMI2__");
777
778 if (HasPOPCNT)
779 Builder.defineMacro("__POPCNT__");
780
781 if (HasRTM)
782 Builder.defineMacro("__RTM__");
783
784 if (HasPRFCHW)
785 Builder.defineMacro("__PRFCHW__");
786
787 if (HasRDSEED)
788 Builder.defineMacro("__RDSEED__");
789
790 if (HasADX)
791 Builder.defineMacro("__ADX__");
792
793 if (HasTBM)
794 Builder.defineMacro("__TBM__");
795
796 if (HasLWP)
797 Builder.defineMacro("__LWP__");
798
799 if (HasMWAITX)
800 Builder.defineMacro("__MWAITX__");
801
802 if (HasMOVBE)
803 Builder.defineMacro("__MOVBE__");
804
805 switch (XOPLevel) {
806 case XOP:
807 Builder.defineMacro("__XOP__");
808 [[fallthrough]];
809 case FMA4:
810 Builder.defineMacro("__FMA4__");
811 [[fallthrough]];
812 case SSE4A:
813 Builder.defineMacro("__SSE4A__");
814 [[fallthrough]];
815 case NoXOP:
816 break;
817 }
818
819 if (HasFMA)
820 Builder.defineMacro("__FMA__");
821
822 if (HasF16C)
823 Builder.defineMacro("__F16C__");
824
825 if (HasGFNI)
826 Builder.defineMacro("__GFNI__");
827
828 if (HasAVX10_1) {
829 Builder.defineMacro("__AVX10_1__");
830 Builder.defineMacro("__AVX10_1_512__");
831 }
832 if (HasAVX10_2) {
833 Builder.defineMacro("__AVX10_2__");
834 Builder.defineMacro("__AVX10_2_512__");
835 }
836 if (HasAVX512CD)
837 Builder.defineMacro("__AVX512CD__");
838 if (HasAVX512VPOPCNTDQ)
839 Builder.defineMacro("__AVX512VPOPCNTDQ__");
840 if (HasAVX512VNNI)
841 Builder.defineMacro("__AVX512VNNI__");
842 if (HasAVX512BF16)
843 Builder.defineMacro("__AVX512BF16__");
844 if (HasAVX512FP16)
845 Builder.defineMacro("__AVX512FP16__");
846 if (HasAVX512DQ)
847 Builder.defineMacro("__AVX512DQ__");
848 if (HasAVX512BITALG)
849 Builder.defineMacro("__AVX512BITALG__");
850 if (HasAVX512BW)
851 Builder.defineMacro("__AVX512BW__");
852 if (HasAVX512VL) {
853 Builder.defineMacro("__AVX512VL__");
854 }
855 if (HasAVX512VBMI)
856 Builder.defineMacro("__AVX512VBMI__");
857 if (HasAVX512VBMI2)
858 Builder.defineMacro("__AVX512VBMI2__");
859 if (HasAVX512IFMA)
860 Builder.defineMacro("__AVX512IFMA__");
861 if (HasAVX512VP2INTERSECT)
862 Builder.defineMacro("__AVX512VP2INTERSECT__");
863 if (HasSHA)
864 Builder.defineMacro("__SHA__");
865 if (HasSHA512)
866 Builder.defineMacro("__SHA512__");
867
868 if (HasFXSR)
869 Builder.defineMacro("__FXSR__");
870 if (HasXSAVE)
871 Builder.defineMacro("__XSAVE__");
872 if (HasXSAVEOPT)
873 Builder.defineMacro("__XSAVEOPT__");
874 if (HasXSAVEC)
875 Builder.defineMacro("__XSAVEC__");
876 if (HasXSAVES)
877 Builder.defineMacro("__XSAVES__");
878 if (HasPKU)
879 Builder.defineMacro("__PKU__");
880 if (HasCLFLUSHOPT)
881 Builder.defineMacro("__CLFLUSHOPT__");
882 if (HasCLWB)
883 Builder.defineMacro("__CLWB__");
884 if (HasWBNOINVD)
885 Builder.defineMacro("__WBNOINVD__");
886 if (HasSHSTK)
887 Builder.defineMacro("__SHSTK__");
888 if (HasSGX)
889 Builder.defineMacro("__SGX__");
890 if (HasSM3)
891 Builder.defineMacro("__SM3__");
892 if (HasSM4)
893 Builder.defineMacro("__SM4__");
894 if (HasPREFETCHI)
895 Builder.defineMacro("__PREFETCHI__");
896 if (HasCLZERO)
897 Builder.defineMacro("__CLZERO__");
898 if (HasKL)
899 Builder.defineMacro("__KL__");
900 if (HasWIDEKL)
901 Builder.defineMacro("__WIDEKL__");
902 if (HasRDPID)
903 Builder.defineMacro("__RDPID__");
904 if (HasRDPRU)
905 Builder.defineMacro("__RDPRU__");
906 if (HasCLDEMOTE)
907 Builder.defineMacro("__CLDEMOTE__");
908 if (HasWAITPKG)
909 Builder.defineMacro("__WAITPKG__");
910 if (HasMOVDIRI)
911 Builder.defineMacro("__MOVDIRI__");
912 if (HasMOVDIR64B)
913 Builder.defineMacro("__MOVDIR64B__");
914 if (HasMOVRS)
915 Builder.defineMacro("__MOVRS__");
916 if (HasPCONFIG)
917 Builder.defineMacro("__PCONFIG__");
918 if (HasPTWRITE)
919 Builder.defineMacro("__PTWRITE__");
920 if (HasINVPCID)
921 Builder.defineMacro("__INVPCID__");
922 if (HasENQCMD)
923 Builder.defineMacro("__ENQCMD__");
924 if (HasHRESET)
925 Builder.defineMacro("__HRESET__");
926 if (HasAMXTILE)
927 Builder.defineMacro("__AMX_TILE__");
928 if (HasAMXINT8)
929 Builder.defineMacro("__AMX_INT8__");
930 if (HasAMXBF16)
931 Builder.defineMacro("__AMX_BF16__");
932 if (HasAMXFP16)
933 Builder.defineMacro("__AMX_FP16__");
934 if (HasAMXCOMPLEX)
935 Builder.defineMacro("__AMX_COMPLEX__");
936 if (HasAMXFP8)
937 Builder.defineMacro("__AMX_FP8__");
938 if (HasAMXMOVRS)
939 Builder.defineMacro("__AMX_MOVRS__");
940 if (HasAMXAVX512)
941 Builder.defineMacro("__AMX_AVX512__");
942 if (HasAMXTF32)
943 Builder.defineMacro("__AMX_TF32__");
944 if (HasCMPCCXADD)
945 Builder.defineMacro("__CMPCCXADD__");
946 if (HasRAOINT)
947 Builder.defineMacro("__RAOINT__");
948 if (HasAVXIFMA)
949 Builder.defineMacro("__AVXIFMA__");
950 if (HasAVXNECONVERT)
951 Builder.defineMacro("__AVXNECONVERT__");
952 if (HasAVXVNNI)
953 Builder.defineMacro("__AVXVNNI__");
954 if (HasAVXVNNIINT16)
955 Builder.defineMacro("__AVXVNNIINT16__");
956 if (HasAVXVNNIINT8)
957 Builder.defineMacro("__AVXVNNIINT8__");
958 if (HasSERIALIZE)
959 Builder.defineMacro("__SERIALIZE__");
960 if (HasTSXLDTRK)
961 Builder.defineMacro("__TSXLDTRK__");
962 if (HasUINTR)
963 Builder.defineMacro("__UINTR__");
964 if (HasUSERMSR)
965 Builder.defineMacro("__USERMSR__");
966 if (HasCRC32)
967 Builder.defineMacro("__CRC32__");
968 if (HasEGPR)
969 Builder.defineMacro("__EGPR__");
970 if (HasPush2Pop2)
971 Builder.defineMacro("__PUSH2POP2__");
972 if (HasPPX)
973 Builder.defineMacro("__PPX__");
974 if (HasNDD)
975 Builder.defineMacro("__NDD__");
976 if (HasCCMP)
977 Builder.defineMacro("__CCMP__");
978 if (HasNF)
979 Builder.defineMacro("__NF__");
980 if (HasCF)
981 Builder.defineMacro("__CF__");
982 if (HasZU)
983 Builder.defineMacro("__ZU__");
984 if (HasJMPABS)
985 Builder.defineMacro("__JMPABS__");
986 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
987 HasZU && HasJMPABS)
988 Builder.defineMacro("__APX_F__");
989 if (HasEGPR && HasInlineAsmUseGPR32)
990 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
991
992 // Each case falls through to the previous one here.
993 switch (SSELevel) {
994 case AVX512F:
995 Builder.defineMacro("__AVX512F__");
996 [[fallthrough]];
997 case AVX2:
998 Builder.defineMacro("__AVX2__");
999 [[fallthrough]];
1000 case AVX:
1001 Builder.defineMacro("__AVX__");
1002 [[fallthrough]];
1003 case SSE42:
1004 Builder.defineMacro("__SSE4_2__");
1005 [[fallthrough]];
1006 case SSE41:
1007 Builder.defineMacro("__SSE4_1__");
1008 [[fallthrough]];
1009 case SSSE3:
1010 Builder.defineMacro("__SSSE3__");
1011 [[fallthrough]];
1012 case SSE3:
1013 Builder.defineMacro("__SSE3__");
1014 [[fallthrough]];
1015 case SSE2:
1016 Builder.defineMacro("__SSE2__");
1017 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1018 [[fallthrough]];
1019 case SSE1:
1020 Builder.defineMacro("__SSE__");
1021 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1022 [[fallthrough]];
1023 case NoSSE:
1024 break;
1025 }
1026
1027 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1028 switch (SSELevel) {
1029 case AVX512F:
1030 case AVX2:
1031 case AVX:
1032 case SSE42:
1033 case SSE41:
1034 case SSSE3:
1035 case SSE3:
1036 case SSE2:
1037 Builder.defineMacro("_M_IX86_FP", Twine(2));
1038 break;
1039 case SSE1:
1040 Builder.defineMacro("_M_IX86_FP", Twine(1));
1041 break;
1042 default:
1043 Builder.defineMacro("_M_IX86_FP", Twine(0));
1044 break;
1045 }
1046 }
1047
1048 // Each case falls through to the previous one here.
1049 if (HasMMX) {
1050 Builder.defineMacro("__MMX__");
1051 }
1052
1053 if (CPU >= CK_i486 || CPU == CK_None) {
1054 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1055 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1056 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1057 }
1058 if (HasCX8)
1059 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1060 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1061 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1062
1063 if (HasFloat128)
1064 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1065
1066 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1067 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1068 Opts.CFProtectionBranch});
1069}
1070
1071bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1072 return llvm::StringSwitch<bool>(Name)
1073 .Case("adx", true)
1074 .Case("aes", true)
1075 .Case("amx-avx512", true)
1076 .Case("amx-bf16", true)
1077 .Case("amx-complex", true)
1078 .Case("amx-fp16", true)
1079 .Case("amx-fp8", true)
1080 .Case("amx-int8", true)
1081 .Case("amx-movrs", true)
1082 .Case("amx-tf32", true)
1083 .Case("amx-tile", true)
1084 .Case("avx", true)
1085 .Case("avx10.1", true)
1086 .Case("avx10.2", true)
1087 .Case("avx2", true)
1088 .Case("avx512f", true)
1089 .Case("avx512cd", true)
1090 .Case("avx512vpopcntdq", true)
1091 .Case("avx512vnni", true)
1092 .Case("avx512bf16", true)
1093 .Case("avx512fp16", true)
1094 .Case("avx512dq", true)
1095 .Case("avx512bitalg", true)
1096 .Case("avx512bw", true)
1097 .Case("avx512vl", true)
1098 .Case("avx512vbmi", true)
1099 .Case("avx512vbmi2", true)
1100 .Case("avx512ifma", true)
1101 .Case("avx512vp2intersect", true)
1102 .Case("avxifma", true)
1103 .Case("avxneconvert", true)
1104 .Case("avxvnni", true)
1105 .Case("avxvnniint16", true)
1106 .Case("avxvnniint8", true)
1107 .Case("bmi", true)
1108 .Case("bmi2", true)
1109 .Case("cldemote", true)
1110 .Case("clflushopt", true)
1111 .Case("clwb", true)
1112 .Case("clzero", true)
1113 .Case("cmpccxadd", true)
1114 .Case("crc32", true)
1115 .Case("cx16", true)
1116 .Case("enqcmd", true)
1117 .Case("f16c", true)
1118 .Case("fma", true)
1119 .Case("fma4", true)
1120 .Case("fsgsbase", true)
1121 .Case("fxsr", true)
1122 .Case("general-regs-only", true)
1123 .Case("gfni", true)
1124 .Case("hreset", true)
1125 .Case("invpcid", true)
1126 .Case("kl", true)
1127 .Case("widekl", true)
1128 .Case("lwp", true)
1129 .Case("lzcnt", true)
1130 .Case("mmx", true)
1131 .Case("movbe", true)
1132 .Case("movrs", true)
1133 .Case("movdiri", true)
1134 .Case("movdir64b", true)
1135 .Case("mwaitx", true)
1136 .Case("pclmul", true)
1137 .Case("pconfig", true)
1138 .Case("pku", true)
1139 .Case("popcnt", true)
1140 .Case("prefer-256-bit", true)
1141 .Case("prefetchi", true)
1142 .Case("prfchw", true)
1143 .Case("ptwrite", true)
1144 .Case("raoint", true)
1145 .Case("rdpid", true)
1146 .Case("rdpru", true)
1147 .Case("rdrnd", true)
1148 .Case("rdseed", true)
1149 .Case("rtm", true)
1150 .Case("sahf", true)
1151 .Case("serialize", true)
1152 .Case("sgx", true)
1153 .Case("sha", true)
1154 .Case("sha512", true)
1155 .Case("shstk", true)
1156 .Case("sm3", true)
1157 .Case("sm4", true)
1158 .Case("sse", true)
1159 .Case("sse2", true)
1160 .Case("sse3", true)
1161 .Case("ssse3", true)
1162 .Case("sse4", true)
1163 .Case("sse4.1", true)
1164 .Case("sse4.2", true)
1165 .Case("sse4a", true)
1166 .Case("tbm", true)
1167 .Case("tsxldtrk", true)
1168 .Case("uintr", true)
1169 .Case("usermsr", true)
1170 .Case("vaes", true)
1171 .Case("vpclmulqdq", true)
1172 .Case("wbnoinvd", true)
1173 .Case("waitpkg", true)
1174 .Case("x87", true)
1175 .Case("xop", true)
1176 .Case("xsave", true)
1177 .Case("xsavec", true)
1178 .Case("xsaves", true)
1179 .Case("xsaveopt", true)
1180 .Case("egpr", true)
1181 .Case("push2pop2", true)
1182 .Case("ppx", true)
1183 .Case("ndd", true)
1184 .Case("ccmp", true)
1185 .Case("nf", true)
1186 .Case("cf", true)
1187 .Case("zu", true)
1188 .Case("jmpabs", true)
1189 .Default(false);
1190}
1191
1192bool X86TargetInfo::hasFeature(StringRef Feature) const {
1193 return llvm::StringSwitch<bool>(Feature)
1194 .Case("adx", HasADX)
1195 .Case("aes", HasAES)
1196 .Case("amx-avx512", HasAMXAVX512)
1197 .Case("amx-bf16", HasAMXBF16)
1198 .Case("amx-complex", HasAMXCOMPLEX)
1199 .Case("amx-fp16", HasAMXFP16)
1200 .Case("amx-fp8", HasAMXFP8)
1201 .Case("amx-int8", HasAMXINT8)
1202 .Case("amx-movrs", HasAMXMOVRS)
1203 .Case("amx-tf32", HasAMXTF32)
1204 .Case("amx-tile", HasAMXTILE)
1205 .Case("avx", SSELevel >= AVX)
1206 .Case("avx10.1", HasAVX10_1)
1207 .Case("avx10.2", HasAVX10_2)
1208 .Case("avx2", SSELevel >= AVX2)
1209 .Case("avx512f", SSELevel >= AVX512F)
1210 .Case("avx512cd", HasAVX512CD)
1211 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1212 .Case("avx512vnni", HasAVX512VNNI)
1213 .Case("avx512bf16", HasAVX512BF16)
1214 .Case("avx512fp16", HasAVX512FP16)
1215 .Case("avx512dq", HasAVX512DQ)
1216 .Case("avx512bitalg", HasAVX512BITALG)
1217 .Case("avx512bw", HasAVX512BW)
1218 .Case("avx512vl", HasAVX512VL)
1219 .Case("avx512vbmi", HasAVX512VBMI)
1220 .Case("avx512vbmi2", HasAVX512VBMI2)
1221 .Case("avx512ifma", HasAVX512IFMA)
1222 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1223 .Case("avxifma", HasAVXIFMA)
1224 .Case("avxneconvert", HasAVXNECONVERT)
1225 .Case("avxvnni", HasAVXVNNI)
1226 .Case("avxvnniint16", HasAVXVNNIINT16)
1227 .Case("avxvnniint8", HasAVXVNNIINT8)
1228 .Case("bmi", HasBMI)
1229 .Case("bmi2", HasBMI2)
1230 .Case("cldemote", HasCLDEMOTE)
1231 .Case("clflushopt", HasCLFLUSHOPT)
1232 .Case("clwb", HasCLWB)
1233 .Case("clzero", HasCLZERO)
1234 .Case("cmpccxadd", HasCMPCCXADD)
1235 .Case("crc32", HasCRC32)
1236 .Case("cx8", HasCX8)
1237 .Case("cx16", HasCX16)
1238 .Case("enqcmd", HasENQCMD)
1239 .Case("f16c", HasF16C)
1240 .Case("fma", HasFMA)
1241 .Case("fma4", XOPLevel >= FMA4)
1242 .Case("fsgsbase", HasFSGSBASE)
1243 .Case("fxsr", HasFXSR)
1244 .Case("gfni", HasGFNI)
1245 .Case("hreset", HasHRESET)
1246 .Case("invpcid", HasINVPCID)
1247 .Case("kl", HasKL)
1248 .Case("widekl", HasWIDEKL)
1249 .Case("lwp", HasLWP)
1250 .Case("lzcnt", HasLZCNT)
1251 .Case("mmx", HasMMX)
1252 .Case("movbe", HasMOVBE)
1253 .Case("movrs", HasMOVRS)
1254 .Case("movdiri", HasMOVDIRI)
1255 .Case("movdir64b", HasMOVDIR64B)
1256 .Case("mwaitx", HasMWAITX)
1257 .Case("pclmul", HasPCLMUL)
1258 .Case("pconfig", HasPCONFIG)
1259 .Case("pku", HasPKU)
1260 .Case("popcnt", HasPOPCNT)
1261 .Case("prefetchi", HasPREFETCHI)
1262 .Case("prfchw", HasPRFCHW)
1263 .Case("ptwrite", HasPTWRITE)
1264 .Case("raoint", HasRAOINT)
1265 .Case("rdpid", HasRDPID)
1266 .Case("rdpru", HasRDPRU)
1267 .Case("rdrnd", HasRDRND)
1268 .Case("rdseed", HasRDSEED)
1269 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1270 .Case("rtm", HasRTM)
1271 .Case("sahf", HasLAHFSAHF)
1272 .Case("serialize", HasSERIALIZE)
1273 .Case("sgx", HasSGX)
1274 .Case("sha", HasSHA)
1275 .Case("sha512", HasSHA512)
1276 .Case("shstk", HasSHSTK)
1277 .Case("sm3", HasSM3)
1278 .Case("sm4", HasSM4)
1279 .Case("sse", SSELevel >= SSE1)
1280 .Case("sse2", SSELevel >= SSE2)
1281 .Case("sse3", SSELevel >= SSE3)
1282 .Case("ssse3", SSELevel >= SSSE3)
1283 .Case("sse4.1", SSELevel >= SSE41)
1284 .Case("sse4.2", SSELevel >= SSE42)
1285 .Case("sse4a", XOPLevel >= SSE4A)
1286 .Case("tbm", HasTBM)
1287 .Case("tsxldtrk", HasTSXLDTRK)
1288 .Case("uintr", HasUINTR)
1289 .Case("usermsr", HasUSERMSR)
1290 .Case("vaes", HasVAES)
1291 .Case("vpclmulqdq", HasVPCLMULQDQ)
1292 .Case("wbnoinvd", HasWBNOINVD)
1293 .Case("waitpkg", HasWAITPKG)
1294 .Case("x86", true)
1295 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1296 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1297 .Case("x87", HasX87)
1298 .Case("xop", XOPLevel >= XOP)
1299 .Case("xsave", HasXSAVE)
1300 .Case("xsavec", HasXSAVEC)
1301 .Case("xsaves", HasXSAVES)
1302 .Case("xsaveopt", HasXSAVEOPT)
1303 .Case("fullbf16", HasFullBFloat16)
1304 .Case("egpr", HasEGPR)
1305 .Case("push2pop2", HasPush2Pop2)
1306 .Case("ppx", HasPPX)
1307 .Case("ndd", HasNDD)
1308 .Case("ccmp", HasCCMP)
1309 .Case("nf", HasNF)
1310 .Case("cf", HasCF)
1311 .Case("zu", HasZU)
1312 .Case("jmpabs", HasJMPABS)
1313 .Case("branch-hint", HasBranchHint)
1314 .Default(false);
1315}
1316
1317// We can't use a generic validation scheme for the features accepted here
1318// versus subtarget features accepted in the target attribute because the
1319// bitfield structure that's initialized in the runtime only supports the
1320// below currently rather than the full range of subtarget features. (See
1321// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1322bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1323 return llvm::StringSwitch<bool>(FeatureStr)
1324#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1325#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1326#include "llvm/TargetParser/X86TargetParser.def"
1327 .Default(false);
1328}
1329
1330static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1331 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1332#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1333 .Case(STR, llvm::X86::FEATURE_##ENUM)
1334
1335#include "llvm/TargetParser/X86TargetParser.def"
1336 ;
1337 // Note, this function should only be used after ensuring the value is
1338 // correct, so it asserts if the value is out of range.
1339}
1340
1341llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1342 auto getPriority = [](StringRef Feature) -> unsigned {
1343 // Valid CPUs have a 'key feature' that compares just better than its key
1344 // feature.
1345 using namespace llvm::X86;
1346 CPUKind Kind = parseArchX86(Feature);
1347 if (Kind != CK_None) {
1348 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1349 return (getFeaturePriority(KeyFeature) << 1) + 1;
1350 }
1351 // Now we know we have a feature, so get its priority and shift it a few so
1352 // that we have sufficient room for the CPUs (above).
1353 return getFeaturePriority(getFeature(Feature)) << 1;
1354 };
1355
1356 unsigned Priority = 0;
1357 for (StringRef Feature : Features)
1358 if (!Feature.empty())
1359 Priority = std::max(Priority, getPriority(Feature));
1360 return llvm::APInt(32, Priority);
1361}
1362
1363bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1364 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1365}
1366
1367char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1368 return llvm::X86::getCPUDispatchMangling(Name);
1369}
1370
1371void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1372 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1373 SmallVector<StringRef, 32> TargetCPUFeatures;
1374 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1375 for (auto &F : TargetCPUFeatures)
1376 Features.push_back(F);
1377}
1378
1379// We can't use a generic validation scheme for the cpus accepted here
1380// versus subtarget cpus accepted in the target attribute because the
1381// variables intitialized by the runtime only support the below currently
1382// rather than the full range of cpus.
1383bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1384 return llvm::StringSwitch<bool>(FeatureStr)
1385#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1386#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1387#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1388#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1389#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1390#include "llvm/TargetParser/X86TargetParser.def"
1391 .Default(false);
1392}
1393
1394static unsigned matchAsmCCConstraint(const char *Name) {
1395 auto RV = llvm::StringSwitch<unsigned>(Name)
1396 .Case("@cca", 4)
1397 .Case("@ccae", 5)
1398 .Case("@ccb", 4)
1399 .Case("@ccbe", 5)
1400 .Case("@ccc", 4)
1401 .Case("@cce", 4)
1402 .Case("@ccz", 4)
1403 .Case("@ccg", 4)
1404 .Case("@ccge", 5)
1405 .Case("@ccl", 4)
1406 .Case("@ccle", 5)
1407 .Case("@ccna", 5)
1408 .Case("@ccnae", 6)
1409 .Case("@ccnb", 5)
1410 .Case("@ccnbe", 6)
1411 .Case("@ccnc", 5)
1412 .Case("@ccne", 5)
1413 .Case("@ccnz", 5)
1414 .Case("@ccng", 5)
1415 .Case("@ccnge", 6)
1416 .Case("@ccnl", 5)
1417 .Case("@ccnle", 6)
1418 .Case("@ccno", 5)
1419 .Case("@ccnp", 5)
1420 .Case("@ccns", 5)
1421 .Case("@cco", 4)
1422 .Case("@ccp", 4)
1423 .Case("@ccs", 4)
1424 .Default(0);
1425 return RV;
1426}
1427
1428bool X86TargetInfo::validateAsmConstraint(
1429 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1430 switch (*Name) {
1431 default:
1432 return false;
1433 // Constant constraints.
1434 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1435 // instructions.
1436 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1437 // x86_64 instructions.
1438 case 's':
1439 Info.setRequiresImmediate();
1440 return true;
1441 case 'I':
1442 Info.setRequiresImmediate(0, 31);
1443 return true;
1444 case 'J':
1445 Info.setRequiresImmediate(0, 63);
1446 return true;
1447 case 'K':
1448 Info.setRequiresImmediate(-128, 127);
1449 return true;
1450 case 'L':
1451 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1452 return true;
1453 case 'M':
1454 Info.setRequiresImmediate(0, 3);
1455 return true;
1456 case 'N':
1457 Info.setRequiresImmediate(0, 255);
1458 return true;
1459 case 'O':
1460 Info.setRequiresImmediate(0, 127);
1461 return true;
1462 case 'W':
1463 switch (*++Name) {
1464 default:
1465 return false;
1466 case 's':
1467 Info.setAllowsRegister();
1468 return true;
1469 }
1470 // Register constraints.
1471 case 'Y': // 'Y' is the first character for several 2-character constraints.
1472 // Shift the pointer to the second character of the constraint.
1473 Name++;
1474 switch (*Name) {
1475 default:
1476 return false;
1477 case 'z': // First SSE register.
1478 case '2':
1479 case 't': // Any SSE register, when SSE2 is enabled.
1480 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1481 case 'm': // Any MMX register, when inter-unit moves enabled.
1482 case 'k': // AVX512 arch mask registers: k1-k7.
1483 Info.setAllowsRegister();
1484 return true;
1485 }
1486 case 'f': // Any x87 floating point stack register.
1487 // Constraint 'f' cannot be used for output operands.
1488 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1489 return false;
1490 Info.setAllowsRegister();
1491 return true;
1492 case 'a': // eax.
1493 case 'b': // ebx.
1494 case 'c': // ecx.
1495 case 'd': // edx.
1496 case 'S': // esi.
1497 case 'D': // edi.
1498 case 'A': // edx:eax.
1499 case 't': // Top of floating point stack.
1500 case 'u': // Second from top of floating point stack.
1501 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1502 case 'y': // Any MMX register.
1503 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1504 case 'x': // Any SSE register.
1505 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1506 // for intermideate k reg operations).
1507 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1508 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1509 case 'l': // "Index" registers: any general register that can be used as an
1510 // index in a base+index memory access.
1511 Info.setAllowsRegister();
1512 return true;
1513 // Floating point constant constraints.
1514 case 'C': // SSE floating point constant.
1515 case 'G': // x87 floating point constant.
1516 return true;
1517 case 'j':
1518 Name++;
1519 switch (*Name) {
1520 default:
1521 return false;
1522 case 'r':
1523 Info.setAllowsRegister();
1524 return true;
1525 case 'R':
1526 Info.setAllowsRegister();
1527 return true;
1528 }
1529 case '@':
1530 // CC condition changes.
1531 if (auto Len = matchAsmCCConstraint(Name)) {
1532 Name += Len - 1;
1533 Info.setAllowsRegister();
1534 Info.setOutputOperandBounds(0, 2);
1535 return true;
1536 }
1537 return false;
1538 }
1539}
1540
1541// Below is based on the following information:
1542// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1543// | Processor Name | Cache Line Size (Bytes) | Source |
1544// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1545// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1546// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1547// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1548// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1549// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1550// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1551// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1552// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1553// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1554// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1555// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1556// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1557// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1558// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1559// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1560// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1561// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1562// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1563std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1564 using namespace llvm::X86;
1565 switch (CPU) {
1566 // i386
1567 case CK_i386:
1568 // i486
1569 case CK_i486:
1570 case CK_WinChipC6:
1571 case CK_WinChip2:
1572 case CK_C3:
1573 // Lakemont
1574 case CK_Lakemont:
1575 return 16;
1576
1577 // i586
1578 case CK_i586:
1579 case CK_Pentium:
1580 case CK_PentiumMMX:
1581 // i686
1582 case CK_PentiumPro:
1583 case CK_i686:
1584 case CK_Pentium2:
1585 case CK_Pentium3:
1586 case CK_PentiumM:
1587 case CK_C3_2:
1588 // K6
1589 case CK_K6:
1590 case CK_K6_2:
1591 case CK_K6_3:
1592 // Geode
1593 case CK_Geode:
1594 return 32;
1595
1596 // Netburst
1597 case CK_Pentium4:
1598 case CK_Prescott:
1599 case CK_Nocona:
1600 // Atom
1601 case CK_Bonnell:
1602 case CK_Silvermont:
1603 case CK_Goldmont:
1604 case CK_GoldmontPlus:
1605 case CK_Tremont:
1606 case CK_Gracemont:
1607
1608 case CK_Westmere:
1609 case CK_SandyBridge:
1610 case CK_IvyBridge:
1611 case CK_Haswell:
1612 case CK_Broadwell:
1613 case CK_SkylakeClient:
1614 case CK_SkylakeServer:
1615 case CK_Cascadelake:
1616 case CK_Nehalem:
1617 case CK_Cooperlake:
1618 case CK_Cannonlake:
1619 case CK_Tigerlake:
1620 case CK_SapphireRapids:
1621 case CK_IcelakeClient:
1622 case CK_Rocketlake:
1623 case CK_IcelakeServer:
1624 case CK_Alderlake:
1625 case CK_Raptorlake:
1626 case CK_Meteorlake:
1627 case CK_Arrowlake:
1628 case CK_ArrowlakeS:
1629 case CK_Lunarlake:
1630 case CK_Pantherlake:
1631 case CK_Wildcatlake:
1632 case CK_Novalake:
1633 case CK_Sierraforest:
1634 case CK_Grandridge:
1635 case CK_Graniterapids:
1636 case CK_GraniterapidsD:
1637 case CK_Emeraldrapids:
1638 case CK_Clearwaterforest:
1639 case CK_Diamondrapids:
1640 case CK_KNL:
1641 case CK_KNM:
1642 // K7
1643 case CK_Athlon:
1644 case CK_AthlonXP:
1645 // K8
1646 case CK_K8:
1647 case CK_K8SSE3:
1648 case CK_AMDFAM10:
1649 // Bobcat
1650 case CK_BTVER1:
1651 case CK_BTVER2:
1652 // Bulldozer
1653 case CK_BDVER1:
1654 case CK_BDVER2:
1655 case CK_BDVER3:
1656 case CK_BDVER4:
1657 // Zen
1658 case CK_ZNVER1:
1659 case CK_ZNVER2:
1660 case CK_ZNVER3:
1661 case CK_ZNVER4:
1662 case CK_ZNVER5:
1663 case CK_ZNVER6:
1664 // Hygon
1665 case CK_C86_4G_M4:
1666 case CK_C86_4G_M6:
1667 case CK_C86_4G_M7:
1668 // Deprecated
1669 case CK_x86_64:
1670 case CK_x86_64_v2:
1671 case CK_x86_64_v3:
1672 case CK_x86_64_v4:
1673 case CK_Yonah:
1674 case CK_Penryn:
1675 case CK_Core2:
1676 return 64;
1677
1678 // The following currently have unknown cache line sizes (but they are probably all 64):
1679 // Core
1680 case CK_None:
1681 return std::nullopt;
1682 }
1683 llvm_unreachable("Unknown CPU kind");
1684}
1685
1686bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1687 StringRef Constraint,
1688 unsigned Size) const {
1689 // Strip off constraint modifiers.
1690 Constraint = Constraint.ltrim("=+&");
1691
1692 return validateOperandSize(FeatureMap, Constraint, Size);
1693}
1694
1695bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1696 StringRef Constraint,
1697 unsigned Size) const {
1698 return validateOperandSize(FeatureMap, Constraint, Size);
1699}
1700
1701bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1702 StringRef Constraint,
1703 unsigned Size) const {
1704 switch (Constraint[0]) {
1705 default:
1706 break;
1707 case 'k':
1708 // Registers k0-k7 (AVX512) size limit is 64 bit.
1709 case 'y':
1710 return Size <= 64;
1711 case 'f':
1712 case 't':
1713 case 'u':
1714 return Size <= 128;
1715 case 'Y':
1716 // 'Y' is the first character for several 2-character constraints.
1717 switch (Constraint[1]) {
1718 default:
1719 return false;
1720 case 'm':
1721 // 'Ym' is synonymous with 'y'.
1722 case 'k':
1723 return Size <= 64;
1724 case 'z':
1725 // XMM0/YMM/ZMM0
1726 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1727 // ZMM0 can be used if target supports AVX512F.
1728 return Size <= 512U;
1729 else if (hasFeatureEnabled(FeatureMap, "avx"))
1730 // YMM0 can be used if target supports AVX.
1731 return Size <= 256U;
1732 else if (hasFeatureEnabled(FeatureMap, "sse"))
1733 return Size <= 128U;
1734 return false;
1735 case 'i':
1736 case 't':
1737 case '2':
1738 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1739 if (SSELevel < SSE2)
1740 return false;
1741 break;
1742 }
1743 break;
1744 case 'v':
1745 case 'x':
1746 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1747 // 512-bit zmm registers can be used if target supports AVX512F.
1748 return Size <= 512U;
1749 else if (hasFeatureEnabled(FeatureMap, "avx"))
1750 // 256-bit ymm registers can be used if target supports AVX.
1751 return Size <= 256U;
1752 return Size <= 128U;
1753
1754 }
1755
1756 return true;
1757}
1758
1759std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1760 switch (*Constraint) {
1761 case '@':
1762 if (auto Len = matchAsmCCConstraint(Constraint)) {
1763 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1764 Constraint += Len - 1;
1765 return Converted;
1766 }
1767 return std::string(1, *Constraint);
1768 case 'a':
1769 return std::string("{ax}");
1770 case 'b':
1771 return std::string("{bx}");
1772 case 'c':
1773 return std::string("{cx}");
1774 case 'd':
1775 return std::string("{dx}");
1776 case 'S':
1777 return std::string("{si}");
1778 case 'D':
1779 return std::string("{di}");
1780 case 'p': // Keep 'p' constraint (address).
1781 return std::string("p");
1782 case 't': // top of floating point stack.
1783 return std::string("{st}");
1784 case 'u': // second from top of floating point stack.
1785 return std::string("{st(1)}"); // second from top of floating point stack.
1786 case 'W':
1787 assert(Constraint[1] == 's');
1788 return '^' + std::string(Constraint++, 2);
1789 case 'Y':
1790 switch (Constraint[1]) {
1791 default:
1792 // Break from inner switch and fall through (copy single char),
1793 // continue parsing after copying the current constraint into
1794 // the return string.
1795 break;
1796 case 'k':
1797 case 'm':
1798 case 'i':
1799 case 't':
1800 case 'z':
1801 case '2':
1802 // "^" hints llvm that this is a 2 letter constraint.
1803 // "Constraint++" is used to promote the string iterator
1804 // to the next constraint.
1805 return std::string("^") + std::string(Constraint++, 2);
1806 }
1807 [[fallthrough]];
1808 case 'j':
1809 switch (Constraint[1]) {
1810 default:
1811 // Break from inner switch and fall through (copy single char),
1812 // continue parsing after copying the current constraint into
1813 // the return string.
1814 break;
1815 case 'r':
1816 case 'R':
1817 // "^" hints llvm that this is a 2 letter constraint.
1818 // "Constraint++" is used to promote the string iterator
1819 // to the next constraint.
1820 return std::string("^") + std::string(Constraint++, 2);
1821 }
1822 [[fallthrough]];
1823 default:
1824 return std::string(1, *Constraint);
1825 }
1826}
1827
1828void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1829 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1830 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1831}
1832
1833void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1834 llvm::X86::fillValidTuneCPUList(Values);
1835}
1836
1840
1844
1845llvm::SmallVector<Builtin::InfosShard>
1846X86_32TargetInfo::getTargetBuiltins() const {
1847 return {
1848 {&X86::BuiltinStrings, X86::BuiltinInfos},
1849 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1850 };
1851}
1852
1853llvm::SmallVector<Builtin::InfosShard>
1854X86_64TargetInfo::getTargetBuiltins() const {
1855 return {
1856 {&X86::BuiltinStrings, X86::BuiltinInfos},
1857 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1858 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1859 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1860 "__builtin_ia32_"},
1861 };
1862}
1863
1864unsigned
1865MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1866 bool HasNonWeakDef) const {
1867 unsigned Align =
1868 WindowsX86_64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1869
1870 return std::max(Align, Microsoft64BitMinGlobalAlign(TypeSize));
1871}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1559
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:232
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1330
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:233
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1580
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:327
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1323
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1452
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:760
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:568
clang::targets::MicrosoftX86_64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition X86.cpp:1865
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:233
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1563
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1428
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1341
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1837
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1367
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1759
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:508
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1371
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1383
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1686
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1701
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1833
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1363
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1322
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1071
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1192
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:214
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:186
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1828
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1841
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1695
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1846
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1854
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Microsoft64BitMinGlobalAlign
unsigned Microsoft64BitMinGlobalAlign(uint64_t TypeSize)
Definition TargetInfo.cpp:1121
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:80
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1234
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1198
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:144
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