clang 19.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/TargetParser/X86TargetParser.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26static constexpr Builtin::Info BuiltinInfoX86[] = {
27#define BUILTIN(ID, TYPE, ATTRS) \
28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
29#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
31#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
33#include "clang/Basic/BuiltinsX86.def"
34
35#define BUILTIN(ID, TYPE, ATTRS) \
36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
37#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
39#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
41#include "clang/Basic/BuiltinsX86_64.def"
42};
43
44static const char *const GCCRegNames[] = {
45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62 "k2", "k3", "k4", "k5", "k6", "k7",
63 "cr0", "cr2", "cr3", "cr4", "cr8",
64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65 "bnd0", "bnd1", "bnd2", "bnd3",
66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
67};
68
70 {{"al", "ah", "eax", "rax"}, 0},
71 {{"bl", "bh", "ebx", "rbx"}, 3},
72 {{"cl", "ch", "ecx", "rcx"}, 2},
73 {{"dl", "dh", "edx", "rdx"}, 1},
74 {{"esi", "rsi"}, 4},
75 {{"edi", "rdi"}, 5},
76 {{"esp", "rsp"}, 7},
77 {{"ebp", "rbp"}, 6},
78 {{"r8d", "r8w", "r8b"}, 38},
79 {{"r9d", "r9w", "r9b"}, 39},
80 {{"r10d", "r10w", "r10b"}, 40},
81 {{"r11d", "r11w", "r11b"}, 41},
82 {{"r12d", "r12w", "r12b"}, 42},
83 {{"r13d", "r13w", "r13b"}, 43},
84 {{"r14d", "r14w", "r14b"}, 44},
85 {{"r15d", "r15w", "r15b"}, 45},
86};
87
88} // namespace targets
89} // namespace clang
90
91using namespace clang;
92using namespace clang::targets;
93
94bool X86TargetInfo::setFPMath(StringRef Name) {
95 if (Name == "387") {
96 FPMath = FP_387;
97 return true;
98 }
99 if (Name == "sse") {
100 FPMath = FP_SSE;
101 return true;
102 }
103 return false;
104}
105
107 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
108 const std::vector<std::string> &FeaturesVec) const {
109 // FIXME: This *really* should not be here.
110 // X86_64 always has SSE2.
111 if (getTriple().getArch() == llvm::Triple::x86_64)
112 setFeatureEnabled(Features, "sse2", true);
113
114 using namespace llvm::X86;
115
116 SmallVector<StringRef, 16> CPUFeatures;
117 getFeaturesForCPU(CPU, CPUFeatures);
118 for (auto &F : CPUFeatures)
119 setFeatureEnabled(Features, F, true);
120
121 std::vector<std::string> UpdatedFeaturesVec;
122 std::vector<std::string> UpdatedAVX10FeaturesVec;
123 enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
124 int HasEVEX512 = FE_NOSET;
125 bool HasAVX512F = Features.lookup("avx512f");
126 bool HasAVX10 = Features.lookup("avx10.1-256");
127 bool HasAVX10_512 = Features.lookup("avx10.1-512");
128 std::string LastAVX10;
129 std::string LastAVX512;
130 for (const auto &Feature : FeaturesVec) {
131 // Expand general-regs-only to -x86, -mmx and -sse
132 if (Feature == "+general-regs-only") {
133 UpdatedFeaturesVec.push_back("-x87");
134 UpdatedFeaturesVec.push_back("-mmx");
135 UpdatedFeaturesVec.push_back("-sse");
136 continue;
137 }
138
139 if (Feature.substr(1, 6) == "avx10.") {
140 if (Feature[0] == '+') {
141 HasAVX10 = true;
142 if (StringRef(Feature).ends_with("512"))
143 HasAVX10_512 = true;
144 LastAVX10 = Feature;
145 } else if (HasAVX10 && Feature == "-avx10.1-256") {
146 HasAVX10 = false;
147 HasAVX10_512 = false;
148 } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
149 HasAVX10_512 = false;
150 }
151 // Postpone AVX10 features handling after AVX512 settled.
152 UpdatedAVX10FeaturesVec.push_back(Feature);
153 continue;
154 } else if (!HasAVX512F && StringRef(Feature).starts_with("+avx512")) {
155 HasAVX512F = true;
156 LastAVX512 = Feature;
157 } else if (HasAVX512F && Feature == "-avx512f") {
158 HasAVX512F = false;
159 } else if (HasEVEX512 != FE_TRUE && Feature == "+evex512") {
160 HasEVEX512 = FE_TRUE;
161 continue;
162 } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512") {
163 HasEVEX512 = FE_FALSE;
164 continue;
165 }
166
167 UpdatedFeaturesVec.push_back(Feature);
168 }
169 llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec);
170 // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512
171 // according to other features.
172 if (HasAVX512F) {
173 UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512"
174 : "+evex512");
175 if (HasAVX10 && !HasAVX10_512 && HasEVEX512 != FE_FALSE)
176 Diags.Report(diag::warn_invalid_feature_combination)
177 << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512";
178 } else if (HasAVX10) {
179 if (HasEVEX512 != FE_NOSET)
180 Diags.Report(diag::warn_invalid_feature_combination)
181 << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512");
182 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512");
183 }
184
185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
186 return false;
187
188 // Can't do this earlier because we need to be able to explicitly enable
189 // or disable these features and the things that they depend upon.
190
191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
192 auto I = Features.find("sse4.2");
193 if (I != Features.end() && I->getValue() &&
194 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
195 Features["popcnt"] = true;
196
197 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
198 // then enable MMX.
199 I = Features.find("sse");
200 if (I != Features.end() && I->getValue() &&
201 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
202 Features["mmx"] = true;
203
204 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
205 I = Features.find("avx");
206 if (I != Features.end() && I->getValue() &&
207 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
208 Features["xsave"] = true;
209
210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
211 I = Features.find("sse4.2");
212 if (I != Features.end() && I->getValue() &&
213 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
214 Features["crc32"] = true;
215
216 return true;
217}
218
219void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
220 StringRef Name, bool Enabled) const {
221 if (Name == "sse4") {
222 // We can get here via the __target__ attribute since that's not controlled
223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
225 // disabled.
226 if (Enabled)
227 Name = "sse4.2";
228 else
229 Name = "sse4.1";
230 }
231
232 Features[Name] = Enabled;
233 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
234}
235
236/// handleTargetFeatures - Perform initialization based on the user
237/// configured set of features.
238bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
239 DiagnosticsEngine &Diags) {
240 for (const auto &Feature : Features) {
241 if (Feature[0] != '+')
242 continue;
243
244 if (Feature == "+aes") {
245 HasAES = true;
246 } else if (Feature == "+vaes") {
247 HasVAES = true;
248 } else if (Feature == "+pclmul") {
249 HasPCLMUL = true;
250 } else if (Feature == "+vpclmulqdq") {
251 HasVPCLMULQDQ = true;
252 } else if (Feature == "+lzcnt") {
253 HasLZCNT = true;
254 } else if (Feature == "+rdrnd") {
255 HasRDRND = true;
256 } else if (Feature == "+fsgsbase") {
257 HasFSGSBASE = true;
258 } else if (Feature == "+bmi") {
259 HasBMI = true;
260 } else if (Feature == "+bmi2") {
261 HasBMI2 = true;
262 } else if (Feature == "+popcnt") {
263 HasPOPCNT = true;
264 } else if (Feature == "+rtm") {
265 HasRTM = true;
266 } else if (Feature == "+prfchw") {
267 HasPRFCHW = true;
268 } else if (Feature == "+rdseed") {
269 HasRDSEED = true;
270 } else if (Feature == "+adx") {
271 HasADX = true;
272 } else if (Feature == "+tbm") {
273 HasTBM = true;
274 } else if (Feature == "+lwp") {
275 HasLWP = true;
276 } else if (Feature == "+fma") {
277 HasFMA = true;
278 } else if (Feature == "+f16c") {
279 HasF16C = true;
280 } else if (Feature == "+gfni") {
281 HasGFNI = true;
282 } else if (Feature == "+evex512") {
283 HasEVEX512 = true;
284 } else if (Feature == "+avx10.1-256") {
285 HasAVX10_1 = true;
286 } else if (Feature == "+avx10.1-512") {
287 HasAVX10_1_512 = true;
288 } else if (Feature == "+avx512cd") {
289 HasAVX512CD = true;
290 } else if (Feature == "+avx512vpopcntdq") {
291 HasAVX512VPOPCNTDQ = true;
292 } else if (Feature == "+avx512vnni") {
293 HasAVX512VNNI = true;
294 } else if (Feature == "+avx512bf16") {
295 HasAVX512BF16 = true;
296 } else if (Feature == "+avx512er") {
297 HasAVX512ER = true;
298 Diags.Report(diag::warn_knl_knm_isa_support_removed);
299 } else if (Feature == "+avx512fp16") {
300 HasAVX512FP16 = true;
301 HasLegalHalfType = true;
302 } else if (Feature == "+avx512pf") {
303 HasAVX512PF = true;
304 Diags.Report(diag::warn_knl_knm_isa_support_removed);
305 } else if (Feature == "+avx512dq") {
306 HasAVX512DQ = true;
307 } else if (Feature == "+avx512bitalg") {
308 HasAVX512BITALG = true;
309 } else if (Feature == "+avx512bw") {
310 HasAVX512BW = true;
311 } else if (Feature == "+avx512vl") {
312 HasAVX512VL = true;
313 } else if (Feature == "+avx512vbmi") {
314 HasAVX512VBMI = true;
315 } else if (Feature == "+avx512vbmi2") {
316 HasAVX512VBMI2 = true;
317 } else if (Feature == "+avx512ifma") {
318 HasAVX512IFMA = true;
319 } else if (Feature == "+avx512vp2intersect") {
320 HasAVX512VP2INTERSECT = true;
321 } else if (Feature == "+sha") {
322 HasSHA = true;
323 } else if (Feature == "+sha512") {
324 HasSHA512 = true;
325 } else if (Feature == "+shstk") {
326 HasSHSTK = true;
327 } else if (Feature == "+sm3") {
328 HasSM3 = true;
329 } else if (Feature == "+sm4") {
330 HasSM4 = true;
331 } else if (Feature == "+movbe") {
332 HasMOVBE = true;
333 } else if (Feature == "+sgx") {
334 HasSGX = true;
335 } else if (Feature == "+cx8") {
336 HasCX8 = true;
337 } else if (Feature == "+cx16") {
338 HasCX16 = true;
339 } else if (Feature == "+fxsr") {
340 HasFXSR = true;
341 } else if (Feature == "+xsave") {
342 HasXSAVE = true;
343 } else if (Feature == "+xsaveopt") {
344 HasXSAVEOPT = true;
345 } else if (Feature == "+xsavec") {
346 HasXSAVEC = true;
347 } else if (Feature == "+xsaves") {
348 HasXSAVES = true;
349 } else if (Feature == "+mwaitx") {
350 HasMWAITX = true;
351 } else if (Feature == "+pku") {
352 HasPKU = true;
353 } else if (Feature == "+clflushopt") {
354 HasCLFLUSHOPT = true;
355 } else if (Feature == "+clwb") {
356 HasCLWB = true;
357 } else if (Feature == "+wbnoinvd") {
358 HasWBNOINVD = true;
359 } else if (Feature == "+prefetchi") {
360 HasPREFETCHI = true;
361 } else if (Feature == "+prefetchwt1") {
362 HasPREFETCHWT1 = true;
363 Diags.Report(diag::warn_knl_knm_isa_support_removed);
364 } else if (Feature == "+clzero") {
365 HasCLZERO = true;
366 } else if (Feature == "+cldemote") {
367 HasCLDEMOTE = true;
368 } else if (Feature == "+rdpid") {
369 HasRDPID = true;
370 } else if (Feature == "+rdpru") {
371 HasRDPRU = true;
372 } else if (Feature == "+kl") {
373 HasKL = true;
374 } else if (Feature == "+widekl") {
375 HasWIDEKL = true;
376 } else if (Feature == "+retpoline-external-thunk") {
377 HasRetpolineExternalThunk = true;
378 } else if (Feature == "+sahf") {
379 HasLAHFSAHF = true;
380 } else if (Feature == "+waitpkg") {
381 HasWAITPKG = true;
382 } else if (Feature == "+movdiri") {
383 HasMOVDIRI = true;
384 } else if (Feature == "+movdir64b") {
385 HasMOVDIR64B = true;
386 } else if (Feature == "+pconfig") {
387 HasPCONFIG = true;
388 } else if (Feature == "+ptwrite") {
389 HasPTWRITE = true;
390 } else if (Feature == "+invpcid") {
391 HasINVPCID = true;
392 } else if (Feature == "+enqcmd") {
393 HasENQCMD = true;
394 } else if (Feature == "+hreset") {
395 HasHRESET = true;
396 } else if (Feature == "+amx-bf16") {
397 HasAMXBF16 = true;
398 } else if (Feature == "+amx-fp16") {
399 HasAMXFP16 = true;
400 } else if (Feature == "+amx-int8") {
401 HasAMXINT8 = true;
402 } else if (Feature == "+amx-tile") {
403 HasAMXTILE = true;
404 } else if (Feature == "+amx-complex") {
405 HasAMXCOMPLEX = true;
406 } else if (Feature == "+cmpccxadd") {
407 HasCMPCCXADD = true;
408 } else if (Feature == "+raoint") {
409 HasRAOINT = true;
410 } else if (Feature == "+avxifma") {
411 HasAVXIFMA = true;
412 } else if (Feature == "+avxneconvert") {
413 HasAVXNECONVERT= true;
414 } else if (Feature == "+avxvnni") {
415 HasAVXVNNI = true;
416 } else if (Feature == "+avxvnniint16") {
417 HasAVXVNNIINT16 = true;
418 } else if (Feature == "+avxvnniint8") {
419 HasAVXVNNIINT8 = true;
420 } else if (Feature == "+serialize") {
421 HasSERIALIZE = true;
422 } else if (Feature == "+tsxldtrk") {
423 HasTSXLDTRK = true;
424 } else if (Feature == "+uintr") {
425 HasUINTR = true;
426 } else if (Feature == "+usermsr") {
427 HasUSERMSR = true;
428 } else if (Feature == "+crc32") {
429 HasCRC32 = true;
430 } else if (Feature == "+x87") {
431 HasX87 = true;
432 } else if (Feature == "+fullbf16") {
433 HasFullBFloat16 = true;
434 } else if (Feature == "+egpr") {
435 HasEGPR = true;
436 } else if (Feature == "+push2pop2") {
437 HasPush2Pop2 = true;
438 } else if (Feature == "+ppx") {
439 HasPPX = true;
440 } else if (Feature == "+ndd") {
441 HasNDD = true;
442 } else if (Feature == "+ccmp") {
443 HasCCMP = true;
444 } else if (Feature == "+cf") {
445 HasCF = true;
446 }
447
448 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
449 .Case("+avx512f", AVX512F)
450 .Case("+avx2", AVX2)
451 .Case("+avx", AVX)
452 .Case("+sse4.2", SSE42)
453 .Case("+sse4.1", SSE41)
454 .Case("+ssse3", SSSE3)
455 .Case("+sse3", SSE3)
456 .Case("+sse2", SSE2)
457 .Case("+sse", SSE1)
458 .Default(NoSSE);
459 SSELevel = std::max(SSELevel, Level);
460
461 HasFloat16 = SSELevel >= SSE2;
462
463 // X86 target has bfloat16 emulation support in the backend, where
464 // bfloat16 is treated as a 32-bit float, arithmetic operations are
465 // performed in 32-bit, and the result is converted back to bfloat16.
466 // Truncation and extension between bfloat16 and 32-bit float are supported
467 // by the compiler-rt library. However, native bfloat16 support is currently
468 // not available in the X86 target. Hence, HasFullBFloat16 will be false
469 // until native bfloat16 support is available. HasFullBFloat16 is used to
470 // determine whether to automatically use excess floating point precision
471 // for bfloat16 arithmetic operations in the front-end.
472 HasBFloat16 = SSELevel >= SSE2;
473
474 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
475 .Case("+3dnowa", AMD3DNowAthlon)
476 .Case("+3dnow", AMD3DNow)
477 .Case("+mmx", MMX)
478 .Default(NoMMX3DNow);
479 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
480
481 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
482 .Case("+xop", XOP)
483 .Case("+fma4", FMA4)
484 .Case("+sse4a", SSE4A)
485 .Default(NoXOP);
486 XOPLevel = std::max(XOPLevel, XLevel);
487 }
488
489 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
490 // matches the selected sse level.
491 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
492 (FPMath == FP_387 && SSELevel >= SSE1)) {
493 Diags.Report(diag::err_target_unsupported_fpmath)
494 << (FPMath == FP_SSE ? "sse" : "387");
495 return false;
496 }
497
498 // FIXME: We should allow long double type on 32-bits to match with GCC.
499 // This requires backend to be able to lower f80 without x87 first.
500 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
501 HasLongDouble = false;
502
503 return true;
504}
505
506/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
507/// definitions for this particular subtarget.
509 MacroBuilder &Builder) const {
510 // Inline assembly supports X86 flag outputs.
511 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
512
513 std::string CodeModel = getTargetOpts().CodeModel;
514 if (CodeModel == "default")
515 CodeModel = "small";
516 Builder.defineMacro("__code_model_" + CodeModel + "__");
517
518 // Target identification.
519 if (getTriple().getArch() == llvm::Triple::x86_64) {
520 Builder.defineMacro("__amd64__");
521 Builder.defineMacro("__amd64");
522 Builder.defineMacro("__x86_64");
523 Builder.defineMacro("__x86_64__");
524 if (getTriple().getArchName() == "x86_64h") {
525 Builder.defineMacro("__x86_64h");
526 Builder.defineMacro("__x86_64h__");
527 }
528 } else {
529 DefineStd(Builder, "i386", Opts);
530 }
531
532 Builder.defineMacro("__SEG_GS");
533 Builder.defineMacro("__SEG_FS");
534 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
535 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
536
537 // Subtarget options.
538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
539 // truly should be based on -mtune options.
540 using namespace llvm::X86;
541 switch (CPU) {
542 case CK_None:
543 break;
544 case CK_i386:
545 // The rest are coming from the i386 define above.
546 Builder.defineMacro("__tune_i386__");
547 break;
548 case CK_i486:
549 case CK_WinChipC6:
550 case CK_WinChip2:
551 case CK_C3:
552 defineCPUMacros(Builder, "i486");
553 break;
554 case CK_PentiumMMX:
555 Builder.defineMacro("__pentium_mmx__");
556 Builder.defineMacro("__tune_pentium_mmx__");
557 [[fallthrough]];
558 case CK_i586:
559 case CK_Pentium:
560 defineCPUMacros(Builder, "i586");
561 defineCPUMacros(Builder, "pentium");
562 break;
563 case CK_Pentium3:
564 case CK_PentiumM:
565 Builder.defineMacro("__tune_pentium3__");
566 [[fallthrough]];
567 case CK_Pentium2:
568 case CK_C3_2:
569 Builder.defineMacro("__tune_pentium2__");
570 [[fallthrough]];
571 case CK_PentiumPro:
572 case CK_i686:
573 defineCPUMacros(Builder, "i686");
574 defineCPUMacros(Builder, "pentiumpro");
575 break;
576 case CK_Pentium4:
577 defineCPUMacros(Builder, "pentium4");
578 break;
579 case CK_Yonah:
580 case CK_Prescott:
581 case CK_Nocona:
582 defineCPUMacros(Builder, "nocona");
583 break;
584 case CK_Core2:
585 case CK_Penryn:
586 defineCPUMacros(Builder, "core2");
587 break;
588 case CK_Bonnell:
589 defineCPUMacros(Builder, "atom");
590 break;
591 case CK_Silvermont:
592 defineCPUMacros(Builder, "slm");
593 break;
594 case CK_Goldmont:
595 defineCPUMacros(Builder, "goldmont");
596 break;
597 case CK_GoldmontPlus:
598 defineCPUMacros(Builder, "goldmont_plus");
599 break;
600 case CK_Tremont:
601 defineCPUMacros(Builder, "tremont");
602 break;
603 // Gracemont and later atom-cores use P-core cpu macros.
604 case CK_Gracemont:
605 case CK_Nehalem:
606 case CK_Westmere:
607 case CK_SandyBridge:
608 case CK_IvyBridge:
609 case CK_Haswell:
610 case CK_Broadwell:
611 case CK_SkylakeClient:
612 case CK_SkylakeServer:
613 case CK_Cascadelake:
614 case CK_Cooperlake:
615 case CK_Cannonlake:
616 case CK_IcelakeClient:
617 case CK_Rocketlake:
618 case CK_IcelakeServer:
619 case CK_Tigerlake:
620 case CK_SapphireRapids:
621 case CK_Alderlake:
622 case CK_Raptorlake:
623 case CK_Meteorlake:
624 case CK_Arrowlake:
625 case CK_ArrowlakeS:
626 case CK_Lunarlake:
627 case CK_Pantherlake:
628 case CK_Sierraforest:
629 case CK_Grandridge:
630 case CK_Graniterapids:
631 case CK_GraniterapidsD:
632 case CK_Emeraldrapids:
633 case CK_Clearwaterforest:
634 // FIXME: Historically, we defined this legacy name, it would be nice to
635 // remove it at some point. We've never exposed fine-grained names for
636 // recent primary x86 CPUs, and we should keep it that way.
637 defineCPUMacros(Builder, "corei7");
638 break;
639 case CK_KNL:
640 defineCPUMacros(Builder, "knl");
641 break;
642 case CK_KNM:
643 break;
644 case CK_Lakemont:
645 defineCPUMacros(Builder, "i586", /*Tuning*/false);
646 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
647 Builder.defineMacro("__tune_lakemont__");
648 break;
649 case CK_K6_2:
650 Builder.defineMacro("__k6_2__");
651 Builder.defineMacro("__tune_k6_2__");
652 [[fallthrough]];
653 case CK_K6_3:
654 if (CPU != CK_K6_2) { // In case of fallthrough
655 // FIXME: GCC may be enabling these in cases where some other k6
656 // architecture is specified but -m3dnow is explicitly provided. The
657 // exact semantics need to be determined and emulated here.
658 Builder.defineMacro("__k6_3__");
659 Builder.defineMacro("__tune_k6_3__");
660 }
661 [[fallthrough]];
662 case CK_K6:
663 defineCPUMacros(Builder, "k6");
664 break;
665 case CK_Athlon:
666 case CK_AthlonXP:
667 defineCPUMacros(Builder, "athlon");
668 if (SSELevel != NoSSE) {
669 Builder.defineMacro("__athlon_sse__");
670 Builder.defineMacro("__tune_athlon_sse__");
671 }
672 break;
673 case CK_K8:
674 case CK_K8SSE3:
675 case CK_x86_64:
676 defineCPUMacros(Builder, "k8");
677 break;
678 case CK_x86_64_v2:
679 case CK_x86_64_v3:
680 case CK_x86_64_v4:
681 break;
682 case CK_AMDFAM10:
683 defineCPUMacros(Builder, "amdfam10");
684 break;
685 case CK_BTVER1:
686 defineCPUMacros(Builder, "btver1");
687 break;
688 case CK_BTVER2:
689 defineCPUMacros(Builder, "btver2");
690 break;
691 case CK_BDVER1:
692 defineCPUMacros(Builder, "bdver1");
693 break;
694 case CK_BDVER2:
695 defineCPUMacros(Builder, "bdver2");
696 break;
697 case CK_BDVER3:
698 defineCPUMacros(Builder, "bdver3");
699 break;
700 case CK_BDVER4:
701 defineCPUMacros(Builder, "bdver4");
702 break;
703 case CK_ZNVER1:
704 defineCPUMacros(Builder, "znver1");
705 break;
706 case CK_ZNVER2:
707 defineCPUMacros(Builder, "znver2");
708 break;
709 case CK_ZNVER3:
710 defineCPUMacros(Builder, "znver3");
711 break;
712 case CK_ZNVER4:
713 defineCPUMacros(Builder, "znver4");
714 break;
715 case CK_Geode:
716 defineCPUMacros(Builder, "geode");
717 break;
718 }
719
720 // Target properties.
721 Builder.defineMacro("__REGISTER_PREFIX__", "");
722
723 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
724 // functions in glibc header files that use FP Stack inline asm which the
725 // backend can't deal with (PR879).
726 Builder.defineMacro("__NO_MATH_INLINES");
727
728 if (HasAES)
729 Builder.defineMacro("__AES__");
730
731 if (HasVAES)
732 Builder.defineMacro("__VAES__");
733
734 if (HasPCLMUL)
735 Builder.defineMacro("__PCLMUL__");
736
737 if (HasVPCLMULQDQ)
738 Builder.defineMacro("__VPCLMULQDQ__");
739
740 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
741 // the feature flag only applies to 64-bit mode.
742 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
743 Builder.defineMacro("__LAHF_SAHF__");
744
745 if (HasLZCNT)
746 Builder.defineMacro("__LZCNT__");
747
748 if (HasRDRND)
749 Builder.defineMacro("__RDRND__");
750
751 if (HasFSGSBASE)
752 Builder.defineMacro("__FSGSBASE__");
753
754 if (HasBMI)
755 Builder.defineMacro("__BMI__");
756
757 if (HasBMI2)
758 Builder.defineMacro("__BMI2__");
759
760 if (HasPOPCNT)
761 Builder.defineMacro("__POPCNT__");
762
763 if (HasRTM)
764 Builder.defineMacro("__RTM__");
765
766 if (HasPRFCHW)
767 Builder.defineMacro("__PRFCHW__");
768
769 if (HasRDSEED)
770 Builder.defineMacro("__RDSEED__");
771
772 if (HasADX)
773 Builder.defineMacro("__ADX__");
774
775 if (HasTBM)
776 Builder.defineMacro("__TBM__");
777
778 if (HasLWP)
779 Builder.defineMacro("__LWP__");
780
781 if (HasMWAITX)
782 Builder.defineMacro("__MWAITX__");
783
784 if (HasMOVBE)
785 Builder.defineMacro("__MOVBE__");
786
787 switch (XOPLevel) {
788 case XOP:
789 Builder.defineMacro("__XOP__");
790 [[fallthrough]];
791 case FMA4:
792 Builder.defineMacro("__FMA4__");
793 [[fallthrough]];
794 case SSE4A:
795 Builder.defineMacro("__SSE4A__");
796 [[fallthrough]];
797 case NoXOP:
798 break;
799 }
800
801 if (HasFMA)
802 Builder.defineMacro("__FMA__");
803
804 if (HasF16C)
805 Builder.defineMacro("__F16C__");
806
807 if (HasGFNI)
808 Builder.defineMacro("__GFNI__");
809
810 if (HasEVEX512)
811 Builder.defineMacro("__EVEX512__");
812 if (HasAVX10_1)
813 Builder.defineMacro("__AVX10_1__");
814 if (HasAVX10_1_512)
815 Builder.defineMacro("__AVX10_1_512__");
816 if (HasAVX512CD)
817 Builder.defineMacro("__AVX512CD__");
818 if (HasAVX512VPOPCNTDQ)
819 Builder.defineMacro("__AVX512VPOPCNTDQ__");
820 if (HasAVX512VNNI)
821 Builder.defineMacro("__AVX512VNNI__");
822 if (HasAVX512BF16)
823 Builder.defineMacro("__AVX512BF16__");
824 if (HasAVX512ER)
825 Builder.defineMacro("__AVX512ER__");
826 if (HasAVX512FP16)
827 Builder.defineMacro("__AVX512FP16__");
828 if (HasAVX512PF)
829 Builder.defineMacro("__AVX512PF__");
830 if (HasAVX512DQ)
831 Builder.defineMacro("__AVX512DQ__");
832 if (HasAVX512BITALG)
833 Builder.defineMacro("__AVX512BITALG__");
834 if (HasAVX512BW)
835 Builder.defineMacro("__AVX512BW__");
836 if (HasAVX512VL) {
837 Builder.defineMacro("__AVX512VL__");
838 Builder.defineMacro("__EVEX256__");
839 }
840 if (HasAVX512VBMI)
841 Builder.defineMacro("__AVX512VBMI__");
842 if (HasAVX512VBMI2)
843 Builder.defineMacro("__AVX512VBMI2__");
844 if (HasAVX512IFMA)
845 Builder.defineMacro("__AVX512IFMA__");
846 if (HasAVX512VP2INTERSECT)
847 Builder.defineMacro("__AVX512VP2INTERSECT__");
848 if (HasSHA)
849 Builder.defineMacro("__SHA__");
850 if (HasSHA512)
851 Builder.defineMacro("__SHA512__");
852
853 if (HasFXSR)
854 Builder.defineMacro("__FXSR__");
855 if (HasXSAVE)
856 Builder.defineMacro("__XSAVE__");
857 if (HasXSAVEOPT)
858 Builder.defineMacro("__XSAVEOPT__");
859 if (HasXSAVEC)
860 Builder.defineMacro("__XSAVEC__");
861 if (HasXSAVES)
862 Builder.defineMacro("__XSAVES__");
863 if (HasPKU)
864 Builder.defineMacro("__PKU__");
865 if (HasCLFLUSHOPT)
866 Builder.defineMacro("__CLFLUSHOPT__");
867 if (HasCLWB)
868 Builder.defineMacro("__CLWB__");
869 if (HasWBNOINVD)
870 Builder.defineMacro("__WBNOINVD__");
871 if (HasSHSTK)
872 Builder.defineMacro("__SHSTK__");
873 if (HasSGX)
874 Builder.defineMacro("__SGX__");
875 if (HasSM3)
876 Builder.defineMacro("__SM3__");
877 if (HasSM4)
878 Builder.defineMacro("__SM4__");
879 if (HasPREFETCHI)
880 Builder.defineMacro("__PREFETCHI__");
881 if (HasPREFETCHWT1)
882 Builder.defineMacro("__PREFETCHWT1__");
883 if (HasCLZERO)
884 Builder.defineMacro("__CLZERO__");
885 if (HasKL)
886 Builder.defineMacro("__KL__");
887 if (HasWIDEKL)
888 Builder.defineMacro("__WIDEKL__");
889 if (HasRDPID)
890 Builder.defineMacro("__RDPID__");
891 if (HasRDPRU)
892 Builder.defineMacro("__RDPRU__");
893 if (HasCLDEMOTE)
894 Builder.defineMacro("__CLDEMOTE__");
895 if (HasWAITPKG)
896 Builder.defineMacro("__WAITPKG__");
897 if (HasMOVDIRI)
898 Builder.defineMacro("__MOVDIRI__");
899 if (HasMOVDIR64B)
900 Builder.defineMacro("__MOVDIR64B__");
901 if (HasPCONFIG)
902 Builder.defineMacro("__PCONFIG__");
903 if (HasPTWRITE)
904 Builder.defineMacro("__PTWRITE__");
905 if (HasINVPCID)
906 Builder.defineMacro("__INVPCID__");
907 if (HasENQCMD)
908 Builder.defineMacro("__ENQCMD__");
909 if (HasHRESET)
910 Builder.defineMacro("__HRESET__");
911 if (HasAMXTILE)
912 Builder.defineMacro("__AMX_TILE__");
913 if (HasAMXINT8)
914 Builder.defineMacro("__AMX_INT8__");
915 if (HasAMXBF16)
916 Builder.defineMacro("__AMX_BF16__");
917 if (HasAMXFP16)
918 Builder.defineMacro("__AMX_FP16__");
919 if (HasAMXCOMPLEX)
920 Builder.defineMacro("__AMX_COMPLEX__");
921 if (HasCMPCCXADD)
922 Builder.defineMacro("__CMPCCXADD__");
923 if (HasRAOINT)
924 Builder.defineMacro("__RAOINT__");
925 if (HasAVXIFMA)
926 Builder.defineMacro("__AVXIFMA__");
927 if (HasAVXNECONVERT)
928 Builder.defineMacro("__AVXNECONVERT__");
929 if (HasAVXVNNI)
930 Builder.defineMacro("__AVXVNNI__");
931 if (HasAVXVNNIINT16)
932 Builder.defineMacro("__AVXVNNIINT16__");
933 if (HasAVXVNNIINT8)
934 Builder.defineMacro("__AVXVNNIINT8__");
935 if (HasSERIALIZE)
936 Builder.defineMacro("__SERIALIZE__");
937 if (HasTSXLDTRK)
938 Builder.defineMacro("__TSXLDTRK__");
939 if (HasUINTR)
940 Builder.defineMacro("__UINTR__");
941 if (HasUSERMSR)
942 Builder.defineMacro("__USERMSR__");
943 if (HasCRC32)
944 Builder.defineMacro("__CRC32__");
945 if (HasEGPR)
946 Builder.defineMacro("__EGPR__");
947 if (HasPush2Pop2)
948 Builder.defineMacro("__PUSH2POP2__");
949 if (HasPPX)
950 Builder.defineMacro("__PPX__");
951 if (HasNDD)
952 Builder.defineMacro("__NDD__");
953 if (HasCCMP)
954 Builder.defineMacro("__CCMP__");
955 if (HasCF)
956 Builder.defineMacro("__CF__");
957 // Condition here is aligned with the feature set of mapxf in Options.td
958 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
959 Builder.defineMacro("__APX_F__");
960
961 // Each case falls through to the previous one here.
962 switch (SSELevel) {
963 case AVX512F:
964 Builder.defineMacro("__AVX512F__");
965 [[fallthrough]];
966 case AVX2:
967 Builder.defineMacro("__AVX2__");
968 [[fallthrough]];
969 case AVX:
970 Builder.defineMacro("__AVX__");
971 [[fallthrough]];
972 case SSE42:
973 Builder.defineMacro("__SSE4_2__");
974 [[fallthrough]];
975 case SSE41:
976 Builder.defineMacro("__SSE4_1__");
977 [[fallthrough]];
978 case SSSE3:
979 Builder.defineMacro("__SSSE3__");
980 [[fallthrough]];
981 case SSE3:
982 Builder.defineMacro("__SSE3__");
983 [[fallthrough]];
984 case SSE2:
985 Builder.defineMacro("__SSE2__");
986 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
987 [[fallthrough]];
988 case SSE1:
989 Builder.defineMacro("__SSE__");
990 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
991 [[fallthrough]];
992 case NoSSE:
993 break;
994 }
995
996 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
997 switch (SSELevel) {
998 case AVX512F:
999 case AVX2:
1000 case AVX:
1001 case SSE42:
1002 case SSE41:
1003 case SSSE3:
1004 case SSE3:
1005 case SSE2:
1006 Builder.defineMacro("_M_IX86_FP", Twine(2));
1007 break;
1008 case SSE1:
1009 Builder.defineMacro("_M_IX86_FP", Twine(1));
1010 break;
1011 default:
1012 Builder.defineMacro("_M_IX86_FP", Twine(0));
1013 break;
1014 }
1015 }
1016
1017 // Each case falls through to the previous one here.
1018 switch (MMX3DNowLevel) {
1019 case AMD3DNowAthlon:
1020 Builder.defineMacro("__3dNOW_A__");
1021 [[fallthrough]];
1022 case AMD3DNow:
1023 Builder.defineMacro("__3dNOW__");
1024 [[fallthrough]];
1025 case MMX:
1026 Builder.defineMacro("__MMX__");
1027 [[fallthrough]];
1028 case NoMMX3DNow:
1029 break;
1030 }
1031
1032 if (CPU >= CK_i486 || CPU == CK_None) {
1033 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1034 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1035 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1036 }
1037 if (HasCX8)
1038 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1039 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1040 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1041
1042 if (HasFloat128)
1043 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1044}
1045
1046bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1047 return llvm::StringSwitch<bool>(Name)
1048 .Case("3dnow", true)
1049 .Case("3dnowa", true)
1050 .Case("adx", true)
1051 .Case("aes", true)
1052 .Case("amx-bf16", true)
1053 .Case("amx-complex", true)
1054 .Case("amx-fp16", true)
1055 .Case("amx-int8", true)
1056 .Case("amx-tile", true)
1057 .Case("avx", true)
1058 .Case("avx10.1-256", true)
1059 .Case("avx10.1-512", true)
1060 .Case("avx2", true)
1061 .Case("avx512f", true)
1062 .Case("avx512cd", true)
1063 .Case("avx512vpopcntdq", true)
1064 .Case("avx512vnni", true)
1065 .Case("avx512bf16", true)
1066 .Case("avx512er", true)
1067 .Case("avx512fp16", true)
1068 .Case("avx512pf", true)
1069 .Case("avx512dq", true)
1070 .Case("avx512bitalg", true)
1071 .Case("avx512bw", true)
1072 .Case("avx512vl", true)
1073 .Case("avx512vbmi", true)
1074 .Case("avx512vbmi2", true)
1075 .Case("avx512ifma", true)
1076 .Case("avx512vp2intersect", true)
1077 .Case("avxifma", true)
1078 .Case("avxneconvert", true)
1079 .Case("avxvnni", true)
1080 .Case("avxvnniint16", true)
1081 .Case("avxvnniint8", true)
1082 .Case("bmi", true)
1083 .Case("bmi2", true)
1084 .Case("cldemote", true)
1085 .Case("clflushopt", true)
1086 .Case("clwb", true)
1087 .Case("clzero", true)
1088 .Case("cmpccxadd", true)
1089 .Case("crc32", true)
1090 .Case("cx16", true)
1091 .Case("enqcmd", true)
1092 .Case("evex512", true)
1093 .Case("f16c", true)
1094 .Case("fma", true)
1095 .Case("fma4", true)
1096 .Case("fsgsbase", true)
1097 .Case("fxsr", true)
1098 .Case("general-regs-only", true)
1099 .Case("gfni", true)
1100 .Case("hreset", true)
1101 .Case("invpcid", true)
1102 .Case("kl", true)
1103 .Case("widekl", true)
1104 .Case("lwp", true)
1105 .Case("lzcnt", true)
1106 .Case("mmx", true)
1107 .Case("movbe", true)
1108 .Case("movdiri", true)
1109 .Case("movdir64b", true)
1110 .Case("mwaitx", true)
1111 .Case("pclmul", true)
1112 .Case("pconfig", true)
1113 .Case("pku", true)
1114 .Case("popcnt", true)
1115 .Case("prefetchi", true)
1116 .Case("prefetchwt1", true)
1117 .Case("prfchw", true)
1118 .Case("ptwrite", true)
1119 .Case("raoint", true)
1120 .Case("rdpid", true)
1121 .Case("rdpru", true)
1122 .Case("rdrnd", true)
1123 .Case("rdseed", true)
1124 .Case("rtm", true)
1125 .Case("sahf", true)
1126 .Case("serialize", true)
1127 .Case("sgx", true)
1128 .Case("sha", true)
1129 .Case("sha512", true)
1130 .Case("shstk", true)
1131 .Case("sm3", true)
1132 .Case("sm4", true)
1133 .Case("sse", true)
1134 .Case("sse2", true)
1135 .Case("sse3", true)
1136 .Case("ssse3", true)
1137 .Case("sse4", true)
1138 .Case("sse4.1", true)
1139 .Case("sse4.2", true)
1140 .Case("sse4a", true)
1141 .Case("tbm", true)
1142 .Case("tsxldtrk", true)
1143 .Case("uintr", true)
1144 .Case("usermsr", true)
1145 .Case("vaes", true)
1146 .Case("vpclmulqdq", true)
1147 .Case("wbnoinvd", true)
1148 .Case("waitpkg", true)
1149 .Case("x87", true)
1150 .Case("xop", true)
1151 .Case("xsave", true)
1152 .Case("xsavec", true)
1153 .Case("xsaves", true)
1154 .Case("xsaveopt", true)
1155 .Case("egpr", true)
1156 .Case("push2pop2", true)
1157 .Case("ppx", true)
1158 .Case("ndd", true)
1159 .Case("ccmp", true)
1160 .Case("cf", true)
1161 .Default(false);
1162}
1163
1164bool X86TargetInfo::hasFeature(StringRef Feature) const {
1165 return llvm::StringSwitch<bool>(Feature)
1166 .Case("adx", HasADX)
1167 .Case("aes", HasAES)
1168 .Case("amx-bf16", HasAMXBF16)
1169 .Case("amx-complex", HasAMXCOMPLEX)
1170 .Case("amx-fp16", HasAMXFP16)
1171 .Case("amx-int8", HasAMXINT8)
1172 .Case("amx-tile", HasAMXTILE)
1173 .Case("avx", SSELevel >= AVX)
1174 .Case("avx10.1-256", HasAVX10_1)
1175 .Case("avx10.1-512", HasAVX10_1_512)
1176 .Case("avx2", SSELevel >= AVX2)
1177 .Case("avx512f", SSELevel >= AVX512F)
1178 .Case("avx512cd", HasAVX512CD)
1179 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1180 .Case("avx512vnni", HasAVX512VNNI)
1181 .Case("avx512bf16", HasAVX512BF16)
1182 .Case("avx512er", HasAVX512ER)
1183 .Case("avx512fp16", HasAVX512FP16)
1184 .Case("avx512pf", HasAVX512PF)
1185 .Case("avx512dq", HasAVX512DQ)
1186 .Case("avx512bitalg", HasAVX512BITALG)
1187 .Case("avx512bw", HasAVX512BW)
1188 .Case("avx512vl", HasAVX512VL)
1189 .Case("avx512vbmi", HasAVX512VBMI)
1190 .Case("avx512vbmi2", HasAVX512VBMI2)
1191 .Case("avx512ifma", HasAVX512IFMA)
1192 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1193 .Case("avxifma", HasAVXIFMA)
1194 .Case("avxneconvert", HasAVXNECONVERT)
1195 .Case("avxvnni", HasAVXVNNI)
1196 .Case("avxvnniint16", HasAVXVNNIINT16)
1197 .Case("avxvnniint8", HasAVXVNNIINT8)
1198 .Case("bmi", HasBMI)
1199 .Case("bmi2", HasBMI2)
1200 .Case("cldemote", HasCLDEMOTE)
1201 .Case("clflushopt", HasCLFLUSHOPT)
1202 .Case("clwb", HasCLWB)
1203 .Case("clzero", HasCLZERO)
1204 .Case("cmpccxadd", HasCMPCCXADD)
1205 .Case("crc32", HasCRC32)
1206 .Case("cx8", HasCX8)
1207 .Case("cx16", HasCX16)
1208 .Case("enqcmd", HasENQCMD)
1209 .Case("evex512", HasEVEX512)
1210 .Case("f16c", HasF16C)
1211 .Case("fma", HasFMA)
1212 .Case("fma4", XOPLevel >= FMA4)
1213 .Case("fsgsbase", HasFSGSBASE)
1214 .Case("fxsr", HasFXSR)
1215 .Case("gfni", HasGFNI)
1216 .Case("hreset", HasHRESET)
1217 .Case("invpcid", HasINVPCID)
1218 .Case("kl", HasKL)
1219 .Case("widekl", HasWIDEKL)
1220 .Case("lwp", HasLWP)
1221 .Case("lzcnt", HasLZCNT)
1222 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1223 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1224 .Case("mmx", MMX3DNowLevel >= MMX)
1225 .Case("movbe", HasMOVBE)
1226 .Case("movdiri", HasMOVDIRI)
1227 .Case("movdir64b", HasMOVDIR64B)
1228 .Case("mwaitx", HasMWAITX)
1229 .Case("pclmul", HasPCLMUL)
1230 .Case("pconfig", HasPCONFIG)
1231 .Case("pku", HasPKU)
1232 .Case("popcnt", HasPOPCNT)
1233 .Case("prefetchi", HasPREFETCHI)
1234 .Case("prefetchwt1", HasPREFETCHWT1)
1235 .Case("prfchw", HasPRFCHW)
1236 .Case("ptwrite", HasPTWRITE)
1237 .Case("raoint", HasRAOINT)
1238 .Case("rdpid", HasRDPID)
1239 .Case("rdpru", HasRDPRU)
1240 .Case("rdrnd", HasRDRND)
1241 .Case("rdseed", HasRDSEED)
1242 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1243 .Case("rtm", HasRTM)
1244 .Case("sahf", HasLAHFSAHF)
1245 .Case("serialize", HasSERIALIZE)
1246 .Case("sgx", HasSGX)
1247 .Case("sha", HasSHA)
1248 .Case("sha512", HasSHA512)
1249 .Case("shstk", HasSHSTK)
1250 .Case("sm3", HasSM3)
1251 .Case("sm4", HasSM4)
1252 .Case("sse", SSELevel >= SSE1)
1253 .Case("sse2", SSELevel >= SSE2)
1254 .Case("sse3", SSELevel >= SSE3)
1255 .Case("ssse3", SSELevel >= SSSE3)
1256 .Case("sse4.1", SSELevel >= SSE41)
1257 .Case("sse4.2", SSELevel >= SSE42)
1258 .Case("sse4a", XOPLevel >= SSE4A)
1259 .Case("tbm", HasTBM)
1260 .Case("tsxldtrk", HasTSXLDTRK)
1261 .Case("uintr", HasUINTR)
1262 .Case("usermsr", HasUSERMSR)
1263 .Case("vaes", HasVAES)
1264 .Case("vpclmulqdq", HasVPCLMULQDQ)
1265 .Case("wbnoinvd", HasWBNOINVD)
1266 .Case("waitpkg", HasWAITPKG)
1267 .Case("x86", true)
1268 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1269 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1270 .Case("x87", HasX87)
1271 .Case("xop", XOPLevel >= XOP)
1272 .Case("xsave", HasXSAVE)
1273 .Case("xsavec", HasXSAVEC)
1274 .Case("xsaves", HasXSAVES)
1275 .Case("xsaveopt", HasXSAVEOPT)
1276 .Case("fullbf16", HasFullBFloat16)
1277 .Case("egpr", HasEGPR)
1278 .Case("push2pop2", HasPush2Pop2)
1279 .Case("ppx", HasPPX)
1280 .Case("ndd", HasNDD)
1281 .Case("ccmp", HasCCMP)
1282 .Case("cf", HasCF)
1283 .Default(false);
1284}
1285
1286// We can't use a generic validation scheme for the features accepted here
1287// versus subtarget features accepted in the target attribute because the
1288// bitfield structure that's initialized in the runtime only supports the
1289// below currently rather than the full range of subtarget features. (See
1290// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1291bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1292 return llvm::StringSwitch<bool>(FeatureStr)
1293#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1294#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true)
1295#include "llvm/TargetParser/X86TargetParser.def"
1296 .Default(false);
1297}
1298
1299static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1300 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1301#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1302 .Case(STR, llvm::X86::FEATURE_##ENUM)
1303
1304#include "llvm/TargetParser/X86TargetParser.def"
1305 ;
1306 // Note, this function should only be used after ensuring the value is
1307 // correct, so it asserts if the value is out of range.
1308}
1309
1310unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1311 // Valid CPUs have a 'key feature' that compares just better than its key
1312 // feature.
1313 using namespace llvm::X86;
1314 CPUKind Kind = parseArchX86(Name);
1315 if (Kind != CK_None) {
1316 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1317 return (getFeaturePriority(KeyFeature) << 1) + 1;
1318 }
1319
1320 // Now we know we have a feature, so get its priority and shift it a few so
1321 // that we have sufficient room for the CPUs (above).
1322 return getFeaturePriority(getFeature(Name)) << 1;
1323}
1324
1326 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1327}
1328
1330 return llvm::X86::getCPUDispatchMangling(Name);
1331}
1332
1334 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1335 SmallVector<StringRef, 32> TargetCPUFeatures;
1336 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1337 for (auto &F : TargetCPUFeatures)
1338 Features.push_back(F);
1339}
1340
1341// We can't use a generic validation scheme for the cpus accepted here
1342// versus subtarget cpus accepted in the target attribute because the
1343// variables intitialized by the runtime only support the below currently
1344// rather than the full range of cpus.
1345bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1346 return llvm::StringSwitch<bool>(FeatureStr)
1347#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1348#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1349#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1350#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1351#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1352#include "llvm/TargetParser/X86TargetParser.def"
1353 .Default(false);
1354}
1355
1356static unsigned matchAsmCCConstraint(const char *Name) {
1357 auto RV = llvm::StringSwitch<unsigned>(Name)
1358 .Case("@cca", 4)
1359 .Case("@ccae", 5)
1360 .Case("@ccb", 4)
1361 .Case("@ccbe", 5)
1362 .Case("@ccc", 4)
1363 .Case("@cce", 4)
1364 .Case("@ccz", 4)
1365 .Case("@ccg", 4)
1366 .Case("@ccge", 5)
1367 .Case("@ccl", 4)
1368 .Case("@ccle", 5)
1369 .Case("@ccna", 5)
1370 .Case("@ccnae", 6)
1371 .Case("@ccnb", 5)
1372 .Case("@ccnbe", 6)
1373 .Case("@ccnc", 5)
1374 .Case("@ccne", 5)
1375 .Case("@ccnz", 5)
1376 .Case("@ccng", 5)
1377 .Case("@ccnge", 6)
1378 .Case("@ccnl", 5)
1379 .Case("@ccnle", 6)
1380 .Case("@ccno", 5)
1381 .Case("@ccnp", 5)
1382 .Case("@ccns", 5)
1383 .Case("@cco", 4)
1384 .Case("@ccp", 4)
1385 .Case("@ccs", 4)
1386 .Default(0);
1387 return RV;
1388}
1389
1391 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1392 switch (*Name) {
1393 default:
1394 return false;
1395 // Constant constraints.
1396 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1397 // instructions.
1398 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1399 // x86_64 instructions.
1400 case 's':
1401 Info.setRequiresImmediate();
1402 return true;
1403 case 'I':
1404 Info.setRequiresImmediate(0, 31);
1405 return true;
1406 case 'J':
1407 Info.setRequiresImmediate(0, 63);
1408 return true;
1409 case 'K':
1410 Info.setRequiresImmediate(-128, 127);
1411 return true;
1412 case 'L':
1413 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1414 return true;
1415 case 'M':
1416 Info.setRequiresImmediate(0, 3);
1417 return true;
1418 case 'N':
1419 Info.setRequiresImmediate(0, 255);
1420 return true;
1421 case 'O':
1422 Info.setRequiresImmediate(0, 127);
1423 return true;
1424 case 'W':
1425 switch (*++Name) {
1426 default:
1427 return false;
1428 case 's':
1429 Info.setAllowsRegister();
1430 return true;
1431 }
1432 // Register constraints.
1433 case 'Y': // 'Y' is the first character for several 2-character constraints.
1434 // Shift the pointer to the second character of the constraint.
1435 Name++;
1436 switch (*Name) {
1437 default:
1438 return false;
1439 case 'z': // First SSE register.
1440 case '2':
1441 case 't': // Any SSE register, when SSE2 is enabled.
1442 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1443 case 'm': // Any MMX register, when inter-unit moves enabled.
1444 case 'k': // AVX512 arch mask registers: k1-k7.
1445 Info.setAllowsRegister();
1446 return true;
1447 }
1448 case 'f': // Any x87 floating point stack register.
1449 // Constraint 'f' cannot be used for output operands.
1450 if (Info.ConstraintStr[0] == '=')
1451 return false;
1452 Info.setAllowsRegister();
1453 return true;
1454 case 'a': // eax.
1455 case 'b': // ebx.
1456 case 'c': // ecx.
1457 case 'd': // edx.
1458 case 'S': // esi.
1459 case 'D': // edi.
1460 case 'A': // edx:eax.
1461 case 't': // Top of floating point stack.
1462 case 'u': // Second from top of floating point stack.
1463 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1464 case 'y': // Any MMX register.
1465 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1466 case 'x': // Any SSE register.
1467 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1468 // for intermideate k reg operations).
1469 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1470 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1471 case 'l': // "Index" registers: any general register that can be used as an
1472 // index in a base+index memory access.
1473 Info.setAllowsRegister();
1474 return true;
1475 // Floating point constant constraints.
1476 case 'C': // SSE floating point constant.
1477 case 'G': // x87 floating point constant.
1478 return true;
1479 case '@':
1480 // CC condition changes.
1481 if (auto Len = matchAsmCCConstraint(Name)) {
1482 Name += Len - 1;
1483 Info.setAllowsRegister();
1484 return true;
1485 }
1486 return false;
1487 }
1488}
1489
1490// Below is based on the following information:
1491// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1492// | Processor Name | Cache Line Size (Bytes) | Source |
1493// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1494// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1495// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1496// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1497// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1498// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1499// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1500// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1501// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1502// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1503// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1504// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1505// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1506// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1507// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1508// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1509// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1510// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1511// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1512std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1513 using namespace llvm::X86;
1514 switch (CPU) {
1515 // i386
1516 case CK_i386:
1517 // i486
1518 case CK_i486:
1519 case CK_WinChipC6:
1520 case CK_WinChip2:
1521 case CK_C3:
1522 // Lakemont
1523 case CK_Lakemont:
1524 return 16;
1525
1526 // i586
1527 case CK_i586:
1528 case CK_Pentium:
1529 case CK_PentiumMMX:
1530 // i686
1531 case CK_PentiumPro:
1532 case CK_i686:
1533 case CK_Pentium2:
1534 case CK_Pentium3:
1535 case CK_PentiumM:
1536 case CK_C3_2:
1537 // K6
1538 case CK_K6:
1539 case CK_K6_2:
1540 case CK_K6_3:
1541 // Geode
1542 case CK_Geode:
1543 return 32;
1544
1545 // Netburst
1546 case CK_Pentium4:
1547 case CK_Prescott:
1548 case CK_Nocona:
1549 // Atom
1550 case CK_Bonnell:
1551 case CK_Silvermont:
1552 case CK_Goldmont:
1553 case CK_GoldmontPlus:
1554 case CK_Tremont:
1555 case CK_Gracemont:
1556
1557 case CK_Westmere:
1558 case CK_SandyBridge:
1559 case CK_IvyBridge:
1560 case CK_Haswell:
1561 case CK_Broadwell:
1562 case CK_SkylakeClient:
1563 case CK_SkylakeServer:
1564 case CK_Cascadelake:
1565 case CK_Nehalem:
1566 case CK_Cooperlake:
1567 case CK_Cannonlake:
1568 case CK_Tigerlake:
1569 case CK_SapphireRapids:
1570 case CK_IcelakeClient:
1571 case CK_Rocketlake:
1572 case CK_IcelakeServer:
1573 case CK_Alderlake:
1574 case CK_Raptorlake:
1575 case CK_Meteorlake:
1576 case CK_Arrowlake:
1577 case CK_ArrowlakeS:
1578 case CK_Lunarlake:
1579 case CK_Pantherlake:
1580 case CK_Sierraforest:
1581 case CK_Grandridge:
1582 case CK_Graniterapids:
1583 case CK_GraniterapidsD:
1584 case CK_Emeraldrapids:
1585 case CK_Clearwaterforest:
1586 case CK_KNL:
1587 case CK_KNM:
1588 // K7
1589 case CK_Athlon:
1590 case CK_AthlonXP:
1591 // K8
1592 case CK_K8:
1593 case CK_K8SSE3:
1594 case CK_AMDFAM10:
1595 // Bobcat
1596 case CK_BTVER1:
1597 case CK_BTVER2:
1598 // Bulldozer
1599 case CK_BDVER1:
1600 case CK_BDVER2:
1601 case CK_BDVER3:
1602 case CK_BDVER4:
1603 // Zen
1604 case CK_ZNVER1:
1605 case CK_ZNVER2:
1606 case CK_ZNVER3:
1607 case CK_ZNVER4:
1608 // Deprecated
1609 case CK_x86_64:
1610 case CK_x86_64_v2:
1611 case CK_x86_64_v3:
1612 case CK_x86_64_v4:
1613 case CK_Yonah:
1614 case CK_Penryn:
1615 case CK_Core2:
1616 return 64;
1617
1618 // The following currently have unknown cache line sizes (but they are probably all 64):
1619 // Core
1620 case CK_None:
1621 return std::nullopt;
1622 }
1623 llvm_unreachable("Unknown CPU kind");
1624}
1625
1626bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1627 StringRef Constraint,
1628 unsigned Size) const {
1629 // Strip off constraint modifiers.
1630 Constraint = Constraint.ltrim("=+&");
1631
1632 return validateOperandSize(FeatureMap, Constraint, Size);
1633}
1634
1635bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1636 StringRef Constraint,
1637 unsigned Size) const {
1638 return validateOperandSize(FeatureMap, Constraint, Size);
1639}
1640
1641bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1642 StringRef Constraint,
1643 unsigned Size) const {
1644 switch (Constraint[0]) {
1645 default:
1646 break;
1647 case 'k':
1648 // Registers k0-k7 (AVX512) size limit is 64 bit.
1649 case 'y':
1650 return Size <= 64;
1651 case 'f':
1652 case 't':
1653 case 'u':
1654 return Size <= 128;
1655 case 'Y':
1656 // 'Y' is the first character for several 2-character constraints.
1657 switch (Constraint[1]) {
1658 default:
1659 return false;
1660 case 'm':
1661 // 'Ym' is synonymous with 'y'.
1662 case 'k':
1663 return Size <= 64;
1664 case 'z':
1665 // XMM0/YMM/ZMM0
1666 if (hasFeatureEnabled(FeatureMap, "avx512f") &&
1667 hasFeatureEnabled(FeatureMap, "evex512"))
1668 // ZMM0 can be used if target supports AVX512F and EVEX512 is set.
1669 return Size <= 512U;
1670 else if (hasFeatureEnabled(FeatureMap, "avx"))
1671 // YMM0 can be used if target supports AVX.
1672 return Size <= 256U;
1673 else if (hasFeatureEnabled(FeatureMap, "sse"))
1674 return Size <= 128U;
1675 return false;
1676 case 'i':
1677 case 't':
1678 case '2':
1679 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1680 if (SSELevel < SSE2)
1681 return false;
1682 break;
1683 }
1684 break;
1685 case 'v':
1686 case 'x':
1687 if (hasFeatureEnabled(FeatureMap, "avx512f") &&
1688 hasFeatureEnabled(FeatureMap, "evex512"))
1689 // 512-bit zmm registers can be used if target supports AVX512F and
1690 // EVEX512 is set.
1691 return Size <= 512U;
1692 else if (hasFeatureEnabled(FeatureMap, "avx"))
1693 // 256-bit ymm registers can be used if target supports AVX.
1694 return Size <= 256U;
1695 return Size <= 128U;
1696
1697 }
1698
1699 return true;
1700}
1701
1702std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1703 switch (*Constraint) {
1704 case '@':
1705 if (auto Len = matchAsmCCConstraint(Constraint)) {
1706 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1707 Constraint += Len - 1;
1708 return Converted;
1709 }
1710 return std::string(1, *Constraint);
1711 case 'a':
1712 return std::string("{ax}");
1713 case 'b':
1714 return std::string("{bx}");
1715 case 'c':
1716 return std::string("{cx}");
1717 case 'd':
1718 return std::string("{dx}");
1719 case 'S':
1720 return std::string("{si}");
1721 case 'D':
1722 return std::string("{di}");
1723 case 'p': // Keep 'p' constraint (address).
1724 return std::string("p");
1725 case 't': // top of floating point stack.
1726 return std::string("{st}");
1727 case 'u': // second from top of floating point stack.
1728 return std::string("{st(1)}"); // second from top of floating point stack.
1729 case 'W':
1730 assert(Constraint[1] == 's');
1731 return '^' + std::string(Constraint++, 2);
1732 case 'Y':
1733 switch (Constraint[1]) {
1734 default:
1735 // Break from inner switch and fall through (copy single char),
1736 // continue parsing after copying the current constraint into
1737 // the return string.
1738 break;
1739 case 'k':
1740 case 'm':
1741 case 'i':
1742 case 't':
1743 case 'z':
1744 case '2':
1745 // "^" hints llvm that this is a 2 letter constraint.
1746 // "Constraint++" is used to promote the string iterator
1747 // to the next constraint.
1748 return std::string("^") + std::string(Constraint++, 2);
1749 }
1750 [[fallthrough]];
1751 default:
1752 return std::string(1, *Constraint);
1753 }
1754}
1755
1757 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1758 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1759}
1760
1762 llvm::X86::fillValidTuneCPUList(Values);
1763}
1764
1767}
1768
1771}
1772
1776}
1777
1781}
Defines the Diagnostic-related interfaces.
static unsigned matchAsmCCConstraint(const char *Name)
Definition: AArch64.cpp:1316
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1299
Defines enum values for all the target-independent builtin functions.
Enumerates target-specific builtins in their own namespaces within namespace clang.
__device__ int
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1547
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:454
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition: TargetInfo.h:307
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1235
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition: TargetInfo.h:1358
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:522
enum clang::targets::X86TargetInfo::FPMathKind FPMath
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition: X86.cpp:238
std::optional< unsigned > getCPUCacheLineSize() const override
Definition: X86.cpp:1512
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1390
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1310
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:94
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1765
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1329
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1702
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:508
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:106
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1333
bool validateCpuIs(StringRef FeatureStr) const override
Definition: X86.cpp:1345
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1626
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1641
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: X86.cpp:1761
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1325
bool validateCpuSupports(StringRef FeatureStr) const override
Definition: X86.cpp:1291
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1046
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition: X86.cpp:1164
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition: X86.cpp:219
llvm::X86::CPUKind CPU
Definition: X86.h:179
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1756
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1769
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1635
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1773
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1778
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:76
static constexpr Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:26
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:69
static const char *const GCCRegNames[]
Definition: X86.cpp:44
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:60
The JSON file list parser is used to communicate input to InstallAPI.
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:1132
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:134