clang 23.0.0git
X86.cpp
Go to the documentation of this file.
1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 if (Features.lookup("egpr") && getTriple().isOSWindows()) {
168 setFeatureEnabled(Features, "push2pop2", false);
169 setFeatureEnabled(Features, "ppx", false);
170 }
171
172 std::vector<std::string> UpdatedFeaturesVec;
173 for (const auto &Feature : FeaturesVec) {
174 // Expand general-regs-only to -x86, -mmx and -sse
175 if (Feature == "+general-regs-only") {
176 UpdatedFeaturesVec.push_back("-x87");
177 UpdatedFeaturesVec.push_back("-mmx");
178 UpdatedFeaturesVec.push_back("-sse");
179 continue;
180 }
181
182 UpdatedFeaturesVec.push_back(Feature);
183 }
184
185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
186 return false;
187
188 // Can't do this earlier because we need to be able to explicitly enable
189 // or disable these features and the things that they depend upon.
190
191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
192 auto I = Features.find("sse4.2");
193 if (I != Features.end() && I->getValue() &&
194 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
195 Features["popcnt"] = true;
196
197 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
198 // then enable MMX.
199 I = Features.find("sse");
200 if (I != Features.end() && I->getValue() &&
201 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
202 Features["mmx"] = true;
203
204 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
205 I = Features.find("avx");
206 if (I != Features.end() && I->getValue() &&
207 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
208 Features["xsave"] = true;
209
210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
211 I = Features.find("sse4.2");
212 if (I != Features.end() && I->getValue() &&
213 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
214 Features["crc32"] = true;
215
216 return true;
217}
218
219void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
220 StringRef Name, bool Enabled) const {
221 if (Name == "sse4") {
222 // We can get here via the __target__ attribute since that's not controlled
223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
225 // disabled.
226 if (Enabled)
227 Name = "sse4.2";
228 else
229 Name = "sse4.1";
230 }
231
232 Features[Name] = Enabled;
233 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
234}
235
236/// handleTargetFeatures - Perform initialization based on the user
237/// configured set of features.
238bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
239 DiagnosticsEngine &Diags) {
240 for (const auto &Feature : Features) {
241 if (Feature[0] != '+')
242 continue;
243
244 if (Feature == "+mmx") {
245 HasMMX = true;
246 } else if (Feature == "+aes") {
247 HasAES = true;
248 } else if (Feature == "+vaes") {
249 HasVAES = true;
250 } else if (Feature == "+pclmul") {
251 HasPCLMUL = true;
252 } else if (Feature == "+vpclmulqdq") {
253 HasVPCLMULQDQ = true;
254 } else if (Feature == "+lzcnt") {
255 HasLZCNT = true;
256 } else if (Feature == "+rdrnd") {
257 HasRDRND = true;
258 } else if (Feature == "+fsgsbase") {
259 HasFSGSBASE = true;
260 } else if (Feature == "+bmi") {
261 HasBMI = true;
262 } else if (Feature == "+bmi2") {
263 HasBMI2 = true;
264 } else if (Feature == "+popcnt") {
265 HasPOPCNT = true;
266 } else if (Feature == "+rtm") {
267 HasRTM = true;
268 } else if (Feature == "+prfchw") {
269 HasPRFCHW = true;
270 } else if (Feature == "+rdseed") {
271 HasRDSEED = true;
272 } else if (Feature == "+adx") {
273 HasADX = true;
274 } else if (Feature == "+tbm") {
275 HasTBM = true;
276 } else if (Feature == "+lwp") {
277 HasLWP = true;
278 } else if (Feature == "+fma") {
279 HasFMA = true;
280 } else if (Feature == "+f16c") {
281 HasF16C = true;
282 } else if (Feature == "+gfni") {
283 HasGFNI = true;
284 } else if (Feature == "+avx10.1") {
285 HasAVX10_1 = true;
286 } else if (Feature == "+avx10.2") {
287 HasAVX10_2 = true;
288 HasFullBFloat16 = true;
289 } else if (Feature == "+avx512cd") {
290 HasAVX512CD = true;
291 } else if (Feature == "+avx512vpopcntdq") {
292 HasAVX512VPOPCNTDQ = true;
293 } else if (Feature == "+avx512vnni") {
294 HasAVX512VNNI = true;
295 } else if (Feature == "+avx512bf16") {
296 HasAVX512BF16 = true;
297 } else if (Feature == "+avx512fp16") {
298 HasAVX512FP16 = true;
299 HasFastHalfType = true;
300 } else if (Feature == "+avx512dq") {
301 HasAVX512DQ = true;
302 } else if (Feature == "+avx512bitalg") {
303 HasAVX512BITALG = true;
304 } else if (Feature == "+avx512bw") {
305 HasAVX512BW = true;
306 } else if (Feature == "+avx512vl") {
307 HasAVX512VL = true;
308 } else if (Feature == "+avx512vbmi") {
309 HasAVX512VBMI = true;
310 } else if (Feature == "+avx512vbmi2") {
311 HasAVX512VBMI2 = true;
312 } else if (Feature == "+avx512ifma") {
313 HasAVX512IFMA = true;
314 } else if (Feature == "+avx512vp2intersect") {
315 HasAVX512VP2INTERSECT = true;
316 } else if (Feature == "+sha") {
317 HasSHA = true;
318 } else if (Feature == "+sha512") {
319 HasSHA512 = true;
320 } else if (Feature == "+shstk") {
321 HasSHSTK = true;
322 } else if (Feature == "+sm3") {
323 HasSM3 = true;
324 } else if (Feature == "+sm4") {
325 HasSM4 = true;
326 } else if (Feature == "+movbe") {
327 HasMOVBE = true;
328 } else if (Feature == "+movrs") {
329 HasMOVRS = true;
330 } else if (Feature == "+sgx") {
331 HasSGX = true;
332 } else if (Feature == "+cx8") {
333 HasCX8 = true;
334 } else if (Feature == "+cx16") {
335 HasCX16 = true;
336 } else if (Feature == "+fxsr") {
337 HasFXSR = true;
338 } else if (Feature == "+xsave") {
339 HasXSAVE = true;
340 } else if (Feature == "+xsaveopt") {
341 HasXSAVEOPT = true;
342 } else if (Feature == "+xsavec") {
343 HasXSAVEC = true;
344 } else if (Feature == "+xsaves") {
345 HasXSAVES = true;
346 } else if (Feature == "+mwaitx") {
347 HasMWAITX = true;
348 } else if (Feature == "+pku") {
349 HasPKU = true;
350 } else if (Feature == "+clflushopt") {
351 HasCLFLUSHOPT = true;
352 } else if (Feature == "+clwb") {
353 HasCLWB = true;
354 } else if (Feature == "+wbnoinvd") {
355 HasWBNOINVD = true;
356 } else if (Feature == "+prefetchi") {
357 HasPREFETCHI = true;
358 } else if (Feature == "+clzero") {
359 HasCLZERO = true;
360 } else if (Feature == "+cldemote") {
361 HasCLDEMOTE = true;
362 } else if (Feature == "+rdpid") {
363 HasRDPID = true;
364 } else if (Feature == "+rdpru") {
365 HasRDPRU = true;
366 } else if (Feature == "+kl") {
367 HasKL = true;
368 } else if (Feature == "+widekl") {
369 HasWIDEKL = true;
370 } else if (Feature == "+retpoline-external-thunk") {
371 HasRetpolineExternalThunk = true;
372 } else if (Feature == "+sahf") {
373 HasLAHFSAHF = true;
374 } else if (Feature == "+waitpkg") {
375 HasWAITPKG = true;
376 } else if (Feature == "+movdiri") {
377 HasMOVDIRI = true;
378 } else if (Feature == "+movdir64b") {
379 HasMOVDIR64B = true;
380 } else if (Feature == "+pconfig") {
381 HasPCONFIG = true;
382 } else if (Feature == "+ptwrite") {
383 HasPTWRITE = true;
384 } else if (Feature == "+invpcid") {
385 HasINVPCID = true;
386 } else if (Feature == "+enqcmd") {
387 HasENQCMD = true;
388 } else if (Feature == "+hreset") {
389 HasHRESET = true;
390 } else if (Feature == "+amx-bf16") {
391 HasAMXBF16 = true;
392 } else if (Feature == "+amx-fp16") {
393 HasAMXFP16 = true;
394 } else if (Feature == "+amx-int8") {
395 HasAMXINT8 = true;
396 } else if (Feature == "+amx-tile") {
397 HasAMXTILE = true;
398 } else if (Feature == "+amx-complex") {
399 HasAMXCOMPLEX = true;
400 } else if (Feature == "+amx-fp8") {
401 HasAMXFP8 = true;
402 } else if (Feature == "+amx-movrs") {
403 HasAMXMOVRS = true;
404 } else if (Feature == "+amx-avx512") {
405 HasAMXAVX512 = true;
406 } else if (Feature == "+amx-tf32") {
407 HasAMXTF32 = true;
408 } else if (Feature == "+cmpccxadd") {
409 HasCMPCCXADD = true;
410 } else if (Feature == "+raoint") {
411 HasRAOINT = true;
412 } else if (Feature == "+avxifma") {
413 HasAVXIFMA = true;
414 } else if (Feature == "+avxneconvert") {
415 HasAVXNECONVERT= true;
416 } else if (Feature == "+avxvnni") {
417 HasAVXVNNI = true;
418 } else if (Feature == "+avxvnniint16") {
419 HasAVXVNNIINT16 = true;
420 } else if (Feature == "+avxvnniint8") {
421 HasAVXVNNIINT8 = true;
422 } else if (Feature == "+serialize") {
423 HasSERIALIZE = true;
424 } else if (Feature == "+tsxldtrk") {
425 HasTSXLDTRK = true;
426 } else if (Feature == "+uintr") {
427 HasUINTR = true;
428 } else if (Feature == "+usermsr") {
429 HasUSERMSR = true;
430 } else if (Feature == "+crc32") {
431 HasCRC32 = true;
432 } else if (Feature == "+x87") {
433 HasX87 = true;
434 } else if (Feature == "+fullbf16") {
435 HasFullBFloat16 = true;
436 } else if (Feature == "+egpr") {
437 HasEGPR = true;
438 } else if (Feature == "+inline-asm-use-gpr32") {
439 HasInlineAsmUseGPR32 = true;
440 } else if (Feature == "+push2pop2") {
441 HasPush2Pop2 = true;
442 } else if (Feature == "+ppx") {
443 HasPPX = true;
444 } else if (Feature == "+ndd") {
445 HasNDD = true;
446 } else if (Feature == "+ccmp") {
447 HasCCMP = true;
448 } else if (Feature == "+nf") {
449 HasNF = true;
450 } else if (Feature == "+cf") {
451 HasCF = true;
452 } else if (Feature == "+zu") {
453 HasZU = true;
454 } else if (Feature == "+jmpabs") {
455 HasJMPABS = true;
456 } else if (Feature == "+branch-hint") {
457 HasBranchHint = true;
458 }
459
460 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
461 .Case("+avx512f", AVX512F)
462 .Case("+avx2", AVX2)
463 .Case("+avx", AVX)
464 .Case("+sse4.2", SSE42)
465 .Case("+sse4.1", SSE41)
466 .Case("+ssse3", SSSE3)
467 .Case("+sse3", SSE3)
468 .Case("+sse2", SSE2)
469 .Case("+sse", SSE1)
470 .Default(NoSSE);
471 SSELevel = std::max(SSELevel, Level);
472
473 HasFloat16 = SSELevel >= SSE2;
474
475 // X86 target has bfloat16 emulation support in the backend, where
476 // bfloat16 is treated as a 32-bit float, arithmetic operations are
477 // performed in 32-bit, and the result is converted back to bfloat16.
478 // Truncation and extension between bfloat16 and 32-bit float are supported
479 // by the compiler-rt library. However, native bfloat16 support is currently
480 // not available in the X86 target. Hence, HasFullBFloat16 will be false
481 // until native bfloat16 support is available. HasFullBFloat16 is used to
482 // determine whether to automatically use excess floating point precision
483 // for bfloat16 arithmetic operations in the front-end.
484 HasBFloat16 = SSELevel >= SSE2;
485
486 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
487 .Case("+xop", XOP)
488 .Case("+fma4", FMA4)
489 .Case("+sse4a", SSE4A)
490 .Default(NoXOP);
491 XOPLevel = std::max(XOPLevel, XLevel);
492 }
493
494 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
495 // matches the selected sse level.
496 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
497 (FPMath == FP_387 && SSELevel >= SSE1)) {
498 Diags.Report(diag::err_target_unsupported_fpmath)
499 << (FPMath == FP_SSE ? "sse" : "387");
500 return false;
501 }
502
503 // FIXME: We should allow long double type on 32-bits to match with GCC.
504 // This requires backend to be able to lower f80 without x87 first.
505 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
506 HasLongDouble = false;
507
508 return true;
509}
510
511/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
512/// definitions for this particular subtarget.
513void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
514 MacroBuilder &Builder) const {
515 // Inline assembly supports X86 flag outputs.
516 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
517
518 std::string CodeModel = getTargetOpts().CodeModel;
519 if (CodeModel == "default")
520 CodeModel = "small";
521 Builder.defineMacro("__code_model_" + CodeModel + "__");
522
523 // Target identification.
524 if (getTriple().getArch() == llvm::Triple::x86_64) {
525 Builder.defineMacro("__amd64__");
526 Builder.defineMacro("__amd64");
527 Builder.defineMacro("__x86_64");
528 Builder.defineMacro("__x86_64__");
529 if (getTriple().getArchName() == "x86_64h") {
530 Builder.defineMacro("__x86_64h");
531 Builder.defineMacro("__x86_64h__");
532 }
533 } else {
534 DefineStd(Builder, "i386", Opts);
535 }
536
537 Builder.defineMacro("__SEG_GS");
538 Builder.defineMacro("__SEG_FS");
539 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
540 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
541
542 // Subtarget options.
543 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
544 // truly should be based on -mtune options.
545 using namespace llvm::X86;
546 switch (CPU) {
547 case CK_None:
548 break;
549 case CK_i386:
550 // The rest are coming from the i386 define above.
551 Builder.defineMacro("__tune_i386__");
552 break;
553 case CK_i486:
554 case CK_WinChipC6:
555 case CK_WinChip2:
556 case CK_C3:
557 defineCPUMacros(Builder, "i486");
558 break;
559 case CK_PentiumMMX:
560 Builder.defineMacro("__pentium_mmx__");
561 Builder.defineMacro("__tune_pentium_mmx__");
562 [[fallthrough]];
563 case CK_i586:
564 case CK_Pentium:
565 defineCPUMacros(Builder, "i586");
566 defineCPUMacros(Builder, "pentium");
567 break;
568 case CK_Pentium3:
569 case CK_PentiumM:
570 Builder.defineMacro("__tune_pentium3__");
571 [[fallthrough]];
572 case CK_Pentium2:
573 case CK_C3_2:
574 Builder.defineMacro("__tune_pentium2__");
575 [[fallthrough]];
576 case CK_PentiumPro:
577 case CK_i686:
578 defineCPUMacros(Builder, "i686");
579 defineCPUMacros(Builder, "pentiumpro");
580 break;
581 case CK_Pentium4:
582 defineCPUMacros(Builder, "pentium4");
583 break;
584 case CK_Yonah:
585 case CK_Prescott:
586 case CK_Nocona:
587 defineCPUMacros(Builder, "nocona");
588 break;
589 case CK_Core2:
590 case CK_Penryn:
591 defineCPUMacros(Builder, "core2");
592 break;
593 case CK_Bonnell:
594 defineCPUMacros(Builder, "atom");
595 break;
596 case CK_Silvermont:
597 defineCPUMacros(Builder, "slm");
598 break;
599 case CK_Goldmont:
600 defineCPUMacros(Builder, "goldmont");
601 break;
602 case CK_GoldmontPlus:
603 defineCPUMacros(Builder, "goldmont_plus");
604 break;
605 case CK_Tremont:
606 defineCPUMacros(Builder, "tremont");
607 break;
608 // Gracemont and later atom-cores use P-core cpu macros.
609 case CK_Gracemont:
610 case CK_Nehalem:
611 case CK_Westmere:
612 case CK_SandyBridge:
613 case CK_IvyBridge:
614 case CK_Haswell:
615 case CK_Broadwell:
616 case CK_SkylakeClient:
617 case CK_SkylakeServer:
618 case CK_Cascadelake:
619 case CK_Cooperlake:
620 case CK_Cannonlake:
621 case CK_IcelakeClient:
622 case CK_Rocketlake:
623 case CK_IcelakeServer:
624 case CK_Tigerlake:
625 case CK_SapphireRapids:
626 case CK_Alderlake:
627 case CK_Raptorlake:
628 case CK_Meteorlake:
629 case CK_Arrowlake:
630 case CK_ArrowlakeS:
631 case CK_Lunarlake:
632 case CK_Pantherlake:
633 case CK_Wildcatlake:
634 case CK_Novalake:
635 case CK_Sierraforest:
636 case CK_Grandridge:
637 case CK_Graniterapids:
638 case CK_GraniterapidsD:
639 case CK_Emeraldrapids:
640 case CK_Clearwaterforest:
641 case CK_Diamondrapids:
642 // FIXME: Historically, we defined this legacy name, it would be nice to
643 // remove it at some point. We've never exposed fine-grained names for
644 // recent primary x86 CPUs, and we should keep it that way.
645 defineCPUMacros(Builder, "corei7");
646 break;
647 case CK_KNL:
648 defineCPUMacros(Builder, "knl");
649 break;
650 case CK_KNM:
651 break;
652 case CK_Lakemont:
653 defineCPUMacros(Builder, "i586", /*Tuning*/false);
654 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
655 Builder.defineMacro("__tune_lakemont__");
656 break;
657 case CK_K6_2:
658 Builder.defineMacro("__k6_2__");
659 Builder.defineMacro("__tune_k6_2__");
660 [[fallthrough]];
661 case CK_K6_3:
662 if (CPU != CK_K6_2) { // In case of fallthrough
663 // FIXME: GCC may be enabling these in cases where some other k6
664 // architecture is specified but -m3dnow is explicitly provided. The
665 // exact semantics need to be determined and emulated here.
666 Builder.defineMacro("__k6_3__");
667 Builder.defineMacro("__tune_k6_3__");
668 }
669 [[fallthrough]];
670 case CK_K6:
671 defineCPUMacros(Builder, "k6");
672 break;
673 case CK_Athlon:
674 case CK_AthlonXP:
675 defineCPUMacros(Builder, "athlon");
676 if (SSELevel != NoSSE) {
677 Builder.defineMacro("__athlon_sse__");
678 Builder.defineMacro("__tune_athlon_sse__");
679 }
680 break;
681 case CK_K8:
682 case CK_K8SSE3:
683 case CK_x86_64:
684 defineCPUMacros(Builder, "k8");
685 break;
686 case CK_x86_64_v2:
687 case CK_x86_64_v3:
688 case CK_x86_64_v4:
689 break;
690 case CK_AMDFAM10:
691 defineCPUMacros(Builder, "amdfam10");
692 break;
693 case CK_BTVER1:
694 defineCPUMacros(Builder, "btver1");
695 break;
696 case CK_BTVER2:
697 defineCPUMacros(Builder, "btver2");
698 break;
699 case CK_BDVER1:
700 defineCPUMacros(Builder, "bdver1");
701 break;
702 case CK_BDVER2:
703 defineCPUMacros(Builder, "bdver2");
704 break;
705 case CK_BDVER3:
706 defineCPUMacros(Builder, "bdver3");
707 break;
708 case CK_BDVER4:
709 defineCPUMacros(Builder, "bdver4");
710 break;
711 case CK_ZNVER1:
712 defineCPUMacros(Builder, "znver1");
713 break;
714 case CK_ZNVER2:
715 defineCPUMacros(Builder, "znver2");
716 break;
717 case CK_ZNVER3:
718 defineCPUMacros(Builder, "znver3");
719 break;
720 case CK_ZNVER4:
721 defineCPUMacros(Builder, "znver4");
722 break;
723 case CK_ZNVER5:
724 defineCPUMacros(Builder, "znver5");
725 break;
726 case CK_ZNVER6:
727 defineCPUMacros(Builder, "znver6");
728 break;
729 case CK_Geode:
730 defineCPUMacros(Builder, "geode");
731 break;
732 }
733
734 // Target properties.
735 Builder.defineMacro("__REGISTER_PREFIX__", "");
736
737 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
738 // functions in glibc header files that use FP Stack inline asm which the
739 // backend can't deal with (PR879).
740 Builder.defineMacro("__NO_MATH_INLINES");
741
742 if (HasAES)
743 Builder.defineMacro("__AES__");
744
745 if (HasVAES)
746 Builder.defineMacro("__VAES__");
747
748 if (HasPCLMUL)
749 Builder.defineMacro("__PCLMUL__");
750
751 if (HasVPCLMULQDQ)
752 Builder.defineMacro("__VPCLMULQDQ__");
753
754 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
755 // the feature flag only applies to 64-bit mode.
756 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
757 Builder.defineMacro("__LAHF_SAHF__");
758
759 if (HasLZCNT)
760 Builder.defineMacro("__LZCNT__");
761
762 if (HasRDRND)
763 Builder.defineMacro("__RDRND__");
764
765 if (HasFSGSBASE)
766 Builder.defineMacro("__FSGSBASE__");
767
768 if (HasBMI)
769 Builder.defineMacro("__BMI__");
770
771 if (HasBMI2)
772 Builder.defineMacro("__BMI2__");
773
774 if (HasPOPCNT)
775 Builder.defineMacro("__POPCNT__");
776
777 if (HasRTM)
778 Builder.defineMacro("__RTM__");
779
780 if (HasPRFCHW)
781 Builder.defineMacro("__PRFCHW__");
782
783 if (HasRDSEED)
784 Builder.defineMacro("__RDSEED__");
785
786 if (HasADX)
787 Builder.defineMacro("__ADX__");
788
789 if (HasTBM)
790 Builder.defineMacro("__TBM__");
791
792 if (HasLWP)
793 Builder.defineMacro("__LWP__");
794
795 if (HasMWAITX)
796 Builder.defineMacro("__MWAITX__");
797
798 if (HasMOVBE)
799 Builder.defineMacro("__MOVBE__");
800
801 switch (XOPLevel) {
802 case XOP:
803 Builder.defineMacro("__XOP__");
804 [[fallthrough]];
805 case FMA4:
806 Builder.defineMacro("__FMA4__");
807 [[fallthrough]];
808 case SSE4A:
809 Builder.defineMacro("__SSE4A__");
810 [[fallthrough]];
811 case NoXOP:
812 break;
813 }
814
815 if (HasFMA)
816 Builder.defineMacro("__FMA__");
817
818 if (HasF16C)
819 Builder.defineMacro("__F16C__");
820
821 if (HasGFNI)
822 Builder.defineMacro("__GFNI__");
823
824 if (HasAVX10_1) {
825 Builder.defineMacro("__AVX10_1__");
826 Builder.defineMacro("__AVX10_1_512__");
827 }
828 if (HasAVX10_2) {
829 Builder.defineMacro("__AVX10_2__");
830 Builder.defineMacro("__AVX10_2_512__");
831 }
832 if (HasAVX512CD)
833 Builder.defineMacro("__AVX512CD__");
834 if (HasAVX512VPOPCNTDQ)
835 Builder.defineMacro("__AVX512VPOPCNTDQ__");
836 if (HasAVX512VNNI)
837 Builder.defineMacro("__AVX512VNNI__");
838 if (HasAVX512BF16)
839 Builder.defineMacro("__AVX512BF16__");
840 if (HasAVX512FP16)
841 Builder.defineMacro("__AVX512FP16__");
842 if (HasAVX512DQ)
843 Builder.defineMacro("__AVX512DQ__");
844 if (HasAVX512BITALG)
845 Builder.defineMacro("__AVX512BITALG__");
846 if (HasAVX512BW)
847 Builder.defineMacro("__AVX512BW__");
848 if (HasAVX512VL) {
849 Builder.defineMacro("__AVX512VL__");
850 }
851 if (HasAVX512VBMI)
852 Builder.defineMacro("__AVX512VBMI__");
853 if (HasAVX512VBMI2)
854 Builder.defineMacro("__AVX512VBMI2__");
855 if (HasAVX512IFMA)
856 Builder.defineMacro("__AVX512IFMA__");
857 if (HasAVX512VP2INTERSECT)
858 Builder.defineMacro("__AVX512VP2INTERSECT__");
859 if (HasSHA)
860 Builder.defineMacro("__SHA__");
861 if (HasSHA512)
862 Builder.defineMacro("__SHA512__");
863
864 if (HasFXSR)
865 Builder.defineMacro("__FXSR__");
866 if (HasXSAVE)
867 Builder.defineMacro("__XSAVE__");
868 if (HasXSAVEOPT)
869 Builder.defineMacro("__XSAVEOPT__");
870 if (HasXSAVEC)
871 Builder.defineMacro("__XSAVEC__");
872 if (HasXSAVES)
873 Builder.defineMacro("__XSAVES__");
874 if (HasPKU)
875 Builder.defineMacro("__PKU__");
876 if (HasCLFLUSHOPT)
877 Builder.defineMacro("__CLFLUSHOPT__");
878 if (HasCLWB)
879 Builder.defineMacro("__CLWB__");
880 if (HasWBNOINVD)
881 Builder.defineMacro("__WBNOINVD__");
882 if (HasSHSTK)
883 Builder.defineMacro("__SHSTK__");
884 if (HasSGX)
885 Builder.defineMacro("__SGX__");
886 if (HasSM3)
887 Builder.defineMacro("__SM3__");
888 if (HasSM4)
889 Builder.defineMacro("__SM4__");
890 if (HasPREFETCHI)
891 Builder.defineMacro("__PREFETCHI__");
892 if (HasCLZERO)
893 Builder.defineMacro("__CLZERO__");
894 if (HasKL)
895 Builder.defineMacro("__KL__");
896 if (HasWIDEKL)
897 Builder.defineMacro("__WIDEKL__");
898 if (HasRDPID)
899 Builder.defineMacro("__RDPID__");
900 if (HasRDPRU)
901 Builder.defineMacro("__RDPRU__");
902 if (HasCLDEMOTE)
903 Builder.defineMacro("__CLDEMOTE__");
904 if (HasWAITPKG)
905 Builder.defineMacro("__WAITPKG__");
906 if (HasMOVDIRI)
907 Builder.defineMacro("__MOVDIRI__");
908 if (HasMOVDIR64B)
909 Builder.defineMacro("__MOVDIR64B__");
910 if (HasMOVRS)
911 Builder.defineMacro("__MOVRS__");
912 if (HasPCONFIG)
913 Builder.defineMacro("__PCONFIG__");
914 if (HasPTWRITE)
915 Builder.defineMacro("__PTWRITE__");
916 if (HasINVPCID)
917 Builder.defineMacro("__INVPCID__");
918 if (HasENQCMD)
919 Builder.defineMacro("__ENQCMD__");
920 if (HasHRESET)
921 Builder.defineMacro("__HRESET__");
922 if (HasAMXTILE)
923 Builder.defineMacro("__AMX_TILE__");
924 if (HasAMXINT8)
925 Builder.defineMacro("__AMX_INT8__");
926 if (HasAMXBF16)
927 Builder.defineMacro("__AMX_BF16__");
928 if (HasAMXFP16)
929 Builder.defineMacro("__AMX_FP16__");
930 if (HasAMXCOMPLEX)
931 Builder.defineMacro("__AMX_COMPLEX__");
932 if (HasAMXFP8)
933 Builder.defineMacro("__AMX_FP8__");
934 if (HasAMXMOVRS)
935 Builder.defineMacro("__AMX_MOVRS__");
936 if (HasAMXAVX512)
937 Builder.defineMacro("__AMX_AVX512__");
938 if (HasAMXTF32)
939 Builder.defineMacro("__AMX_TF32__");
940 if (HasCMPCCXADD)
941 Builder.defineMacro("__CMPCCXADD__");
942 if (HasRAOINT)
943 Builder.defineMacro("__RAOINT__");
944 if (HasAVXIFMA)
945 Builder.defineMacro("__AVXIFMA__");
946 if (HasAVXNECONVERT)
947 Builder.defineMacro("__AVXNECONVERT__");
948 if (HasAVXVNNI)
949 Builder.defineMacro("__AVXVNNI__");
950 if (HasAVXVNNIINT16)
951 Builder.defineMacro("__AVXVNNIINT16__");
952 if (HasAVXVNNIINT8)
953 Builder.defineMacro("__AVXVNNIINT8__");
954 if (HasSERIALIZE)
955 Builder.defineMacro("__SERIALIZE__");
956 if (HasTSXLDTRK)
957 Builder.defineMacro("__TSXLDTRK__");
958 if (HasUINTR)
959 Builder.defineMacro("__UINTR__");
960 if (HasUSERMSR)
961 Builder.defineMacro("__USERMSR__");
962 if (HasCRC32)
963 Builder.defineMacro("__CRC32__");
964 if (HasEGPR)
965 Builder.defineMacro("__EGPR__");
966 if (HasPush2Pop2)
967 Builder.defineMacro("__PUSH2POP2__");
968 if (HasPPX)
969 Builder.defineMacro("__PPX__");
970 if (HasNDD)
971 Builder.defineMacro("__NDD__");
972 if (HasCCMP)
973 Builder.defineMacro("__CCMP__");
974 if (HasNF)
975 Builder.defineMacro("__NF__");
976 if (HasCF)
977 Builder.defineMacro("__CF__");
978 if (HasZU)
979 Builder.defineMacro("__ZU__");
980 if (HasJMPABS)
981 Builder.defineMacro("__JMPABS__");
982 if (HasEGPR && HasNDD && HasCCMP && HasNF && HasZU && HasJMPABS)
983 if (getTriple().isOSWindows() || (HasPush2Pop2 && HasPPX))
984 Builder.defineMacro("__APX_F__");
985 if (HasEGPR && HasInlineAsmUseGPR32)
986 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
987
988 // Each case falls through to the previous one here.
989 switch (SSELevel) {
990 case AVX512F:
991 Builder.defineMacro("__AVX512F__");
992 [[fallthrough]];
993 case AVX2:
994 Builder.defineMacro("__AVX2__");
995 [[fallthrough]];
996 case AVX:
997 Builder.defineMacro("__AVX__");
998 [[fallthrough]];
999 case SSE42:
1000 Builder.defineMacro("__SSE4_2__");
1001 [[fallthrough]];
1002 case SSE41:
1003 Builder.defineMacro("__SSE4_1__");
1004 [[fallthrough]];
1005 case SSSE3:
1006 Builder.defineMacro("__SSSE3__");
1007 [[fallthrough]];
1008 case SSE3:
1009 Builder.defineMacro("__SSE3__");
1010 [[fallthrough]];
1011 case SSE2:
1012 Builder.defineMacro("__SSE2__");
1013 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1014 [[fallthrough]];
1015 case SSE1:
1016 Builder.defineMacro("__SSE__");
1017 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1018 [[fallthrough]];
1019 case NoSSE:
1020 break;
1021 }
1022
1023 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1024 switch (SSELevel) {
1025 case AVX512F:
1026 case AVX2:
1027 case AVX:
1028 case SSE42:
1029 case SSE41:
1030 case SSSE3:
1031 case SSE3:
1032 case SSE2:
1033 Builder.defineMacro("_M_IX86_FP", Twine(2));
1034 break;
1035 case SSE1:
1036 Builder.defineMacro("_M_IX86_FP", Twine(1));
1037 break;
1038 default:
1039 Builder.defineMacro("_M_IX86_FP", Twine(0));
1040 break;
1041 }
1042 }
1043
1044 // Each case falls through to the previous one here.
1045 if (HasMMX) {
1046 Builder.defineMacro("__MMX__");
1047 }
1048
1049 if (CPU >= CK_i486 || CPU == CK_None) {
1050 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1051 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1052 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1053 }
1054 if (HasCX8)
1055 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1056 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1057 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1058
1059 if (HasFloat128)
1060 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1061
1062 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1063 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1064 Opts.CFProtectionBranch});
1065}
1066
1067bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1068 return llvm::StringSwitch<bool>(Name)
1069 .Case("adx", true)
1070 .Case("aes", true)
1071 .Case("amx-avx512", true)
1072 .Case("amx-bf16", true)
1073 .Case("amx-complex", true)
1074 .Case("amx-fp16", true)
1075 .Case("amx-fp8", true)
1076 .Case("amx-int8", true)
1077 .Case("amx-movrs", true)
1078 .Case("amx-tf32", true)
1079 .Case("amx-tile", true)
1080 .Case("avx", true)
1081 .Case("avx10.1", true)
1082 .Case("avx10.2", true)
1083 .Case("avx2", true)
1084 .Case("avx512f", true)
1085 .Case("avx512cd", true)
1086 .Case("avx512vpopcntdq", true)
1087 .Case("avx512vnni", true)
1088 .Case("avx512bf16", true)
1089 .Case("avx512fp16", true)
1090 .Case("avx512dq", true)
1091 .Case("avx512bitalg", true)
1092 .Case("avx512bw", true)
1093 .Case("avx512vl", true)
1094 .Case("avx512vbmi", true)
1095 .Case("avx512vbmi2", true)
1096 .Case("avx512ifma", true)
1097 .Case("avx512vp2intersect", true)
1098 .Case("avxifma", true)
1099 .Case("avxneconvert", true)
1100 .Case("avxvnni", true)
1101 .Case("avxvnniint16", true)
1102 .Case("avxvnniint8", true)
1103 .Case("bmi", true)
1104 .Case("bmi2", true)
1105 .Case("cldemote", true)
1106 .Case("clflushopt", true)
1107 .Case("clwb", true)
1108 .Case("clzero", true)
1109 .Case("cmpccxadd", true)
1110 .Case("crc32", true)
1111 .Case("cx16", true)
1112 .Case("enqcmd", true)
1113 .Case("f16c", true)
1114 .Case("fma", true)
1115 .Case("fma4", true)
1116 .Case("fsgsbase", true)
1117 .Case("fxsr", true)
1118 .Case("general-regs-only", true)
1119 .Case("gfni", true)
1120 .Case("hreset", true)
1121 .Case("invpcid", true)
1122 .Case("kl", true)
1123 .Case("widekl", true)
1124 .Case("lwp", true)
1125 .Case("lzcnt", true)
1126 .Case("mmx", true)
1127 .Case("movbe", true)
1128 .Case("movrs", true)
1129 .Case("movdiri", true)
1130 .Case("movdir64b", true)
1131 .Case("mwaitx", true)
1132 .Case("pclmul", true)
1133 .Case("pconfig", true)
1134 .Case("pku", true)
1135 .Case("popcnt", true)
1136 .Case("prefer-256-bit", true)
1137 .Case("prefetchi", true)
1138 .Case("prfchw", true)
1139 .Case("ptwrite", true)
1140 .Case("raoint", true)
1141 .Case("rdpid", true)
1142 .Case("rdpru", true)
1143 .Case("rdrnd", true)
1144 .Case("rdseed", true)
1145 .Case("rtm", true)
1146 .Case("sahf", true)
1147 .Case("serialize", true)
1148 .Case("sgx", true)
1149 .Case("sha", true)
1150 .Case("sha512", true)
1151 .Case("shstk", true)
1152 .Case("sm3", true)
1153 .Case("sm4", true)
1154 .Case("sse", true)
1155 .Case("sse2", true)
1156 .Case("sse3", true)
1157 .Case("ssse3", true)
1158 .Case("sse4", true)
1159 .Case("sse4.1", true)
1160 .Case("sse4.2", true)
1161 .Case("sse4a", true)
1162 .Case("tbm", true)
1163 .Case("tsxldtrk", true)
1164 .Case("uintr", true)
1165 .Case("usermsr", true)
1166 .Case("vaes", true)
1167 .Case("vpclmulqdq", true)
1168 .Case("wbnoinvd", true)
1169 .Case("waitpkg", true)
1170 .Case("x87", true)
1171 .Case("xop", true)
1172 .Case("xsave", true)
1173 .Case("xsavec", true)
1174 .Case("xsaves", true)
1175 .Case("xsaveopt", true)
1176 .Case("egpr", true)
1177 .Case("push2pop2", true)
1178 .Case("ppx", true)
1179 .Case("ndd", true)
1180 .Case("ccmp", true)
1181 .Case("nf", true)
1182 .Case("cf", true)
1183 .Case("zu", true)
1184 .Case("jmpabs", true)
1185 .Default(false);
1186}
1187
1188bool X86TargetInfo::hasFeature(StringRef Feature) const {
1189 return llvm::StringSwitch<bool>(Feature)
1190 .Case("adx", HasADX)
1191 .Case("aes", HasAES)
1192 .Case("amx-avx512", HasAMXAVX512)
1193 .Case("amx-bf16", HasAMXBF16)
1194 .Case("amx-complex", HasAMXCOMPLEX)
1195 .Case("amx-fp16", HasAMXFP16)
1196 .Case("amx-fp8", HasAMXFP8)
1197 .Case("amx-int8", HasAMXINT8)
1198 .Case("amx-movrs", HasAMXMOVRS)
1199 .Case("amx-tf32", HasAMXTF32)
1200 .Case("amx-tile", HasAMXTILE)
1201 .Case("avx", SSELevel >= AVX)
1202 .Case("avx10.1", HasAVX10_1)
1203 .Case("avx10.2", HasAVX10_2)
1204 .Case("avx2", SSELevel >= AVX2)
1205 .Case("avx512f", SSELevel >= AVX512F)
1206 .Case("avx512cd", HasAVX512CD)
1207 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1208 .Case("avx512vnni", HasAVX512VNNI)
1209 .Case("avx512bf16", HasAVX512BF16)
1210 .Case("avx512fp16", HasAVX512FP16)
1211 .Case("avx512dq", HasAVX512DQ)
1212 .Case("avx512bitalg", HasAVX512BITALG)
1213 .Case("avx512bw", HasAVX512BW)
1214 .Case("avx512vl", HasAVX512VL)
1215 .Case("avx512vbmi", HasAVX512VBMI)
1216 .Case("avx512vbmi2", HasAVX512VBMI2)
1217 .Case("avx512ifma", HasAVX512IFMA)
1218 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1219 .Case("avxifma", HasAVXIFMA)
1220 .Case("avxneconvert", HasAVXNECONVERT)
1221 .Case("avxvnni", HasAVXVNNI)
1222 .Case("avxvnniint16", HasAVXVNNIINT16)
1223 .Case("avxvnniint8", HasAVXVNNIINT8)
1224 .Case("bmi", HasBMI)
1225 .Case("bmi2", HasBMI2)
1226 .Case("cldemote", HasCLDEMOTE)
1227 .Case("clflushopt", HasCLFLUSHOPT)
1228 .Case("clwb", HasCLWB)
1229 .Case("clzero", HasCLZERO)
1230 .Case("cmpccxadd", HasCMPCCXADD)
1231 .Case("crc32", HasCRC32)
1232 .Case("cx8", HasCX8)
1233 .Case("cx16", HasCX16)
1234 .Case("enqcmd", HasENQCMD)
1235 .Case("f16c", HasF16C)
1236 .Case("fma", HasFMA)
1237 .Case("fma4", XOPLevel >= FMA4)
1238 .Case("fsgsbase", HasFSGSBASE)
1239 .Case("fxsr", HasFXSR)
1240 .Case("gfni", HasGFNI)
1241 .Case("hreset", HasHRESET)
1242 .Case("invpcid", HasINVPCID)
1243 .Case("kl", HasKL)
1244 .Case("widekl", HasWIDEKL)
1245 .Case("lwp", HasLWP)
1246 .Case("lzcnt", HasLZCNT)
1247 .Case("mmx", HasMMX)
1248 .Case("movbe", HasMOVBE)
1249 .Case("movrs", HasMOVRS)
1250 .Case("movdiri", HasMOVDIRI)
1251 .Case("movdir64b", HasMOVDIR64B)
1252 .Case("mwaitx", HasMWAITX)
1253 .Case("pclmul", HasPCLMUL)
1254 .Case("pconfig", HasPCONFIG)
1255 .Case("pku", HasPKU)
1256 .Case("popcnt", HasPOPCNT)
1257 .Case("prefetchi", HasPREFETCHI)
1258 .Case("prfchw", HasPRFCHW)
1259 .Case("ptwrite", HasPTWRITE)
1260 .Case("raoint", HasRAOINT)
1261 .Case("rdpid", HasRDPID)
1262 .Case("rdpru", HasRDPRU)
1263 .Case("rdrnd", HasRDRND)
1264 .Case("rdseed", HasRDSEED)
1265 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1266 .Case("rtm", HasRTM)
1267 .Case("sahf", HasLAHFSAHF)
1268 .Case("serialize", HasSERIALIZE)
1269 .Case("sgx", HasSGX)
1270 .Case("sha", HasSHA)
1271 .Case("sha512", HasSHA512)
1272 .Case("shstk", HasSHSTK)
1273 .Case("sm3", HasSM3)
1274 .Case("sm4", HasSM4)
1275 .Case("sse", SSELevel >= SSE1)
1276 .Case("sse2", SSELevel >= SSE2)
1277 .Case("sse3", SSELevel >= SSE3)
1278 .Case("ssse3", SSELevel >= SSSE3)
1279 .Case("sse4.1", SSELevel >= SSE41)
1280 .Case("sse4.2", SSELevel >= SSE42)
1281 .Case("sse4a", XOPLevel >= SSE4A)
1282 .Case("tbm", HasTBM)
1283 .Case("tsxldtrk", HasTSXLDTRK)
1284 .Case("uintr", HasUINTR)
1285 .Case("usermsr", HasUSERMSR)
1286 .Case("vaes", HasVAES)
1287 .Case("vpclmulqdq", HasVPCLMULQDQ)
1288 .Case("wbnoinvd", HasWBNOINVD)
1289 .Case("waitpkg", HasWAITPKG)
1290 .Case("x86", true)
1291 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1292 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1293 .Case("x87", HasX87)
1294 .Case("xop", XOPLevel >= XOP)
1295 .Case("xsave", HasXSAVE)
1296 .Case("xsavec", HasXSAVEC)
1297 .Case("xsaves", HasXSAVES)
1298 .Case("xsaveopt", HasXSAVEOPT)
1299 .Case("fullbf16", HasFullBFloat16)
1300 .Case("egpr", HasEGPR)
1301 .Case("push2pop2", HasPush2Pop2)
1302 .Case("ppx", HasPPX)
1303 .Case("ndd", HasNDD)
1304 .Case("ccmp", HasCCMP)
1305 .Case("nf", HasNF)
1306 .Case("cf", HasCF)
1307 .Case("zu", HasZU)
1308 .Case("jmpabs", HasJMPABS)
1309 .Case("branch-hint", HasBranchHint)
1310 .Default(false);
1311}
1312
1313// We can't use a generic validation scheme for the features accepted here
1314// versus subtarget features accepted in the target attribute because the
1315// bitfield structure that's initialized in the runtime only supports the
1316// below currently rather than the full range of subtarget features. (See
1317// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1318bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1319 return llvm::StringSwitch<bool>(FeatureStr)
1320#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1321#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1322#include "llvm/TargetParser/X86TargetParser.def"
1323 .Default(false);
1324}
1325
1326static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1327 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1328#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1329 .Case(STR, llvm::X86::FEATURE_##ENUM)
1330
1331#include "llvm/TargetParser/X86TargetParser.def"
1332 ;
1333 // Note, this function should only be used after ensuring the value is
1334 // correct, so it asserts if the value is out of range.
1335}
1336
1337llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1338 auto getPriority = [](StringRef Feature) -> unsigned {
1339 // Valid CPUs have a 'key feature' that compares just better than its key
1340 // feature.
1341 using namespace llvm::X86;
1342 CPUKind Kind = parseArchX86(Feature);
1343 if (Kind != CK_None) {
1344 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1345 return (getFeaturePriority(KeyFeature) << 1) + 1;
1346 }
1347 // Now we know we have a feature, so get its priority and shift it a few so
1348 // that we have sufficient room for the CPUs (above).
1349 return getFeaturePriority(getFeature(Feature)) << 1;
1350 };
1351
1352 unsigned Priority = 0;
1353 for (StringRef Feature : Features)
1354 if (!Feature.empty())
1355 Priority = std::max(Priority, getPriority(Feature));
1356 return llvm::APInt(32, Priority);
1357}
1358
1359bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1360 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1361}
1362
1363char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1364 return llvm::X86::getCPUDispatchMangling(Name);
1365}
1366
1367void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1368 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1369 SmallVector<StringRef, 32> TargetCPUFeatures;
1370 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1371 for (auto &F : TargetCPUFeatures)
1372 Features.push_back(F);
1373}
1374
1375// We can't use a generic validation scheme for the cpus accepted here
1376// versus subtarget cpus accepted in the target attribute because the
1377// variables intitialized by the runtime only support the below currently
1378// rather than the full range of cpus.
1379bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1380 return llvm::StringSwitch<bool>(FeatureStr)
1381#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1382#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1383#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1384#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1385#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1386#include "llvm/TargetParser/X86TargetParser.def"
1387 .Default(false);
1388}
1389
1390static unsigned matchAsmCCConstraint(const char *Name) {
1391 auto RV = llvm::StringSwitch<unsigned>(Name)
1392 .Case("@cca", 4)
1393 .Case("@ccae", 5)
1394 .Case("@ccb", 4)
1395 .Case("@ccbe", 5)
1396 .Case("@ccc", 4)
1397 .Case("@cce", 4)
1398 .Case("@ccz", 4)
1399 .Case("@ccg", 4)
1400 .Case("@ccge", 5)
1401 .Case("@ccl", 4)
1402 .Case("@ccle", 5)
1403 .Case("@ccna", 5)
1404 .Case("@ccnae", 6)
1405 .Case("@ccnb", 5)
1406 .Case("@ccnbe", 6)
1407 .Case("@ccnc", 5)
1408 .Case("@ccne", 5)
1409 .Case("@ccnz", 5)
1410 .Case("@ccng", 5)
1411 .Case("@ccnge", 6)
1412 .Case("@ccnl", 5)
1413 .Case("@ccnle", 6)
1414 .Case("@ccno", 5)
1415 .Case("@ccnp", 5)
1416 .Case("@ccns", 5)
1417 .Case("@cco", 4)
1418 .Case("@ccp", 4)
1419 .Case("@ccs", 4)
1420 .Default(0);
1421 return RV;
1422}
1423
1424bool X86TargetInfo::validateAsmConstraint(
1425 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1426 switch (*Name) {
1427 default:
1428 return false;
1429 // Constant constraints.
1430 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1431 // instructions.
1432 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1433 // x86_64 instructions.
1434 case 's':
1435 Info.setRequiresImmediate();
1436 return true;
1437 case 'I':
1438 Info.setRequiresImmediate(0, 31);
1439 return true;
1440 case 'J':
1441 Info.setRequiresImmediate(0, 63);
1442 return true;
1443 case 'K':
1444 Info.setRequiresImmediate(-128, 127);
1445 return true;
1446 case 'L':
1447 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1448 return true;
1449 case 'M':
1450 Info.setRequiresImmediate(0, 3);
1451 return true;
1452 case 'N':
1453 Info.setRequiresImmediate(0, 255);
1454 return true;
1455 case 'O':
1456 Info.setRequiresImmediate(0, 127);
1457 return true;
1458 case 'W':
1459 switch (*++Name) {
1460 default:
1461 return false;
1462 case 's':
1463 Info.setAllowsRegister();
1464 return true;
1465 }
1466 // Register constraints.
1467 case 'Y': // 'Y' is the first character for several 2-character constraints.
1468 // Shift the pointer to the second character of the constraint.
1469 Name++;
1470 switch (*Name) {
1471 default:
1472 return false;
1473 case 'z': // First SSE register.
1474 case '2':
1475 case 't': // Any SSE register, when SSE2 is enabled.
1476 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1477 case 'm': // Any MMX register, when inter-unit moves enabled.
1478 case 'k': // AVX512 arch mask registers: k1-k7.
1479 Info.setAllowsRegister();
1480 return true;
1481 }
1482 case 'f': // Any x87 floating point stack register.
1483 // Constraint 'f' cannot be used for output operands.
1484 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1485 return false;
1486 Info.setAllowsRegister();
1487 return true;
1488 case 'a': // eax.
1489 case 'b': // ebx.
1490 case 'c': // ecx.
1491 case 'd': // edx.
1492 case 'S': // esi.
1493 case 'D': // edi.
1494 case 'A': // edx:eax.
1495 case 't': // Top of floating point stack.
1496 case 'u': // Second from top of floating point stack.
1497 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1498 case 'y': // Any MMX register.
1499 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1500 case 'x': // Any SSE register.
1501 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1502 // for intermideate k reg operations).
1503 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1504 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1505 case 'l': // "Index" registers: any general register that can be used as an
1506 // index in a base+index memory access.
1507 Info.setAllowsRegister();
1508 return true;
1509 // Floating point constant constraints.
1510 case 'C': // SSE floating point constant.
1511 case 'G': // x87 floating point constant.
1512 return true;
1513 case 'j':
1514 Name++;
1515 switch (*Name) {
1516 default:
1517 return false;
1518 case 'r':
1519 Info.setAllowsRegister();
1520 return true;
1521 case 'R':
1522 Info.setAllowsRegister();
1523 return true;
1524 }
1525 case '@':
1526 // CC condition changes.
1527 if (auto Len = matchAsmCCConstraint(Name)) {
1528 Name += Len - 1;
1529 Info.setAllowsRegister();
1530 Info.setOutputOperandBounds(0, 2);
1531 return true;
1532 }
1533 return false;
1534 }
1535}
1536
1537// Below is based on the following information:
1538// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1539// | Processor Name | Cache Line Size (Bytes) | Source |
1540// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1541// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1542// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1543// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1544// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1545// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1546// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1547// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1548// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1549// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1550// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1551// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1552// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1553// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1554// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1555// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1556// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1557// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1558// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1559std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1560 using namespace llvm::X86;
1561 switch (CPU) {
1562 // i386
1563 case CK_i386:
1564 // i486
1565 case CK_i486:
1566 case CK_WinChipC6:
1567 case CK_WinChip2:
1568 case CK_C3:
1569 // Lakemont
1570 case CK_Lakemont:
1571 return 16;
1572
1573 // i586
1574 case CK_i586:
1575 case CK_Pentium:
1576 case CK_PentiumMMX:
1577 // i686
1578 case CK_PentiumPro:
1579 case CK_i686:
1580 case CK_Pentium2:
1581 case CK_Pentium3:
1582 case CK_PentiumM:
1583 case CK_C3_2:
1584 // K6
1585 case CK_K6:
1586 case CK_K6_2:
1587 case CK_K6_3:
1588 // Geode
1589 case CK_Geode:
1590 return 32;
1591
1592 // Netburst
1593 case CK_Pentium4:
1594 case CK_Prescott:
1595 case CK_Nocona:
1596 // Atom
1597 case CK_Bonnell:
1598 case CK_Silvermont:
1599 case CK_Goldmont:
1600 case CK_GoldmontPlus:
1601 case CK_Tremont:
1602 case CK_Gracemont:
1603
1604 case CK_Westmere:
1605 case CK_SandyBridge:
1606 case CK_IvyBridge:
1607 case CK_Haswell:
1608 case CK_Broadwell:
1609 case CK_SkylakeClient:
1610 case CK_SkylakeServer:
1611 case CK_Cascadelake:
1612 case CK_Nehalem:
1613 case CK_Cooperlake:
1614 case CK_Cannonlake:
1615 case CK_Tigerlake:
1616 case CK_SapphireRapids:
1617 case CK_IcelakeClient:
1618 case CK_Rocketlake:
1619 case CK_IcelakeServer:
1620 case CK_Alderlake:
1621 case CK_Raptorlake:
1622 case CK_Meteorlake:
1623 case CK_Arrowlake:
1624 case CK_ArrowlakeS:
1625 case CK_Lunarlake:
1626 case CK_Pantherlake:
1627 case CK_Wildcatlake:
1628 case CK_Novalake:
1629 case CK_Sierraforest:
1630 case CK_Grandridge:
1631 case CK_Graniterapids:
1632 case CK_GraniterapidsD:
1633 case CK_Emeraldrapids:
1634 case CK_Clearwaterforest:
1635 case CK_Diamondrapids:
1636 case CK_KNL:
1637 case CK_KNM:
1638 // K7
1639 case CK_Athlon:
1640 case CK_AthlonXP:
1641 // K8
1642 case CK_K8:
1643 case CK_K8SSE3:
1644 case CK_AMDFAM10:
1645 // Bobcat
1646 case CK_BTVER1:
1647 case CK_BTVER2:
1648 // Bulldozer
1649 case CK_BDVER1:
1650 case CK_BDVER2:
1651 case CK_BDVER3:
1652 case CK_BDVER4:
1653 // Zen
1654 case CK_ZNVER1:
1655 case CK_ZNVER2:
1656 case CK_ZNVER3:
1657 case CK_ZNVER4:
1658 case CK_ZNVER5:
1659 case CK_ZNVER6:
1660 // Deprecated
1661 case CK_x86_64:
1662 case CK_x86_64_v2:
1663 case CK_x86_64_v3:
1664 case CK_x86_64_v4:
1665 case CK_Yonah:
1666 case CK_Penryn:
1667 case CK_Core2:
1668 return 64;
1669
1670 // The following currently have unknown cache line sizes (but they are probably all 64):
1671 // Core
1672 case CK_None:
1673 return std::nullopt;
1674 }
1675 llvm_unreachable("Unknown CPU kind");
1676}
1677
1678bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1679 StringRef Constraint,
1680 unsigned Size) const {
1681 // Strip off constraint modifiers.
1682 Constraint = Constraint.ltrim("=+&");
1683
1684 return validateOperandSize(FeatureMap, Constraint, Size);
1685}
1686
1687bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1688 StringRef Constraint,
1689 unsigned Size) const {
1690 return validateOperandSize(FeatureMap, Constraint, Size);
1691}
1692
1693bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1694 StringRef Constraint,
1695 unsigned Size) const {
1696 switch (Constraint[0]) {
1697 default:
1698 break;
1699 case 'k':
1700 // Registers k0-k7 (AVX512) size limit is 64 bit.
1701 case 'y':
1702 return Size <= 64;
1703 case 'f':
1704 case 't':
1705 case 'u':
1706 return Size <= 128;
1707 case 'Y':
1708 // 'Y' is the first character for several 2-character constraints.
1709 switch (Constraint[1]) {
1710 default:
1711 return false;
1712 case 'm':
1713 // 'Ym' is synonymous with 'y'.
1714 case 'k':
1715 return Size <= 64;
1716 case 'z':
1717 // XMM0/YMM/ZMM0
1718 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1719 // ZMM0 can be used if target supports AVX512F.
1720 return Size <= 512U;
1721 else if (hasFeatureEnabled(FeatureMap, "avx"))
1722 // YMM0 can be used if target supports AVX.
1723 return Size <= 256U;
1724 else if (hasFeatureEnabled(FeatureMap, "sse"))
1725 return Size <= 128U;
1726 return false;
1727 case 'i':
1728 case 't':
1729 case '2':
1730 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1731 if (SSELevel < SSE2)
1732 return false;
1733 break;
1734 }
1735 break;
1736 case 'v':
1737 case 'x':
1738 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1739 // 512-bit zmm registers can be used if target supports AVX512F.
1740 return Size <= 512U;
1741 else if (hasFeatureEnabled(FeatureMap, "avx"))
1742 // 256-bit ymm registers can be used if target supports AVX.
1743 return Size <= 256U;
1744 return Size <= 128U;
1745
1746 }
1747
1748 return true;
1749}
1750
1751std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1752 switch (*Constraint) {
1753 case '@':
1754 if (auto Len = matchAsmCCConstraint(Constraint)) {
1755 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1756 Constraint += Len - 1;
1757 return Converted;
1758 }
1759 return std::string(1, *Constraint);
1760 case 'a':
1761 return std::string("{ax}");
1762 case 'b':
1763 return std::string("{bx}");
1764 case 'c':
1765 return std::string("{cx}");
1766 case 'd':
1767 return std::string("{dx}");
1768 case 'S':
1769 return std::string("{si}");
1770 case 'D':
1771 return std::string("{di}");
1772 case 'p': // Keep 'p' constraint (address).
1773 return std::string("p");
1774 case 't': // top of floating point stack.
1775 return std::string("{st}");
1776 case 'u': // second from top of floating point stack.
1777 return std::string("{st(1)}"); // second from top of floating point stack.
1778 case 'W':
1779 assert(Constraint[1] == 's');
1780 return '^' + std::string(Constraint++, 2);
1781 case 'Y':
1782 switch (Constraint[1]) {
1783 default:
1784 // Break from inner switch and fall through (copy single char),
1785 // continue parsing after copying the current constraint into
1786 // the return string.
1787 break;
1788 case 'k':
1789 case 'm':
1790 case 'i':
1791 case 't':
1792 case 'z':
1793 case '2':
1794 // "^" hints llvm that this is a 2 letter constraint.
1795 // "Constraint++" is used to promote the string iterator
1796 // to the next constraint.
1797 return std::string("^") + std::string(Constraint++, 2);
1798 }
1799 [[fallthrough]];
1800 case 'j':
1801 switch (Constraint[1]) {
1802 default:
1803 // Break from inner switch and fall through (copy single char),
1804 // continue parsing after copying the current constraint into
1805 // the return string.
1806 break;
1807 case 'r':
1808 case 'R':
1809 // "^" hints llvm that this is a 2 letter constraint.
1810 // "Constraint++" is used to promote the string iterator
1811 // to the next constraint.
1812 return std::string("^") + std::string(Constraint++, 2);
1813 }
1814 [[fallthrough]];
1815 default:
1816 return std::string(1, *Constraint);
1817 }
1818}
1819
1820void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1821 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1822 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1823}
1824
1825void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1826 llvm::X86::fillValidTuneCPUList(Values);
1827}
1828
1832
1836
1837llvm::SmallVector<Builtin::InfosShard>
1838X86_32TargetInfo::getTargetBuiltins() const {
1839 return {
1840 {&X86::BuiltinStrings, X86::BuiltinInfos},
1841 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1842 };
1843}
1844
1845llvm::SmallVector<Builtin::InfosShard>
1846X86_64TargetInfo::getTargetBuiltins() const {
1847 return {
1848 {&X86::BuiltinStrings, X86::BuiltinInfos},
1849 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1850 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1851 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1852 "__builtin_ia32_"},
1853 };
1854}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1559
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:232
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1326
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:232
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1554
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:327
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1323
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1452
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:568
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:238
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1559
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1424
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1337
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1829
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1363
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1751
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:513
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1367
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1379
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1678
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1693
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1825
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1359
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1318
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1067
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1188
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:219
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:186
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1820
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1833
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1687
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1838
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1846
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:79
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1234
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1198
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:144
Generated on for clang by doxygen 1.14.0