clang  9.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65 };
66 
68  {{"al", "ah", "eax", "rax"}, 0},
69  {{"bl", "bh", "ebx", "rbx"}, 3},
70  {{"cl", "ch", "ecx", "rcx"}, 2},
71  {{"dl", "dh", "edx", "rdx"}, 1},
72  {{"esi", "rsi"}, 4},
73  {{"edi", "rdi"}, 5},
74  {{"esp", "rsp"}, 7},
75  {{"ebp", "rbp"}, 6},
76  {{"r8d", "r8w", "r8b"}, 38},
77  {{"r9d", "r9w", "r9b"}, 39},
78  {{"r10d", "r10w", "r10b"}, 40},
79  {{"r11d", "r11w", "r11b"}, 41},
80  {{"r12d", "r12w", "r12b"}, 42},
81  {{"r13d", "r13w", "r13b"}, 43},
82  {{"r14d", "r14w", "r14b"}, 44},
83  {{"r15d", "r15w", "r15b"}, 45},
84 };
85 
86 } // namespace targets
87 } // namespace clang
88 
89 using namespace clang;
90 using namespace clang::targets;
91 
92 bool X86TargetInfo::setFPMath(StringRef Name) {
93  if (Name == "387") {
94  FPMath = FP_387;
95  return true;
96  }
97  if (Name == "sse") {
98  FPMath = FP_SSE;
99  return true;
100  }
101  return false;
102 }
103 
105  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106  const std::vector<std::string> &FeaturesVec) const {
107  // FIXME: This *really* should not be here.
108  // X86_64 always has SSE2.
109  if (getTriple().getArch() == llvm::Triple::x86_64)
110  setFeatureEnabledImpl(Features, "sse2", true);
111 
112  const CPUKind Kind = getCPUKind(CPU);
113 
114  // Enable X87 for all X86 processors but Lakemont.
115  if (Kind != CK_Lakemont)
116  setFeatureEnabledImpl(Features, "x87", true);
117 
118  // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
119  // compatibility.
120  if (Kind >= CK_i586 || Kind == CK_Generic)
121  setFeatureEnabledImpl(Features, "cx8", true);
122 
123  switch (Kind) {
124  case CK_Generic:
125  case CK_i386:
126  case CK_i486:
127  case CK_i586:
128  case CK_Pentium:
129  case CK_PentiumPro:
130  case CK_i686:
131  case CK_Lakemont:
132  break;
133 
134  case CK_PentiumMMX:
135  case CK_Pentium2:
136  case CK_K6:
137  case CK_WinChipC6:
138  setFeatureEnabledImpl(Features, "mmx", true);
139  break;
140 
141  case CK_IcelakeServer:
142  setFeatureEnabledImpl(Features, "pconfig", true);
143  setFeatureEnabledImpl(Features, "wbnoinvd", true);
144  LLVM_FALLTHROUGH;
145  case CK_IcelakeClient:
146  setFeatureEnabledImpl(Features, "vaes", true);
147  setFeatureEnabledImpl(Features, "gfni", true);
148  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
149  setFeatureEnabledImpl(Features, "avx512bitalg", true);
150  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
151  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
152  setFeatureEnabledImpl(Features, "rdpid", true);
153  LLVM_FALLTHROUGH;
154  case CK_Cannonlake:
155  setFeatureEnabledImpl(Features, "avx512ifma", true);
156  setFeatureEnabledImpl(Features, "avx512vbmi", true);
157  setFeatureEnabledImpl(Features, "sha", true);
158  LLVM_FALLTHROUGH;
159  case CK_Cascadelake:
160  //Cannonlake has no VNNI feature inside while Icelake has
161  if (Kind != CK_Cannonlake)
162  // CLK inherits all SKX features plus AVX512_VNNI
163  setFeatureEnabledImpl(Features, "avx512vnni", true);
164  LLVM_FALLTHROUGH;
165  case CK_SkylakeServer:
166  setFeatureEnabledImpl(Features, "avx512f", true);
167  setFeatureEnabledImpl(Features, "avx512cd", true);
168  setFeatureEnabledImpl(Features, "avx512dq", true);
169  setFeatureEnabledImpl(Features, "avx512bw", true);
170  setFeatureEnabledImpl(Features, "avx512vl", true);
171  setFeatureEnabledImpl(Features, "pku", true);
172  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
173  setFeatureEnabledImpl(Features, "clwb", true);
174  LLVM_FALLTHROUGH;
175  case CK_SkylakeClient:
176  setFeatureEnabledImpl(Features, "xsavec", true);
177  setFeatureEnabledImpl(Features, "xsaves", true);
178  setFeatureEnabledImpl(Features, "mpx", true);
179  if (Kind != CK_SkylakeServer
180  && Kind != CK_Cascadelake)
181  // SKX/CLX inherits all SKL features, except SGX
182  setFeatureEnabledImpl(Features, "sgx", true);
183  setFeatureEnabledImpl(Features, "clflushopt", true);
184  setFeatureEnabledImpl(Features, "aes", true);
185  LLVM_FALLTHROUGH;
186  case CK_Broadwell:
187  setFeatureEnabledImpl(Features, "rdseed", true);
188  setFeatureEnabledImpl(Features, "adx", true);
189  setFeatureEnabledImpl(Features, "prfchw", true);
190  LLVM_FALLTHROUGH;
191  case CK_Haswell:
192  setFeatureEnabledImpl(Features, "avx2", true);
193  setFeatureEnabledImpl(Features, "lzcnt", true);
194  setFeatureEnabledImpl(Features, "bmi", true);
195  setFeatureEnabledImpl(Features, "bmi2", true);
196  setFeatureEnabledImpl(Features, "fma", true);
197  setFeatureEnabledImpl(Features, "invpcid", true);
198  setFeatureEnabledImpl(Features, "movbe", true);
199  LLVM_FALLTHROUGH;
200  case CK_IvyBridge:
201  setFeatureEnabledImpl(Features, "rdrnd", true);
202  setFeatureEnabledImpl(Features, "f16c", true);
203  setFeatureEnabledImpl(Features, "fsgsbase", true);
204  LLVM_FALLTHROUGH;
205  case CK_SandyBridge:
206  setFeatureEnabledImpl(Features, "avx", true);
207  setFeatureEnabledImpl(Features, "xsave", true);
208  setFeatureEnabledImpl(Features, "xsaveopt", true);
209  LLVM_FALLTHROUGH;
210  case CK_Westmere:
211  setFeatureEnabledImpl(Features, "pclmul", true);
212  LLVM_FALLTHROUGH;
213  case CK_Nehalem:
214  setFeatureEnabledImpl(Features, "sse4.2", true);
215  LLVM_FALLTHROUGH;
216  case CK_Penryn:
217  setFeatureEnabledImpl(Features, "sse4.1", true);
218  LLVM_FALLTHROUGH;
219  case CK_Core2:
220  setFeatureEnabledImpl(Features, "ssse3", true);
221  setFeatureEnabledImpl(Features, "sahf", true);
222  LLVM_FALLTHROUGH;
223  case CK_Nocona:
224  setFeatureEnabledImpl(Features, "cx16", true);
225  LLVM_FALLTHROUGH;
226  case CK_Yonah:
227  case CK_Prescott:
228  setFeatureEnabledImpl(Features, "sse3", true);
229  LLVM_FALLTHROUGH;
230  case CK_PentiumM:
231  case CK_Pentium4:
232  case CK_x86_64:
233  setFeatureEnabledImpl(Features, "sse2", true);
234  LLVM_FALLTHROUGH;
235  case CK_Pentium3:
236  case CK_C3_2:
237  setFeatureEnabledImpl(Features, "sse", true);
238  setFeatureEnabledImpl(Features, "fxsr", true);
239  break;
240 
241  case CK_Tremont:
242  setFeatureEnabledImpl(Features, "cldemote", true);
243  setFeatureEnabledImpl(Features, "movdiri", true);
244  setFeatureEnabledImpl(Features, "movdir64b", true);
245  setFeatureEnabledImpl(Features, "gfni", true);
246  setFeatureEnabledImpl(Features, "waitpkg", true);
247  LLVM_FALLTHROUGH;
248  case CK_GoldmontPlus:
249  setFeatureEnabledImpl(Features, "ptwrite", true);
250  setFeatureEnabledImpl(Features, "rdpid", true);
251  setFeatureEnabledImpl(Features, "sgx", true);
252  LLVM_FALLTHROUGH;
253  case CK_Goldmont:
254  setFeatureEnabledImpl(Features, "sha", true);
255  setFeatureEnabledImpl(Features, "rdseed", true);
256  setFeatureEnabledImpl(Features, "xsave", true);
257  setFeatureEnabledImpl(Features, "xsaveopt", true);
258  setFeatureEnabledImpl(Features, "xsavec", true);
259  setFeatureEnabledImpl(Features, "xsaves", true);
260  setFeatureEnabledImpl(Features, "clflushopt", true);
261  setFeatureEnabledImpl(Features, "mpx", true);
262  setFeatureEnabledImpl(Features, "fsgsbase", true);
263  setFeatureEnabledImpl(Features, "aes", true);
264  LLVM_FALLTHROUGH;
265  case CK_Silvermont:
266  setFeatureEnabledImpl(Features, "rdrnd", true);
267  setFeatureEnabledImpl(Features, "pclmul", true);
268  setFeatureEnabledImpl(Features, "sse4.2", true);
269  setFeatureEnabledImpl(Features, "prfchw", true);
270  LLVM_FALLTHROUGH;
271  case CK_Bonnell:
272  setFeatureEnabledImpl(Features, "movbe", true);
273  setFeatureEnabledImpl(Features, "ssse3", true);
274  setFeatureEnabledImpl(Features, "fxsr", true);
275  setFeatureEnabledImpl(Features, "cx16", true);
276  setFeatureEnabledImpl(Features, "sahf", true);
277  break;
278 
279  case CK_KNM:
280  // TODO: Add avx5124fmaps/avx5124vnniw.
281  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
282  LLVM_FALLTHROUGH;
283  case CK_KNL:
284  setFeatureEnabledImpl(Features, "avx512f", true);
285  setFeatureEnabledImpl(Features, "avx512cd", true);
286  setFeatureEnabledImpl(Features, "avx512er", true);
287  setFeatureEnabledImpl(Features, "avx512pf", true);
288  setFeatureEnabledImpl(Features, "prfchw", true);
289  setFeatureEnabledImpl(Features, "prefetchwt1", true);
290  setFeatureEnabledImpl(Features, "fxsr", true);
291  setFeatureEnabledImpl(Features, "rdseed", true);
292  setFeatureEnabledImpl(Features, "adx", true);
293  setFeatureEnabledImpl(Features, "lzcnt", true);
294  setFeatureEnabledImpl(Features, "bmi", true);
295  setFeatureEnabledImpl(Features, "bmi2", true);
296  setFeatureEnabledImpl(Features, "fma", true);
297  setFeatureEnabledImpl(Features, "rdrnd", true);
298  setFeatureEnabledImpl(Features, "f16c", true);
299  setFeatureEnabledImpl(Features, "fsgsbase", true);
300  setFeatureEnabledImpl(Features, "aes", true);
301  setFeatureEnabledImpl(Features, "pclmul", true);
302  setFeatureEnabledImpl(Features, "cx16", true);
303  setFeatureEnabledImpl(Features, "xsaveopt", true);
304  setFeatureEnabledImpl(Features, "xsave", true);
305  setFeatureEnabledImpl(Features, "movbe", true);
306  setFeatureEnabledImpl(Features, "sahf", true);
307  break;
308 
309  case CK_K6_2:
310  case CK_K6_3:
311  case CK_WinChip2:
312  case CK_C3:
313  setFeatureEnabledImpl(Features, "3dnow", true);
314  break;
315 
316  case CK_AMDFAM10:
317  setFeatureEnabledImpl(Features, "sse4a", true);
318  setFeatureEnabledImpl(Features, "lzcnt", true);
319  setFeatureEnabledImpl(Features, "popcnt", true);
320  setFeatureEnabledImpl(Features, "sahf", true);
321  LLVM_FALLTHROUGH;
322  case CK_K8SSE3:
323  setFeatureEnabledImpl(Features, "sse3", true);
324  LLVM_FALLTHROUGH;
325  case CK_K8:
326  setFeatureEnabledImpl(Features, "sse2", true);
327  LLVM_FALLTHROUGH;
328  case CK_AthlonXP:
329  setFeatureEnabledImpl(Features, "sse", true);
330  setFeatureEnabledImpl(Features, "fxsr", true);
331  LLVM_FALLTHROUGH;
332  case CK_Athlon:
333  case CK_Geode:
334  setFeatureEnabledImpl(Features, "3dnowa", true);
335  break;
336 
337  case CK_BTVER2:
338  setFeatureEnabledImpl(Features, "avx", true);
339  setFeatureEnabledImpl(Features, "aes", true);
340  setFeatureEnabledImpl(Features, "pclmul", true);
341  setFeatureEnabledImpl(Features, "bmi", true);
342  setFeatureEnabledImpl(Features, "f16c", true);
343  setFeatureEnabledImpl(Features, "xsaveopt", true);
344  setFeatureEnabledImpl(Features, "movbe", true);
345  LLVM_FALLTHROUGH;
346  case CK_BTVER1:
347  setFeatureEnabledImpl(Features, "ssse3", true);
348  setFeatureEnabledImpl(Features, "sse4a", true);
349  setFeatureEnabledImpl(Features, "lzcnt", true);
350  setFeatureEnabledImpl(Features, "popcnt", true);
351  setFeatureEnabledImpl(Features, "prfchw", true);
352  setFeatureEnabledImpl(Features, "cx16", true);
353  setFeatureEnabledImpl(Features, "fxsr", true);
354  setFeatureEnabledImpl(Features, "sahf", true);
355  break;
356 
357  case CK_ZNVER2:
358  setFeatureEnabledImpl(Features, "clwb", true);
359  setFeatureEnabledImpl(Features, "rdpid", true);
360  setFeatureEnabledImpl(Features, "wbnoinvd", true);
361  LLVM_FALLTHROUGH;
362  case CK_ZNVER1:
363  setFeatureEnabledImpl(Features, "adx", true);
364  setFeatureEnabledImpl(Features, "aes", true);
365  setFeatureEnabledImpl(Features, "avx2", true);
366  setFeatureEnabledImpl(Features, "bmi", true);
367  setFeatureEnabledImpl(Features, "bmi2", true);
368  setFeatureEnabledImpl(Features, "clflushopt", true);
369  setFeatureEnabledImpl(Features, "clzero", true);
370  setFeatureEnabledImpl(Features, "cx16", true);
371  setFeatureEnabledImpl(Features, "f16c", true);
372  setFeatureEnabledImpl(Features, "fma", true);
373  setFeatureEnabledImpl(Features, "fsgsbase", true);
374  setFeatureEnabledImpl(Features, "fxsr", true);
375  setFeatureEnabledImpl(Features, "lzcnt", true);
376  setFeatureEnabledImpl(Features, "mwaitx", true);
377  setFeatureEnabledImpl(Features, "movbe", true);
378  setFeatureEnabledImpl(Features, "pclmul", true);
379  setFeatureEnabledImpl(Features, "popcnt", true);
380  setFeatureEnabledImpl(Features, "prfchw", true);
381  setFeatureEnabledImpl(Features, "rdrnd", true);
382  setFeatureEnabledImpl(Features, "rdseed", true);
383  setFeatureEnabledImpl(Features, "sahf", true);
384  setFeatureEnabledImpl(Features, "sha", true);
385  setFeatureEnabledImpl(Features, "sse4a", true);
386  setFeatureEnabledImpl(Features, "xsave", true);
387  setFeatureEnabledImpl(Features, "xsavec", true);
388  setFeatureEnabledImpl(Features, "xsaveopt", true);
389  setFeatureEnabledImpl(Features, "xsaves", true);
390  break;
391 
392  case CK_BDVER4:
393  setFeatureEnabledImpl(Features, "avx2", true);
394  setFeatureEnabledImpl(Features, "bmi2", true);
395  setFeatureEnabledImpl(Features, "mwaitx", true);
396  LLVM_FALLTHROUGH;
397  case CK_BDVER3:
398  setFeatureEnabledImpl(Features, "fsgsbase", true);
399  setFeatureEnabledImpl(Features, "xsaveopt", true);
400  LLVM_FALLTHROUGH;
401  case CK_BDVER2:
402  setFeatureEnabledImpl(Features, "bmi", true);
403  setFeatureEnabledImpl(Features, "fma", true);
404  setFeatureEnabledImpl(Features, "f16c", true);
405  setFeatureEnabledImpl(Features, "tbm", true);
406  LLVM_FALLTHROUGH;
407  case CK_BDVER1:
408  // xop implies avx, sse4a and fma4.
409  setFeatureEnabledImpl(Features, "xop", true);
410  setFeatureEnabledImpl(Features, "lwp", true);
411  setFeatureEnabledImpl(Features, "lzcnt", true);
412  setFeatureEnabledImpl(Features, "aes", true);
413  setFeatureEnabledImpl(Features, "pclmul", true);
414  setFeatureEnabledImpl(Features, "prfchw", true);
415  setFeatureEnabledImpl(Features, "cx16", true);
416  setFeatureEnabledImpl(Features, "fxsr", true);
417  setFeatureEnabledImpl(Features, "xsave", true);
418  setFeatureEnabledImpl(Features, "sahf", true);
419  break;
420  }
421  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
422  return false;
423 
424  // Can't do this earlier because we need to be able to explicitly enable
425  // or disable these features and the things that they depend upon.
426 
427  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
428  auto I = Features.find("sse4.2");
429  if (I != Features.end() && I->getValue() &&
430  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
431  FeaturesVec.end())
432  Features["popcnt"] = true;
433 
434  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
435  I = Features.find("3dnow");
436  if (I != Features.end() && I->getValue() &&
437  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
438  FeaturesVec.end())
439  Features["prfchw"] = true;
440 
441  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
442  // then enable MMX.
443  I = Features.find("sse");
444  if (I != Features.end() && I->getValue() &&
445  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
446  FeaturesVec.end())
447  Features["mmx"] = true;
448 
449  return true;
450 }
451 
452 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
453  X86SSEEnum Level, bool Enabled) {
454  if (Enabled) {
455  switch (Level) {
456  case AVX512F:
457  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
458  LLVM_FALLTHROUGH;
459  case AVX2:
460  Features["avx2"] = true;
461  LLVM_FALLTHROUGH;
462  case AVX:
463  Features["avx"] = true;
464  Features["xsave"] = true;
465  LLVM_FALLTHROUGH;
466  case SSE42:
467  Features["sse4.2"] = true;
468  LLVM_FALLTHROUGH;
469  case SSE41:
470  Features["sse4.1"] = true;
471  LLVM_FALLTHROUGH;
472  case SSSE3:
473  Features["ssse3"] = true;
474  LLVM_FALLTHROUGH;
475  case SSE3:
476  Features["sse3"] = true;
477  LLVM_FALLTHROUGH;
478  case SSE2:
479  Features["sse2"] = true;
480  LLVM_FALLTHROUGH;
481  case SSE1:
482  Features["sse"] = true;
483  LLVM_FALLTHROUGH;
484  case NoSSE:
485  break;
486  }
487  return;
488  }
489 
490  switch (Level) {
491  case NoSSE:
492  case SSE1:
493  Features["sse"] = false;
494  LLVM_FALLTHROUGH;
495  case SSE2:
496  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
497  Features["gfni"] = false;
498  LLVM_FALLTHROUGH;
499  case SSE3:
500  Features["sse3"] = false;
501  setXOPLevel(Features, NoXOP, false);
502  LLVM_FALLTHROUGH;
503  case SSSE3:
504  Features["ssse3"] = false;
505  LLVM_FALLTHROUGH;
506  case SSE41:
507  Features["sse4.1"] = false;
508  LLVM_FALLTHROUGH;
509  case SSE42:
510  Features["sse4.2"] = false;
511  LLVM_FALLTHROUGH;
512  case AVX:
513  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
514  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
515  setXOPLevel(Features, FMA4, false);
516  LLVM_FALLTHROUGH;
517  case AVX2:
518  Features["avx2"] = false;
519  LLVM_FALLTHROUGH;
520  case AVX512F:
521  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
522  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
523  Features["avx512vl"] = Features["avx512vbmi"] =
524  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
525  Features["avx512bitalg"] = Features["avx512vnni"] =
526  Features["avx512vbmi2"] = false;
527  break;
528  }
529 }
530 
531 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
532  MMX3DNowEnum Level, bool Enabled) {
533  if (Enabled) {
534  switch (Level) {
535  case AMD3DNowAthlon:
536  Features["3dnowa"] = true;
537  LLVM_FALLTHROUGH;
538  case AMD3DNow:
539  Features["3dnow"] = true;
540  LLVM_FALLTHROUGH;
541  case MMX:
542  Features["mmx"] = true;
543  LLVM_FALLTHROUGH;
544  case NoMMX3DNow:
545  break;
546  }
547  return;
548  }
549 
550  switch (Level) {
551  case NoMMX3DNow:
552  case MMX:
553  Features["mmx"] = false;
554  LLVM_FALLTHROUGH;
555  case AMD3DNow:
556  Features["3dnow"] = false;
557  LLVM_FALLTHROUGH;
558  case AMD3DNowAthlon:
559  Features["3dnowa"] = false;
560  break;
561  }
562 }
563 
564 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
565  bool Enabled) {
566  if (Enabled) {
567  switch (Level) {
568  case XOP:
569  Features["xop"] = true;
570  LLVM_FALLTHROUGH;
571  case FMA4:
572  Features["fma4"] = true;
573  setSSELevel(Features, AVX, true);
574  LLVM_FALLTHROUGH;
575  case SSE4A:
576  Features["sse4a"] = true;
577  setSSELevel(Features, SSE3, true);
578  LLVM_FALLTHROUGH;
579  case NoXOP:
580  break;
581  }
582  return;
583  }
584 
585  switch (Level) {
586  case NoXOP:
587  case SSE4A:
588  Features["sse4a"] = false;
589  LLVM_FALLTHROUGH;
590  case FMA4:
591  Features["fma4"] = false;
592  LLVM_FALLTHROUGH;
593  case XOP:
594  Features["xop"] = false;
595  break;
596  }
597 }
598 
599 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
600  StringRef Name, bool Enabled) {
601  // This is a bit of a hack to deal with the sse4 target feature when used
602  // as part of the target attribute. We handle sse4 correctly everywhere
603  // else. See below for more information on how we handle the sse4 options.
604  if (Name != "sse4")
605  Features[Name] = Enabled;
606 
607  if (Name == "mmx") {
608  setMMXLevel(Features, MMX, Enabled);
609  } else if (Name == "sse") {
610  setSSELevel(Features, SSE1, Enabled);
611  } else if (Name == "sse2") {
612  setSSELevel(Features, SSE2, Enabled);
613  } else if (Name == "sse3") {
614  setSSELevel(Features, SSE3, Enabled);
615  } else if (Name == "ssse3") {
616  setSSELevel(Features, SSSE3, Enabled);
617  } else if (Name == "sse4.2") {
618  setSSELevel(Features, SSE42, Enabled);
619  } else if (Name == "sse4.1") {
620  setSSELevel(Features, SSE41, Enabled);
621  } else if (Name == "3dnow") {
622  setMMXLevel(Features, AMD3DNow, Enabled);
623  } else if (Name == "3dnowa") {
624  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
625  } else if (Name == "aes") {
626  if (Enabled)
627  setSSELevel(Features, SSE2, Enabled);
628  else
629  Features["vaes"] = false;
630  } else if (Name == "vaes") {
631  if (Enabled) {
632  setSSELevel(Features, AVX, Enabled);
633  Features["aes"] = true;
634  }
635  } else if (Name == "pclmul") {
636  if (Enabled)
637  setSSELevel(Features, SSE2, Enabled);
638  else
639  Features["vpclmulqdq"] = false;
640  } else if (Name == "vpclmulqdq") {
641  if (Enabled) {
642  setSSELevel(Features, AVX, Enabled);
643  Features["pclmul"] = true;
644  }
645  } else if (Name == "gfni") {
646  if (Enabled)
647  setSSELevel(Features, SSE2, Enabled);
648  } else if (Name == "avx") {
649  setSSELevel(Features, AVX, Enabled);
650  } else if (Name == "avx2") {
651  setSSELevel(Features, AVX2, Enabled);
652  } else if (Name == "avx512f") {
653  setSSELevel(Features, AVX512F, Enabled);
654  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
655  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
656  Name == "avx512vbmi" || Name == "avx512ifma" ||
657  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
658  Name == "avx512vnni" || Name == "avx512vbmi2") {
659  if (Enabled)
660  setSSELevel(Features, AVX512F, Enabled);
661  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
662  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
663  Features["avx512bw"] = true;
664  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
665  if (Name == "avx512bw" && !Enabled)
666  Features["avx512vbmi"] = Features["avx512vbmi2"] =
667  Features["avx512bitalg"] = false;
668  } else if (Name == "fma") {
669  if (Enabled)
670  setSSELevel(Features, AVX, Enabled);
671  else
672  setSSELevel(Features, AVX512F, Enabled);
673  } else if (Name == "fma4") {
674  setXOPLevel(Features, FMA4, Enabled);
675  } else if (Name == "xop") {
676  setXOPLevel(Features, XOP, Enabled);
677  } else if (Name == "sse4a") {
678  setXOPLevel(Features, SSE4A, Enabled);
679  } else if (Name == "f16c") {
680  if (Enabled)
681  setSSELevel(Features, AVX, Enabled);
682  else
683  setSSELevel(Features, AVX512F, Enabled);
684  } else if (Name == "sha") {
685  if (Enabled)
686  setSSELevel(Features, SSE2, Enabled);
687  } else if (Name == "sse4") {
688  // We can get here via the __target__ attribute since that's not controlled
689  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
690  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
691  // disabled.
692  if (Enabled)
693  setSSELevel(Features, SSE42, Enabled);
694  else
695  setSSELevel(Features, SSE41, Enabled);
696  } else if (Name == "xsave") {
697  if (!Enabled)
698  Features["xsaveopt"] = false;
699  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
700  if (Enabled)
701  Features["xsave"] = true;
702  }
703 }
704 
705 /// handleTargetFeatures - Perform initialization based on the user
706 /// configured set of features.
707 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
708  DiagnosticsEngine &Diags) {
709  for (const auto &Feature : Features) {
710  if (Feature[0] != '+')
711  continue;
712 
713  if (Feature == "+aes") {
714  HasAES = true;
715  } else if (Feature == "+vaes") {
716  HasVAES = true;
717  } else if (Feature == "+pclmul") {
718  HasPCLMUL = true;
719  } else if (Feature == "+vpclmulqdq") {
720  HasVPCLMULQDQ = true;
721  } else if (Feature == "+lzcnt") {
722  HasLZCNT = true;
723  } else if (Feature == "+rdrnd") {
724  HasRDRND = true;
725  } else if (Feature == "+fsgsbase") {
726  HasFSGSBASE = true;
727  } else if (Feature == "+bmi") {
728  HasBMI = true;
729  } else if (Feature == "+bmi2") {
730  HasBMI2 = true;
731  } else if (Feature == "+popcnt") {
732  HasPOPCNT = true;
733  } else if (Feature == "+rtm") {
734  HasRTM = true;
735  } else if (Feature == "+prfchw") {
736  HasPRFCHW = true;
737  } else if (Feature == "+rdseed") {
738  HasRDSEED = true;
739  } else if (Feature == "+adx") {
740  HasADX = true;
741  } else if (Feature == "+tbm") {
742  HasTBM = true;
743  } else if (Feature == "+lwp") {
744  HasLWP = true;
745  } else if (Feature == "+fma") {
746  HasFMA = true;
747  } else if (Feature == "+f16c") {
748  HasF16C = true;
749  } else if (Feature == "+gfni") {
750  HasGFNI = true;
751  } else if (Feature == "+avx512cd") {
752  HasAVX512CD = true;
753  } else if (Feature == "+avx512vpopcntdq") {
754  HasAVX512VPOPCNTDQ = true;
755  } else if (Feature == "+avx512vnni") {
756  HasAVX512VNNI = true;
757  } else if (Feature == "+avx512er") {
758  HasAVX512ER = true;
759  } else if (Feature == "+avx512pf") {
760  HasAVX512PF = true;
761  } else if (Feature == "+avx512dq") {
762  HasAVX512DQ = true;
763  } else if (Feature == "+avx512bitalg") {
764  HasAVX512BITALG = true;
765  } else if (Feature == "+avx512bw") {
766  HasAVX512BW = true;
767  } else if (Feature == "+avx512vl") {
768  HasAVX512VL = true;
769  } else if (Feature == "+avx512vbmi") {
770  HasAVX512VBMI = true;
771  } else if (Feature == "+avx512vbmi2") {
772  HasAVX512VBMI2 = true;
773  } else if (Feature == "+avx512ifma") {
774  HasAVX512IFMA = true;
775  } else if (Feature == "+sha") {
776  HasSHA = true;
777  } else if (Feature == "+mpx") {
778  HasMPX = true;
779  } else if (Feature == "+shstk") {
780  HasSHSTK = true;
781  } else if (Feature == "+movbe") {
782  HasMOVBE = true;
783  } else if (Feature == "+sgx") {
784  HasSGX = true;
785  } else if (Feature == "+cx8") {
786  HasCX8 = true;
787  } else if (Feature == "+cx16") {
788  HasCX16 = true;
789  } else if (Feature == "+fxsr") {
790  HasFXSR = true;
791  } else if (Feature == "+xsave") {
792  HasXSAVE = true;
793  } else if (Feature == "+xsaveopt") {
794  HasXSAVEOPT = true;
795  } else if (Feature == "+xsavec") {
796  HasXSAVEC = true;
797  } else if (Feature == "+xsaves") {
798  HasXSAVES = true;
799  } else if (Feature == "+mwaitx") {
800  HasMWAITX = true;
801  } else if (Feature == "+pku") {
802  HasPKU = true;
803  } else if (Feature == "+clflushopt") {
804  HasCLFLUSHOPT = true;
805  } else if (Feature == "+clwb") {
806  HasCLWB = true;
807  } else if (Feature == "+wbnoinvd") {
808  HasWBNOINVD = true;
809  } else if (Feature == "+prefetchwt1") {
810  HasPREFETCHWT1 = true;
811  } else if (Feature == "+clzero") {
812  HasCLZERO = true;
813  } else if (Feature == "+cldemote") {
814  HasCLDEMOTE = true;
815  } else if (Feature == "+rdpid") {
816  HasRDPID = true;
817  } else if (Feature == "+retpoline-external-thunk") {
818  HasRetpolineExternalThunk = true;
819  } else if (Feature == "+sahf") {
820  HasLAHFSAHF = true;
821  } else if (Feature == "+waitpkg") {
822  HasWAITPKG = true;
823  } else if (Feature == "+movdiri") {
824  HasMOVDIRI = true;
825  } else if (Feature == "+movdir64b") {
826  HasMOVDIR64B = true;
827  } else if (Feature == "+pconfig") {
828  HasPCONFIG = true;
829  } else if (Feature == "+ptwrite") {
830  HasPTWRITE = true;
831  } else if (Feature == "+invpcid") {
832  HasINVPCID = true;
833  }
834 
835  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
836  .Case("+avx512f", AVX512F)
837  .Case("+avx2", AVX2)
838  .Case("+avx", AVX)
839  .Case("+sse4.2", SSE42)
840  .Case("+sse4.1", SSE41)
841  .Case("+ssse3", SSSE3)
842  .Case("+sse3", SSE3)
843  .Case("+sse2", SSE2)
844  .Case("+sse", SSE1)
845  .Default(NoSSE);
846  SSELevel = std::max(SSELevel, Level);
847 
848  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
849  .Case("+3dnowa", AMD3DNowAthlon)
850  .Case("+3dnow", AMD3DNow)
851  .Case("+mmx", MMX)
852  .Default(NoMMX3DNow);
853  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
854 
855  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
856  .Case("+xop", XOP)
857  .Case("+fma4", FMA4)
858  .Case("+sse4a", SSE4A)
859  .Default(NoXOP);
860  XOPLevel = std::max(XOPLevel, XLevel);
861  }
862 
863  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
864  // matches the selected sse level.
865  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
866  (FPMath == FP_387 && SSELevel >= SSE1)) {
867  Diags.Report(diag::err_target_unsupported_fpmath)
868  << (FPMath == FP_SSE ? "sse" : "387");
869  return false;
870  }
871 
872  SimdDefaultAlign =
873  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
874  return true;
875 }
876 
877 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
878 /// definitions for this particular subtarget.
880  MacroBuilder &Builder) const {
881  // Inline assembly supports X86 flag outputs.
882  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
883 
884  std::string CodeModel = getTargetOpts().CodeModel;
885  if (CodeModel == "default")
886  CodeModel = "small";
887  Builder.defineMacro("__code_model_" + CodeModel + "_");
888 
889  // Target identification.
890  if (getTriple().getArch() == llvm::Triple::x86_64) {
891  Builder.defineMacro("__amd64__");
892  Builder.defineMacro("__amd64");
893  Builder.defineMacro("__x86_64");
894  Builder.defineMacro("__x86_64__");
895  if (getTriple().getArchName() == "x86_64h") {
896  Builder.defineMacro("__x86_64h");
897  Builder.defineMacro("__x86_64h__");
898  }
899  } else {
900  DefineStd(Builder, "i386", Opts);
901  }
902 
903  // Subtarget options.
904  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
905  // truly should be based on -mtune options.
906  switch (CPU) {
907  case CK_Generic:
908  break;
909  case CK_i386:
910  // The rest are coming from the i386 define above.
911  Builder.defineMacro("__tune_i386__");
912  break;
913  case CK_i486:
914  case CK_WinChipC6:
915  case CK_WinChip2:
916  case CK_C3:
917  defineCPUMacros(Builder, "i486");
918  break;
919  case CK_PentiumMMX:
920  Builder.defineMacro("__pentium_mmx__");
921  Builder.defineMacro("__tune_pentium_mmx__");
922  LLVM_FALLTHROUGH;
923  case CK_i586:
924  case CK_Pentium:
925  defineCPUMacros(Builder, "i586");
926  defineCPUMacros(Builder, "pentium");
927  break;
928  case CK_Pentium3:
929  case CK_PentiumM:
930  Builder.defineMacro("__tune_pentium3__");
931  LLVM_FALLTHROUGH;
932  case CK_Pentium2:
933  case CK_C3_2:
934  Builder.defineMacro("__tune_pentium2__");
935  LLVM_FALLTHROUGH;
936  case CK_PentiumPro:
937  case CK_i686:
938  defineCPUMacros(Builder, "i686");
939  defineCPUMacros(Builder, "pentiumpro");
940  break;
941  case CK_Pentium4:
942  defineCPUMacros(Builder, "pentium4");
943  break;
944  case CK_Yonah:
945  case CK_Prescott:
946  case CK_Nocona:
947  defineCPUMacros(Builder, "nocona");
948  break;
949  case CK_Core2:
950  case CK_Penryn:
951  defineCPUMacros(Builder, "core2");
952  break;
953  case CK_Bonnell:
954  defineCPUMacros(Builder, "atom");
955  break;
956  case CK_Silvermont:
957  defineCPUMacros(Builder, "slm");
958  break;
959  case CK_Goldmont:
960  defineCPUMacros(Builder, "goldmont");
961  break;
962  case CK_GoldmontPlus:
963  defineCPUMacros(Builder, "goldmont_plus");
964  break;
965  case CK_Tremont:
966  defineCPUMacros(Builder, "tremont");
967  break;
968  case CK_Nehalem:
969  case CK_Westmere:
970  case CK_SandyBridge:
971  case CK_IvyBridge:
972  case CK_Haswell:
973  case CK_Broadwell:
974  case CK_SkylakeClient:
975  case CK_SkylakeServer:
976  case CK_Cascadelake:
977  case CK_Cannonlake:
978  case CK_IcelakeClient:
979  case CK_IcelakeServer:
980  // FIXME: Historically, we defined this legacy name, it would be nice to
981  // remove it at some point. We've never exposed fine-grained names for
982  // recent primary x86 CPUs, and we should keep it that way.
983  defineCPUMacros(Builder, "corei7");
984  break;
985  case CK_KNL:
986  defineCPUMacros(Builder, "knl");
987  break;
988  case CK_KNM:
989  break;
990  case CK_Lakemont:
991  defineCPUMacros(Builder, "i586", /*Tuning*/false);
992  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
993  Builder.defineMacro("__tune_lakemont__");
994  break;
995  case CK_K6_2:
996  Builder.defineMacro("__k6_2__");
997  Builder.defineMacro("__tune_k6_2__");
998  LLVM_FALLTHROUGH;
999  case CK_K6_3:
1000  if (CPU != CK_K6_2) { // In case of fallthrough
1001  // FIXME: GCC may be enabling these in cases where some other k6
1002  // architecture is specified but -m3dnow is explicitly provided. The
1003  // exact semantics need to be determined and emulated here.
1004  Builder.defineMacro("__k6_3__");
1005  Builder.defineMacro("__tune_k6_3__");
1006  }
1007  LLVM_FALLTHROUGH;
1008  case CK_K6:
1009  defineCPUMacros(Builder, "k6");
1010  break;
1011  case CK_Athlon:
1012  case CK_AthlonXP:
1013  defineCPUMacros(Builder, "athlon");
1014  if (SSELevel != NoSSE) {
1015  Builder.defineMacro("__athlon_sse__");
1016  Builder.defineMacro("__tune_athlon_sse__");
1017  }
1018  break;
1019  case CK_K8:
1020  case CK_K8SSE3:
1021  case CK_x86_64:
1022  defineCPUMacros(Builder, "k8");
1023  break;
1024  case CK_AMDFAM10:
1025  defineCPUMacros(Builder, "amdfam10");
1026  break;
1027  case CK_BTVER1:
1028  defineCPUMacros(Builder, "btver1");
1029  break;
1030  case CK_BTVER2:
1031  defineCPUMacros(Builder, "btver2");
1032  break;
1033  case CK_BDVER1:
1034  defineCPUMacros(Builder, "bdver1");
1035  break;
1036  case CK_BDVER2:
1037  defineCPUMacros(Builder, "bdver2");
1038  break;
1039  case CK_BDVER3:
1040  defineCPUMacros(Builder, "bdver3");
1041  break;
1042  case CK_BDVER4:
1043  defineCPUMacros(Builder, "bdver4");
1044  break;
1045  case CK_ZNVER1:
1046  defineCPUMacros(Builder, "znver1");
1047  break;
1048  case CK_ZNVER2:
1049  defineCPUMacros(Builder, "znver2");
1050  break;
1051  case CK_Geode:
1052  defineCPUMacros(Builder, "geode");
1053  break;
1054  }
1055 
1056  // Target properties.
1057  Builder.defineMacro("__REGISTER_PREFIX__", "");
1058 
1059  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1060  // functions in glibc header files that use FP Stack inline asm which the
1061  // backend can't deal with (PR879).
1062  Builder.defineMacro("__NO_MATH_INLINES");
1063 
1064  if (HasAES)
1065  Builder.defineMacro("__AES__");
1066 
1067  if (HasVAES)
1068  Builder.defineMacro("__VAES__");
1069 
1070  if (HasPCLMUL)
1071  Builder.defineMacro("__PCLMUL__");
1072 
1073  if (HasVPCLMULQDQ)
1074  Builder.defineMacro("__VPCLMULQDQ__");
1075 
1076  if (HasLZCNT)
1077  Builder.defineMacro("__LZCNT__");
1078 
1079  if (HasRDRND)
1080  Builder.defineMacro("__RDRND__");
1081 
1082  if (HasFSGSBASE)
1083  Builder.defineMacro("__FSGSBASE__");
1084 
1085  if (HasBMI)
1086  Builder.defineMacro("__BMI__");
1087 
1088  if (HasBMI2)
1089  Builder.defineMacro("__BMI2__");
1090 
1091  if (HasPOPCNT)
1092  Builder.defineMacro("__POPCNT__");
1093 
1094  if (HasRTM)
1095  Builder.defineMacro("__RTM__");
1096 
1097  if (HasPRFCHW)
1098  Builder.defineMacro("__PRFCHW__");
1099 
1100  if (HasRDSEED)
1101  Builder.defineMacro("__RDSEED__");
1102 
1103  if (HasADX)
1104  Builder.defineMacro("__ADX__");
1105 
1106  if (HasTBM)
1107  Builder.defineMacro("__TBM__");
1108 
1109  if (HasLWP)
1110  Builder.defineMacro("__LWP__");
1111 
1112  if (HasMWAITX)
1113  Builder.defineMacro("__MWAITX__");
1114 
1115  if (HasMOVBE)
1116  Builder.defineMacro("__MOVBE__");
1117 
1118  switch (XOPLevel) {
1119  case XOP:
1120  Builder.defineMacro("__XOP__");
1121  LLVM_FALLTHROUGH;
1122  case FMA4:
1123  Builder.defineMacro("__FMA4__");
1124  LLVM_FALLTHROUGH;
1125  case SSE4A:
1126  Builder.defineMacro("__SSE4A__");
1127  LLVM_FALLTHROUGH;
1128  case NoXOP:
1129  break;
1130  }
1131 
1132  if (HasFMA)
1133  Builder.defineMacro("__FMA__");
1134 
1135  if (HasF16C)
1136  Builder.defineMacro("__F16C__");
1137 
1138  if (HasGFNI)
1139  Builder.defineMacro("__GFNI__");
1140 
1141  if (HasAVX512CD)
1142  Builder.defineMacro("__AVX512CD__");
1143  if (HasAVX512VPOPCNTDQ)
1144  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1145  if (HasAVX512VNNI)
1146  Builder.defineMacro("__AVX512VNNI__");
1147  if (HasAVX512ER)
1148  Builder.defineMacro("__AVX512ER__");
1149  if (HasAVX512PF)
1150  Builder.defineMacro("__AVX512PF__");
1151  if (HasAVX512DQ)
1152  Builder.defineMacro("__AVX512DQ__");
1153  if (HasAVX512BITALG)
1154  Builder.defineMacro("__AVX512BITALG__");
1155  if (HasAVX512BW)
1156  Builder.defineMacro("__AVX512BW__");
1157  if (HasAVX512VL)
1158  Builder.defineMacro("__AVX512VL__");
1159  if (HasAVX512VBMI)
1160  Builder.defineMacro("__AVX512VBMI__");
1161  if (HasAVX512VBMI2)
1162  Builder.defineMacro("__AVX512VBMI2__");
1163  if (HasAVX512IFMA)
1164  Builder.defineMacro("__AVX512IFMA__");
1165 
1166  if (HasSHA)
1167  Builder.defineMacro("__SHA__");
1168 
1169  if (HasFXSR)
1170  Builder.defineMacro("__FXSR__");
1171  if (HasXSAVE)
1172  Builder.defineMacro("__XSAVE__");
1173  if (HasXSAVEOPT)
1174  Builder.defineMacro("__XSAVEOPT__");
1175  if (HasXSAVEC)
1176  Builder.defineMacro("__XSAVEC__");
1177  if (HasXSAVES)
1178  Builder.defineMacro("__XSAVES__");
1179  if (HasPKU)
1180  Builder.defineMacro("__PKU__");
1181  if (HasCLFLUSHOPT)
1182  Builder.defineMacro("__CLFLUSHOPT__");
1183  if (HasCLWB)
1184  Builder.defineMacro("__CLWB__");
1185  if (HasWBNOINVD)
1186  Builder.defineMacro("__WBNOINVD__");
1187  if (HasMPX)
1188  Builder.defineMacro("__MPX__");
1189  if (HasSHSTK)
1190  Builder.defineMacro("__SHSTK__");
1191  if (HasSGX)
1192  Builder.defineMacro("__SGX__");
1193  if (HasPREFETCHWT1)
1194  Builder.defineMacro("__PREFETCHWT1__");
1195  if (HasCLZERO)
1196  Builder.defineMacro("__CLZERO__");
1197  if (HasRDPID)
1198  Builder.defineMacro("__RDPID__");
1199  if (HasCLDEMOTE)
1200  Builder.defineMacro("__CLDEMOTE__");
1201  if (HasWAITPKG)
1202  Builder.defineMacro("__WAITPKG__");
1203  if (HasMOVDIRI)
1204  Builder.defineMacro("__MOVDIRI__");
1205  if (HasMOVDIR64B)
1206  Builder.defineMacro("__MOVDIR64B__");
1207  if (HasPCONFIG)
1208  Builder.defineMacro("__PCONFIG__");
1209  if (HasPTWRITE)
1210  Builder.defineMacro("__PTWRITE__");
1211  if (HasINVPCID)
1212  Builder.defineMacro("__INVPCID__");
1213 
1214  // Each case falls through to the previous one here.
1215  switch (SSELevel) {
1216  case AVX512F:
1217  Builder.defineMacro("__AVX512F__");
1218  LLVM_FALLTHROUGH;
1219  case AVX2:
1220  Builder.defineMacro("__AVX2__");
1221  LLVM_FALLTHROUGH;
1222  case AVX:
1223  Builder.defineMacro("__AVX__");
1224  LLVM_FALLTHROUGH;
1225  case SSE42:
1226  Builder.defineMacro("__SSE4_2__");
1227  LLVM_FALLTHROUGH;
1228  case SSE41:
1229  Builder.defineMacro("__SSE4_1__");
1230  LLVM_FALLTHROUGH;
1231  case SSSE3:
1232  Builder.defineMacro("__SSSE3__");
1233  LLVM_FALLTHROUGH;
1234  case SSE3:
1235  Builder.defineMacro("__SSE3__");
1236  LLVM_FALLTHROUGH;
1237  case SSE2:
1238  Builder.defineMacro("__SSE2__");
1239  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1240  LLVM_FALLTHROUGH;
1241  case SSE1:
1242  Builder.defineMacro("__SSE__");
1243  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1244  LLVM_FALLTHROUGH;
1245  case NoSSE:
1246  break;
1247  }
1248 
1249  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1250  switch (SSELevel) {
1251  case AVX512F:
1252  case AVX2:
1253  case AVX:
1254  case SSE42:
1255  case SSE41:
1256  case SSSE3:
1257  case SSE3:
1258  case SSE2:
1259  Builder.defineMacro("_M_IX86_FP", Twine(2));
1260  break;
1261  case SSE1:
1262  Builder.defineMacro("_M_IX86_FP", Twine(1));
1263  break;
1264  default:
1265  Builder.defineMacro("_M_IX86_FP", Twine(0));
1266  break;
1267  }
1268  }
1269 
1270  // Each case falls through to the previous one here.
1271  switch (MMX3DNowLevel) {
1272  case AMD3DNowAthlon:
1273  Builder.defineMacro("__3dNOW_A__");
1274  LLVM_FALLTHROUGH;
1275  case AMD3DNow:
1276  Builder.defineMacro("__3dNOW__");
1277  LLVM_FALLTHROUGH;
1278  case MMX:
1279  Builder.defineMacro("__MMX__");
1280  LLVM_FALLTHROUGH;
1281  case NoMMX3DNow:
1282  break;
1283  }
1284 
1285  if (CPU >= CK_i486 || CPU == CK_Generic) {
1286  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1287  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1288  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1289  }
1290  if (HasCX8)
1291  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1292  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1293  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1294 
1295  if (HasFloat128)
1296  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1297 }
1298 
1299 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1300  return llvm::StringSwitch<bool>(Name)
1301  .Case("3dnow", true)
1302  .Case("3dnowa", true)
1303  .Case("adx", true)
1304  .Case("aes", true)
1305  .Case("avx", true)
1306  .Case("avx2", true)
1307  .Case("avx512f", true)
1308  .Case("avx512cd", true)
1309  .Case("avx512vpopcntdq", true)
1310  .Case("avx512vnni", true)
1311  .Case("avx512er", true)
1312  .Case("avx512pf", true)
1313  .Case("avx512dq", true)
1314  .Case("avx512bitalg", true)
1315  .Case("avx512bw", true)
1316  .Case("avx512vl", true)
1317  .Case("avx512vbmi", true)
1318  .Case("avx512vbmi2", true)
1319  .Case("avx512ifma", true)
1320  .Case("bmi", true)
1321  .Case("bmi2", true)
1322  .Case("cldemote", true)
1323  .Case("clflushopt", true)
1324  .Case("clwb", true)
1325  .Case("clzero", true)
1326  .Case("cx16", true)
1327  .Case("f16c", true)
1328  .Case("fma", true)
1329  .Case("fma4", true)
1330  .Case("fsgsbase", true)
1331  .Case("fxsr", true)
1332  .Case("gfni", true)
1333  .Case("invpcid", true)
1334  .Case("lwp", true)
1335  .Case("lzcnt", true)
1336  .Case("mmx", true)
1337  .Case("movbe", true)
1338  .Case("movdiri", true)
1339  .Case("movdir64b", true)
1340  .Case("mpx", true)
1341  .Case("mwaitx", true)
1342  .Case("pclmul", true)
1343  .Case("pconfig", true)
1344  .Case("pku", true)
1345  .Case("popcnt", true)
1346  .Case("prefetchwt1", true)
1347  .Case("prfchw", true)
1348  .Case("ptwrite", true)
1349  .Case("rdpid", true)
1350  .Case("rdrnd", true)
1351  .Case("rdseed", true)
1352  .Case("rtm", true)
1353  .Case("sahf", true)
1354  .Case("sgx", true)
1355  .Case("sha", true)
1356  .Case("shstk", true)
1357  .Case("sse", true)
1358  .Case("sse2", true)
1359  .Case("sse3", true)
1360  .Case("ssse3", true)
1361  .Case("sse4", true)
1362  .Case("sse4.1", true)
1363  .Case("sse4.2", true)
1364  .Case("sse4a", true)
1365  .Case("tbm", true)
1366  .Case("vaes", true)
1367  .Case("vpclmulqdq", true)
1368  .Case("wbnoinvd", true)
1369  .Case("waitpkg", true)
1370  .Case("x87", true)
1371  .Case("xop", true)
1372  .Case("xsave", true)
1373  .Case("xsavec", true)
1374  .Case("xsaves", true)
1375  .Case("xsaveopt", true)
1376  .Default(false);
1377 }
1378 
1379 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1380  return llvm::StringSwitch<bool>(Feature)
1381  .Case("adx", HasADX)
1382  .Case("aes", HasAES)
1383  .Case("avx", SSELevel >= AVX)
1384  .Case("avx2", SSELevel >= AVX2)
1385  .Case("avx512f", SSELevel >= AVX512F)
1386  .Case("avx512cd", HasAVX512CD)
1387  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1388  .Case("avx512vnni", HasAVX512VNNI)
1389  .Case("avx512er", HasAVX512ER)
1390  .Case("avx512pf", HasAVX512PF)
1391  .Case("avx512dq", HasAVX512DQ)
1392  .Case("avx512bitalg", HasAVX512BITALG)
1393  .Case("avx512bw", HasAVX512BW)
1394  .Case("avx512vl", HasAVX512VL)
1395  .Case("avx512vbmi", HasAVX512VBMI)
1396  .Case("avx512vbmi2", HasAVX512VBMI2)
1397  .Case("avx512ifma", HasAVX512IFMA)
1398  .Case("bmi", HasBMI)
1399  .Case("bmi2", HasBMI2)
1400  .Case("cldemote", HasCLDEMOTE)
1401  .Case("clflushopt", HasCLFLUSHOPT)
1402  .Case("clwb", HasCLWB)
1403  .Case("clzero", HasCLZERO)
1404  .Case("cx8", HasCX8)
1405  .Case("cx16", HasCX16)
1406  .Case("f16c", HasF16C)
1407  .Case("fma", HasFMA)
1408  .Case("fma4", XOPLevel >= FMA4)
1409  .Case("fsgsbase", HasFSGSBASE)
1410  .Case("fxsr", HasFXSR)
1411  .Case("gfni", HasGFNI)
1412  .Case("invpcid", HasINVPCID)
1413  .Case("lwp", HasLWP)
1414  .Case("lzcnt", HasLZCNT)
1415  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1416  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1417  .Case("mmx", MMX3DNowLevel >= MMX)
1418  .Case("movbe", HasMOVBE)
1419  .Case("movdiri", HasMOVDIRI)
1420  .Case("movdir64b", HasMOVDIR64B)
1421  .Case("mpx", HasMPX)
1422  .Case("mwaitx", HasMWAITX)
1423  .Case("pclmul", HasPCLMUL)
1424  .Case("pconfig", HasPCONFIG)
1425  .Case("pku", HasPKU)
1426  .Case("popcnt", HasPOPCNT)
1427  .Case("prefetchwt1", HasPREFETCHWT1)
1428  .Case("prfchw", HasPRFCHW)
1429  .Case("ptwrite", HasPTWRITE)
1430  .Case("rdpid", HasRDPID)
1431  .Case("rdrnd", HasRDRND)
1432  .Case("rdseed", HasRDSEED)
1433  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1434  .Case("rtm", HasRTM)
1435  .Case("sahf", HasLAHFSAHF)
1436  .Case("sgx", HasSGX)
1437  .Case("sha", HasSHA)
1438  .Case("shstk", HasSHSTK)
1439  .Case("sse", SSELevel >= SSE1)
1440  .Case("sse2", SSELevel >= SSE2)
1441  .Case("sse3", SSELevel >= SSE3)
1442  .Case("ssse3", SSELevel >= SSSE3)
1443  .Case("sse4.1", SSELevel >= SSE41)
1444  .Case("sse4.2", SSELevel >= SSE42)
1445  .Case("sse4a", XOPLevel >= SSE4A)
1446  .Case("tbm", HasTBM)
1447  .Case("vaes", HasVAES)
1448  .Case("vpclmulqdq", HasVPCLMULQDQ)
1449  .Case("wbnoinvd", HasWBNOINVD)
1450  .Case("waitpkg", HasWAITPKG)
1451  .Case("x86", true)
1452  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1453  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1454  .Case("xop", XOPLevel >= XOP)
1455  .Case("xsave", HasXSAVE)
1456  .Case("xsavec", HasXSAVEC)
1457  .Case("xsaves", HasXSAVES)
1458  .Case("xsaveopt", HasXSAVEOPT)
1459  .Default(false);
1460 }
1461 
1462 // We can't use a generic validation scheme for the features accepted here
1463 // versus subtarget features accepted in the target attribute because the
1464 // bitfield structure that's initialized in the runtime only supports the
1465 // below currently rather than the full range of subtarget features. (See
1466 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1467 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1468  return llvm::StringSwitch<bool>(FeatureStr)
1469 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1470 #include "llvm/Support/X86TargetParser.def"
1471  .Default(false);
1472 }
1473 
1474 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1475  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1476 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1477 #include "llvm/Support/X86TargetParser.def"
1478  ;
1479  // Note, this function should only be used after ensuring the value is
1480  // correct, so it asserts if the value is out of range.
1481 }
1482 
1483 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1484  enum class FeatPriority {
1485 #define FEATURE(FEAT) FEAT,
1486 #include "clang/Basic/X86Target.def"
1487  };
1488  switch (Feat) {
1489 #define FEATURE(FEAT) \
1490  case llvm::X86::FEAT: \
1491  return static_cast<unsigned>(FeatPriority::FEAT);
1492 #include "clang/Basic/X86Target.def"
1493  default:
1494  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1495  }
1496 }
1497 
1498 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1499  // Valid CPUs have a 'key feature' that compares just better than its key
1500  // feature.
1501  CPUKind Kind = getCPUKind(Name);
1502  if (Kind != CK_Generic) {
1503  switch (Kind) {
1504  default:
1505  llvm_unreachable(
1506  "CPU Type without a key feature used in 'target' attribute");
1507 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1508  case CK_##ENUM: \
1509  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1510 #include "clang/Basic/X86Target.def"
1511  }
1512  }
1513 
1514  // Now we know we have a feature, so get its priority and shift it a few so
1515  // that we have sufficient room for the CPUs (above).
1516  return getFeaturePriority(getFeature(Name)) << 1;
1517 }
1518 
1520  return llvm::StringSwitch<bool>(Name)
1521 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1522 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1523 #include "clang/Basic/X86Target.def"
1524  .Default(false);
1525 }
1526 
1527 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1528  return llvm::StringSwitch<StringRef>(Name)
1529 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1530 #include "clang/Basic/X86Target.def"
1531  .Default(Name);
1532 }
1533 
1535  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1536 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1537 #include "clang/Basic/X86Target.def"
1538  .Default(0);
1539 }
1540 
1542  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1543  StringRef WholeList =
1544  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1545 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1546 #include "clang/Basic/X86Target.def"
1547  .Default("");
1548  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1549 }
1550 
1551 // We can't use a generic validation scheme for the cpus accepted here
1552 // versus subtarget cpus accepted in the target attribute because the
1553 // variables intitialized by the runtime only support the below currently
1554 // rather than the full range of cpus.
1555 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1556  return llvm::StringSwitch<bool>(FeatureStr)
1557 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1558 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1559  .Cases(STR, ALIAS, true)
1560 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1561 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1562 #include "llvm/Support/X86TargetParser.def"
1563  .Default(false);
1564 }
1565 
1566 static unsigned matchAsmCCConstraint(const char *&Name) {
1567  auto RV = llvm::StringSwitch<unsigned>(Name)
1568  .Case("@cca", 4)
1569  .Case("@ccae", 5)
1570  .Case("@ccb", 4)
1571  .Case("@ccbe", 5)
1572  .Case("@ccc", 4)
1573  .Case("@cce", 4)
1574  .Case("@ccz", 4)
1575  .Case("@ccg", 4)
1576  .Case("@ccge", 5)
1577  .Case("@ccl", 4)
1578  .Case("@ccle", 5)
1579  .Case("@ccna", 5)
1580  .Case("@ccnae", 6)
1581  .Case("@ccnb", 5)
1582  .Case("@ccnbe", 6)
1583  .Case("@ccnc", 5)
1584  .Case("@ccne", 5)
1585  .Case("@ccnz", 5)
1586  .Case("@ccng", 5)
1587  .Case("@ccnge", 6)
1588  .Case("@ccnl", 5)
1589  .Case("@ccnle", 6)
1590  .Case("@ccno", 5)
1591  .Case("@ccnp", 5)
1592  .Case("@ccns", 5)
1593  .Case("@cco", 4)
1594  .Case("@ccp", 4)
1595  .Case("@ccs", 4)
1596  .Default(0);
1597  return RV;
1598 }
1599 
1601  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1602  switch (*Name) {
1603  default:
1604  return false;
1605  // Constant constraints.
1606  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1607  // instructions.
1608  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1609  // x86_64 instructions.
1610  case 's':
1611  Info.setRequiresImmediate();
1612  return true;
1613  case 'I':
1614  Info.setRequiresImmediate(0, 31);
1615  return true;
1616  case 'J':
1617  Info.setRequiresImmediate(0, 63);
1618  return true;
1619  case 'K':
1620  Info.setRequiresImmediate(-128, 127);
1621  return true;
1622  case 'L':
1623  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1624  return true;
1625  case 'M':
1626  Info.setRequiresImmediate(0, 3);
1627  return true;
1628  case 'N':
1629  Info.setRequiresImmediate(0, 255);
1630  return true;
1631  case 'O':
1632  Info.setRequiresImmediate(0, 127);
1633  return true;
1634  // Register constraints.
1635  case 'Y': // 'Y' is the first character for several 2-character constraints.
1636  // Shift the pointer to the second character of the constraint.
1637  Name++;
1638  switch (*Name) {
1639  default:
1640  return false;
1641  case 'z':
1642  case '0': // First SSE register.
1643  case '2':
1644  case 't': // Any SSE register, when SSE2 is enabled.
1645  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1646  case 'm': // Any MMX register, when inter-unit moves enabled.
1647  case 'k': // AVX512 arch mask registers: k1-k7.
1648  Info.setAllowsRegister();
1649  return true;
1650  }
1651  case 'f': // Any x87 floating point stack register.
1652  // Constraint 'f' cannot be used for output operands.
1653  if (Info.ConstraintStr[0] == '=')
1654  return false;
1655  Info.setAllowsRegister();
1656  return true;
1657  case 'a': // eax.
1658  case 'b': // ebx.
1659  case 'c': // ecx.
1660  case 'd': // edx.
1661  case 'S': // esi.
1662  case 'D': // edi.
1663  case 'A': // edx:eax.
1664  case 't': // Top of floating point stack.
1665  case 'u': // Second from top of floating point stack.
1666  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1667  case 'y': // Any MMX register.
1668  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1669  case 'x': // Any SSE register.
1670  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1671  // for intermideate k reg operations).
1672  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1673  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1674  case 'l': // "Index" registers: any general register that can be used as an
1675  // index in a base+index memory access.
1676  Info.setAllowsRegister();
1677  return true;
1678  // Floating point constant constraints.
1679  case 'C': // SSE floating point constant.
1680  case 'G': // x87 floating point constant.
1681  return true;
1682  case '@':
1683  // CC condition changes.
1684  if (auto Len = matchAsmCCConstraint(Name)) {
1685  Name += Len - 1;
1686  Info.setAllowsRegister();
1687  return true;
1688  }
1689  return false;
1690  }
1691 }
1692 
1693 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1694  unsigned Size) const {
1695  // Strip off constraint modifiers.
1696  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1697  Constraint = Constraint.substr(1);
1698 
1699  return validateOperandSize(Constraint, Size);
1700 }
1701 
1702 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1703  unsigned Size) const {
1704  return validateOperandSize(Constraint, Size);
1705 }
1706 
1707 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1708  unsigned Size) const {
1709  switch (Constraint[0]) {
1710  default:
1711  break;
1712  case 'k':
1713  // Registers k0-k7 (AVX512) size limit is 64 bit.
1714  case 'y':
1715  return Size <= 64;
1716  case 'f':
1717  case 't':
1718  case 'u':
1719  return Size <= 128;
1720  case 'Y':
1721  // 'Y' is the first character for several 2-character constraints.
1722  switch (Constraint[1]) {
1723  default:
1724  return false;
1725  case 'm':
1726  // 'Ym' is synonymous with 'y'.
1727  case 'k':
1728  return Size <= 64;
1729  case 'z':
1730  case '0':
1731  // XMM0
1732  if (SSELevel >= SSE1)
1733  return Size <= 128U;
1734  return false;
1735  case 'i':
1736  case 't':
1737  case '2':
1738  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1739  if (SSELevel < SSE2)
1740  return false;
1741  break;
1742  }
1743  LLVM_FALLTHROUGH;
1744  case 'v':
1745  case 'x':
1746  if (SSELevel >= AVX512F)
1747  // 512-bit zmm registers can be used if target supports AVX512F.
1748  return Size <= 512U;
1749  else if (SSELevel >= AVX)
1750  // 256-bit ymm registers can be used if target supports AVX.
1751  return Size <= 256U;
1752  return Size <= 128U;
1753 
1754  }
1755 
1756  return true;
1757 }
1758 
1759 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1760  switch (*Constraint) {
1761  case '@':
1762  if (auto Len = matchAsmCCConstraint(Constraint)) {
1763  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1764  Constraint += Len - 1;
1765  return Converted;
1766  }
1767  return std::string(1, *Constraint);
1768  case 'a':
1769  return std::string("{ax}");
1770  case 'b':
1771  return std::string("{bx}");
1772  case 'c':
1773  return std::string("{cx}");
1774  case 'd':
1775  return std::string("{dx}");
1776  case 'S':
1777  return std::string("{si}");
1778  case 'D':
1779  return std::string("{di}");
1780  case 'p': // address
1781  return std::string("im");
1782  case 't': // top of floating point stack.
1783  return std::string("{st}");
1784  case 'u': // second from top of floating point stack.
1785  return std::string("{st(1)}"); // second from top of floating point stack.
1786  case 'Y':
1787  switch (Constraint[1]) {
1788  default:
1789  // Break from inner switch and fall through (copy single char),
1790  // continue parsing after copying the current constraint into
1791  // the return string.
1792  break;
1793  case 'k':
1794  case 'm':
1795  case 'i':
1796  case 't':
1797  case 'z':
1798  case '0':
1799  case '2':
1800  // "^" hints llvm that this is a 2 letter constraint.
1801  // "Constraint++" is used to promote the string iterator
1802  // to the next constraint.
1803  return std::string("^") + std::string(Constraint++, 2);
1804  }
1805  LLVM_FALLTHROUGH;
1806  default:
1807  return std::string(1, *Constraint);
1808  }
1809 }
1810 
1812  // Perform any per-CPU checks necessary to determine if this CPU is
1813  // acceptable.
1814  switch (Kind) {
1815  case CK_Generic:
1816  // No processor selected!
1817  return false;
1818 #define PROC(ENUM, STRING, IS64BIT) \
1819  case CK_##ENUM: \
1820  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1821 #include "clang/Basic/X86Target.def"
1822  }
1823  llvm_unreachable("Unhandled CPU kind");
1824 }
1825 
1827 #define PROC(ENUM, STRING, IS64BIT) \
1828  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1829  Values.emplace_back(STRING);
1830  // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
1831 #define PROC_ALIAS(ENUM, ALIAS) \
1832  if (checkCPUKind(CK_##ENUM)) \
1833  Values.emplace_back(ALIAS);
1834 #include "clang/Basic/X86Target.def"
1835 }
1836 
1838  return llvm::StringSwitch<CPUKind>(CPU)
1839 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1840 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1841 #include "clang/Basic/X86Target.def"
1842  .Default(CK_Generic);
1843 }
1844 
1846  return llvm::makeArrayRef(GCCRegNames);
1847 }
1848 
1850  return llvm::makeArrayRef(AddlRegNames);
1851 }
1852 
1854  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1856 }
1857 
1859  return llvm::makeArrayRef(BuiltinInfoX86,
1861 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:54
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:92
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:531
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1296
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1693
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1849
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:871
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1707
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1826
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:564
static unsigned matchAsmCCConstraint(const char *&Name)
Definition: X86.cpp:1566
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:67
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:49
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1467
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1541
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:148
Defines the Diagnostic-related interfaces.
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1474
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1600
static const char *const GCCRegNames[]
Definition: X86.cpp:43
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1519
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1299
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:385
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1527
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1837
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1379
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:452
Enumerates target-specific builtins in their own namespaces within namespace clang.
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:115
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1858
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1483
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1759
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1853
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1534
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1498
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:707
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1702
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:879
#define PROC(ENUM, STRING, IS64BIT)
__DEVICE__ int max(int __a, int __b)
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1811
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:70
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:29
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:599
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1555
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1845
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:104