clang 23.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 if (Features.lookup("egpr") && getTriple().isOSWindows()) {
168 setFeatureEnabled(Features, "push2pop2", false);
169 setFeatureEnabled(Features, "ppx", false);
170 }
171
172 std::vector<std::string> UpdatedFeaturesVec;
173 for (const auto &Feature : FeaturesVec) {
174 // Expand general-regs-only to -x86, -mmx and -sse
175 if (Feature == "+general-regs-only") {
176 UpdatedFeaturesVec.push_back("-x87");
177 UpdatedFeaturesVec.push_back("-mmx");
178 UpdatedFeaturesVec.push_back("-sse");
179 continue;
180 }
181
182 UpdatedFeaturesVec.push_back(Feature);
183 }
184
185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
186 return false;
187
188 // Can't do this earlier because we need to be able to explicitly enable
189 // or disable these features and the things that they depend upon.
190
191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
192 auto I = Features.find("sse4.2");
193 if (I != Features.end() && I->getValue() &&
194 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
195 Features["popcnt"] = true;
196
197 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
198 // then enable MMX.
199 I = Features.find("sse");
200 if (I != Features.end() && I->getValue() &&
201 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
202 Features["mmx"] = true;
203
204 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
205 I = Features.find("avx");
206 if (I != Features.end() && I->getValue() &&
207 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
208 Features["xsave"] = true;
209
210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
211 I = Features.find("sse4.2");
212 if (I != Features.end() && I->getValue() &&
213 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
214 Features["crc32"] = true;
215
216 return true;
217}
218
219void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
220 StringRef Name, bool Enabled) const {
221 if (Name == "sse4") {
222 // We can get here via the __target__ attribute since that's not controlled
223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
225 // disabled.
226 if (Enabled)
227 Name = "sse4.2";
228 else
229 Name = "sse4.1";
230 }
231
232 Features[Name] = Enabled;
233 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
234}
235
236/// handleTargetFeatures - Perform initialization based on the user
237/// configured set of features.
238bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
239 DiagnosticsEngine &Diags) {
240 for (const auto &Feature : Features) {
241 if (Feature[0] != '+')
242 continue;
243
244 if (Feature == "+mmx") {
245 HasMMX = true;
246 } else if (Feature == "+aes") {
247 HasAES = true;
248 } else if (Feature == "+vaes") {
249 HasVAES = true;
250 } else if (Feature == "+pclmul") {
251 HasPCLMUL = true;
252 } else if (Feature == "+vpclmulqdq") {
253 HasVPCLMULQDQ = true;
254 } else if (Feature == "+lzcnt") {
255 HasLZCNT = true;
256 } else if (Feature == "+rdrnd") {
257 HasRDRND = true;
258 } else if (Feature == "+fsgsbase") {
259 HasFSGSBASE = true;
260 } else if (Feature == "+bmi") {
261 HasBMI = true;
262 } else if (Feature == "+bmi2") {
263 HasBMI2 = true;
264 } else if (Feature == "+popcnt") {
265 HasPOPCNT = true;
266 } else if (Feature == "+rtm") {
267 HasRTM = true;
268 } else if (Feature == "+prfchw") {
269 HasPRFCHW = true;
270 } else if (Feature == "+rdseed") {
271 HasRDSEED = true;
272 } else if (Feature == "+adx") {
273 HasADX = true;
274 } else if (Feature == "+tbm") {
275 HasTBM = true;
276 } else if (Feature == "+lwp") {
277 HasLWP = true;
278 } else if (Feature == "+fma") {
279 HasFMA = true;
280 } else if (Feature == "+f16c") {
281 HasF16C = true;
282 } else if (Feature == "+gfni") {
283 HasGFNI = true;
284 } else if (Feature == "+avx10.1") {
285 HasAVX10_1 = true;
286 } else if (Feature == "+avx10.2") {
287 HasAVX10_2 = true;
288 HasFullBFloat16 = true;
289 } else if (Feature == "+avx512cd") {
290 HasAVX512CD = true;
291 } else if (Feature == "+avx512vpopcntdq") {
292 HasAVX512VPOPCNTDQ = true;
293 } else if (Feature == "+avx512vnni") {
294 HasAVX512VNNI = true;
295 } else if (Feature == "+avx512bf16") {
296 HasAVX512BF16 = true;
297 } else if (Feature == "+avx512fp16") {
298 HasAVX512FP16 = true;
299 HasFastHalfType = true;
300 } else if (Feature == "+avx512dq") {
301 HasAVX512DQ = true;
302 } else if (Feature == "+avx512bitalg") {
303 HasAVX512BITALG = true;
304 } else if (Feature == "+avx512bw") {
305 HasAVX512BW = true;
306 } else if (Feature == "+avx512vl") {
307 HasAVX512VL = true;
308 } else if (Feature == "+avx512vbmi") {
309 HasAVX512VBMI = true;
310 } else if (Feature == "+avx512vbmi2") {
311 HasAVX512VBMI2 = true;
312 } else if (Feature == "+avx512ifma") {
313 HasAVX512IFMA = true;
314 } else if (Feature == "+avx512vp2intersect") {
315 HasAVX512VP2INTERSECT = true;
316 } else if (Feature == "+sha") {
317 HasSHA = true;
318 } else if (Feature == "+sha512") {
319 HasSHA512 = true;
320 } else if (Feature == "+shstk") {
321 HasSHSTK = true;
322 } else if (Feature == "+sm3") {
323 HasSM3 = true;
324 } else if (Feature == "+sm4") {
325 HasSM4 = true;
326 } else if (Feature == "+movbe") {
327 HasMOVBE = true;
328 } else if (Feature == "+movrs") {
329 HasMOVRS = true;
330 } else if (Feature == "+sgx") {
331 HasSGX = true;
332 } else if (Feature == "+cx8") {
333 HasCX8 = true;
334 } else if (Feature == "+cx16") {
335 HasCX16 = true;
336 } else if (Feature == "+fxsr") {
337 HasFXSR = true;
338 } else if (Feature == "+xsave") {
339 HasXSAVE = true;
340 } else if (Feature == "+xsaveopt") {
341 HasXSAVEOPT = true;
342 } else if (Feature == "+xsavec") {
343 HasXSAVEC = true;
344 } else if (Feature == "+xsaves") {
345 HasXSAVES = true;
346 } else if (Feature == "+mwaitx") {
347 HasMWAITX = true;
348 } else if (Feature == "+pku") {
349 HasPKU = true;
350 } else if (Feature == "+clflushopt") {
351 HasCLFLUSHOPT = true;
352 } else if (Feature == "+clwb") {
353 HasCLWB = true;
354 } else if (Feature == "+wbnoinvd") {
355 HasWBNOINVD = true;
356 } else if (Feature == "+prefetchi") {
357 HasPREFETCHI = true;
358 } else if (Feature == "+clzero") {
359 HasCLZERO = true;
360 } else if (Feature == "+cldemote") {
361 HasCLDEMOTE = true;
362 } else if (Feature == "+rdpid") {
363 HasRDPID = true;
364 } else if (Feature == "+rdpru") {
365 HasRDPRU = true;
366 } else if (Feature == "+kl") {
367 HasKL = true;
368 } else if (Feature == "+widekl") {
369 HasWIDEKL = true;
370 } else if (Feature == "+retpoline-external-thunk") {
371 HasRetpolineExternalThunk = true;
372 } else if (Feature == "+sahf") {
373 HasLAHFSAHF = true;
374 } else if (Feature == "+waitpkg") {
375 HasWAITPKG = true;
376 } else if (Feature == "+movdiri") {
377 HasMOVDIRI = true;
378 } else if (Feature == "+movdir64b") {
379 HasMOVDIR64B = true;
380 } else if (Feature == "+pconfig") {
381 HasPCONFIG = true;
382 } else if (Feature == "+ptwrite") {
383 HasPTWRITE = true;
384 } else if (Feature == "+invpcid") {
385 HasINVPCID = true;
386 } else if (Feature == "+enqcmd") {
387 HasENQCMD = true;
388 } else if (Feature == "+hreset") {
389 HasHRESET = true;
390 } else if (Feature == "+amx-bf16") {
391 HasAMXBF16 = true;
392 } else if (Feature == "+amx-fp16") {
393 HasAMXFP16 = true;
394 } else if (Feature == "+amx-int8") {
395 HasAMXINT8 = true;
396 } else if (Feature == "+amx-tile") {
397 HasAMXTILE = true;
398 } else if (Feature == "+amx-complex") {
399 HasAMXCOMPLEX = true;
400 } else if (Feature == "+amx-fp8") {
401 HasAMXFP8 = true;
402 } else if (Feature == "+amx-movrs") {
403 HasAMXMOVRS = true;
404 } else if (Feature == "+amx-avx512") {
405 HasAMXAVX512 = true;
406 } else if (Feature == "+amx-tf32") {
407 HasAMXTF32 = true;
408 } else if (Feature == "+cmpccxadd") {
409 HasCMPCCXADD = true;
410 } else if (Feature == "+raoint") {
411 HasRAOINT = true;
412 } else if (Feature == "+avxifma") {
413 HasAVXIFMA = true;
414 } else if (Feature == "+avxneconvert") {
415 HasAVXNECONVERT= true;
416 } else if (Feature == "+avxvnni") {
417 HasAVXVNNI = true;
418 } else if (Feature == "+avxvnniint16") {
419 HasAVXVNNIINT16 = true;
420 } else if (Feature == "+avxvnniint8") {
421 HasAVXVNNIINT8 = true;
422 } else if (Feature == "+serialize") {
423 HasSERIALIZE = true;
424 } else if (Feature == "+tsxldtrk") {
425 HasTSXLDTRK = true;
426 } else if (Feature == "+uintr") {
427 HasUINTR = true;
428 } else if (Feature == "+usermsr") {
429 HasUSERMSR = true;
430 } else if (Feature == "+crc32") {
431 HasCRC32 = true;
432 } else if (Feature == "+x87") {
433 HasX87 = true;
434 } else if (Feature == "+fullbf16") {
435 HasFullBFloat16 = true;
436 } else if (Feature == "+egpr") {
437 HasEGPR = true;
438 } else if (Feature == "+inline-asm-use-gpr32") {
439 HasInlineAsmUseGPR32 = true;
440 } else if (Feature == "+push2pop2") {
441 HasPush2Pop2 = true;
442 } else if (Feature == "+ppx") {
443 HasPPX = true;
444 } else if (Feature == "+ndd") {
445 HasNDD = true;
446 } else if (Feature == "+ccmp") {
447 HasCCMP = true;
448 } else if (Feature == "+nf") {
449 HasNF = true;
450 } else if (Feature == "+cf") {
451 HasCF = true;
452 } else if (Feature == "+zu") {
453 HasZU = true;
454 } else if (Feature == "+branch-hint") {
455 HasBranchHint = true;
456 }
457
458 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
459 .Case("+avx512f", AVX512F)
460 .Case("+avx2", AVX2)
461 .Case("+avx", AVX)
462 .Case("+sse4.2", SSE42)
463 .Case("+sse4.1", SSE41)
464 .Case("+ssse3", SSSE3)
465 .Case("+sse3", SSE3)
466 .Case("+sse2", SSE2)
467 .Case("+sse", SSE1)
468 .Default(NoSSE);
469 SSELevel = std::max(SSELevel, Level);
470
471 HasFloat16 = SSELevel >= SSE2;
472
473 // X86 target has bfloat16 emulation support in the backend, where
474 // bfloat16 is treated as a 32-bit float, arithmetic operations are
475 // performed in 32-bit, and the result is converted back to bfloat16.
476 // Truncation and extension between bfloat16 and 32-bit float are supported
477 // by the compiler-rt library. However, native bfloat16 support is currently
478 // not available in the X86 target. Hence, HasFullBFloat16 will be false
479 // until native bfloat16 support is available. HasFullBFloat16 is used to
480 // determine whether to automatically use excess floating point precision
481 // for bfloat16 arithmetic operations in the front-end.
482 HasBFloat16 = SSELevel >= SSE2;
483
484 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
485 .Case("+xop", XOP)
486 .Case("+fma4", FMA4)
487 .Case("+sse4a", SSE4A)
488 .Default(NoXOP);
489 XOPLevel = std::max(XOPLevel, XLevel);
490 }
491
492 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
493 // matches the selected sse level.
494 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
495 (FPMath == FP_387 && SSELevel >= SSE1)) {
496 Diags.Report(diag::err_target_unsupported_fpmath)
497 << (FPMath == FP_SSE ? "sse" : "387");
498 return false;
499 }
500
501 // FIXME: We should allow long double type on 32-bits to match with GCC.
502 // This requires backend to be able to lower f80 without x87 first.
503 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
504 HasLongDouble = false;
505
506 return true;
507}
508
509/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
510/// definitions for this particular subtarget.
511void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
512 MacroBuilder &Builder) const {
513 // Inline assembly supports X86 flag outputs.
514 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
515
516 std::string CodeModel = getTargetOpts().CodeModel;
517 if (CodeModel == "default")
518 CodeModel = "small";
519 Builder.defineMacro("__code_model_" + CodeModel + "__");
520
521 // Target identification.
522 if (getTriple().getArch() == llvm::Triple::x86_64) {
523 Builder.defineMacro("__amd64__");
524 Builder.defineMacro("__amd64");
525 Builder.defineMacro("__x86_64");
526 Builder.defineMacro("__x86_64__");
527 if (getTriple().getArchName() == "x86_64h") {
528 Builder.defineMacro("__x86_64h");
529 Builder.defineMacro("__x86_64h__");
530 }
531 } else {
532 DefineStd(Builder, "i386", Opts);
533 }
534
535 Builder.defineMacro("__SEG_GS");
536 Builder.defineMacro("__SEG_FS");
537 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
538 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
539
540 // Subtarget options.
541 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
542 // truly should be based on -mtune options.
543 using namespace llvm::X86;
544 switch (CPU) {
545 case CK_None:
546 break;
547 case CK_i386:
548 // The rest are coming from the i386 define above.
549 Builder.defineMacro("__tune_i386__");
550 break;
551 case CK_i486:
552 case CK_WinChipC6:
553 case CK_WinChip2:
554 case CK_C3:
555 defineCPUMacros(Builder, "i486");
556 break;
557 case CK_PentiumMMX:
558 Builder.defineMacro("__pentium_mmx__");
559 Builder.defineMacro("__tune_pentium_mmx__");
560 [[fallthrough]];
561 case CK_i586:
562 case CK_Pentium:
563 defineCPUMacros(Builder, "i586");
564 defineCPUMacros(Builder, "pentium");
565 break;
566 case CK_Pentium3:
567 case CK_PentiumM:
568 Builder.defineMacro("__tune_pentium3__");
569 [[fallthrough]];
570 case CK_Pentium2:
571 case CK_C3_2:
572 Builder.defineMacro("__tune_pentium2__");
573 [[fallthrough]];
574 case CK_PentiumPro:
575 case CK_i686:
576 defineCPUMacros(Builder, "i686");
577 defineCPUMacros(Builder, "pentiumpro");
578 break;
579 case CK_Pentium4:
580 defineCPUMacros(Builder, "pentium4");
581 break;
582 case CK_Yonah:
583 case CK_Prescott:
584 case CK_Nocona:
585 defineCPUMacros(Builder, "nocona");
586 break;
587 case CK_Core2:
588 case CK_Penryn:
589 defineCPUMacros(Builder, "core2");
590 break;
591 case CK_Bonnell:
592 defineCPUMacros(Builder, "atom");
593 break;
594 case CK_Silvermont:
595 defineCPUMacros(Builder, "slm");
596 break;
597 case CK_Goldmont:
598 defineCPUMacros(Builder, "goldmont");
599 break;
600 case CK_GoldmontPlus:
601 defineCPUMacros(Builder, "goldmont_plus");
602 break;
603 case CK_Tremont:
604 defineCPUMacros(Builder, "tremont");
605 break;
606 // Gracemont and later atom-cores use P-core cpu macros.
607 case CK_Gracemont:
608 case CK_Nehalem:
609 case CK_Westmere:
610 case CK_SandyBridge:
611 case CK_IvyBridge:
612 case CK_Haswell:
613 case CK_Broadwell:
614 case CK_SkylakeClient:
615 case CK_SkylakeServer:
616 case CK_Cascadelake:
617 case CK_Cooperlake:
618 case CK_Cannonlake:
619 case CK_IcelakeClient:
620 case CK_Rocketlake:
621 case CK_IcelakeServer:
622 case CK_Tigerlake:
623 case CK_SapphireRapids:
624 case CK_Alderlake:
625 case CK_Raptorlake:
626 case CK_Meteorlake:
627 case CK_Arrowlake:
628 case CK_ArrowlakeS:
629 case CK_Lunarlake:
630 case CK_Pantherlake:
631 case CK_Wildcatlake:
632 case CK_Novalake:
633 case CK_Sierraforest:
634 case CK_Grandridge:
635 case CK_Graniterapids:
636 case CK_GraniterapidsD:
637 case CK_Emeraldrapids:
638 case CK_Clearwaterforest:
639 case CK_Diamondrapids:
640 // FIXME: Historically, we defined this legacy name, it would be nice to
641 // remove it at some point. We've never exposed fine-grained names for
642 // recent primary x86 CPUs, and we should keep it that way.
643 defineCPUMacros(Builder, "corei7");
644 break;
645 case CK_KNL:
646 defineCPUMacros(Builder, "knl");
647 break;
648 case CK_KNM:
649 break;
650 case CK_Lakemont:
651 defineCPUMacros(Builder, "i586", /*Tuning*/false);
652 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
653 Builder.defineMacro("__tune_lakemont__");
654 break;
655 case CK_K6_2:
656 Builder.defineMacro("__k6_2__");
657 Builder.defineMacro("__tune_k6_2__");
658 [[fallthrough]];
659 case CK_K6_3:
660 if (CPU != CK_K6_2) { // In case of fallthrough
661 // FIXME: GCC may be enabling these in cases where some other k6
662 // architecture is specified but -m3dnow is explicitly provided. The
663 // exact semantics need to be determined and emulated here.
664 Builder.defineMacro("__k6_3__");
665 Builder.defineMacro("__tune_k6_3__");
666 }
667 [[fallthrough]];
668 case CK_K6:
669 defineCPUMacros(Builder, "k6");
670 break;
671 case CK_Athlon:
672 case CK_AthlonXP:
673 defineCPUMacros(Builder, "athlon");
674 if (SSELevel != NoSSE) {
675 Builder.defineMacro("__athlon_sse__");
676 Builder.defineMacro("__tune_athlon_sse__");
677 }
678 break;
679 case CK_K8:
680 case CK_K8SSE3:
681 case CK_x86_64:
682 defineCPUMacros(Builder, "k8");
683 break;
684 case CK_x86_64_v2:
685 case CK_x86_64_v3:
686 case CK_x86_64_v4:
687 break;
688 case CK_AMDFAM10:
689 defineCPUMacros(Builder, "amdfam10");
690 break;
691 case CK_BTVER1:
692 defineCPUMacros(Builder, "btver1");
693 break;
694 case CK_BTVER2:
695 defineCPUMacros(Builder, "btver2");
696 break;
697 case CK_BDVER1:
698 defineCPUMacros(Builder, "bdver1");
699 break;
700 case CK_BDVER2:
701 defineCPUMacros(Builder, "bdver2");
702 break;
703 case CK_BDVER3:
704 defineCPUMacros(Builder, "bdver3");
705 break;
706 case CK_BDVER4:
707 defineCPUMacros(Builder, "bdver4");
708 break;
709 case CK_ZNVER1:
710 defineCPUMacros(Builder, "znver1");
711 break;
712 case CK_ZNVER2:
713 defineCPUMacros(Builder, "znver2");
714 break;
715 case CK_ZNVER3:
716 defineCPUMacros(Builder, "znver3");
717 break;
718 case CK_ZNVER4:
719 defineCPUMacros(Builder, "znver4");
720 break;
721 case CK_ZNVER5:
722 defineCPUMacros(Builder, "znver5");
723 break;
724 case CK_ZNVER6:
725 defineCPUMacros(Builder, "znver6");
726 break;
727 case CK_Geode:
728 defineCPUMacros(Builder, "geode");
729 break;
730 }
731
732 // Target properties.
733 Builder.defineMacro("__REGISTER_PREFIX__", "");
734
735 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
736 // functions in glibc header files that use FP Stack inline asm which the
737 // backend can't deal with (PR879).
738 Builder.defineMacro("__NO_MATH_INLINES");
739
740 if (HasAES)
741 Builder.defineMacro("__AES__");
742
743 if (HasVAES)
744 Builder.defineMacro("__VAES__");
745
746 if (HasPCLMUL)
747 Builder.defineMacro("__PCLMUL__");
748
749 if (HasVPCLMULQDQ)
750 Builder.defineMacro("__VPCLMULQDQ__");
751
752 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
753 // the feature flag only applies to 64-bit mode.
754 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
755 Builder.defineMacro("__LAHF_SAHF__");
756
757 if (HasLZCNT)
758 Builder.defineMacro("__LZCNT__");
759
760 if (HasRDRND)
761 Builder.defineMacro("__RDRND__");
762
763 if (HasFSGSBASE)
764 Builder.defineMacro("__FSGSBASE__");
765
766 if (HasBMI)
767 Builder.defineMacro("__BMI__");
768
769 if (HasBMI2)
770 Builder.defineMacro("__BMI2__");
771
772 if (HasPOPCNT)
773 Builder.defineMacro("__POPCNT__");
774
775 if (HasRTM)
776 Builder.defineMacro("__RTM__");
777
778 if (HasPRFCHW)
779 Builder.defineMacro("__PRFCHW__");
780
781 if (HasRDSEED)
782 Builder.defineMacro("__RDSEED__");
783
784 if (HasADX)
785 Builder.defineMacro("__ADX__");
786
787 if (HasTBM)
788 Builder.defineMacro("__TBM__");
789
790 if (HasLWP)
791 Builder.defineMacro("__LWP__");
792
793 if (HasMWAITX)
794 Builder.defineMacro("__MWAITX__");
795
796 if (HasMOVBE)
797 Builder.defineMacro("__MOVBE__");
798
799 switch (XOPLevel) {
800 case XOP:
801 Builder.defineMacro("__XOP__");
802 [[fallthrough]];
803 case FMA4:
804 Builder.defineMacro("__FMA4__");
805 [[fallthrough]];
806 case SSE4A:
807 Builder.defineMacro("__SSE4A__");
808 [[fallthrough]];
809 case NoXOP:
810 break;
811 }
812
813 if (HasFMA)
814 Builder.defineMacro("__FMA__");
815
816 if (HasF16C)
817 Builder.defineMacro("__F16C__");
818
819 if (HasGFNI)
820 Builder.defineMacro("__GFNI__");
821
822 if (HasAVX10_1) {
823 Builder.defineMacro("__AVX10_1__");
824 Builder.defineMacro("__AVX10_1_512__");
825 }
826 if (HasAVX10_2) {
827 Builder.defineMacro("__AVX10_2__");
828 Builder.defineMacro("__AVX10_2_512__");
829 }
830 if (HasAVX512CD)
831 Builder.defineMacro("__AVX512CD__");
832 if (HasAVX512VPOPCNTDQ)
833 Builder.defineMacro("__AVX512VPOPCNTDQ__");
834 if (HasAVX512VNNI)
835 Builder.defineMacro("__AVX512VNNI__");
836 if (HasAVX512BF16)
837 Builder.defineMacro("__AVX512BF16__");
838 if (HasAVX512FP16)
839 Builder.defineMacro("__AVX512FP16__");
840 if (HasAVX512DQ)
841 Builder.defineMacro("__AVX512DQ__");
842 if (HasAVX512BITALG)
843 Builder.defineMacro("__AVX512BITALG__");
844 if (HasAVX512BW)
845 Builder.defineMacro("__AVX512BW__");
846 if (HasAVX512VL) {
847 Builder.defineMacro("__AVX512VL__");
848 }
849 if (HasAVX512VBMI)
850 Builder.defineMacro("__AVX512VBMI__");
851 if (HasAVX512VBMI2)
852 Builder.defineMacro("__AVX512VBMI2__");
853 if (HasAVX512IFMA)
854 Builder.defineMacro("__AVX512IFMA__");
855 if (HasAVX512VP2INTERSECT)
856 Builder.defineMacro("__AVX512VP2INTERSECT__");
857 if (HasSHA)
858 Builder.defineMacro("__SHA__");
859 if (HasSHA512)
860 Builder.defineMacro("__SHA512__");
861
862 if (HasFXSR)
863 Builder.defineMacro("__FXSR__");
864 if (HasXSAVE)
865 Builder.defineMacro("__XSAVE__");
866 if (HasXSAVEOPT)
867 Builder.defineMacro("__XSAVEOPT__");
868 if (HasXSAVEC)
869 Builder.defineMacro("__XSAVEC__");
870 if (HasXSAVES)
871 Builder.defineMacro("__XSAVES__");
872 if (HasPKU)
873 Builder.defineMacro("__PKU__");
874 if (HasCLFLUSHOPT)
875 Builder.defineMacro("__CLFLUSHOPT__");
876 if (HasCLWB)
877 Builder.defineMacro("__CLWB__");
878 if (HasWBNOINVD)
879 Builder.defineMacro("__WBNOINVD__");
880 if (HasSHSTK)
881 Builder.defineMacro("__SHSTK__");
882 if (HasSGX)
883 Builder.defineMacro("__SGX__");
884 if (HasSM3)
885 Builder.defineMacro("__SM3__");
886 if (HasSM4)
887 Builder.defineMacro("__SM4__");
888 if (HasPREFETCHI)
889 Builder.defineMacro("__PREFETCHI__");
890 if (HasCLZERO)
891 Builder.defineMacro("__CLZERO__");
892 if (HasKL)
893 Builder.defineMacro("__KL__");
894 if (HasWIDEKL)
895 Builder.defineMacro("__WIDEKL__");
896 if (HasRDPID)
897 Builder.defineMacro("__RDPID__");
898 if (HasRDPRU)
899 Builder.defineMacro("__RDPRU__");
900 if (HasCLDEMOTE)
901 Builder.defineMacro("__CLDEMOTE__");
902 if (HasWAITPKG)
903 Builder.defineMacro("__WAITPKG__");
904 if (HasMOVDIRI)
905 Builder.defineMacro("__MOVDIRI__");
906 if (HasMOVDIR64B)
907 Builder.defineMacro("__MOVDIR64B__");
908 if (HasMOVRS)
909 Builder.defineMacro("__MOVRS__");
910 if (HasPCONFIG)
911 Builder.defineMacro("__PCONFIG__");
912 if (HasPTWRITE)
913 Builder.defineMacro("__PTWRITE__");
914 if (HasINVPCID)
915 Builder.defineMacro("__INVPCID__");
916 if (HasENQCMD)
917 Builder.defineMacro("__ENQCMD__");
918 if (HasHRESET)
919 Builder.defineMacro("__HRESET__");
920 if (HasAMXTILE)
921 Builder.defineMacro("__AMX_TILE__");
922 if (HasAMXINT8)
923 Builder.defineMacro("__AMX_INT8__");
924 if (HasAMXBF16)
925 Builder.defineMacro("__AMX_BF16__");
926 if (HasAMXFP16)
927 Builder.defineMacro("__AMX_FP16__");
928 if (HasAMXCOMPLEX)
929 Builder.defineMacro("__AMX_COMPLEX__");
930 if (HasAMXFP8)
931 Builder.defineMacro("__AMX_FP8__");
932 if (HasAMXMOVRS)
933 Builder.defineMacro("__AMX_MOVRS__");
934 if (HasAMXAVX512)
935 Builder.defineMacro("__AMX_AVX512__");
936 if (HasAMXTF32)
937 Builder.defineMacro("__AMX_TF32__");
938 if (HasCMPCCXADD)
939 Builder.defineMacro("__CMPCCXADD__");
940 if (HasRAOINT)
941 Builder.defineMacro("__RAOINT__");
942 if (HasAVXIFMA)
943 Builder.defineMacro("__AVXIFMA__");
944 if (HasAVXNECONVERT)
945 Builder.defineMacro("__AVXNECONVERT__");
946 if (HasAVXVNNI)
947 Builder.defineMacro("__AVXVNNI__");
948 if (HasAVXVNNIINT16)
949 Builder.defineMacro("__AVXVNNIINT16__");
950 if (HasAVXVNNIINT8)
951 Builder.defineMacro("__AVXVNNIINT8__");
952 if (HasSERIALIZE)
953 Builder.defineMacro("__SERIALIZE__");
954 if (HasTSXLDTRK)
955 Builder.defineMacro("__TSXLDTRK__");
956 if (HasUINTR)
957 Builder.defineMacro("__UINTR__");
958 if (HasUSERMSR)
959 Builder.defineMacro("__USERMSR__");
960 if (HasCRC32)
961 Builder.defineMacro("__CRC32__");
962 if (HasEGPR)
963 Builder.defineMacro("__EGPR__");
964 if (HasPush2Pop2)
965 Builder.defineMacro("__PUSH2POP2__");
966 if (HasPPX)
967 Builder.defineMacro("__PPX__");
968 if (HasNDD)
969 Builder.defineMacro("__NDD__");
970 if (HasCCMP)
971 Builder.defineMacro("__CCMP__");
972 if (HasNF)
973 Builder.defineMacro("__NF__");
974 if (HasCF)
975 Builder.defineMacro("__CF__");
976 if (HasZU)
977 Builder.defineMacro("__ZU__");
978 if (HasEGPR && HasNDD && HasCCMP && HasNF && HasZU)
979 if (getTriple().isOSWindows() || (HasPush2Pop2 && HasPPX))
980 Builder.defineMacro("__APX_F__");
981 if (HasEGPR && HasInlineAsmUseGPR32)
982 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
983
984 // Each case falls through to the previous one here.
985 switch (SSELevel) {
986 case AVX512F:
987 Builder.defineMacro("__AVX512F__");
988 [[fallthrough]];
989 case AVX2:
990 Builder.defineMacro("__AVX2__");
991 [[fallthrough]];
992 case AVX:
993 Builder.defineMacro("__AVX__");
994 [[fallthrough]];
995 case SSE42:
996 Builder.defineMacro("__SSE4_2__");
997 [[fallthrough]];
998 case SSE41:
999 Builder.defineMacro("__SSE4_1__");
1000 [[fallthrough]];
1001 case SSSE3:
1002 Builder.defineMacro("__SSSE3__");
1003 [[fallthrough]];
1004 case SSE3:
1005 Builder.defineMacro("__SSE3__");
1006 [[fallthrough]];
1007 case SSE2:
1008 Builder.defineMacro("__SSE2__");
1009 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1010 [[fallthrough]];
1011 case SSE1:
1012 Builder.defineMacro("__SSE__");
1013 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1014 [[fallthrough]];
1015 case NoSSE:
1016 break;
1017 }
1018
1019 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1020 switch (SSELevel) {
1021 case AVX512F:
1022 case AVX2:
1023 case AVX:
1024 case SSE42:
1025 case SSE41:
1026 case SSSE3:
1027 case SSE3:
1028 case SSE2:
1029 Builder.defineMacro("_M_IX86_FP", Twine(2));
1030 break;
1031 case SSE1:
1032 Builder.defineMacro("_M_IX86_FP", Twine(1));
1033 break;
1034 default:
1035 Builder.defineMacro("_M_IX86_FP", Twine(0));
1036 break;
1037 }
1038 }
1039
1040 // Each case falls through to the previous one here.
1041 if (HasMMX) {
1042 Builder.defineMacro("__MMX__");
1043 }
1044
1045 if (CPU >= CK_i486 || CPU == CK_None) {
1046 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1047 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1048 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1049 }
1050 if (HasCX8)
1051 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1052 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1053 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1054
1055 if (HasFloat128)
1056 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1057
1058 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1059 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1060 Opts.CFProtectionBranch});
1061}
1062
1063bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1064 return llvm::StringSwitch<bool>(Name)
1065 .Case("adx", true)
1066 .Case("aes", true)
1067 .Case("amx-avx512", true)
1068 .Case("amx-bf16", true)
1069 .Case("amx-complex", true)
1070 .Case("amx-fp16", true)
1071 .Case("amx-fp8", true)
1072 .Case("amx-int8", true)
1073 .Case("amx-movrs", true)
1074 .Case("amx-tf32", true)
1075 .Case("amx-tile", true)
1076 .Case("avx", true)
1077 .Case("avx10.1", true)
1078 .Case("avx10.2", true)
1079 .Case("avx2", true)
1080 .Case("avx512f", true)
1081 .Case("avx512cd", true)
1082 .Case("avx512vpopcntdq", true)
1083 .Case("avx512vnni", true)
1084 .Case("avx512bf16", true)
1085 .Case("avx512fp16", true)
1086 .Case("avx512dq", true)
1087 .Case("avx512bitalg", true)
1088 .Case("avx512bw", true)
1089 .Case("avx512vl", true)
1090 .Case("avx512vbmi", true)
1091 .Case("avx512vbmi2", true)
1092 .Case("avx512ifma", true)
1093 .Case("avx512vp2intersect", true)
1094 .Case("avxifma", true)
1095 .Case("avxneconvert", true)
1096 .Case("avxvnni", true)
1097 .Case("avxvnniint16", true)
1098 .Case("avxvnniint8", true)
1099 .Case("bmi", true)
1100 .Case("bmi2", true)
1101 .Case("cldemote", true)
1102 .Case("clflushopt", true)
1103 .Case("clwb", true)
1104 .Case("clzero", true)
1105 .Case("cmpccxadd", true)
1106 .Case("crc32", true)
1107 .Case("cx16", true)
1108 .Case("enqcmd", true)
1109 .Case("f16c", true)
1110 .Case("fma", true)
1111 .Case("fma4", true)
1112 .Case("fsgsbase", true)
1113 .Case("fxsr", true)
1114 .Case("general-regs-only", true)
1115 .Case("gfni", true)
1116 .Case("hreset", true)
1117 .Case("invpcid", true)
1118 .Case("kl", true)
1119 .Case("widekl", true)
1120 .Case("lwp", true)
1121 .Case("lzcnt", true)
1122 .Case("mmx", true)
1123 .Case("movbe", true)
1124 .Case("movrs", true)
1125 .Case("movdiri", true)
1126 .Case("movdir64b", true)
1127 .Case("mwaitx", true)
1128 .Case("pclmul", true)
1129 .Case("pconfig", true)
1130 .Case("pku", true)
1131 .Case("popcnt", true)
1132 .Case("prefer-256-bit", true)
1133 .Case("prefetchi", true)
1134 .Case("prfchw", true)
1135 .Case("ptwrite", true)
1136 .Case("raoint", true)
1137 .Case("rdpid", true)
1138 .Case("rdpru", true)
1139 .Case("rdrnd", true)
1140 .Case("rdseed", true)
1141 .Case("rtm", true)
1142 .Case("sahf", true)
1143 .Case("serialize", true)
1144 .Case("sgx", true)
1145 .Case("sha", true)
1146 .Case("sha512", true)
1147 .Case("shstk", true)
1148 .Case("sm3", true)
1149 .Case("sm4", true)
1150 .Case("sse", true)
1151 .Case("sse2", true)
1152 .Case("sse3", true)
1153 .Case("ssse3", true)
1154 .Case("sse4", true)
1155 .Case("sse4.1", true)
1156 .Case("sse4.2", true)
1157 .Case("sse4a", true)
1158 .Case("tbm", true)
1159 .Case("tsxldtrk", true)
1160 .Case("uintr", true)
1161 .Case("usermsr", true)
1162 .Case("vaes", true)
1163 .Case("vpclmulqdq", true)
1164 .Case("wbnoinvd", true)
1165 .Case("waitpkg", true)
1166 .Case("x87", true)
1167 .Case("xop", true)
1168 .Case("xsave", true)
1169 .Case("xsavec", true)
1170 .Case("xsaves", true)
1171 .Case("xsaveopt", true)
1172 .Case("egpr", true)
1173 .Case("push2pop2", true)
1174 .Case("ppx", true)
1175 .Case("ndd", true)
1176 .Case("ccmp", true)
1177 .Case("nf", true)
1178 .Case("cf", true)
1179 .Case("zu", true)
1180 .Default(false);
1181}
1182
1183bool X86TargetInfo::hasFeature(StringRef Feature) const {
1184 return llvm::StringSwitch<bool>(Feature)
1185 .Case("adx", HasADX)
1186 .Case("aes", HasAES)
1187 .Case("amx-avx512", HasAMXAVX512)
1188 .Case("amx-bf16", HasAMXBF16)
1189 .Case("amx-complex", HasAMXCOMPLEX)
1190 .Case("amx-fp16", HasAMXFP16)
1191 .Case("amx-fp8", HasAMXFP8)
1192 .Case("amx-int8", HasAMXINT8)
1193 .Case("amx-movrs", HasAMXMOVRS)
1194 .Case("amx-tf32", HasAMXTF32)
1195 .Case("amx-tile", HasAMXTILE)
1196 .Case("avx", SSELevel >= AVX)
1197 .Case("avx10.1", HasAVX10_1)
1198 .Case("avx10.2", HasAVX10_2)
1199 .Case("avx2", SSELevel >= AVX2)
1200 .Case("avx512f", SSELevel >= AVX512F)
1201 .Case("avx512cd", HasAVX512CD)
1202 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1203 .Case("avx512vnni", HasAVX512VNNI)
1204 .Case("avx512bf16", HasAVX512BF16)
1205 .Case("avx512fp16", HasAVX512FP16)
1206 .Case("avx512dq", HasAVX512DQ)
1207 .Case("avx512bitalg", HasAVX512BITALG)
1208 .Case("avx512bw", HasAVX512BW)
1209 .Case("avx512vl", HasAVX512VL)
1210 .Case("avx512vbmi", HasAVX512VBMI)
1211 .Case("avx512vbmi2", HasAVX512VBMI2)
1212 .Case("avx512ifma", HasAVX512IFMA)
1213 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1214 .Case("avxifma", HasAVXIFMA)
1215 .Case("avxneconvert", HasAVXNECONVERT)
1216 .Case("avxvnni", HasAVXVNNI)
1217 .Case("avxvnniint16", HasAVXVNNIINT16)
1218 .Case("avxvnniint8", HasAVXVNNIINT8)
1219 .Case("bmi", HasBMI)
1220 .Case("bmi2", HasBMI2)
1221 .Case("cldemote", HasCLDEMOTE)
1222 .Case("clflushopt", HasCLFLUSHOPT)
1223 .Case("clwb", HasCLWB)
1224 .Case("clzero", HasCLZERO)
1225 .Case("cmpccxadd", HasCMPCCXADD)
1226 .Case("crc32", HasCRC32)
1227 .Case("cx8", HasCX8)
1228 .Case("cx16", HasCX16)
1229 .Case("enqcmd", HasENQCMD)
1230 .Case("f16c", HasF16C)
1231 .Case("fma", HasFMA)
1232 .Case("fma4", XOPLevel >= FMA4)
1233 .Case("fsgsbase", HasFSGSBASE)
1234 .Case("fxsr", HasFXSR)
1235 .Case("gfni", HasGFNI)
1236 .Case("hreset", HasHRESET)
1237 .Case("invpcid", HasINVPCID)
1238 .Case("kl", HasKL)
1239 .Case("widekl", HasWIDEKL)
1240 .Case("lwp", HasLWP)
1241 .Case("lzcnt", HasLZCNT)
1242 .Case("mmx", HasMMX)
1243 .Case("movbe", HasMOVBE)
1244 .Case("movrs", HasMOVRS)
1245 .Case("movdiri", HasMOVDIRI)
1246 .Case("movdir64b", HasMOVDIR64B)
1247 .Case("mwaitx", HasMWAITX)
1248 .Case("pclmul", HasPCLMUL)
1249 .Case("pconfig", HasPCONFIG)
1250 .Case("pku", HasPKU)
1251 .Case("popcnt", HasPOPCNT)
1252 .Case("prefetchi", HasPREFETCHI)
1253 .Case("prfchw", HasPRFCHW)
1254 .Case("ptwrite", HasPTWRITE)
1255 .Case("raoint", HasRAOINT)
1256 .Case("rdpid", HasRDPID)
1257 .Case("rdpru", HasRDPRU)
1258 .Case("rdrnd", HasRDRND)
1259 .Case("rdseed", HasRDSEED)
1260 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1261 .Case("rtm", HasRTM)
1262 .Case("sahf", HasLAHFSAHF)
1263 .Case("serialize", HasSERIALIZE)
1264 .Case("sgx", HasSGX)
1265 .Case("sha", HasSHA)
1266 .Case("sha512", HasSHA512)
1267 .Case("shstk", HasSHSTK)
1268 .Case("sm3", HasSM3)
1269 .Case("sm4", HasSM4)
1270 .Case("sse", SSELevel >= SSE1)
1271 .Case("sse2", SSELevel >= SSE2)
1272 .Case("sse3", SSELevel >= SSE3)
1273 .Case("ssse3", SSELevel >= SSSE3)
1274 .Case("sse4.1", SSELevel >= SSE41)
1275 .Case("sse4.2", SSELevel >= SSE42)
1276 .Case("sse4a", XOPLevel >= SSE4A)
1277 .Case("tbm", HasTBM)
1278 .Case("tsxldtrk", HasTSXLDTRK)
1279 .Case("uintr", HasUINTR)
1280 .Case("usermsr", HasUSERMSR)
1281 .Case("vaes", HasVAES)
1282 .Case("vpclmulqdq", HasVPCLMULQDQ)
1283 .Case("wbnoinvd", HasWBNOINVD)
1284 .Case("waitpkg", HasWAITPKG)
1285 .Case("x86", true)
1286 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1287 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1288 .Case("x87", HasX87)
1289 .Case("xop", XOPLevel >= XOP)
1290 .Case("xsave", HasXSAVE)
1291 .Case("xsavec", HasXSAVEC)
1292 .Case("xsaves", HasXSAVES)
1293 .Case("xsaveopt", HasXSAVEOPT)
1294 .Case("fullbf16", HasFullBFloat16)
1295 .Case("egpr", HasEGPR)
1296 .Case("push2pop2", HasPush2Pop2)
1297 .Case("ppx", HasPPX)
1298 .Case("ndd", HasNDD)
1299 .Case("ccmp", HasCCMP)
1300 .Case("nf", HasNF)
1301 .Case("cf", HasCF)
1302 .Case("zu", HasZU)
1303 .Case("branch-hint", HasBranchHint)
1304 .Default(false);
1305}
1306
1307// We can't use a generic validation scheme for the features accepted here
1308// versus subtarget features accepted in the target attribute because the
1309// bitfield structure that's initialized in the runtime only supports the
1310// below currently rather than the full range of subtarget features. (See
1311// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1312bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1313 return llvm::StringSwitch<bool>(FeatureStr)
1314#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1315#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1316#include "llvm/TargetParser/X86TargetParser.def"
1317 .Default(false);
1318}
1319
1320static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1321 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1322#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1323 .Case(STR, llvm::X86::FEATURE_##ENUM)
1324
1325#include "llvm/TargetParser/X86TargetParser.def"
1326 ;
1327 // Note, this function should only be used after ensuring the value is
1328 // correct, so it asserts if the value is out of range.
1329}
1330
1331llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1332 auto getPriority = [](StringRef Feature) -> unsigned {
1333 // Valid CPUs have a 'key feature' that compares just better than its key
1334 // feature.
1335 using namespace llvm::X86;
1336 CPUKind Kind = parseArchX86(Feature);
1337 if (Kind != CK_None) {
1338 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1339 return (getFeaturePriority(KeyFeature) << 1) + 1;
1340 }
1341 // Now we know we have a feature, so get its priority and shift it a few so
1342 // that we have sufficient room for the CPUs (above).
1343 return getFeaturePriority(getFeature(Feature)) << 1;
1344 };
1345
1346 unsigned Priority = 0;
1347 for (StringRef Feature : Features)
1348 if (!Feature.empty())
1349 Priority = std::max(Priority, getPriority(Feature));
1350 return llvm::APInt(32, Priority);
1351}
1352
1353bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1354 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1355}
1356
1357char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1358 return llvm::X86::getCPUDispatchMangling(Name);
1359}
1360
1361void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1362 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1363 SmallVector<StringRef, 32> TargetCPUFeatures;
1364 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1365 for (auto &F : TargetCPUFeatures)
1366 Features.push_back(F);
1367}
1368
1369// We can't use a generic validation scheme for the cpus accepted here
1370// versus subtarget cpus accepted in the target attribute because the
1371// variables intitialized by the runtime only support the below currently
1372// rather than the full range of cpus.
1373bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1374 return llvm::StringSwitch<bool>(FeatureStr)
1375#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1376#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1377#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1378#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1379#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1380#include "llvm/TargetParser/X86TargetParser.def"
1381 .Default(false);
1382}
1383
1384static unsigned matchAsmCCConstraint(const char *Name) {
1385 auto RV = llvm::StringSwitch<unsigned>(Name)
1386 .Case("@cca", 4)
1387 .Case("@ccae", 5)
1388 .Case("@ccb", 4)
1389 .Case("@ccbe", 5)
1390 .Case("@ccc", 4)
1391 .Case("@cce", 4)
1392 .Case("@ccz", 4)
1393 .Case("@ccg", 4)
1394 .Case("@ccge", 5)
1395 .Case("@ccl", 4)
1396 .Case("@ccle", 5)
1397 .Case("@ccna", 5)
1398 .Case("@ccnae", 6)
1399 .Case("@ccnb", 5)
1400 .Case("@ccnbe", 6)
1401 .Case("@ccnc", 5)
1402 .Case("@ccne", 5)
1403 .Case("@ccnz", 5)
1404 .Case("@ccng", 5)
1405 .Case("@ccnge", 6)
1406 .Case("@ccnl", 5)
1407 .Case("@ccnle", 6)
1408 .Case("@ccno", 5)
1409 .Case("@ccnp", 5)
1410 .Case("@ccns", 5)
1411 .Case("@cco", 4)
1412 .Case("@ccp", 4)
1413 .Case("@ccs", 4)
1414 .Default(0);
1415 return RV;
1416}
1417
1418bool X86TargetInfo::validateAsmConstraint(
1419 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1420 switch (*Name) {
1421 default:
1422 return false;
1423 // Constant constraints.
1424 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1425 // instructions.
1426 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1427 // x86_64 instructions.
1428 case 's':
1429 Info.setRequiresImmediate();
1430 return true;
1431 case 'I':
1432 Info.setRequiresImmediate(0, 31);
1433 return true;
1434 case 'J':
1435 Info.setRequiresImmediate(0, 63);
1436 return true;
1437 case 'K':
1438 Info.setRequiresImmediate(-128, 127);
1439 return true;
1440 case 'L':
1441 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1442 return true;
1443 case 'M':
1444 Info.setRequiresImmediate(0, 3);
1445 return true;
1446 case 'N':
1447 Info.setRequiresImmediate(0, 255);
1448 return true;
1449 case 'O':
1450 Info.setRequiresImmediate(0, 127);
1451 return true;
1452 case 'W':
1453 switch (*++Name) {
1454 default:
1455 return false;
1456 case 's':
1457 Info.setAllowsRegister();
1458 return true;
1459 }
1460 // Register constraints.
1461 case 'Y': // 'Y' is the first character for several 2-character constraints.
1462 // Shift the pointer to the second character of the constraint.
1463 Name++;
1464 switch (*Name) {
1465 default:
1466 return false;
1467 case 'z': // First SSE register.
1468 case '2':
1469 case 't': // Any SSE register, when SSE2 is enabled.
1470 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1471 case 'm': // Any MMX register, when inter-unit moves enabled.
1472 case 'k': // AVX512 arch mask registers: k1-k7.
1473 Info.setAllowsRegister();
1474 return true;
1475 }
1476 case 'f': // Any x87 floating point stack register.
1477 // Constraint 'f' cannot be used for output operands.
1478 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1479 return false;
1480 Info.setAllowsRegister();
1481 return true;
1482 case 'a': // eax.
1483 case 'b': // ebx.
1484 case 'c': // ecx.
1485 case 'd': // edx.
1486 case 'S': // esi.
1487 case 'D': // edi.
1488 case 'A': // edx:eax.
1489 case 't': // Top of floating point stack.
1490 case 'u': // Second from top of floating point stack.
1491 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1492 case 'y': // Any MMX register.
1493 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1494 case 'x': // Any SSE register.
1495 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1496 // for intermideate k reg operations).
1497 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1498 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1499 case 'l': // "Index" registers: any general register that can be used as an
1500 // index in a base+index memory access.
1501 Info.setAllowsRegister();
1502 return true;
1503 // Floating point constant constraints.
1504 case 'C': // SSE floating point constant.
1505 case 'G': // x87 floating point constant.
1506 return true;
1507 case 'j':
1508 Name++;
1509 switch (*Name) {
1510 default:
1511 return false;
1512 case 'r':
1513 Info.setAllowsRegister();
1514 return true;
1515 case 'R':
1516 Info.setAllowsRegister();
1517 return true;
1518 }
1519 case '@':
1520 // CC condition changes.
1521 if (auto Len = matchAsmCCConstraint(Name)) {
1522 Name += Len - 1;
1523 Info.setAllowsRegister();
1524 Info.setOutputOperandBounds(0, 2);
1525 return true;
1526 }
1527 return false;
1528 }
1529}
1530
1531// Below is based on the following information:
1532// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1533// | Processor Name | Cache Line Size (Bytes) | Source |
1534// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1535// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1536// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1537// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1538// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1539// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1540// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1541// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1542// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1543// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1544// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1545// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1546// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1547// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1548// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1549// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1550// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1551// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1552// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1553std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1554 using namespace llvm::X86;
1555 switch (CPU) {
1556 // i386
1557 case CK_i386:
1558 // i486
1559 case CK_i486:
1560 case CK_WinChipC6:
1561 case CK_WinChip2:
1562 case CK_C3:
1563 // Lakemont
1564 case CK_Lakemont:
1565 return 16;
1566
1567 // i586
1568 case CK_i586:
1569 case CK_Pentium:
1570 case CK_PentiumMMX:
1571 // i686
1572 case CK_PentiumPro:
1573 case CK_i686:
1574 case CK_Pentium2:
1575 case CK_Pentium3:
1576 case CK_PentiumM:
1577 case CK_C3_2:
1578 // K6
1579 case CK_K6:
1580 case CK_K6_2:
1581 case CK_K6_3:
1582 // Geode
1583 case CK_Geode:
1584 return 32;
1585
1586 // Netburst
1587 case CK_Pentium4:
1588 case CK_Prescott:
1589 case CK_Nocona:
1590 // Atom
1591 case CK_Bonnell:
1592 case CK_Silvermont:
1593 case CK_Goldmont:
1594 case CK_GoldmontPlus:
1595 case CK_Tremont:
1596 case CK_Gracemont:
1597
1598 case CK_Westmere:
1599 case CK_SandyBridge:
1600 case CK_IvyBridge:
1601 case CK_Haswell:
1602 case CK_Broadwell:
1603 case CK_SkylakeClient:
1604 case CK_SkylakeServer:
1605 case CK_Cascadelake:
1606 case CK_Nehalem:
1607 case CK_Cooperlake:
1608 case CK_Cannonlake:
1609 case CK_Tigerlake:
1610 case CK_SapphireRapids:
1611 case CK_IcelakeClient:
1612 case CK_Rocketlake:
1613 case CK_IcelakeServer:
1614 case CK_Alderlake:
1615 case CK_Raptorlake:
1616 case CK_Meteorlake:
1617 case CK_Arrowlake:
1618 case CK_ArrowlakeS:
1619 case CK_Lunarlake:
1620 case CK_Pantherlake:
1621 case CK_Wildcatlake:
1622 case CK_Novalake:
1623 case CK_Sierraforest:
1624 case CK_Grandridge:
1625 case CK_Graniterapids:
1626 case CK_GraniterapidsD:
1627 case CK_Emeraldrapids:
1628 case CK_Clearwaterforest:
1629 case CK_Diamondrapids:
1630 case CK_KNL:
1631 case CK_KNM:
1632 // K7
1633 case CK_Athlon:
1634 case CK_AthlonXP:
1635 // K8
1636 case CK_K8:
1637 case CK_K8SSE3:
1638 case CK_AMDFAM10:
1639 // Bobcat
1640 case CK_BTVER1:
1641 case CK_BTVER2:
1642 // Bulldozer
1643 case CK_BDVER1:
1644 case CK_BDVER2:
1645 case CK_BDVER3:
1646 case CK_BDVER4:
1647 // Zen
1648 case CK_ZNVER1:
1649 case CK_ZNVER2:
1650 case CK_ZNVER3:
1651 case CK_ZNVER4:
1652 case CK_ZNVER5:
1653 case CK_ZNVER6:
1654 // Deprecated
1655 case CK_x86_64:
1656 case CK_x86_64_v2:
1657 case CK_x86_64_v3:
1658 case CK_x86_64_v4:
1659 case CK_Yonah:
1660 case CK_Penryn:
1661 case CK_Core2:
1662 return 64;
1663
1664 // The following currently have unknown cache line sizes (but they are probably all 64):
1665 // Core
1666 case CK_None:
1667 return std::nullopt;
1668 }
1669 llvm_unreachable("Unknown CPU kind");
1670}
1671
1672bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1673 StringRef Constraint,
1674 unsigned Size) const {
1675 // Strip off constraint modifiers.
1676 Constraint = Constraint.ltrim("=+&");
1677
1678 return validateOperandSize(FeatureMap, Constraint, Size);
1679}
1680
1681bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1682 StringRef Constraint,
1683 unsigned Size) const {
1684 return validateOperandSize(FeatureMap, Constraint, Size);
1685}
1686
1687bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1688 StringRef Constraint,
1689 unsigned Size) const {
1690 switch (Constraint[0]) {
1691 default:
1692 break;
1693 case 'k':
1694 // Registers k0-k7 (AVX512) size limit is 64 bit.
1695 case 'y':
1696 return Size <= 64;
1697 case 'f':
1698 case 't':
1699 case 'u':
1700 return Size <= 128;
1701 case 'Y':
1702 // 'Y' is the first character for several 2-character constraints.
1703 switch (Constraint[1]) {
1704 default:
1705 return false;
1706 case 'm':
1707 // 'Ym' is synonymous with 'y'.
1708 case 'k':
1709 return Size <= 64;
1710 case 'z':
1711 // XMM0/YMM/ZMM0
1712 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1713 // ZMM0 can be used if target supports AVX512F.
1714 return Size <= 512U;
1715 else if (hasFeatureEnabled(FeatureMap, "avx"))
1716 // YMM0 can be used if target supports AVX.
1717 return Size <= 256U;
1718 else if (hasFeatureEnabled(FeatureMap, "sse"))
1719 return Size <= 128U;
1720 return false;
1721 case 'i':
1722 case 't':
1723 case '2':
1724 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1725 if (SSELevel < SSE2)
1726 return false;
1727 break;
1728 }
1729 break;
1730 case 'v':
1731 case 'x':
1732 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1733 // 512-bit zmm registers can be used if target supports AVX512F.
1734 return Size <= 512U;
1735 else if (hasFeatureEnabled(FeatureMap, "avx"))
1736 // 256-bit ymm registers can be used if target supports AVX.
1737 return Size <= 256U;
1738 return Size <= 128U;
1739
1740 }
1741
1742 return true;
1743}
1744
1745std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1746 switch (*Constraint) {
1747 case '@':
1748 if (auto Len = matchAsmCCConstraint(Constraint)) {
1749 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1750 Constraint += Len - 1;
1751 return Converted;
1752 }
1753 return std::string(1, *Constraint);
1754 case 'a':
1755 return std::string("{ax}");
1756 case 'b':
1757 return std::string("{bx}");
1758 case 'c':
1759 return std::string("{cx}");
1760 case 'd':
1761 return std::string("{dx}");
1762 case 'S':
1763 return std::string("{si}");
1764 case 'D':
1765 return std::string("{di}");
1766 case 'p': // Keep 'p' constraint (address).
1767 return std::string("p");
1768 case 't': // top of floating point stack.
1769 return std::string("{st}");
1770 case 'u': // second from top of floating point stack.
1771 return std::string("{st(1)}"); // second from top of floating point stack.
1772 case 'W':
1773 assert(Constraint[1] == 's');
1774 return '^' + std::string(Constraint++, 2);
1775 case 'Y':
1776 switch (Constraint[1]) {
1777 default:
1778 // Break from inner switch and fall through (copy single char),
1779 // continue parsing after copying the current constraint into
1780 // the return string.
1781 break;
1782 case 'k':
1783 case 'm':
1784 case 'i':
1785 case 't':
1786 case 'z':
1787 case '2':
1788 // "^" hints llvm that this is a 2 letter constraint.
1789 // "Constraint++" is used to promote the string iterator
1790 // to the next constraint.
1791 return std::string("^") + std::string(Constraint++, 2);
1792 }
1793 [[fallthrough]];
1794 case 'j':
1795 switch (Constraint[1]) {
1796 default:
1797 // Break from inner switch and fall through (copy single char),
1798 // continue parsing after copying the current constraint into
1799 // the return string.
1800 break;
1801 case 'r':
1802 case 'R':
1803 // "^" hints llvm that this is a 2 letter constraint.
1804 // "Constraint++" is used to promote the string iterator
1805 // to the next constraint.
1806 return std::string("^") + std::string(Constraint++, 2);
1807 }
1808 [[fallthrough]];
1809 default:
1810 return std::string(1, *Constraint);
1811 }
1812}
1813
1814void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1815 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1816 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1817}
1818
1819void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1820 llvm::X86::fillValidTuneCPUList(Values);
1821}
1822
1826
1830
1831llvm::SmallVector<Builtin::InfosShard>
1832X86_32TargetInfo::getTargetBuiltins() const {
1833 return {
1834 {&X86::BuiltinStrings, X86::BuiltinInfos},
1835 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1836 };
1837}
1838
1839llvm::SmallVector<Builtin::InfosShard>
1840X86_64TargetInfo::getTargetBuiltins() const {
1841 return {
1842 {&X86::BuiltinStrings, X86::BuiltinInfos},
1843 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1844 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1845 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1846 "__builtin_ia32_"},
1847 };
1848}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1552
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:232
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1320
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:232
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1554
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:326
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1319
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1448
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:566
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:238
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1553
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1418
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1331
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1823
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1357
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1745
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:511
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1361
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1373
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1672
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1687
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1819
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1353
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1312
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1063
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1183
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:219
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:184
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1814
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1827
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1681
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1832
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1840
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:79
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1230
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1194
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
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