clang 24.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 if (Feature == "+apxf" || Feature == "-apxf") {
178 char Sign = Feature[0];
179 for (const char *Sub :
180 {"egpr", "push2pop2", "ppx", "ndd", "ccmp", "nf", "zu", "jmpabs"})
181 UpdatedFeaturesVec.push_back(Sign + std::string(Sub));
182 continue;
183 }
184
185 UpdatedFeaturesVec.push_back(Feature);
186 }
187
188 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
189 return false;
190
191 // Can't do this earlier because we need to be able to explicitly enable
192 // or disable these features and the things that they depend upon.
193
194 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
195 auto I = Features.find("sse4.2");
196 if (I != Features.end() && I->getValue() &&
197 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
198 Features["popcnt"] = true;
199
200 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
201 // then enable MMX.
202 I = Features.find("sse");
203 if (I != Features.end() && I->getValue() &&
204 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
205 Features["mmx"] = true;
206
207 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
208 I = Features.find("avx");
209 if (I != Features.end() && I->getValue() &&
210 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
211 Features["xsave"] = true;
212
213 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
214 I = Features.find("sse4.2");
215 if (I != Features.end() && I->getValue() &&
216 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
217 Features["crc32"] = true;
218
219 return true;
220}
221
222void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
223 StringRef Name, bool Enabled) const {
224 if (Name == "sse4") {
225 // We can get here via the __target__ attribute since that's not controlled
226 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
227 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
228 // disabled.
229 if (Enabled)
230 Name = "sse4.2";
231 else
232 Name = "sse4.1";
233 }
234
235 Features[Name] = Enabled;
236 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
237}
238
239/// handleTargetFeatures - Perform initialization based on the user
240/// configured set of features.
241bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
242 DiagnosticsEngine &Diags) {
243 for (const auto &Feature : Features) {
244 if (Feature[0] != '+')
245 continue;
246
247 if (Feature == "+mmx") {
248 HasMMX = true;
249 } else if (Feature == "+aes") {
250 HasAES = true;
251 } else if (Feature == "+vaes") {
252 HasVAES = true;
253 } else if (Feature == "+pclmul") {
254 HasPCLMUL = true;
255 } else if (Feature == "+vpclmulqdq") {
256 HasVPCLMULQDQ = true;
257 } else if (Feature == "+lzcnt") {
258 HasLZCNT = true;
259 } else if (Feature == "+rdrnd") {
260 HasRDRND = true;
261 } else if (Feature == "+fsgsbase") {
262 HasFSGSBASE = true;
263 } else if (Feature == "+bmi") {
264 HasBMI = true;
265 } else if (Feature == "+bmi2") {
266 HasBMI2 = true;
267 } else if (Feature == "+popcnt") {
268 HasPOPCNT = true;
269 } else if (Feature == "+rtm") {
270 HasRTM = true;
271 } else if (Feature == "+prfchw") {
272 HasPRFCHW = true;
273 } else if (Feature == "+rdseed") {
274 HasRDSEED = true;
275 } else if (Feature == "+adx") {
276 HasADX = true;
277 } else if (Feature == "+tbm") {
278 HasTBM = true;
279 } else if (Feature == "+lwp") {
280 HasLWP = true;
281 } else if (Feature == "+fma") {
282 HasFMA = true;
283 } else if (Feature == "+f16c") {
284 HasF16C = true;
285 } else if (Feature == "+gfni") {
286 HasGFNI = true;
287 } else if (Feature == "+avx10.1") {
288 HasAVX10_1 = true;
289 } else if (Feature == "+avx10.2") {
290 HasAVX10_2 = true;
291 HasFullBFloat16 = true;
292 } else if (Feature == "+avx512cd") {
293 HasAVX512CD = true;
294 } else if (Feature == "+avx512vpopcntdq") {
295 HasAVX512VPOPCNTDQ = true;
296 } else if (Feature == "+avx512vnni") {
297 HasAVX512VNNI = true;
298 } else if (Feature == "+avx512bf16") {
299 HasAVX512BF16 = true;
300 } else if (Feature == "+avx512fp16") {
301 HasAVX512FP16 = true;
302 HasFastHalfType = true;
303 } else if (Feature == "+avx512dq") {
304 HasAVX512DQ = true;
305 } else if (Feature == "+avx512bitalg") {
306 HasAVX512BITALG = true;
307 } else if (Feature == "+avx512bmm") {
308 HasAVX512BMM = true;
309 } else if (Feature == "+avx512bw") {
310 HasAVX512BW = true;
311 } else if (Feature == "+avx512vl") {
312 HasAVX512VL = true;
313 } else if (Feature == "+avx512vbmi") {
314 HasAVX512VBMI = true;
315 } else if (Feature == "+avx512vbmi2") {
316 HasAVX512VBMI2 = true;
317 } else if (Feature == "+avx512ifma") {
318 HasAVX512IFMA = true;
319 } else if (Feature == "+avx512vp2intersect") {
320 HasAVX512VP2INTERSECT = true;
321 } else if (Feature == "+sha") {
322 HasSHA = true;
323 } else if (Feature == "+sha512") {
324 HasSHA512 = true;
325 } else if (Feature == "+shstk") {
326 HasSHSTK = true;
327 } else if (Feature == "+sm3") {
328 HasSM3 = true;
329 } else if (Feature == "+sm4") {
330 HasSM4 = true;
331 } else if (Feature == "+movbe") {
332 HasMOVBE = true;
333 } else if (Feature == "+movrs") {
334 HasMOVRS = true;
335 } else if (Feature == "+sgx") {
336 HasSGX = true;
337 } else if (Feature == "+cx8") {
338 HasCX8 = true;
339 } else if (Feature == "+cx16") {
340 HasCX16 = true;
341 } else if (Feature == "+fxsr") {
342 HasFXSR = true;
343 } else if (Feature == "+xsave") {
344 HasXSAVE = true;
345 } else if (Feature == "+xsaveopt") {
346 HasXSAVEOPT = true;
347 } else if (Feature == "+xsavec") {
348 HasXSAVEC = true;
349 } else if (Feature == "+xsaves") {
350 HasXSAVES = true;
351 } else if (Feature == "+mwaitx") {
352 HasMWAITX = true;
353 } else if (Feature == "+pku") {
354 HasPKU = true;
355 } else if (Feature == "+clflushopt") {
356 HasCLFLUSHOPT = true;
357 } else if (Feature == "+clwb") {
358 HasCLWB = true;
359 } else if (Feature == "+wbnoinvd") {
360 HasWBNOINVD = true;
361 } else if (Feature == "+prefetchi") {
362 HasPREFETCHI = true;
363 } else if (Feature == "+clzero") {
364 HasCLZERO = true;
365 } else if (Feature == "+cldemote") {
366 HasCLDEMOTE = true;
367 } else if (Feature == "+rdpid") {
368 HasRDPID = true;
369 } else if (Feature == "+rdpru") {
370 HasRDPRU = true;
371 } else if (Feature == "+kl") {
372 HasKL = true;
373 } else if (Feature == "+widekl") {
374 HasWIDEKL = true;
375 } else if (Feature == "+retpoline-external-thunk") {
376 HasRetpolineExternalThunk = true;
377 } else if (Feature == "+sahf") {
378 HasLAHFSAHF = true;
379 } else if (Feature == "+waitpkg") {
380 HasWAITPKG = true;
381 } else if (Feature == "+movdiri") {
382 HasMOVDIRI = true;
383 } else if (Feature == "+movdir64b") {
384 HasMOVDIR64B = true;
385 } else if (Feature == "+pconfig") {
386 HasPCONFIG = true;
387 } else if (Feature == "+ptwrite") {
388 HasPTWRITE = true;
389 } else if (Feature == "+invpcid") {
390 HasINVPCID = true;
391 } else if (Feature == "+enqcmd") {
392 HasENQCMD = true;
393 } else if (Feature == "+hreset") {
394 HasHRESET = true;
395 } else if (Feature == "+amx-bf16") {
396 HasAMXBF16 = true;
397 } else if (Feature == "+amx-fp16") {
398 HasAMXFP16 = true;
399 } else if (Feature == "+amx-int8") {
400 HasAMXINT8 = true;
401 } else if (Feature == "+amx-tile") {
402 HasAMXTILE = true;
403 } else if (Feature == "+amx-complex") {
404 HasAMXCOMPLEX = true;
405 } else if (Feature == "+amx-fp8") {
406 HasAMXFP8 = true;
407 } else if (Feature == "+amx-movrs") {
408 HasAMXMOVRS = true;
409 } else if (Feature == "+amx-avx512") {
410 HasAMXAVX512 = true;
411 } else if (Feature == "+cmpccxadd") {
412 HasCMPCCXADD = true;
413 } else if (Feature == "+raoint") {
414 HasRAOINT = true;
415 } else if (Feature == "+avxifma") {
416 HasAVXIFMA = true;
417 } else if (Feature == "+avxneconvert") {
418 HasAVXNECONVERT= true;
419 } else if (Feature == "+avxvnni") {
420 HasAVXVNNI = true;
421 } else if (Feature == "+avxvnniint16") {
422 HasAVXVNNIINT16 = true;
423 } else if (Feature == "+avxvnniint8") {
424 HasAVXVNNIINT8 = true;
425 } else if (Feature == "+serialize") {
426 HasSERIALIZE = true;
427 } else if (Feature == "+tsxldtrk") {
428 HasTSXLDTRK = true;
429 } else if (Feature == "+uintr") {
430 HasUINTR = true;
431 } else if (Feature == "+usermsr") {
432 HasUSERMSR = true;
433 } else if (Feature == "+crc32") {
434 HasCRC32 = true;
435 } else if (Feature == "+x87") {
436 HasX87 = true;
437 } else if (Feature == "+fullbf16") {
438 HasFullBFloat16 = true;
439 } else if (Feature == "+egpr") {
440 HasEGPR = true;
441 } else if (Feature == "+inline-asm-use-gpr32") {
442 HasInlineAsmUseGPR32 = true;
443 } else if (Feature == "+push2pop2") {
444 HasPush2Pop2 = true;
445 } else if (Feature == "+ppx") {
446 HasPPX = true;
447 } else if (Feature == "+ndd") {
448 HasNDD = true;
449 } else if (Feature == "+ccmp") {
450 HasCCMP = true;
451 } else if (Feature == "+nf") {
452 HasNF = true;
453 } else if (Feature == "+cf") {
454 HasCF = true;
455 } else if (Feature == "+zu") {
456 HasZU = true;
457 } else if (Feature == "+jmpabs") {
458 HasJMPABS = true;
459 } else if (Feature == "+branch-hint") {
460 HasBranchHint = true;
461 }
462
463 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
464 .Case("+avx512f", AVX512F)
465 .Case("+avx2", AVX2)
466 .Case("+avx", AVX)
467 .Case("+sse4.2", SSE42)
468 .Case("+sse4.1", SSE41)
469 .Case("+ssse3", SSSE3)
470 .Case("+sse3", SSE3)
471 .Case("+sse2", SSE2)
472 .Case("+sse", SSE1)
473 .Default(NoSSE);
474 SSELevel = std::max(SSELevel, Level);
475
476 HasFloat16 = SSELevel >= SSE2;
477
478 // X86 target has bfloat16 emulation support in the backend, where
479 // bfloat16 is treated as a 32-bit float, arithmetic operations are
480 // performed in 32-bit, and the result is converted back to bfloat16.
481 // Truncation and extension between bfloat16 and 32-bit float are supported
482 // by the compiler-rt library. However, native bfloat16 support is currently
483 // not available in the X86 target. Hence, HasFullBFloat16 will be false
484 // until native bfloat16 support is available. HasFullBFloat16 is used to
485 // determine whether to automatically use excess floating point precision
486 // for bfloat16 arithmetic operations in the front-end.
487 HasBFloat16 = SSELevel >= SSE2;
488
489 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
490 .Case("+xop", XOP)
491 .Case("+fma4", FMA4)
492 .Case("+sse4a", SSE4A)
493 .Default(NoXOP);
494 XOPLevel = std::max(XOPLevel, XLevel);
495 }
496
497 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
498 // matches the selected sse level.
499 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
500 (FPMath == FP_387 && SSELevel >= SSE1)) {
501 Diags.Report(diag::err_target_unsupported_fpmath)
502 << (FPMath == FP_SSE ? "sse" : "387");
503 return false;
504 }
505
506 // FIXME: We should allow long double type on 32-bits to match with GCC.
507 // This requires backend to be able to lower f80 without x87 first.
508 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
509 HasLongDouble = false;
510
511 return true;
512}
513
514/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
515/// definitions for this particular subtarget.
516void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
517 MacroBuilder &Builder) const {
518 // Inline assembly supports X86 flag outputs.
519 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
520
521 std::string CodeModel = getTargetOpts().CodeModel;
522 if (CodeModel == "default")
523 CodeModel = "small";
524 Builder.defineMacro("__code_model_" + CodeModel + "__");
525
526 // Target identification.
527 if (getTriple().getArch() == llvm::Triple::x86_64) {
528 Builder.defineMacro("__amd64__");
529 Builder.defineMacro("__amd64");
530 Builder.defineMacro("__x86_64");
531 Builder.defineMacro("__x86_64__");
532 if (getTriple().getArchName() == "x86_64h") {
533 Builder.defineMacro("__x86_64h");
534 Builder.defineMacro("__x86_64h__");
535 }
536 } else {
537 DefineStd(Builder, "i386", Opts);
538 }
539
540 if (getTriple().isLFI()) {
541 Builder.defineMacro("__LFI__");
542 }
543
544 Builder.defineMacro("__SEG_GS");
545 Builder.defineMacro("__SEG_FS");
546 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
547 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
548
549 // Subtarget options.
550 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
551 // truly should be based on -mtune options.
552 using namespace llvm::X86;
553 switch (CPU) {
554 case CK_None:
555 break;
556 case CK_i386:
557 // The rest are coming from the i386 define above.
558 Builder.defineMacro("__tune_i386__");
559 break;
560 case CK_i486:
561 case CK_WinChipC6:
562 case CK_WinChip2:
563 case CK_C3:
564 defineCPUMacros(Builder, "i486");
565 break;
566 case CK_PentiumMMX:
567 Builder.defineMacro("__pentium_mmx__");
568 Builder.defineMacro("__tune_pentium_mmx__");
569 [[fallthrough]];
570 case CK_i586:
571 case CK_Pentium:
572 defineCPUMacros(Builder, "i586");
573 defineCPUMacros(Builder, "pentium");
574 break;
575 case CK_Pentium3:
576 case CK_PentiumM:
577 Builder.defineMacro("__tune_pentium3__");
578 [[fallthrough]];
579 case CK_Pentium2:
580 case CK_C3_2:
581 Builder.defineMacro("__tune_pentium2__");
582 [[fallthrough]];
583 case CK_PentiumPro:
584 case CK_i686:
585 defineCPUMacros(Builder, "i686");
586 defineCPUMacros(Builder, "pentiumpro");
587 break;
588 case CK_Pentium4:
589 defineCPUMacros(Builder, "pentium4");
590 break;
591 case CK_Yonah:
592 case CK_Prescott:
593 case CK_Nocona:
594 defineCPUMacros(Builder, "nocona");
595 break;
596 case CK_Core2:
597 case CK_Penryn:
598 defineCPUMacros(Builder, "core2");
599 break;
600 case CK_Bonnell:
601 defineCPUMacros(Builder, "atom");
602 break;
603 case CK_Silvermont:
604 defineCPUMacros(Builder, "slm");
605 break;
606 case CK_Goldmont:
607 defineCPUMacros(Builder, "goldmont");
608 break;
609 case CK_GoldmontPlus:
610 defineCPUMacros(Builder, "goldmont_plus");
611 break;
612 case CK_Tremont:
613 defineCPUMacros(Builder, "tremont");
614 break;
615 // Gracemont and later atom-cores use P-core cpu macros.
616 case CK_Gracemont:
617 case CK_Nehalem:
618 case CK_Westmere:
619 case CK_SandyBridge:
620 case CK_IvyBridge:
621 case CK_Haswell:
622 case CK_Broadwell:
623 case CK_SkylakeClient:
624 case CK_SkylakeServer:
625 case CK_Cascadelake:
626 case CK_Cooperlake:
627 case CK_Cannonlake:
628 case CK_IcelakeClient:
629 case CK_Rocketlake:
630 case CK_IcelakeServer:
631 case CK_Tigerlake:
632 case CK_SapphireRapids:
633 case CK_Alderlake:
634 case CK_Raptorlake:
635 case CK_Meteorlake:
636 case CK_Arrowlake:
637 case CK_ArrowlakeS:
638 case CK_Lunarlake:
639 case CK_Pantherlake:
640 case CK_Wildcatlake:
641 case CK_Novalake:
642 case CK_Sierraforest:
643 case CK_Grandridge:
644 case CK_Graniterapids:
645 case CK_GraniterapidsD:
646 case CK_Emeraldrapids:
647 case CK_Clearwaterforest:
648 case CK_Diamondrapids:
649 // FIXME: Historically, we defined this legacy name, it would be nice to
650 // remove it at some point. We've never exposed fine-grained names for
651 // recent primary x86 CPUs, and we should keep it that way.
652 defineCPUMacros(Builder, "corei7");
653 break;
654 case CK_KNL:
655 defineCPUMacros(Builder, "knl");
656 break;
657 case CK_KNM:
658 break;
659 case CK_Lakemont:
660 defineCPUMacros(Builder, "i586", /*Tuning*/false);
661 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
662 Builder.defineMacro("__tune_lakemont__");
663 break;
664 case CK_K6_2:
665 Builder.defineMacro("__k6_2__");
666 Builder.defineMacro("__tune_k6_2__");
667 [[fallthrough]];
668 case CK_K6_3:
669 if (CPU != CK_K6_2) { // In case of fallthrough
670 // FIXME: GCC may be enabling these in cases where some other k6
671 // architecture is specified but -m3dnow is explicitly provided. The
672 // exact semantics need to be determined and emulated here.
673 Builder.defineMacro("__k6_3__");
674 Builder.defineMacro("__tune_k6_3__");
675 }
676 [[fallthrough]];
677 case CK_K6:
678 defineCPUMacros(Builder, "k6");
679 break;
680 case CK_Athlon:
681 case CK_AthlonXP:
682 defineCPUMacros(Builder, "athlon");
683 if (SSELevel != NoSSE) {
684 Builder.defineMacro("__athlon_sse__");
685 Builder.defineMacro("__tune_athlon_sse__");
686 }
687 break;
688 case CK_K8:
689 case CK_K8SSE3:
690 case CK_x86_64:
691 defineCPUMacros(Builder, "k8");
692 break;
693 case CK_x86_64_v2:
694 case CK_x86_64_v3:
695 case CK_x86_64_v4:
696 break;
697 case CK_AMDFAM10:
698 defineCPUMacros(Builder, "amdfam10");
699 break;
700 case CK_BTVER1:
701 defineCPUMacros(Builder, "btver1");
702 break;
703 case CK_BTVER2:
704 defineCPUMacros(Builder, "btver2");
705 break;
706 case CK_BDVER1:
707 defineCPUMacros(Builder, "bdver1");
708 break;
709 case CK_BDVER2:
710 defineCPUMacros(Builder, "bdver2");
711 break;
712 case CK_BDVER3:
713 defineCPUMacros(Builder, "bdver3");
714 break;
715 case CK_BDVER4:
716 defineCPUMacros(Builder, "bdver4");
717 break;
718 case CK_ZNVER1:
719 defineCPUMacros(Builder, "znver1");
720 break;
721 case CK_ZNVER2:
722 defineCPUMacros(Builder, "znver2");
723 break;
724 case CK_ZNVER3:
725 defineCPUMacros(Builder, "znver3");
726 break;
727 case CK_ZNVER4:
728 defineCPUMacros(Builder, "znver4");
729 break;
730 case CK_ZNVER5:
731 defineCPUMacros(Builder, "znver5");
732 break;
733 case CK_ZNVER6:
734 defineCPUMacros(Builder, "znver6");
735 break;
736 case CK_Geode:
737 defineCPUMacros(Builder, "geode");
738 break;
739 case CK_C86_4G_M4:
740 defineCPUMacros(Builder, "c86_4g_m4");
741 break;
742 case CK_C86_4G_M6:
743 defineCPUMacros(Builder, "c86_4g_m6");
744 break;
745 case CK_C86_4G_M7:
746 defineCPUMacros(Builder, "c86_4g_m7");
747 break;
748 case CK_C86_4G_M8:
749 defineCPUMacros(Builder, "c86_4g_m8");
750 break;
751 }
752
753 // Target properties.
754 Builder.defineMacro("__REGISTER_PREFIX__", "");
755
756 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
757 // functions in glibc header files that use FP Stack inline asm which the
758 // backend can't deal with (PR879).
759 Builder.defineMacro("__NO_MATH_INLINES");
760
761 if (HasAES)
762 Builder.defineMacro("__AES__");
763
764 if (HasVAES)
765 Builder.defineMacro("__VAES__");
766
767 if (HasPCLMUL)
768 Builder.defineMacro("__PCLMUL__");
769
770 if (HasVPCLMULQDQ)
771 Builder.defineMacro("__VPCLMULQDQ__");
772
773 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
774 // the feature flag only applies to 64-bit mode.
775 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
776 Builder.defineMacro("__LAHF_SAHF__");
777
778 if (HasLZCNT)
779 Builder.defineMacro("__LZCNT__");
780
781 if (HasRDRND)
782 Builder.defineMacro("__RDRND__");
783
784 if (HasFSGSBASE)
785 Builder.defineMacro("__FSGSBASE__");
786
787 if (HasBMI)
788 Builder.defineMacro("__BMI__");
789
790 if (HasBMI2)
791 Builder.defineMacro("__BMI2__");
792
793 if (HasPOPCNT)
794 Builder.defineMacro("__POPCNT__");
795
796 if (HasRTM)
797 Builder.defineMacro("__RTM__");
798
799 if (HasPRFCHW)
800 Builder.defineMacro("__PRFCHW__");
801
802 if (HasRDSEED)
803 Builder.defineMacro("__RDSEED__");
804
805 if (HasADX)
806 Builder.defineMacro("__ADX__");
807
808 if (HasTBM)
809 Builder.defineMacro("__TBM__");
810
811 if (HasLWP)
812 Builder.defineMacro("__LWP__");
813
814 if (HasMWAITX)
815 Builder.defineMacro("__MWAITX__");
816
817 if (HasMOVBE)
818 Builder.defineMacro("__MOVBE__");
819
820 switch (XOPLevel) {
821 case XOP:
822 Builder.defineMacro("__XOP__");
823 [[fallthrough]];
824 case FMA4:
825 Builder.defineMacro("__FMA4__");
826 [[fallthrough]];
827 case SSE4A:
828 Builder.defineMacro("__SSE4A__");
829 [[fallthrough]];
830 case NoXOP:
831 break;
832 }
833
834 if (HasFMA)
835 Builder.defineMacro("__FMA__");
836
837 if (HasF16C)
838 Builder.defineMacro("__F16C__");
839
840 if (HasGFNI)
841 Builder.defineMacro("__GFNI__");
842
843 if (HasAVX10_1) {
844 Builder.defineMacro("__AVX10_1__");
845 Builder.defineMacro("__AVX10_1_512__");
846 }
847 if (HasAVX10_2) {
848 Builder.defineMacro("__AVX10_2__");
849 Builder.defineMacro("__AVX10_2_512__");
850 }
851 if (HasAVX512CD)
852 Builder.defineMacro("__AVX512CD__");
853 if (HasAVX512VPOPCNTDQ)
854 Builder.defineMacro("__AVX512VPOPCNTDQ__");
855 if (HasAVX512VNNI)
856 Builder.defineMacro("__AVX512VNNI__");
857 if (HasAVX512BF16)
858 Builder.defineMacro("__AVX512BF16__");
859 if (HasAVX512FP16)
860 Builder.defineMacro("__AVX512FP16__");
861 if (HasAVX512DQ)
862 Builder.defineMacro("__AVX512DQ__");
863 if (HasAVX512BITALG)
864 Builder.defineMacro("__AVX512BITALG__");
865 if (HasAVX512BMM)
866 Builder.defineMacro("__AVX512BMM__");
867 if (HasAVX512BW)
868 Builder.defineMacro("__AVX512BW__");
869 if (HasAVX512VL) {
870 Builder.defineMacro("__AVX512VL__");
871 }
872 if (HasAVX512VBMI)
873 Builder.defineMacro("__AVX512VBMI__");
874 if (HasAVX512VBMI2)
875 Builder.defineMacro("__AVX512VBMI2__");
876 if (HasAVX512IFMA)
877 Builder.defineMacro("__AVX512IFMA__");
878 if (HasAVX512VP2INTERSECT)
879 Builder.defineMacro("__AVX512VP2INTERSECT__");
880 if (HasSHA)
881 Builder.defineMacro("__SHA__");
882 if (HasSHA512)
883 Builder.defineMacro("__SHA512__");
884
885 if (HasFXSR)
886 Builder.defineMacro("__FXSR__");
887 if (HasXSAVE)
888 Builder.defineMacro("__XSAVE__");
889 if (HasXSAVEOPT)
890 Builder.defineMacro("__XSAVEOPT__");
891 if (HasXSAVEC)
892 Builder.defineMacro("__XSAVEC__");
893 if (HasXSAVES)
894 Builder.defineMacro("__XSAVES__");
895 if (HasPKU)
896 Builder.defineMacro("__PKU__");
897 if (HasCLFLUSHOPT)
898 Builder.defineMacro("__CLFLUSHOPT__");
899 if (HasCLWB)
900 Builder.defineMacro("__CLWB__");
901 if (HasWBNOINVD)
902 Builder.defineMacro("__WBNOINVD__");
903 if (HasSHSTK)
904 Builder.defineMacro("__SHSTK__");
905 if (HasSGX)
906 Builder.defineMacro("__SGX__");
907 if (HasSM3)
908 Builder.defineMacro("__SM3__");
909 if (HasSM4)
910 Builder.defineMacro("__SM4__");
911 if (HasPREFETCHI)
912 Builder.defineMacro("__PREFETCHI__");
913 if (HasCLZERO)
914 Builder.defineMacro("__CLZERO__");
915 if (HasKL)
916 Builder.defineMacro("__KL__");
917 if (HasWIDEKL)
918 Builder.defineMacro("__WIDEKL__");
919 if (HasRDPID)
920 Builder.defineMacro("__RDPID__");
921 if (HasRDPRU)
922 Builder.defineMacro("__RDPRU__");
923 if (HasCLDEMOTE)
924 Builder.defineMacro("__CLDEMOTE__");
925 if (HasWAITPKG)
926 Builder.defineMacro("__WAITPKG__");
927 if (HasMOVDIRI)
928 Builder.defineMacro("__MOVDIRI__");
929 if (HasMOVDIR64B)
930 Builder.defineMacro("__MOVDIR64B__");
931 if (HasMOVRS)
932 Builder.defineMacro("__MOVRS__");
933 if (HasPCONFIG)
934 Builder.defineMacro("__PCONFIG__");
935 if (HasPTWRITE)
936 Builder.defineMacro("__PTWRITE__");
937 if (HasINVPCID)
938 Builder.defineMacro("__INVPCID__");
939 if (HasENQCMD)
940 Builder.defineMacro("__ENQCMD__");
941 if (HasHRESET)
942 Builder.defineMacro("__HRESET__");
943 if (HasAMXTILE)
944 Builder.defineMacro("__AMX_TILE__");
945 if (HasAMXINT8)
946 Builder.defineMacro("__AMX_INT8__");
947 if (HasAMXBF16)
948 Builder.defineMacro("__AMX_BF16__");
949 if (HasAMXFP16)
950 Builder.defineMacro("__AMX_FP16__");
951 if (HasAMXCOMPLEX)
952 Builder.defineMacro("__AMX_COMPLEX__");
953 if (HasAMXFP8)
954 Builder.defineMacro("__AMX_FP8__");
955 if (HasAMXMOVRS)
956 Builder.defineMacro("__AMX_MOVRS__");
957 if (HasAMXAVX512)
958 Builder.defineMacro("__AMX_AVX512__");
959 if (HasCMPCCXADD)
960 Builder.defineMacro("__CMPCCXADD__");
961 if (HasRAOINT)
962 Builder.defineMacro("__RAOINT__");
963 if (HasAVXIFMA)
964 Builder.defineMacro("__AVXIFMA__");
965 if (HasAVXNECONVERT)
966 Builder.defineMacro("__AVXNECONVERT__");
967 if (HasAVXVNNI)
968 Builder.defineMacro("__AVXVNNI__");
969 if (HasAVXVNNIINT16)
970 Builder.defineMacro("__AVXVNNIINT16__");
971 if (HasAVXVNNIINT8)
972 Builder.defineMacro("__AVXVNNIINT8__");
973 if (HasSERIALIZE)
974 Builder.defineMacro("__SERIALIZE__");
975 if (HasTSXLDTRK)
976 Builder.defineMacro("__TSXLDTRK__");
977 if (HasUINTR)
978 Builder.defineMacro("__UINTR__");
979 if (HasUSERMSR)
980 Builder.defineMacro("__USERMSR__");
981 if (HasCRC32)
982 Builder.defineMacro("__CRC32__");
983 if (HasEGPR)
984 Builder.defineMacro("__EGPR__");
985 if (HasPush2Pop2)
986 Builder.defineMacro("__PUSH2POP2__");
987 if (HasPPX)
988 Builder.defineMacro("__PPX__");
989 if (HasNDD)
990 Builder.defineMacro("__NDD__");
991 if (HasCCMP)
992 Builder.defineMacro("__CCMP__");
993 if (HasNF)
994 Builder.defineMacro("__NF__");
995 if (HasCF)
996 Builder.defineMacro("__CF__");
997 if (HasZU)
998 Builder.defineMacro("__ZU__");
999 if (HasJMPABS)
1000 Builder.defineMacro("__JMPABS__");
1001 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
1002 HasZU && HasJMPABS)
1003 Builder.defineMacro("__APX_F__");
1004 if (HasEGPR && HasInlineAsmUseGPR32)
1005 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
1006
1007 // Each case falls through to the previous one here.
1008 switch (SSELevel) {
1009 case AVX512F:
1010 Builder.defineMacro("__AVX512F__");
1011 [[fallthrough]];
1012 case AVX2:
1013 Builder.defineMacro("__AVX2__");
1014 [[fallthrough]];
1015 case AVX:
1016 Builder.defineMacro("__AVX__");
1017 [[fallthrough]];
1018 case SSE42:
1019 Builder.defineMacro("__SSE4_2__");
1020 [[fallthrough]];
1021 case SSE41:
1022 Builder.defineMacro("__SSE4_1__");
1023 [[fallthrough]];
1024 case SSSE3:
1025 Builder.defineMacro("__SSSE3__");
1026 [[fallthrough]];
1027 case SSE3:
1028 Builder.defineMacro("__SSE3__");
1029 [[fallthrough]];
1030 case SSE2:
1031 Builder.defineMacro("__SSE2__");
1032 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1033 [[fallthrough]];
1034 case SSE1:
1035 Builder.defineMacro("__SSE__");
1036 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1037 [[fallthrough]];
1038 case NoSSE:
1039 break;
1040 }
1041
1042 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1043 switch (SSELevel) {
1044 case AVX512F:
1045 case AVX2:
1046 case AVX:
1047 case SSE42:
1048 case SSE41:
1049 case SSSE3:
1050 case SSE3:
1051 case SSE2:
1052 Builder.defineMacro("_M_IX86_FP", Twine(2));
1053 break;
1054 case SSE1:
1055 Builder.defineMacro("_M_IX86_FP", Twine(1));
1056 break;
1057 default:
1058 Builder.defineMacro("_M_IX86_FP", Twine(0));
1059 break;
1060 }
1061 }
1062
1063 // Each case falls through to the previous one here.
1064 if (HasMMX) {
1065 Builder.defineMacro("__MMX__");
1066 }
1067
1068 if (CPU >= CK_i486 || CPU == CK_None) {
1069 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1070 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1071 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1072 }
1073 if (HasCX8)
1074 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1075 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1077
1078 if (HasFloat128)
1079 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1080
1081 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1082 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1083 Opts.CFProtectionBranch});
1084}
1085
1086bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1087 return llvm::StringSwitch<bool>(Name)
1088 .Case("adx", true)
1089 .Case("aes", true)
1090 .Case("amx-avx512", true)
1091 .Case("amx-bf16", true)
1092 .Case("amx-complex", true)
1093 .Case("amx-fp16", true)
1094 .Case("amx-fp8", true)
1095 .Case("amx-int8", true)
1096 .Case("amx-movrs", true)
1097 .Case("amx-tile", true)
1098 .Case("avx", true)
1099 .Case("avx10.1", true)
1100 .Case("avx10.2", true)
1101 .Case("avx2", true)
1102 .Case("avx512f", true)
1103 .Case("avx512cd", true)
1104 .Case("avx512vpopcntdq", true)
1105 .Case("avx512vnni", true)
1106 .Case("avx512bf16", true)
1107 .Case("avx512fp16", true)
1108 .Case("avx512dq", true)
1109 .Case("avx512bitalg", true)
1110 .Case("avx512bmm", true)
1111 .Case("avx512bw", true)
1112 .Case("avx512vl", true)
1113 .Case("avx512vbmi", true)
1114 .Case("avx512vbmi2", true)
1115 .Case("avx512ifma", true)
1116 .Case("avx512vp2intersect", true)
1117 .Case("avxifma", true)
1118 .Case("avxneconvert", true)
1119 .Case("avxvnni", true)
1120 .Case("avxvnniint16", true)
1121 .Case("avxvnniint8", true)
1122 .Case("bmi", true)
1123 .Case("bmi2", true)
1124 .Case("cldemote", true)
1125 .Case("clflushopt", true)
1126 .Case("clwb", true)
1127 .Case("clzero", true)
1128 .Case("cmpccxadd", true)
1129 .Case("crc32", true)
1130 .Case("cx16", true)
1131 .Case("enqcmd", true)
1132 .Case("f16c", true)
1133 .Case("fma", true)
1134 .Case("fma4", true)
1135 .Case("fsgsbase", true)
1136 .Case("fxsr", true)
1137 .Case("general-regs-only", true)
1138 .Case("gfni", true)
1139 .Case("hreset", true)
1140 .Case("invpcid", true)
1141 .Case("kl", true)
1142 .Case("widekl", true)
1143 .Case("lwp", true)
1144 .Case("lzcnt", true)
1145 .Case("mmx", true)
1146 .Case("movbe", true)
1147 .Case("movrs", true)
1148 .Case("movdiri", true)
1149 .Case("movdir64b", true)
1150 .Case("mwaitx", true)
1151 .Case("pclmul", true)
1152 .Case("pconfig", true)
1153 .Case("pku", true)
1154 .Case("popcnt", true)
1155 .Case("prefer-256-bit", true)
1156 .Case("prefetchi", true)
1157 .Case("prfchw", true)
1158 .Case("ptwrite", true)
1159 .Case("raoint", true)
1160 .Case("rdpid", true)
1161 .Case("rdpru", true)
1162 .Case("rdrnd", true)
1163 .Case("rdseed", true)
1164 .Case("rtm", true)
1165 .Case("sahf", true)
1166 .Case("serialize", true)
1167 .Case("sgx", true)
1168 .Case("sha", true)
1169 .Case("sha512", true)
1170 .Case("shstk", true)
1171 .Case("sm3", true)
1172 .Case("sm4", true)
1173 .Case("sse", true)
1174 .Case("sse2", true)
1175 .Case("sse3", true)
1176 .Case("ssse3", true)
1177 .Case("sse4", true)
1178 .Case("sse4.1", true)
1179 .Case("sse4.2", true)
1180 .Case("sse4a", true)
1181 .Case("tbm", true)
1182 .Case("tsxldtrk", true)
1183 .Case("uintr", true)
1184 .Case("usermsr", true)
1185 .Case("vaes", true)
1186 .Case("vpclmulqdq", true)
1187 .Case("wbnoinvd", true)
1188 .Case("waitpkg", true)
1189 .Case("x87", true)
1190 .Case("xop", true)
1191 .Case("xsave", true)
1192 .Case("xsavec", true)
1193 .Case("xsaves", true)
1194 .Case("xsaveopt", true)
1195 .Case("apxf", true)
1196 .Case("egpr", true)
1197 .Case("push2pop2", true)
1198 .Case("ppx", true)
1199 .Case("ndd", true)
1200 .Case("ccmp", true)
1201 .Case("nf", true)
1202 .Case("cf", true)
1203 .Case("zu", true)
1204 .Case("jmpabs", true)
1205 .Default(false);
1206}
1207
1208bool X86TargetInfo::hasFeature(StringRef Feature) const {
1209 return llvm::StringSwitch<bool>(Feature)
1210 .Case("adx", HasADX)
1211 .Case("aes", HasAES)
1212 .Case("amx-avx512", HasAMXAVX512)
1213 .Case("amx-bf16", HasAMXBF16)
1214 .Case("amx-complex", HasAMXCOMPLEX)
1215 .Case("amx-fp16", HasAMXFP16)
1216 .Case("amx-fp8", HasAMXFP8)
1217 .Case("amx-int8", HasAMXINT8)
1218 .Case("amx-movrs", HasAMXMOVRS)
1219 .Case("amx-tile", HasAMXTILE)
1220 .Case("avx", SSELevel >= AVX)
1221 .Case("avx10.1", HasAVX10_1)
1222 .Case("avx10.2", HasAVX10_2)
1223 .Case("avx2", SSELevel >= AVX2)
1224 .Case("avx512f", SSELevel >= AVX512F)
1225 .Case("avx512cd", HasAVX512CD)
1226 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1227 .Case("avx512vnni", HasAVX512VNNI)
1228 .Case("avx512bf16", HasAVX512BF16)
1229 .Case("avx512fp16", HasAVX512FP16)
1230 .Case("avx512dq", HasAVX512DQ)
1231 .Case("avx512bitalg", HasAVX512BITALG)
1232 .Case("avx512bmm", HasAVX512BMM)
1233 .Case("avx512bw", HasAVX512BW)
1234 .Case("avx512vl", HasAVX512VL)
1235 .Case("avx512vbmi", HasAVX512VBMI)
1236 .Case("avx512vbmi2", HasAVX512VBMI2)
1237 .Case("avx512ifma", HasAVX512IFMA)
1238 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1239 .Case("avxifma", HasAVXIFMA)
1240 .Case("avxneconvert", HasAVXNECONVERT)
1241 .Case("avxvnni", HasAVXVNNI)
1242 .Case("avxvnniint16", HasAVXVNNIINT16)
1243 .Case("avxvnniint8", HasAVXVNNIINT8)
1244 .Case("bmi", HasBMI)
1245 .Case("bmi2", HasBMI2)
1246 .Case("cldemote", HasCLDEMOTE)
1247 .Case("clflushopt", HasCLFLUSHOPT)
1248 .Case("clwb", HasCLWB)
1249 .Case("clzero", HasCLZERO)
1250 .Case("cmpccxadd", HasCMPCCXADD)
1251 .Case("crc32", HasCRC32)
1252 .Case("cx8", HasCX8)
1253 .Case("cx16", HasCX16)
1254 .Case("enqcmd", HasENQCMD)
1255 .Case("f16c", HasF16C)
1256 .Case("fma", HasFMA)
1257 .Case("fma4", XOPLevel >= FMA4)
1258 .Case("fsgsbase", HasFSGSBASE)
1259 .Case("fxsr", HasFXSR)
1260 .Case("gfni", HasGFNI)
1261 .Case("hreset", HasHRESET)
1262 .Case("invpcid", HasINVPCID)
1263 .Case("kl", HasKL)
1264 .Case("widekl", HasWIDEKL)
1265 .Case("lwp", HasLWP)
1266 .Case("lzcnt", HasLZCNT)
1267 .Case("mmx", HasMMX)
1268 .Case("movbe", HasMOVBE)
1269 .Case("movrs", HasMOVRS)
1270 .Case("movdiri", HasMOVDIRI)
1271 .Case("movdir64b", HasMOVDIR64B)
1272 .Case("mwaitx", HasMWAITX)
1273 .Case("pclmul", HasPCLMUL)
1274 .Case("pconfig", HasPCONFIG)
1275 .Case("pku", HasPKU)
1276 .Case("popcnt", HasPOPCNT)
1277 .Case("prefetchi", HasPREFETCHI)
1278 .Case("prfchw", HasPRFCHW)
1279 .Case("ptwrite", HasPTWRITE)
1280 .Case("raoint", HasRAOINT)
1281 .Case("rdpid", HasRDPID)
1282 .Case("rdpru", HasRDPRU)
1283 .Case("rdrnd", HasRDRND)
1284 .Case("rdseed", HasRDSEED)
1285 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1286 .Case("rtm", HasRTM)
1287 .Case("sahf", HasLAHFSAHF)
1288 .Case("serialize", HasSERIALIZE)
1289 .Case("sgx", HasSGX)
1290 .Case("sha", HasSHA)
1291 .Case("sha512", HasSHA512)
1292 .Case("shstk", HasSHSTK)
1293 .Case("sm3", HasSM3)
1294 .Case("sm4", HasSM4)
1295 .Case("sse", SSELevel >= SSE1)
1296 .Case("sse2", SSELevel >= SSE2)
1297 .Case("sse3", SSELevel >= SSE3)
1298 .Case("ssse3", SSELevel >= SSSE3)
1299 .Case("sse4.1", SSELevel >= SSE41)
1300 .Case("sse4.2", SSELevel >= SSE42)
1301 .Case("sse4a", XOPLevel >= SSE4A)
1302 .Case("tbm", HasTBM)
1303 .Case("tsxldtrk", HasTSXLDTRK)
1304 .Case("uintr", HasUINTR)
1305 .Case("usermsr", HasUSERMSR)
1306 .Case("vaes", HasVAES)
1307 .Case("vpclmulqdq", HasVPCLMULQDQ)
1308 .Case("wbnoinvd", HasWBNOINVD)
1309 .Case("waitpkg", HasWAITPKG)
1310 .Case("x86", true)
1311 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1312 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1313 .Case("x87", HasX87)
1314 .Case("xop", XOPLevel >= XOP)
1315 .Case("xsave", HasXSAVE)
1316 .Case("xsavec", HasXSAVEC)
1317 .Case("xsaves", HasXSAVES)
1318 .Case("xsaveopt", HasXSAVEOPT)
1319 .Case("fullbf16", HasFullBFloat16)
1320 .Case("egpr", HasEGPR)
1321 .Case("push2pop2", HasPush2Pop2)
1322 .Case("ppx", HasPPX)
1323 .Case("ndd", HasNDD)
1324 .Case("ccmp", HasCCMP)
1325 .Case("nf", HasNF)
1326 .Case("cf", HasCF)
1327 .Case("zu", HasZU)
1328 .Case("jmpabs", HasJMPABS)
1329 .Case("branch-hint", HasBranchHint)
1330 .Default(false);
1331}
1332
1333// We can't use a generic validation scheme for the features accepted here
1334// versus subtarget features accepted in the target attribute because the
1335// bitfield structure that's initialized in the runtime only supports the
1336// below currently rather than the full range of subtarget features. (See
1337// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1338bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1339 return llvm::StringSwitch<bool>(FeatureStr)
1340#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1341#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1342#include "llvm/TargetParser/X86TargetParser.def"
1343 .Default(false);
1344}
1345
1346static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1347 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1348#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1349 .Case(STR, llvm::X86::FEATURE_##ENUM)
1350
1351#include "llvm/TargetParser/X86TargetParser.def"
1352 ;
1353 // Note, this function should only be used after ensuring the value is
1354 // correct, so it asserts if the value is out of range.
1355}
1356
1357llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1358 auto getPriority = [](StringRef Feature) -> unsigned {
1359 // Valid CPUs have a 'key feature' that compares just better than its key
1360 // feature.
1361 using namespace llvm::X86;
1362 CPUKind Kind = parseArchX86(Feature);
1363 if (Kind != CK_None) {
1364 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1365 return (getFeaturePriority(KeyFeature) << 1) + 1;
1366 }
1367 // Now we know we have a feature, so get its priority and shift it a few so
1368 // that we have sufficient room for the CPUs (above).
1369 return getFeaturePriority(getFeature(Feature)) << 1;
1370 };
1371
1372 unsigned Priority = 0;
1373 for (StringRef Feature : Features)
1374 if (!Feature.empty())
1375 Priority = std::max(Priority, getPriority(Feature));
1376 return llvm::APInt(32, Priority);
1377}
1378
1379bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1380 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1381}
1382
1383char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1384 return llvm::X86::getCPUDispatchMangling(Name);
1385}
1386
1387void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1388 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1389 SmallVector<StringRef, 32> TargetCPUFeatures;
1390 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1391 for (auto &F : TargetCPUFeatures)
1392 Features.push_back(F);
1393}
1394
1395// We can't use a generic validation scheme for the cpus accepted here
1396// versus subtarget cpus accepted in the target attribute because the
1397// variables intitialized by the runtime only support the below currently
1398// rather than the full range of cpus.
1399bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1400 return llvm::StringSwitch<bool>(FeatureStr)
1401#define X86_VENDOR(ENUM, STRING, ABI_VALUE) .Case(STRING, true)
1402#define X86_CPU_TYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1403#define X86_CPU_SUBTYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1404#include "llvm/TargetParser/X86TargetParser.def"
1405 .Default(false);
1406}
1407
1408static unsigned matchAsmCCConstraint(const char *Name) {
1409 auto RV = llvm::StringSwitch<unsigned>(Name)
1410 .Case("@cca", 4)
1411 .Case("@ccae", 5)
1412 .Case("@ccb", 4)
1413 .Case("@ccbe", 5)
1414 .Case("@ccc", 4)
1415 .Case("@cce", 4)
1416 .Case("@ccz", 4)
1417 .Case("@ccg", 4)
1418 .Case("@ccge", 5)
1419 .Case("@ccl", 4)
1420 .Case("@ccle", 5)
1421 .Case("@ccna", 5)
1422 .Case("@ccnae", 6)
1423 .Case("@ccnb", 5)
1424 .Case("@ccnbe", 6)
1425 .Case("@ccnc", 5)
1426 .Case("@ccne", 5)
1427 .Case("@ccnz", 5)
1428 .Case("@ccng", 5)
1429 .Case("@ccnge", 6)
1430 .Case("@ccnl", 5)
1431 .Case("@ccnle", 6)
1432 .Case("@ccno", 5)
1433 .Case("@ccnp", 5)
1434 .Case("@ccns", 5)
1435 .Case("@cco", 4)
1436 .Case("@ccp", 4)
1437 .Case("@ccs", 4)
1438 .Default(0);
1439 return RV;
1440}
1441
1442bool X86TargetInfo::validateAsmConstraint(
1443 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1444 switch (*Name) {
1445 default:
1446 return false;
1447 // Constant constraints.
1448 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1449 // instructions.
1450 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1451 // x86_64 instructions.
1452 case 's':
1453 Info.setRequiresImmediate();
1454 return true;
1455 case 'I':
1456 Info.setRequiresImmediate(0, 31);
1457 return true;
1458 case 'J':
1459 Info.setRequiresImmediate(0, 63);
1460 return true;
1461 case 'K':
1462 Info.setRequiresImmediate(-128, 127);
1463 return true;
1464 case 'L':
1465 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1466 return true;
1467 case 'M':
1468 Info.setRequiresImmediate(0, 3);
1469 return true;
1470 case 'N':
1471 Info.setRequiresImmediate(0, 255);
1472 return true;
1473 case 'O':
1474 Info.setRequiresImmediate(0, 127);
1475 return true;
1476 case 'W':
1477 switch (*++Name) {
1478 default:
1479 return false;
1480 case 's':
1481 Info.setAllowsRegister();
1482 return true;
1483 }
1484 // Register constraints.
1485 case 'Y': // 'Y' is the first character for several 2-character constraints.
1486 // Shift the pointer to the second character of the constraint.
1487 Name++;
1488 switch (*Name) {
1489 default:
1490 return false;
1491 case 'z': // First SSE register.
1492 case '2':
1493 case 't': // Any SSE register, when SSE2 is enabled.
1494 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1495 case 'm': // Any MMX register, when inter-unit moves enabled.
1496 case 'k': // AVX512 arch mask registers: k1-k7.
1497 Info.setAllowsRegister();
1498 return true;
1499 }
1500 case 'f': // Any x87 floating point stack register.
1501 // Constraint 'f' cannot be used for output operands.
1502 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1503 return false;
1504 Info.setAllowsRegister();
1505 return true;
1506 case 'a': // eax.
1507 case 'b': // ebx.
1508 case 'c': // ecx.
1509 case 'd': // edx.
1510 case 'S': // esi.
1511 case 'D': // edi.
1512 case 'A': // edx:eax.
1513 case 't': // Top of floating point stack.
1514 case 'u': // Second from top of floating point stack.
1515 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1516 case 'y': // Any MMX register.
1517 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1518 case 'x': // Any SSE register.
1519 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1520 // for intermideate k reg operations).
1521 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1522 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1523 case 'l': // "Index" registers: any general register that can be used as an
1524 // index in a base+index memory access.
1525 Info.setAllowsRegister();
1526 return true;
1527 // Floating point constant constraints.
1528 case 'C': // SSE floating point constant.
1529 case 'G': // x87 floating point constant.
1530 return true;
1531 case 'j':
1532 Name++;
1533 switch (*Name) {
1534 default:
1535 return false;
1536 case 'r':
1537 Info.setAllowsRegister();
1538 return true;
1539 case 'R':
1540 Info.setAllowsRegister();
1541 return true;
1542 }
1543 case '@':
1544 // CC condition changes.
1545 if (auto Len = matchAsmCCConstraint(Name)) {
1546 Name += Len - 1;
1547 Info.setAllowsRegister();
1548 Info.setOutputOperandBounds(0, 2);
1549 return true;
1550 }
1551 return false;
1552 }
1553}
1554
1555// Below is based on the following information:
1556// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1557// | Processor Name | Cache Line Size (Bytes) | Source |
1558// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1559// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1560// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1561// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1562// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1563// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1564// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1565// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1566// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1567// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1568// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1569// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1570// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1571// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1572// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1573// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1574// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1575// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1576// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1577std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1578 using namespace llvm::X86;
1579 switch (CPU) {
1580 // i386
1581 case CK_i386:
1582 // i486
1583 case CK_i486:
1584 case CK_WinChipC6:
1585 case CK_WinChip2:
1586 case CK_C3:
1587 // Lakemont
1588 case CK_Lakemont:
1589 return 16;
1590
1591 // i586
1592 case CK_i586:
1593 case CK_Pentium:
1594 case CK_PentiumMMX:
1595 // i686
1596 case CK_PentiumPro:
1597 case CK_i686:
1598 case CK_Pentium2:
1599 case CK_Pentium3:
1600 case CK_PentiumM:
1601 case CK_C3_2:
1602 // K6
1603 case CK_K6:
1604 case CK_K6_2:
1605 case CK_K6_3:
1606 // Geode
1607 case CK_Geode:
1608 return 32;
1609
1610 // Netburst
1611 case CK_Pentium4:
1612 case CK_Prescott:
1613 case CK_Nocona:
1614 // Atom
1615 case CK_Bonnell:
1616 case CK_Silvermont:
1617 case CK_Goldmont:
1618 case CK_GoldmontPlus:
1619 case CK_Tremont:
1620 case CK_Gracemont:
1621
1622 case CK_Westmere:
1623 case CK_SandyBridge:
1624 case CK_IvyBridge:
1625 case CK_Haswell:
1626 case CK_Broadwell:
1627 case CK_SkylakeClient:
1628 case CK_SkylakeServer:
1629 case CK_Cascadelake:
1630 case CK_Nehalem:
1631 case CK_Cooperlake:
1632 case CK_Cannonlake:
1633 case CK_Tigerlake:
1634 case CK_SapphireRapids:
1635 case CK_IcelakeClient:
1636 case CK_Rocketlake:
1637 case CK_IcelakeServer:
1638 case CK_Alderlake:
1639 case CK_Raptorlake:
1640 case CK_Meteorlake:
1641 case CK_Arrowlake:
1642 case CK_ArrowlakeS:
1643 case CK_Lunarlake:
1644 case CK_Pantherlake:
1645 case CK_Wildcatlake:
1646 case CK_Novalake:
1647 case CK_Sierraforest:
1648 case CK_Grandridge:
1649 case CK_Graniterapids:
1650 case CK_GraniterapidsD:
1651 case CK_Emeraldrapids:
1652 case CK_Clearwaterforest:
1653 case CK_Diamondrapids:
1654 case CK_KNL:
1655 case CK_KNM:
1656 // K7
1657 case CK_Athlon:
1658 case CK_AthlonXP:
1659 // K8
1660 case CK_K8:
1661 case CK_K8SSE3:
1662 case CK_AMDFAM10:
1663 // Bobcat
1664 case CK_BTVER1:
1665 case CK_BTVER2:
1666 // Bulldozer
1667 case CK_BDVER1:
1668 case CK_BDVER2:
1669 case CK_BDVER3:
1670 case CK_BDVER4:
1671 // Zen
1672 case CK_ZNVER1:
1673 case CK_ZNVER2:
1674 case CK_ZNVER3:
1675 case CK_ZNVER4:
1676 case CK_ZNVER5:
1677 case CK_ZNVER6:
1678 // Hygon
1679 case CK_C86_4G_M4:
1680 case CK_C86_4G_M6:
1681 case CK_C86_4G_M7:
1682 case CK_C86_4G_M8:
1683 // Deprecated
1684 case CK_x86_64:
1685 case CK_x86_64_v2:
1686 case CK_x86_64_v3:
1687 case CK_x86_64_v4:
1688 case CK_Yonah:
1689 case CK_Penryn:
1690 case CK_Core2:
1691 return 64;
1692
1693 // The following currently have unknown cache line sizes (but they are probably all 64):
1694 // Core
1695 case CK_None:
1696 return std::nullopt;
1697 }
1698 llvm_unreachable("Unknown CPU kind");
1699}
1700
1701bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1702 StringRef Constraint,
1703 unsigned Size) const {
1704 // Strip off constraint modifiers.
1705 Constraint = Constraint.ltrim("=+&");
1706
1707 return validateOperandSize(FeatureMap, Constraint, Size);
1708}
1709
1710bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1711 StringRef Constraint,
1712 unsigned Size) const {
1713 return validateOperandSize(FeatureMap, Constraint, Size);
1714}
1715
1716bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1717 StringRef Constraint,
1718 unsigned Size) const {
1719 switch (Constraint[0]) {
1720 default:
1721 break;
1722 case 'k':
1723 // Registers k0-k7 (AVX512) size limit is 64 bit.
1724 case 'y':
1725 return Size <= 64;
1726 case 'f':
1727 case 't':
1728 case 'u':
1729 return Size <= 128;
1730 case 'Y':
1731 // 'Y' is the first character for several 2-character constraints.
1732 switch (Constraint[1]) {
1733 default:
1734 return false;
1735 case 'm':
1736 // 'Ym' is synonymous with 'y'.
1737 case 'k':
1738 return Size <= 64;
1739 case 'z':
1740 // XMM0/YMM/ZMM0
1741 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1742 // ZMM0 can be used if target supports AVX512F.
1743 return Size <= 512U;
1744 else if (hasFeatureEnabled(FeatureMap, "avx"))
1745 // YMM0 can be used if target supports AVX.
1746 return Size <= 256U;
1747 else if (hasFeatureEnabled(FeatureMap, "sse"))
1748 return Size <= 128U;
1749 return false;
1750 case 'i':
1751 case 't':
1752 case '2':
1753 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1754 if (SSELevel < SSE2)
1755 return false;
1756 break;
1757 }
1758 break;
1759 case 'v':
1760 case 'x':
1761 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1762 // 512-bit zmm registers can be used if target supports AVX512F.
1763 return Size <= 512U;
1764 else if (hasFeatureEnabled(FeatureMap, "avx"))
1765 // 256-bit ymm registers can be used if target supports AVX.
1766 return Size <= 256U;
1767 return Size <= 128U;
1768
1769 }
1770
1771 return true;
1772}
1773
1774std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1775 switch (*Constraint) {
1776 case '@':
1777 if (auto Len = matchAsmCCConstraint(Constraint)) {
1778 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1779 Constraint += Len - 1;
1780 return Converted;
1781 }
1782 return std::string(1, *Constraint);
1783 case 'a':
1784 return std::string("{ax}");
1785 case 'b':
1786 return std::string("{bx}");
1787 case 'c':
1788 return std::string("{cx}");
1789 case 'd':
1790 return std::string("{dx}");
1791 case 'S':
1792 return std::string("{si}");
1793 case 'D':
1794 return std::string("{di}");
1795 case 'p': // Keep 'p' constraint (address).
1796 return std::string("p");
1797 case 't': // top of floating point stack.
1798 return std::string("{st}");
1799 case 'u': // second from top of floating point stack.
1800 return std::string("{st(1)}"); // second from top of floating point stack.
1801 case 'W':
1802 assert(Constraint[1] == 's');
1803 return '^' + std::string(Constraint++, 2);
1804 case 'Y':
1805 switch (Constraint[1]) {
1806 default:
1807 // Break from inner switch and fall through (copy single char),
1808 // continue parsing after copying the current constraint into
1809 // the return string.
1810 break;
1811 case 'k':
1812 case 'm':
1813 case 'i':
1814 case 't':
1815 case 'z':
1816 case '2':
1817 // "^" hints llvm that this is a 2 letter constraint.
1818 // "Constraint++" is used to promote the string iterator
1819 // to the next constraint.
1820 return std::string("^") + std::string(Constraint++, 2);
1821 }
1822 [[fallthrough]];
1823 case 'j':
1824 switch (Constraint[1]) {
1825 default:
1826 // Break from inner switch and fall through (copy single char),
1827 // continue parsing after copying the current constraint into
1828 // the return string.
1829 break;
1830 case 'r':
1831 case 'R':
1832 // "^" hints llvm that this is a 2 letter constraint.
1833 // "Constraint++" is used to promote the string iterator
1834 // to the next constraint.
1835 return std::string("^") + std::string(Constraint++, 2);
1836 }
1837 [[fallthrough]];
1838 default:
1839 return std::string(1, *Constraint);
1840 }
1841}
1842
1843void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1844 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1845 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1846}
1847
1848void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1849 llvm::X86::fillValidTuneCPUList(Values);
1850}
1851
1855
1859
1860llvm::SmallVector<Builtin::InfosShard>
1861X86_32TargetInfo::getTargetBuiltins() const {
1862 return {
1863 {&X86::BuiltinStrings, X86::BuiltinInfos},
1864 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1865 };
1866}
1867
1868llvm::SmallVector<Builtin::InfosShard>
1869X86_64TargetInfo::getTargetBuiltins() const {
1870 return {
1871 {&X86::BuiltinStrings, X86::BuiltinInfos},
1872 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1873 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1874 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1875 "__builtin_ia32_"},
1876 };
1877}
1878
1879unsigned
1880MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1881 bool HasNonWeakDef) const {
1882 unsigned Align =
1883 WindowsX86_64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1884
1885 // Skip the MSVC size-based global-alignment increase under
1886 // -fclang-abi-compat<=22.
1887 if (!UseMSVCCompatGlobalAlign)
1888 return Align;
1889
1890 return std::max(Align, Microsoft64BitMinGlobalAlign(TypeSize));
1891}
1892
1893void MicrosoftX86_64TargetInfo::adjust(DiagnosticsEngine &Diags,
1894 LangOptions &Opts,
1895 const TargetInfo *Aux) {
1896 WindowsX86_64TargetInfo::adjust(Diags, Opts, Aux);
1897 // Under -fclang-abi-compat<=22, restore the prior x86_64-windows-msvc
1898 // behavior: apply the Sys V "large array" alignment increase and skip the
1899 // MSVC size-based global-alignment increase.
1900 if (Opts.isCompatibleWith(LangOptions::ClangABI::Ver22)) {
1901 UseMSVCCompatGlobalAlign = false;
1902 LargeArrayMinWidth = 128;
1903 LargeArrayAlign = 128;
1904 }
1905}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1594
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:235
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1346
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:39
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:61
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:234
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1581
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::LangOptions::isCompatibleWith
bool isCompatibleWith(ClangABI Version) const
Definition LangOptions.h:677
clang::TargetInfo
Exposes information about the current target.
Definition TargetInfo.h:227
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:330
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1320
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1447
clang::TargetInfo::adjust
virtual void adjust(DiagnosticsEngine &Diags, LangOptions &Opts, const TargetInfo *Aux)
Set forced language options.
Definition TargetInfo.cpp:422
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:763
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:569
clang::targets::MicrosoftX86_64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition X86.cpp:1880
clang::targets::MicrosoftX86_64TargetInfo::adjust
void adjust(DiagnosticsEngine &Diags, LangOptions &Opts, const TargetInfo *Aux) override
Set forced language options.
Definition X86.cpp:1893
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:241
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1577
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1442
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1357
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1852
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1383
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1774
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:516
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1387
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1399
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1701
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1716
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1848
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1379
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1338
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1086
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1208
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:222
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:160
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1843
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1856
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1710
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1861
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1869
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Microsoft64BitMinGlobalAlign
unsigned Microsoft64BitMinGlobalAlign(uint64_t TypeSize)
Definition TargetInfo.cpp:1126
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:80
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1231
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1195
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:144
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