clang 23.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 if (Features.lookup("egpr") && getTriple().isOSWindows()) {
168 setFeatureEnabled(Features, "push2pop2", false);
169 setFeatureEnabled(Features, "ppx", false);
170 }
171
172 std::vector<std::string> UpdatedFeaturesVec;
173 for (const auto &Feature : FeaturesVec) {
174 // Expand general-regs-only to -x86, -mmx and -sse
175 if (Feature == "+general-regs-only") {
176 UpdatedFeaturesVec.push_back("-x87");
177 UpdatedFeaturesVec.push_back("-mmx");
178 UpdatedFeaturesVec.push_back("-sse");
179 continue;
180 }
181
182 UpdatedFeaturesVec.push_back(Feature);
183 }
184
185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
186 return false;
187
188 // Can't do this earlier because we need to be able to explicitly enable
189 // or disable these features and the things that they depend upon.
190
191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
192 auto I = Features.find("sse4.2");
193 if (I != Features.end() && I->getValue() &&
194 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
195 Features["popcnt"] = true;
196
197 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
198 // then enable MMX.
199 I = Features.find("sse");
200 if (I != Features.end() && I->getValue() &&
201 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
202 Features["mmx"] = true;
203
204 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
205 I = Features.find("avx");
206 if (I != Features.end() && I->getValue() &&
207 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
208 Features["xsave"] = true;
209
210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
211 I = Features.find("sse4.2");
212 if (I != Features.end() && I->getValue() &&
213 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
214 Features["crc32"] = true;
215
216 return true;
217}
218
219void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
220 StringRef Name, bool Enabled) const {
221 if (Name == "sse4") {
222 // We can get here via the __target__ attribute since that's not controlled
223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
225 // disabled.
226 if (Enabled)
227 Name = "sse4.2";
228 else
229 Name = "sse4.1";
230 }
231
232 Features[Name] = Enabled;
233 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
234}
235
236/// handleTargetFeatures - Perform initialization based on the user
237/// configured set of features.
238bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
239 DiagnosticsEngine &Diags) {
240 for (const auto &Feature : Features) {
241 if (Feature[0] != '+')
242 continue;
243
244 if (Feature == "+mmx") {
245 HasMMX = true;
246 } else if (Feature == "+aes") {
247 HasAES = true;
248 } else if (Feature == "+vaes") {
249 HasVAES = true;
250 } else if (Feature == "+pclmul") {
251 HasPCLMUL = true;
252 } else if (Feature == "+vpclmulqdq") {
253 HasVPCLMULQDQ = true;
254 } else if (Feature == "+lzcnt") {
255 HasLZCNT = true;
256 } else if (Feature == "+rdrnd") {
257 HasRDRND = true;
258 } else if (Feature == "+fsgsbase") {
259 HasFSGSBASE = true;
260 } else if (Feature == "+bmi") {
261 HasBMI = true;
262 } else if (Feature == "+bmi2") {
263 HasBMI2 = true;
264 } else if (Feature == "+popcnt") {
265 HasPOPCNT = true;
266 } else if (Feature == "+rtm") {
267 HasRTM = true;
268 } else if (Feature == "+prfchw") {
269 HasPRFCHW = true;
270 } else if (Feature == "+rdseed") {
271 HasRDSEED = true;
272 } else if (Feature == "+adx") {
273 HasADX = true;
274 } else if (Feature == "+tbm") {
275 HasTBM = true;
276 } else if (Feature == "+lwp") {
277 HasLWP = true;
278 } else if (Feature == "+fma") {
279 HasFMA = true;
280 } else if (Feature == "+f16c") {
281 HasF16C = true;
282 } else if (Feature == "+gfni") {
283 HasGFNI = true;
284 } else if (Feature == "+avx10.1") {
285 HasAVX10_1 = true;
286 } else if (Feature == "+avx10.2") {
287 HasAVX10_2 = true;
288 HasFullBFloat16 = true;
289 } else if (Feature == "+avx512cd") {
290 HasAVX512CD = true;
291 } else if (Feature == "+avx512vpopcntdq") {
292 HasAVX512VPOPCNTDQ = true;
293 } else if (Feature == "+avx512vnni") {
294 HasAVX512VNNI = true;
295 } else if (Feature == "+avx512bf16") {
296 HasAVX512BF16 = true;
297 } else if (Feature == "+avx512fp16") {
298 HasAVX512FP16 = true;
299 HasFastHalfType = true;
300 } else if (Feature == "+avx512dq") {
301 HasAVX512DQ = true;
302 } else if (Feature == "+avx512bitalg") {
303 HasAVX512BITALG = true;
304 } else if (Feature == "+avx512bw") {
305 HasAVX512BW = true;
306 } else if (Feature == "+avx512vl") {
307 HasAVX512VL = true;
308 } else if (Feature == "+avx512vbmi") {
309 HasAVX512VBMI = true;
310 } else if (Feature == "+avx512vbmi2") {
311 HasAVX512VBMI2 = true;
312 } else if (Feature == "+avx512ifma") {
313 HasAVX512IFMA = true;
314 } else if (Feature == "+avx512vp2intersect") {
315 HasAVX512VP2INTERSECT = true;
316 } else if (Feature == "+sha") {
317 HasSHA = true;
318 } else if (Feature == "+sha512") {
319 HasSHA512 = true;
320 } else if (Feature == "+shstk") {
321 HasSHSTK = true;
322 } else if (Feature == "+sm3") {
323 HasSM3 = true;
324 } else if (Feature == "+sm4") {
325 HasSM4 = true;
326 } else if (Feature == "+movbe") {
327 HasMOVBE = true;
328 } else if (Feature == "+movrs") {
329 HasMOVRS = true;
330 } else if (Feature == "+sgx") {
331 HasSGX = true;
332 } else if (Feature == "+cx8") {
333 HasCX8 = true;
334 } else if (Feature == "+cx16") {
335 HasCX16 = true;
336 } else if (Feature == "+fxsr") {
337 HasFXSR = true;
338 } else if (Feature == "+xsave") {
339 HasXSAVE = true;
340 } else if (Feature == "+xsaveopt") {
341 HasXSAVEOPT = true;
342 } else if (Feature == "+xsavec") {
343 HasXSAVEC = true;
344 } else if (Feature == "+xsaves") {
345 HasXSAVES = true;
346 } else if (Feature == "+mwaitx") {
347 HasMWAITX = true;
348 } else if (Feature == "+pku") {
349 HasPKU = true;
350 } else if (Feature == "+clflushopt") {
351 HasCLFLUSHOPT = true;
352 } else if (Feature == "+clwb") {
353 HasCLWB = true;
354 } else if (Feature == "+wbnoinvd") {
355 HasWBNOINVD = true;
356 } else if (Feature == "+prefetchi") {
357 HasPREFETCHI = true;
358 } else if (Feature == "+clzero") {
359 HasCLZERO = true;
360 } else if (Feature == "+cldemote") {
361 HasCLDEMOTE = true;
362 } else if (Feature == "+rdpid") {
363 HasRDPID = true;
364 } else if (Feature == "+rdpru") {
365 HasRDPRU = true;
366 } else if (Feature == "+kl") {
367 HasKL = true;
368 } else if (Feature == "+widekl") {
369 HasWIDEKL = true;
370 } else if (Feature == "+retpoline-external-thunk") {
371 HasRetpolineExternalThunk = true;
372 } else if (Feature == "+sahf") {
373 HasLAHFSAHF = true;
374 } else if (Feature == "+waitpkg") {
375 HasWAITPKG = true;
376 } else if (Feature == "+movdiri") {
377 HasMOVDIRI = true;
378 } else if (Feature == "+movdir64b") {
379 HasMOVDIR64B = true;
380 } else if (Feature == "+pconfig") {
381 HasPCONFIG = true;
382 } else if (Feature == "+ptwrite") {
383 HasPTWRITE = true;
384 } else if (Feature == "+invpcid") {
385 HasINVPCID = true;
386 } else if (Feature == "+enqcmd") {
387 HasENQCMD = true;
388 } else if (Feature == "+hreset") {
389 HasHRESET = true;
390 } else if (Feature == "+amx-bf16") {
391 HasAMXBF16 = true;
392 } else if (Feature == "+amx-fp16") {
393 HasAMXFP16 = true;
394 } else if (Feature == "+amx-int8") {
395 HasAMXINT8 = true;
396 } else if (Feature == "+amx-tile") {
397 HasAMXTILE = true;
398 } else if (Feature == "+amx-complex") {
399 HasAMXCOMPLEX = true;
400 } else if (Feature == "+amx-fp8") {
401 HasAMXFP8 = true;
402 } else if (Feature == "+amx-movrs") {
403 HasAMXMOVRS = true;
404 } else if (Feature == "+amx-avx512") {
405 HasAMXAVX512 = true;
406 } else if (Feature == "+amx-tf32") {
407 HasAMXTF32 = true;
408 } else if (Feature == "+cmpccxadd") {
409 HasCMPCCXADD = true;
410 } else if (Feature == "+raoint") {
411 HasRAOINT = true;
412 } else if (Feature == "+avxifma") {
413 HasAVXIFMA = true;
414 } else if (Feature == "+avxneconvert") {
415 HasAVXNECONVERT= true;
416 } else if (Feature == "+avxvnni") {
417 HasAVXVNNI = true;
418 } else if (Feature == "+avxvnniint16") {
419 HasAVXVNNIINT16 = true;
420 } else if (Feature == "+avxvnniint8") {
421 HasAVXVNNIINT8 = true;
422 } else if (Feature == "+serialize") {
423 HasSERIALIZE = true;
424 } else if (Feature == "+tsxldtrk") {
425 HasTSXLDTRK = true;
426 } else if (Feature == "+uintr") {
427 HasUINTR = true;
428 } else if (Feature == "+usermsr") {
429 HasUSERMSR = true;
430 } else if (Feature == "+crc32") {
431 HasCRC32 = true;
432 } else if (Feature == "+x87") {
433 HasX87 = true;
434 } else if (Feature == "+fullbf16") {
435 HasFullBFloat16 = true;
436 } else if (Feature == "+egpr") {
437 HasEGPR = true;
438 } else if (Feature == "+inline-asm-use-gpr32") {
439 HasInlineAsmUseGPR32 = true;
440 } else if (Feature == "+push2pop2") {
441 HasPush2Pop2 = true;
442 } else if (Feature == "+ppx") {
443 HasPPX = true;
444 } else if (Feature == "+ndd") {
445 HasNDD = true;
446 } else if (Feature == "+ccmp") {
447 HasCCMP = true;
448 } else if (Feature == "+nf") {
449 HasNF = true;
450 } else if (Feature == "+cf") {
451 HasCF = true;
452 } else if (Feature == "+zu") {
453 HasZU = true;
454 } else if (Feature == "+jmpabs") {
455 HasJMPABS = true;
456 } else if (Feature == "+branch-hint") {
457 HasBranchHint = true;
458 }
459
460 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
461 .Case("+avx512f", AVX512F)
462 .Case("+avx2", AVX2)
463 .Case("+avx", AVX)
464 .Case("+sse4.2", SSE42)
465 .Case("+sse4.1", SSE41)
466 .Case("+ssse3", SSSE3)
467 .Case("+sse3", SSE3)
468 .Case("+sse2", SSE2)
469 .Case("+sse", SSE1)
470 .Default(NoSSE);
471 SSELevel = std::max(SSELevel, Level);
472
473 HasFloat16 = SSELevel >= SSE2;
474
475 // X86 target has bfloat16 emulation support in the backend, where
476 // bfloat16 is treated as a 32-bit float, arithmetic operations are
477 // performed in 32-bit, and the result is converted back to bfloat16.
478 // Truncation and extension between bfloat16 and 32-bit float are supported
479 // by the compiler-rt library. However, native bfloat16 support is currently
480 // not available in the X86 target. Hence, HasFullBFloat16 will be false
481 // until native bfloat16 support is available. HasFullBFloat16 is used to
482 // determine whether to automatically use excess floating point precision
483 // for bfloat16 arithmetic operations in the front-end.
484 HasBFloat16 = SSELevel >= SSE2;
485
486 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
487 .Case("+xop", XOP)
488 .Case("+fma4", FMA4)
489 .Case("+sse4a", SSE4A)
490 .Default(NoXOP);
491 XOPLevel = std::max(XOPLevel, XLevel);
492 }
493
494 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
495 // matches the selected sse level.
496 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
497 (FPMath == FP_387 && SSELevel >= SSE1)) {
498 Diags.Report(diag::err_target_unsupported_fpmath)
499 << (FPMath == FP_SSE ? "sse" : "387");
500 return false;
501 }
502
503 // FIXME: We should allow long double type on 32-bits to match with GCC.
504 // This requires backend to be able to lower f80 without x87 first.
505 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
506 HasLongDouble = false;
507
508 return true;
509}
510
511/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
512/// definitions for this particular subtarget.
513void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
514 MacroBuilder &Builder) const {
515 // Inline assembly supports X86 flag outputs.
516 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
517
518 std::string CodeModel = getTargetOpts().CodeModel;
519 if (CodeModel == "default")
520 CodeModel = "small";
521 Builder.defineMacro("__code_model_" + CodeModel + "__");
522
523 // Target identification.
524 if (getTriple().getArch() == llvm::Triple::x86_64) {
525 Builder.defineMacro("__amd64__");
526 Builder.defineMacro("__amd64");
527 Builder.defineMacro("__x86_64");
528 Builder.defineMacro("__x86_64__");
529 if (getTriple().getArchName() == "x86_64h") {
530 Builder.defineMacro("__x86_64h");
531 Builder.defineMacro("__x86_64h__");
532 }
533 } else {
534 DefineStd(Builder, "i386", Opts);
535 }
536
537 Builder.defineMacro("__SEG_GS");
538 Builder.defineMacro("__SEG_FS");
539 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
540 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
541
542 // Subtarget options.
543 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
544 // truly should be based on -mtune options.
545 using namespace llvm::X86;
546 switch (CPU) {
547 case CK_None:
548 break;
549 case CK_i386:
550 // The rest are coming from the i386 define above.
551 Builder.defineMacro("__tune_i386__");
552 break;
553 case CK_i486:
554 case CK_WinChipC6:
555 case CK_WinChip2:
556 case CK_C3:
557 defineCPUMacros(Builder, "i486");
558 break;
559 case CK_PentiumMMX:
560 Builder.defineMacro("__pentium_mmx__");
561 Builder.defineMacro("__tune_pentium_mmx__");
562 [[fallthrough]];
563 case CK_i586:
564 case CK_Pentium:
565 defineCPUMacros(Builder, "i586");
566 defineCPUMacros(Builder, "pentium");
567 break;
568 case CK_Pentium3:
569 case CK_PentiumM:
570 Builder.defineMacro("__tune_pentium3__");
571 [[fallthrough]];
572 case CK_Pentium2:
573 case CK_C3_2:
574 Builder.defineMacro("__tune_pentium2__");
575 [[fallthrough]];
576 case CK_PentiumPro:
577 case CK_i686:
578 defineCPUMacros(Builder, "i686");
579 defineCPUMacros(Builder, "pentiumpro");
580 break;
581 case CK_Pentium4:
582 defineCPUMacros(Builder, "pentium4");
583 break;
584 case CK_Yonah:
585 case CK_Prescott:
586 case CK_Nocona:
587 defineCPUMacros(Builder, "nocona");
588 break;
589 case CK_Core2:
590 case CK_Penryn:
591 defineCPUMacros(Builder, "core2");
592 break;
593 case CK_Bonnell:
594 defineCPUMacros(Builder, "atom");
595 break;
596 case CK_Silvermont:
597 defineCPUMacros(Builder, "slm");
598 break;
599 case CK_Goldmont:
600 defineCPUMacros(Builder, "goldmont");
601 break;
602 case CK_GoldmontPlus:
603 defineCPUMacros(Builder, "goldmont_plus");
604 break;
605 case CK_Tremont:
606 defineCPUMacros(Builder, "tremont");
607 break;
608 // Gracemont and later atom-cores use P-core cpu macros.
609 case CK_Gracemont:
610 case CK_Nehalem:
611 case CK_Westmere:
612 case CK_SandyBridge:
613 case CK_IvyBridge:
614 case CK_Haswell:
615 case CK_Broadwell:
616 case CK_SkylakeClient:
617 case CK_SkylakeServer:
618 case CK_Cascadelake:
619 case CK_Cooperlake:
620 case CK_Cannonlake:
621 case CK_IcelakeClient:
622 case CK_Rocketlake:
623 case CK_IcelakeServer:
624 case CK_Tigerlake:
625 case CK_SapphireRapids:
626 case CK_Alderlake:
627 case CK_Raptorlake:
628 case CK_Meteorlake:
629 case CK_Arrowlake:
630 case CK_ArrowlakeS:
631 case CK_Lunarlake:
632 case CK_Pantherlake:
633 case CK_Wildcatlake:
634 case CK_Novalake:
635 case CK_Sierraforest:
636 case CK_Grandridge:
637 case CK_Graniterapids:
638 case CK_GraniterapidsD:
639 case CK_Emeraldrapids:
640 case CK_Clearwaterforest:
641 case CK_Diamondrapids:
642 // FIXME: Historically, we defined this legacy name, it would be nice to
643 // remove it at some point. We've never exposed fine-grained names for
644 // recent primary x86 CPUs, and we should keep it that way.
645 defineCPUMacros(Builder, "corei7");
646 break;
647 case CK_KNL:
648 defineCPUMacros(Builder, "knl");
649 break;
650 case CK_KNM:
651 break;
652 case CK_Lakemont:
653 defineCPUMacros(Builder, "i586", /*Tuning*/false);
654 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
655 Builder.defineMacro("__tune_lakemont__");
656 break;
657 case CK_K6_2:
658 Builder.defineMacro("__k6_2__");
659 Builder.defineMacro("__tune_k6_2__");
660 [[fallthrough]];
661 case CK_K6_3:
662 if (CPU != CK_K6_2) { // In case of fallthrough
663 // FIXME: GCC may be enabling these in cases where some other k6
664 // architecture is specified but -m3dnow is explicitly provided. The
665 // exact semantics need to be determined and emulated here.
666 Builder.defineMacro("__k6_3__");
667 Builder.defineMacro("__tune_k6_3__");
668 }
669 [[fallthrough]];
670 case CK_K6:
671 defineCPUMacros(Builder, "k6");
672 break;
673 case CK_Athlon:
674 case CK_AthlonXP:
675 defineCPUMacros(Builder, "athlon");
676 if (SSELevel != NoSSE) {
677 Builder.defineMacro("__athlon_sse__");
678 Builder.defineMacro("__tune_athlon_sse__");
679 }
680 break;
681 case CK_K8:
682 case CK_K8SSE3:
683 case CK_x86_64:
684 defineCPUMacros(Builder, "k8");
685 break;
686 case CK_x86_64_v2:
687 case CK_x86_64_v3:
688 case CK_x86_64_v4:
689 break;
690 case CK_AMDFAM10:
691 defineCPUMacros(Builder, "amdfam10");
692 break;
693 case CK_BTVER1:
694 defineCPUMacros(Builder, "btver1");
695 break;
696 case CK_BTVER2:
697 defineCPUMacros(Builder, "btver2");
698 break;
699 case CK_BDVER1:
700 defineCPUMacros(Builder, "bdver1");
701 break;
702 case CK_BDVER2:
703 defineCPUMacros(Builder, "bdver2");
704 break;
705 case CK_BDVER3:
706 defineCPUMacros(Builder, "bdver3");
707 break;
708 case CK_BDVER4:
709 defineCPUMacros(Builder, "bdver4");
710 break;
711 case CK_ZNVER1:
712 defineCPUMacros(Builder, "znver1");
713 break;
714 case CK_ZNVER2:
715 defineCPUMacros(Builder, "znver2");
716 break;
717 case CK_ZNVER3:
718 defineCPUMacros(Builder, "znver3");
719 break;
720 case CK_ZNVER4:
721 defineCPUMacros(Builder, "znver4");
722 break;
723 case CK_ZNVER5:
724 defineCPUMacros(Builder, "znver5");
725 break;
726 case CK_ZNVER6:
727 defineCPUMacros(Builder, "znver6");
728 break;
729 case CK_Geode:
730 defineCPUMacros(Builder, "geode");
731 break;
732 case CK_C86_4G_M4:
733 defineCPUMacros(Builder, "c86_4g_m4");
734 break;
735 case CK_C86_4G_M6:
736 defineCPUMacros(Builder, "c86_4g_m6");
737 break;
738 case CK_C86_4G_M7:
739 defineCPUMacros(Builder, "c86_4g_m7");
740 break;
741 }
742
743 // Target properties.
744 Builder.defineMacro("__REGISTER_PREFIX__", "");
745
746 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
747 // functions in glibc header files that use FP Stack inline asm which the
748 // backend can't deal with (PR879).
749 Builder.defineMacro("__NO_MATH_INLINES");
750
751 if (HasAES)
752 Builder.defineMacro("__AES__");
753
754 if (HasVAES)
755 Builder.defineMacro("__VAES__");
756
757 if (HasPCLMUL)
758 Builder.defineMacro("__PCLMUL__");
759
760 if (HasVPCLMULQDQ)
761 Builder.defineMacro("__VPCLMULQDQ__");
762
763 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
764 // the feature flag only applies to 64-bit mode.
765 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
766 Builder.defineMacro("__LAHF_SAHF__");
767
768 if (HasLZCNT)
769 Builder.defineMacro("__LZCNT__");
770
771 if (HasRDRND)
772 Builder.defineMacro("__RDRND__");
773
774 if (HasFSGSBASE)
775 Builder.defineMacro("__FSGSBASE__");
776
777 if (HasBMI)
778 Builder.defineMacro("__BMI__");
779
780 if (HasBMI2)
781 Builder.defineMacro("__BMI2__");
782
783 if (HasPOPCNT)
784 Builder.defineMacro("__POPCNT__");
785
786 if (HasRTM)
787 Builder.defineMacro("__RTM__");
788
789 if (HasPRFCHW)
790 Builder.defineMacro("__PRFCHW__");
791
792 if (HasRDSEED)
793 Builder.defineMacro("__RDSEED__");
794
795 if (HasADX)
796 Builder.defineMacro("__ADX__");
797
798 if (HasTBM)
799 Builder.defineMacro("__TBM__");
800
801 if (HasLWP)
802 Builder.defineMacro("__LWP__");
803
804 if (HasMWAITX)
805 Builder.defineMacro("__MWAITX__");
806
807 if (HasMOVBE)
808 Builder.defineMacro("__MOVBE__");
809
810 switch (XOPLevel) {
811 case XOP:
812 Builder.defineMacro("__XOP__");
813 [[fallthrough]];
814 case FMA4:
815 Builder.defineMacro("__FMA4__");
816 [[fallthrough]];
817 case SSE4A:
818 Builder.defineMacro("__SSE4A__");
819 [[fallthrough]];
820 case NoXOP:
821 break;
822 }
823
824 if (HasFMA)
825 Builder.defineMacro("__FMA__");
826
827 if (HasF16C)
828 Builder.defineMacro("__F16C__");
829
830 if (HasGFNI)
831 Builder.defineMacro("__GFNI__");
832
833 if (HasAVX10_1) {
834 Builder.defineMacro("__AVX10_1__");
835 Builder.defineMacro("__AVX10_1_512__");
836 }
837 if (HasAVX10_2) {
838 Builder.defineMacro("__AVX10_2__");
839 Builder.defineMacro("__AVX10_2_512__");
840 }
841 if (HasAVX512CD)
842 Builder.defineMacro("__AVX512CD__");
843 if (HasAVX512VPOPCNTDQ)
844 Builder.defineMacro("__AVX512VPOPCNTDQ__");
845 if (HasAVX512VNNI)
846 Builder.defineMacro("__AVX512VNNI__");
847 if (HasAVX512BF16)
848 Builder.defineMacro("__AVX512BF16__");
849 if (HasAVX512FP16)
850 Builder.defineMacro("__AVX512FP16__");
851 if (HasAVX512DQ)
852 Builder.defineMacro("__AVX512DQ__");
853 if (HasAVX512BITALG)
854 Builder.defineMacro("__AVX512BITALG__");
855 if (HasAVX512BW)
856 Builder.defineMacro("__AVX512BW__");
857 if (HasAVX512VL) {
858 Builder.defineMacro("__AVX512VL__");
859 }
860 if (HasAVX512VBMI)
861 Builder.defineMacro("__AVX512VBMI__");
862 if (HasAVX512VBMI2)
863 Builder.defineMacro("__AVX512VBMI2__");
864 if (HasAVX512IFMA)
865 Builder.defineMacro("__AVX512IFMA__");
866 if (HasAVX512VP2INTERSECT)
867 Builder.defineMacro("__AVX512VP2INTERSECT__");
868 if (HasSHA)
869 Builder.defineMacro("__SHA__");
870 if (HasSHA512)
871 Builder.defineMacro("__SHA512__");
872
873 if (HasFXSR)
874 Builder.defineMacro("__FXSR__");
875 if (HasXSAVE)
876 Builder.defineMacro("__XSAVE__");
877 if (HasXSAVEOPT)
878 Builder.defineMacro("__XSAVEOPT__");
879 if (HasXSAVEC)
880 Builder.defineMacro("__XSAVEC__");
881 if (HasXSAVES)
882 Builder.defineMacro("__XSAVES__");
883 if (HasPKU)
884 Builder.defineMacro("__PKU__");
885 if (HasCLFLUSHOPT)
886 Builder.defineMacro("__CLFLUSHOPT__");
887 if (HasCLWB)
888 Builder.defineMacro("__CLWB__");
889 if (HasWBNOINVD)
890 Builder.defineMacro("__WBNOINVD__");
891 if (HasSHSTK)
892 Builder.defineMacro("__SHSTK__");
893 if (HasSGX)
894 Builder.defineMacro("__SGX__");
895 if (HasSM3)
896 Builder.defineMacro("__SM3__");
897 if (HasSM4)
898 Builder.defineMacro("__SM4__");
899 if (HasPREFETCHI)
900 Builder.defineMacro("__PREFETCHI__");
901 if (HasCLZERO)
902 Builder.defineMacro("__CLZERO__");
903 if (HasKL)
904 Builder.defineMacro("__KL__");
905 if (HasWIDEKL)
906 Builder.defineMacro("__WIDEKL__");
907 if (HasRDPID)
908 Builder.defineMacro("__RDPID__");
909 if (HasRDPRU)
910 Builder.defineMacro("__RDPRU__");
911 if (HasCLDEMOTE)
912 Builder.defineMacro("__CLDEMOTE__");
913 if (HasWAITPKG)
914 Builder.defineMacro("__WAITPKG__");
915 if (HasMOVDIRI)
916 Builder.defineMacro("__MOVDIRI__");
917 if (HasMOVDIR64B)
918 Builder.defineMacro("__MOVDIR64B__");
919 if (HasMOVRS)
920 Builder.defineMacro("__MOVRS__");
921 if (HasPCONFIG)
922 Builder.defineMacro("__PCONFIG__");
923 if (HasPTWRITE)
924 Builder.defineMacro("__PTWRITE__");
925 if (HasINVPCID)
926 Builder.defineMacro("__INVPCID__");
927 if (HasENQCMD)
928 Builder.defineMacro("__ENQCMD__");
929 if (HasHRESET)
930 Builder.defineMacro("__HRESET__");
931 if (HasAMXTILE)
932 Builder.defineMacro("__AMX_TILE__");
933 if (HasAMXINT8)
934 Builder.defineMacro("__AMX_INT8__");
935 if (HasAMXBF16)
936 Builder.defineMacro("__AMX_BF16__");
937 if (HasAMXFP16)
938 Builder.defineMacro("__AMX_FP16__");
939 if (HasAMXCOMPLEX)
940 Builder.defineMacro("__AMX_COMPLEX__");
941 if (HasAMXFP8)
942 Builder.defineMacro("__AMX_FP8__");
943 if (HasAMXMOVRS)
944 Builder.defineMacro("__AMX_MOVRS__");
945 if (HasAMXAVX512)
946 Builder.defineMacro("__AMX_AVX512__");
947 if (HasAMXTF32)
948 Builder.defineMacro("__AMX_TF32__");
949 if (HasCMPCCXADD)
950 Builder.defineMacro("__CMPCCXADD__");
951 if (HasRAOINT)
952 Builder.defineMacro("__RAOINT__");
953 if (HasAVXIFMA)
954 Builder.defineMacro("__AVXIFMA__");
955 if (HasAVXNECONVERT)
956 Builder.defineMacro("__AVXNECONVERT__");
957 if (HasAVXVNNI)
958 Builder.defineMacro("__AVXVNNI__");
959 if (HasAVXVNNIINT16)
960 Builder.defineMacro("__AVXVNNIINT16__");
961 if (HasAVXVNNIINT8)
962 Builder.defineMacro("__AVXVNNIINT8__");
963 if (HasSERIALIZE)
964 Builder.defineMacro("__SERIALIZE__");
965 if (HasTSXLDTRK)
966 Builder.defineMacro("__TSXLDTRK__");
967 if (HasUINTR)
968 Builder.defineMacro("__UINTR__");
969 if (HasUSERMSR)
970 Builder.defineMacro("__USERMSR__");
971 if (HasCRC32)
972 Builder.defineMacro("__CRC32__");
973 if (HasEGPR)
974 Builder.defineMacro("__EGPR__");
975 if (HasPush2Pop2)
976 Builder.defineMacro("__PUSH2POP2__");
977 if (HasPPX)
978 Builder.defineMacro("__PPX__");
979 if (HasNDD)
980 Builder.defineMacro("__NDD__");
981 if (HasCCMP)
982 Builder.defineMacro("__CCMP__");
983 if (HasNF)
984 Builder.defineMacro("__NF__");
985 if (HasCF)
986 Builder.defineMacro("__CF__");
987 if (HasZU)
988 Builder.defineMacro("__ZU__");
989 if (HasJMPABS)
990 Builder.defineMacro("__JMPABS__");
991 if (HasEGPR && HasNDD && HasCCMP && HasNF && HasZU && HasJMPABS)
992 if (getTriple().isOSWindows() || (HasPush2Pop2 && HasPPX))
993 Builder.defineMacro("__APX_F__");
994 if (HasEGPR && HasInlineAsmUseGPR32)
995 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
996
997 // Each case falls through to the previous one here.
998 switch (SSELevel) {
999 case AVX512F:
1000 Builder.defineMacro("__AVX512F__");
1001 [[fallthrough]];
1002 case AVX2:
1003 Builder.defineMacro("__AVX2__");
1004 [[fallthrough]];
1005 case AVX:
1006 Builder.defineMacro("__AVX__");
1007 [[fallthrough]];
1008 case SSE42:
1009 Builder.defineMacro("__SSE4_2__");
1010 [[fallthrough]];
1011 case SSE41:
1012 Builder.defineMacro("__SSE4_1__");
1013 [[fallthrough]];
1014 case SSSE3:
1015 Builder.defineMacro("__SSSE3__");
1016 [[fallthrough]];
1017 case SSE3:
1018 Builder.defineMacro("__SSE3__");
1019 [[fallthrough]];
1020 case SSE2:
1021 Builder.defineMacro("__SSE2__");
1022 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1023 [[fallthrough]];
1024 case SSE1:
1025 Builder.defineMacro("__SSE__");
1026 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1027 [[fallthrough]];
1028 case NoSSE:
1029 break;
1030 }
1031
1032 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1033 switch (SSELevel) {
1034 case AVX512F:
1035 case AVX2:
1036 case AVX:
1037 case SSE42:
1038 case SSE41:
1039 case SSSE3:
1040 case SSE3:
1041 case SSE2:
1042 Builder.defineMacro("_M_IX86_FP", Twine(2));
1043 break;
1044 case SSE1:
1045 Builder.defineMacro("_M_IX86_FP", Twine(1));
1046 break;
1047 default:
1048 Builder.defineMacro("_M_IX86_FP", Twine(0));
1049 break;
1050 }
1051 }
1052
1053 // Each case falls through to the previous one here.
1054 if (HasMMX) {
1055 Builder.defineMacro("__MMX__");
1056 }
1057
1058 if (CPU >= CK_i486 || CPU == CK_None) {
1059 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1060 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1061 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1062 }
1063 if (HasCX8)
1064 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1065 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1066 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1067
1068 if (HasFloat128)
1069 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1070
1071 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1072 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1073 Opts.CFProtectionBranch});
1074}
1075
1076bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1077 return llvm::StringSwitch<bool>(Name)
1078 .Case("adx", true)
1079 .Case("aes", true)
1080 .Case("amx-avx512", true)
1081 .Case("amx-bf16", true)
1082 .Case("amx-complex", true)
1083 .Case("amx-fp16", true)
1084 .Case("amx-fp8", true)
1085 .Case("amx-int8", true)
1086 .Case("amx-movrs", true)
1087 .Case("amx-tf32", true)
1088 .Case("amx-tile", true)
1089 .Case("avx", true)
1090 .Case("avx10.1", true)
1091 .Case("avx10.2", true)
1092 .Case("avx2", true)
1093 .Case("avx512f", true)
1094 .Case("avx512cd", true)
1095 .Case("avx512vpopcntdq", true)
1096 .Case("avx512vnni", true)
1097 .Case("avx512bf16", true)
1098 .Case("avx512fp16", true)
1099 .Case("avx512dq", true)
1100 .Case("avx512bitalg", true)
1101 .Case("avx512bw", true)
1102 .Case("avx512vl", true)
1103 .Case("avx512vbmi", true)
1104 .Case("avx512vbmi2", true)
1105 .Case("avx512ifma", true)
1106 .Case("avx512vp2intersect", true)
1107 .Case("avxifma", true)
1108 .Case("avxneconvert", true)
1109 .Case("avxvnni", true)
1110 .Case("avxvnniint16", true)
1111 .Case("avxvnniint8", true)
1112 .Case("bmi", true)
1113 .Case("bmi2", true)
1114 .Case("cldemote", true)
1115 .Case("clflushopt", true)
1116 .Case("clwb", true)
1117 .Case("clzero", true)
1118 .Case("cmpccxadd", true)
1119 .Case("crc32", true)
1120 .Case("cx16", true)
1121 .Case("enqcmd", true)
1122 .Case("f16c", true)
1123 .Case("fma", true)
1124 .Case("fma4", true)
1125 .Case("fsgsbase", true)
1126 .Case("fxsr", true)
1127 .Case("general-regs-only", true)
1128 .Case("gfni", true)
1129 .Case("hreset", true)
1130 .Case("invpcid", true)
1131 .Case("kl", true)
1132 .Case("widekl", true)
1133 .Case("lwp", true)
1134 .Case("lzcnt", true)
1135 .Case("mmx", true)
1136 .Case("movbe", true)
1137 .Case("movrs", true)
1138 .Case("movdiri", true)
1139 .Case("movdir64b", true)
1140 .Case("mwaitx", true)
1141 .Case("pclmul", true)
1142 .Case("pconfig", true)
1143 .Case("pku", true)
1144 .Case("popcnt", true)
1145 .Case("prefer-256-bit", true)
1146 .Case("prefetchi", true)
1147 .Case("prfchw", true)
1148 .Case("ptwrite", true)
1149 .Case("raoint", true)
1150 .Case("rdpid", true)
1151 .Case("rdpru", true)
1152 .Case("rdrnd", true)
1153 .Case("rdseed", true)
1154 .Case("rtm", true)
1155 .Case("sahf", true)
1156 .Case("serialize", true)
1157 .Case("sgx", true)
1158 .Case("sha", true)
1159 .Case("sha512", true)
1160 .Case("shstk", true)
1161 .Case("sm3", true)
1162 .Case("sm4", true)
1163 .Case("sse", true)
1164 .Case("sse2", true)
1165 .Case("sse3", true)
1166 .Case("ssse3", true)
1167 .Case("sse4", true)
1168 .Case("sse4.1", true)
1169 .Case("sse4.2", true)
1170 .Case("sse4a", true)
1171 .Case("tbm", true)
1172 .Case("tsxldtrk", true)
1173 .Case("uintr", true)
1174 .Case("usermsr", true)
1175 .Case("vaes", true)
1176 .Case("vpclmulqdq", true)
1177 .Case("wbnoinvd", true)
1178 .Case("waitpkg", true)
1179 .Case("x87", true)
1180 .Case("xop", true)
1181 .Case("xsave", true)
1182 .Case("xsavec", true)
1183 .Case("xsaves", true)
1184 .Case("xsaveopt", true)
1185 .Case("egpr", true)
1186 .Case("push2pop2", true)
1187 .Case("ppx", true)
1188 .Case("ndd", true)
1189 .Case("ccmp", true)
1190 .Case("nf", true)
1191 .Case("cf", true)
1192 .Case("zu", true)
1193 .Case("jmpabs", true)
1194 .Default(false);
1195}
1196
1197bool X86TargetInfo::hasFeature(StringRef Feature) const {
1198 return llvm::StringSwitch<bool>(Feature)
1199 .Case("adx", HasADX)
1200 .Case("aes", HasAES)
1201 .Case("amx-avx512", HasAMXAVX512)
1202 .Case("amx-bf16", HasAMXBF16)
1203 .Case("amx-complex", HasAMXCOMPLEX)
1204 .Case("amx-fp16", HasAMXFP16)
1205 .Case("amx-fp8", HasAMXFP8)
1206 .Case("amx-int8", HasAMXINT8)
1207 .Case("amx-movrs", HasAMXMOVRS)
1208 .Case("amx-tf32", HasAMXTF32)
1209 .Case("amx-tile", HasAMXTILE)
1210 .Case("avx", SSELevel >= AVX)
1211 .Case("avx10.1", HasAVX10_1)
1212 .Case("avx10.2", HasAVX10_2)
1213 .Case("avx2", SSELevel >= AVX2)
1214 .Case("avx512f", SSELevel >= AVX512F)
1215 .Case("avx512cd", HasAVX512CD)
1216 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1217 .Case("avx512vnni", HasAVX512VNNI)
1218 .Case("avx512bf16", HasAVX512BF16)
1219 .Case("avx512fp16", HasAVX512FP16)
1220 .Case("avx512dq", HasAVX512DQ)
1221 .Case("avx512bitalg", HasAVX512BITALG)
1222 .Case("avx512bw", HasAVX512BW)
1223 .Case("avx512vl", HasAVX512VL)
1224 .Case("avx512vbmi", HasAVX512VBMI)
1225 .Case("avx512vbmi2", HasAVX512VBMI2)
1226 .Case("avx512ifma", HasAVX512IFMA)
1227 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1228 .Case("avxifma", HasAVXIFMA)
1229 .Case("avxneconvert", HasAVXNECONVERT)
1230 .Case("avxvnni", HasAVXVNNI)
1231 .Case("avxvnniint16", HasAVXVNNIINT16)
1232 .Case("avxvnniint8", HasAVXVNNIINT8)
1233 .Case("bmi", HasBMI)
1234 .Case("bmi2", HasBMI2)
1235 .Case("cldemote", HasCLDEMOTE)
1236 .Case("clflushopt", HasCLFLUSHOPT)
1237 .Case("clwb", HasCLWB)
1238 .Case("clzero", HasCLZERO)
1239 .Case("cmpccxadd", HasCMPCCXADD)
1240 .Case("crc32", HasCRC32)
1241 .Case("cx8", HasCX8)
1242 .Case("cx16", HasCX16)
1243 .Case("enqcmd", HasENQCMD)
1244 .Case("f16c", HasF16C)
1245 .Case("fma", HasFMA)
1246 .Case("fma4", XOPLevel >= FMA4)
1247 .Case("fsgsbase", HasFSGSBASE)
1248 .Case("fxsr", HasFXSR)
1249 .Case("gfni", HasGFNI)
1250 .Case("hreset", HasHRESET)
1251 .Case("invpcid", HasINVPCID)
1252 .Case("kl", HasKL)
1253 .Case("widekl", HasWIDEKL)
1254 .Case("lwp", HasLWP)
1255 .Case("lzcnt", HasLZCNT)
1256 .Case("mmx", HasMMX)
1257 .Case("movbe", HasMOVBE)
1258 .Case("movrs", HasMOVRS)
1259 .Case("movdiri", HasMOVDIRI)
1260 .Case("movdir64b", HasMOVDIR64B)
1261 .Case("mwaitx", HasMWAITX)
1262 .Case("pclmul", HasPCLMUL)
1263 .Case("pconfig", HasPCONFIG)
1264 .Case("pku", HasPKU)
1265 .Case("popcnt", HasPOPCNT)
1266 .Case("prefetchi", HasPREFETCHI)
1267 .Case("prfchw", HasPRFCHW)
1268 .Case("ptwrite", HasPTWRITE)
1269 .Case("raoint", HasRAOINT)
1270 .Case("rdpid", HasRDPID)
1271 .Case("rdpru", HasRDPRU)
1272 .Case("rdrnd", HasRDRND)
1273 .Case("rdseed", HasRDSEED)
1274 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1275 .Case("rtm", HasRTM)
1276 .Case("sahf", HasLAHFSAHF)
1277 .Case("serialize", HasSERIALIZE)
1278 .Case("sgx", HasSGX)
1279 .Case("sha", HasSHA)
1280 .Case("sha512", HasSHA512)
1281 .Case("shstk", HasSHSTK)
1282 .Case("sm3", HasSM3)
1283 .Case("sm4", HasSM4)
1284 .Case("sse", SSELevel >= SSE1)
1285 .Case("sse2", SSELevel >= SSE2)
1286 .Case("sse3", SSELevel >= SSE3)
1287 .Case("ssse3", SSELevel >= SSSE3)
1288 .Case("sse4.1", SSELevel >= SSE41)
1289 .Case("sse4.2", SSELevel >= SSE42)
1290 .Case("sse4a", XOPLevel >= SSE4A)
1291 .Case("tbm", HasTBM)
1292 .Case("tsxldtrk", HasTSXLDTRK)
1293 .Case("uintr", HasUINTR)
1294 .Case("usermsr", HasUSERMSR)
1295 .Case("vaes", HasVAES)
1296 .Case("vpclmulqdq", HasVPCLMULQDQ)
1297 .Case("wbnoinvd", HasWBNOINVD)
1298 .Case("waitpkg", HasWAITPKG)
1299 .Case("x86", true)
1300 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1301 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1302 .Case("x87", HasX87)
1303 .Case("xop", XOPLevel >= XOP)
1304 .Case("xsave", HasXSAVE)
1305 .Case("xsavec", HasXSAVEC)
1306 .Case("xsaves", HasXSAVES)
1307 .Case("xsaveopt", HasXSAVEOPT)
1308 .Case("fullbf16", HasFullBFloat16)
1309 .Case("egpr", HasEGPR)
1310 .Case("push2pop2", HasPush2Pop2)
1311 .Case("ppx", HasPPX)
1312 .Case("ndd", HasNDD)
1313 .Case("ccmp", HasCCMP)
1314 .Case("nf", HasNF)
1315 .Case("cf", HasCF)
1316 .Case("zu", HasZU)
1317 .Case("jmpabs", HasJMPABS)
1318 .Case("branch-hint", HasBranchHint)
1319 .Default(false);
1320}
1321
1322// We can't use a generic validation scheme for the features accepted here
1323// versus subtarget features accepted in the target attribute because the
1324// bitfield structure that's initialized in the runtime only supports the
1325// below currently rather than the full range of subtarget features. (See
1326// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1327bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1328 return llvm::StringSwitch<bool>(FeatureStr)
1329#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1330#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1331#include "llvm/TargetParser/X86TargetParser.def"
1332 .Default(false);
1333}
1334
1335static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1336 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1337#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1338 .Case(STR, llvm::X86::FEATURE_##ENUM)
1339
1340#include "llvm/TargetParser/X86TargetParser.def"
1341 ;
1342 // Note, this function should only be used after ensuring the value is
1343 // correct, so it asserts if the value is out of range.
1344}
1345
1346llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1347 auto getPriority = [](StringRef Feature) -> unsigned {
1348 // Valid CPUs have a 'key feature' that compares just better than its key
1349 // feature.
1350 using namespace llvm::X86;
1351 CPUKind Kind = parseArchX86(Feature);
1352 if (Kind != CK_None) {
1353 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1354 return (getFeaturePriority(KeyFeature) << 1) + 1;
1355 }
1356 // Now we know we have a feature, so get its priority and shift it a few so
1357 // that we have sufficient room for the CPUs (above).
1358 return getFeaturePriority(getFeature(Feature)) << 1;
1359 };
1360
1361 unsigned Priority = 0;
1362 for (StringRef Feature : Features)
1363 if (!Feature.empty())
1364 Priority = std::max(Priority, getPriority(Feature));
1365 return llvm::APInt(32, Priority);
1366}
1367
1368bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1369 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1370}
1371
1372char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1373 return llvm::X86::getCPUDispatchMangling(Name);
1374}
1375
1376void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1377 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1378 SmallVector<StringRef, 32> TargetCPUFeatures;
1379 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1380 for (auto &F : TargetCPUFeatures)
1381 Features.push_back(F);
1382}
1383
1384// We can't use a generic validation scheme for the cpus accepted here
1385// versus subtarget cpus accepted in the target attribute because the
1386// variables intitialized by the runtime only support the below currently
1387// rather than the full range of cpus.
1388bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1389 return llvm::StringSwitch<bool>(FeatureStr)
1390#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1391#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1392#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1393#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1394#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1395#include "llvm/TargetParser/X86TargetParser.def"
1396 .Default(false);
1397}
1398
1399static unsigned matchAsmCCConstraint(const char *Name) {
1400 auto RV = llvm::StringSwitch<unsigned>(Name)
1401 .Case("@cca", 4)
1402 .Case("@ccae", 5)
1403 .Case("@ccb", 4)
1404 .Case("@ccbe", 5)
1405 .Case("@ccc", 4)
1406 .Case("@cce", 4)
1407 .Case("@ccz", 4)
1408 .Case("@ccg", 4)
1409 .Case("@ccge", 5)
1410 .Case("@ccl", 4)
1411 .Case("@ccle", 5)
1412 .Case("@ccna", 5)
1413 .Case("@ccnae", 6)
1414 .Case("@ccnb", 5)
1415 .Case("@ccnbe", 6)
1416 .Case("@ccnc", 5)
1417 .Case("@ccne", 5)
1418 .Case("@ccnz", 5)
1419 .Case("@ccng", 5)
1420 .Case("@ccnge", 6)
1421 .Case("@ccnl", 5)
1422 .Case("@ccnle", 6)
1423 .Case("@ccno", 5)
1424 .Case("@ccnp", 5)
1425 .Case("@ccns", 5)
1426 .Case("@cco", 4)
1427 .Case("@ccp", 4)
1428 .Case("@ccs", 4)
1429 .Default(0);
1430 return RV;
1431}
1432
1433bool X86TargetInfo::validateAsmConstraint(
1434 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1435 switch (*Name) {
1436 default:
1437 return false;
1438 // Constant constraints.
1439 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1440 // instructions.
1441 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1442 // x86_64 instructions.
1443 case 's':
1444 Info.setRequiresImmediate();
1445 return true;
1446 case 'I':
1447 Info.setRequiresImmediate(0, 31);
1448 return true;
1449 case 'J':
1450 Info.setRequiresImmediate(0, 63);
1451 return true;
1452 case 'K':
1453 Info.setRequiresImmediate(-128, 127);
1454 return true;
1455 case 'L':
1456 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1457 return true;
1458 case 'M':
1459 Info.setRequiresImmediate(0, 3);
1460 return true;
1461 case 'N':
1462 Info.setRequiresImmediate(0, 255);
1463 return true;
1464 case 'O':
1465 Info.setRequiresImmediate(0, 127);
1466 return true;
1467 case 'W':
1468 switch (*++Name) {
1469 default:
1470 return false;
1471 case 's':
1472 Info.setAllowsRegister();
1473 return true;
1474 }
1475 // Register constraints.
1476 case 'Y': // 'Y' is the first character for several 2-character constraints.
1477 // Shift the pointer to the second character of the constraint.
1478 Name++;
1479 switch (*Name) {
1480 default:
1481 return false;
1482 case 'z': // First SSE register.
1483 case '2':
1484 case 't': // Any SSE register, when SSE2 is enabled.
1485 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1486 case 'm': // Any MMX register, when inter-unit moves enabled.
1487 case 'k': // AVX512 arch mask registers: k1-k7.
1488 Info.setAllowsRegister();
1489 return true;
1490 }
1491 case 'f': // Any x87 floating point stack register.
1492 // Constraint 'f' cannot be used for output operands.
1493 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1494 return false;
1495 Info.setAllowsRegister();
1496 return true;
1497 case 'a': // eax.
1498 case 'b': // ebx.
1499 case 'c': // ecx.
1500 case 'd': // edx.
1501 case 'S': // esi.
1502 case 'D': // edi.
1503 case 'A': // edx:eax.
1504 case 't': // Top of floating point stack.
1505 case 'u': // Second from top of floating point stack.
1506 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1507 case 'y': // Any MMX register.
1508 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1509 case 'x': // Any SSE register.
1510 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1511 // for intermideate k reg operations).
1512 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1513 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1514 case 'l': // "Index" registers: any general register that can be used as an
1515 // index in a base+index memory access.
1516 Info.setAllowsRegister();
1517 return true;
1518 // Floating point constant constraints.
1519 case 'C': // SSE floating point constant.
1520 case 'G': // x87 floating point constant.
1521 return true;
1522 case 'j':
1523 Name++;
1524 switch (*Name) {
1525 default:
1526 return false;
1527 case 'r':
1528 Info.setAllowsRegister();
1529 return true;
1530 case 'R':
1531 Info.setAllowsRegister();
1532 return true;
1533 }
1534 case '@':
1535 // CC condition changes.
1536 if (auto Len = matchAsmCCConstraint(Name)) {
1537 Name += Len - 1;
1538 Info.setAllowsRegister();
1539 Info.setOutputOperandBounds(0, 2);
1540 return true;
1541 }
1542 return false;
1543 }
1544}
1545
1546// Below is based on the following information:
1547// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1548// | Processor Name | Cache Line Size (Bytes) | Source |
1549// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1550// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1551// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1552// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1553// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1554// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1555// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1556// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1557// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1558// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1559// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1560// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1561// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1562// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1563// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1564// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1565// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1566// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1567// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1568std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1569 using namespace llvm::X86;
1570 switch (CPU) {
1571 // i386
1572 case CK_i386:
1573 // i486
1574 case CK_i486:
1575 case CK_WinChipC6:
1576 case CK_WinChip2:
1577 case CK_C3:
1578 // Lakemont
1579 case CK_Lakemont:
1580 return 16;
1581
1582 // i586
1583 case CK_i586:
1584 case CK_Pentium:
1585 case CK_PentiumMMX:
1586 // i686
1587 case CK_PentiumPro:
1588 case CK_i686:
1589 case CK_Pentium2:
1590 case CK_Pentium3:
1591 case CK_PentiumM:
1592 case CK_C3_2:
1593 // K6
1594 case CK_K6:
1595 case CK_K6_2:
1596 case CK_K6_3:
1597 // Geode
1598 case CK_Geode:
1599 return 32;
1600
1601 // Netburst
1602 case CK_Pentium4:
1603 case CK_Prescott:
1604 case CK_Nocona:
1605 // Atom
1606 case CK_Bonnell:
1607 case CK_Silvermont:
1608 case CK_Goldmont:
1609 case CK_GoldmontPlus:
1610 case CK_Tremont:
1611 case CK_Gracemont:
1612
1613 case CK_Westmere:
1614 case CK_SandyBridge:
1615 case CK_IvyBridge:
1616 case CK_Haswell:
1617 case CK_Broadwell:
1618 case CK_SkylakeClient:
1619 case CK_SkylakeServer:
1620 case CK_Cascadelake:
1621 case CK_Nehalem:
1622 case CK_Cooperlake:
1623 case CK_Cannonlake:
1624 case CK_Tigerlake:
1625 case CK_SapphireRapids:
1626 case CK_IcelakeClient:
1627 case CK_Rocketlake:
1628 case CK_IcelakeServer:
1629 case CK_Alderlake:
1630 case CK_Raptorlake:
1631 case CK_Meteorlake:
1632 case CK_Arrowlake:
1633 case CK_ArrowlakeS:
1634 case CK_Lunarlake:
1635 case CK_Pantherlake:
1636 case CK_Wildcatlake:
1637 case CK_Novalake:
1638 case CK_Sierraforest:
1639 case CK_Grandridge:
1640 case CK_Graniterapids:
1641 case CK_GraniterapidsD:
1642 case CK_Emeraldrapids:
1643 case CK_Clearwaterforest:
1644 case CK_Diamondrapids:
1645 case CK_KNL:
1646 case CK_KNM:
1647 // K7
1648 case CK_Athlon:
1649 case CK_AthlonXP:
1650 // K8
1651 case CK_K8:
1652 case CK_K8SSE3:
1653 case CK_AMDFAM10:
1654 // Bobcat
1655 case CK_BTVER1:
1656 case CK_BTVER2:
1657 // Bulldozer
1658 case CK_BDVER1:
1659 case CK_BDVER2:
1660 case CK_BDVER3:
1661 case CK_BDVER4:
1662 // Zen
1663 case CK_ZNVER1:
1664 case CK_ZNVER2:
1665 case CK_ZNVER3:
1666 case CK_ZNVER4:
1667 case CK_ZNVER5:
1668 case CK_ZNVER6:
1669 // Hygon
1670 case CK_C86_4G_M4:
1671 case CK_C86_4G_M6:
1672 case CK_C86_4G_M7:
1673 // Deprecated
1674 case CK_x86_64:
1675 case CK_x86_64_v2:
1676 case CK_x86_64_v3:
1677 case CK_x86_64_v4:
1678 case CK_Yonah:
1679 case CK_Penryn:
1680 case CK_Core2:
1681 return 64;
1682
1683 // The following currently have unknown cache line sizes (but they are probably all 64):
1684 // Core
1685 case CK_None:
1686 return std::nullopt;
1687 }
1688 llvm_unreachable("Unknown CPU kind");
1689}
1690
1691bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1692 StringRef Constraint,
1693 unsigned Size) const {
1694 // Strip off constraint modifiers.
1695 Constraint = Constraint.ltrim("=+&");
1696
1697 return validateOperandSize(FeatureMap, Constraint, Size);
1698}
1699
1700bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1701 StringRef Constraint,
1702 unsigned Size) const {
1703 return validateOperandSize(FeatureMap, Constraint, Size);
1704}
1705
1706bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1707 StringRef Constraint,
1708 unsigned Size) const {
1709 switch (Constraint[0]) {
1710 default:
1711 break;
1712 case 'k':
1713 // Registers k0-k7 (AVX512) size limit is 64 bit.
1714 case 'y':
1715 return Size <= 64;
1716 case 'f':
1717 case 't':
1718 case 'u':
1719 return Size <= 128;
1720 case 'Y':
1721 // 'Y' is the first character for several 2-character constraints.
1722 switch (Constraint[1]) {
1723 default:
1724 return false;
1725 case 'm':
1726 // 'Ym' is synonymous with 'y'.
1727 case 'k':
1728 return Size <= 64;
1729 case 'z':
1730 // XMM0/YMM/ZMM0
1731 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1732 // ZMM0 can be used if target supports AVX512F.
1733 return Size <= 512U;
1734 else if (hasFeatureEnabled(FeatureMap, "avx"))
1735 // YMM0 can be used if target supports AVX.
1736 return Size <= 256U;
1737 else if (hasFeatureEnabled(FeatureMap, "sse"))
1738 return Size <= 128U;
1739 return false;
1740 case 'i':
1741 case 't':
1742 case '2':
1743 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1744 if (SSELevel < SSE2)
1745 return false;
1746 break;
1747 }
1748 break;
1749 case 'v':
1750 case 'x':
1751 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1752 // 512-bit zmm registers can be used if target supports AVX512F.
1753 return Size <= 512U;
1754 else if (hasFeatureEnabled(FeatureMap, "avx"))
1755 // 256-bit ymm registers can be used if target supports AVX.
1756 return Size <= 256U;
1757 return Size <= 128U;
1758
1759 }
1760
1761 return true;
1762}
1763
1764std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1765 switch (*Constraint) {
1766 case '@':
1767 if (auto Len = matchAsmCCConstraint(Constraint)) {
1768 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1769 Constraint += Len - 1;
1770 return Converted;
1771 }
1772 return std::string(1, *Constraint);
1773 case 'a':
1774 return std::string("{ax}");
1775 case 'b':
1776 return std::string("{bx}");
1777 case 'c':
1778 return std::string("{cx}");
1779 case 'd':
1780 return std::string("{dx}");
1781 case 'S':
1782 return std::string("{si}");
1783 case 'D':
1784 return std::string("{di}");
1785 case 'p': // Keep 'p' constraint (address).
1786 return std::string("p");
1787 case 't': // top of floating point stack.
1788 return std::string("{st}");
1789 case 'u': // second from top of floating point stack.
1790 return std::string("{st(1)}"); // second from top of floating point stack.
1791 case 'W':
1792 assert(Constraint[1] == 's');
1793 return '^' + std::string(Constraint++, 2);
1794 case 'Y':
1795 switch (Constraint[1]) {
1796 default:
1797 // Break from inner switch and fall through (copy single char),
1798 // continue parsing after copying the current constraint into
1799 // the return string.
1800 break;
1801 case 'k':
1802 case 'm':
1803 case 'i':
1804 case 't':
1805 case 'z':
1806 case '2':
1807 // "^" hints llvm that this is a 2 letter constraint.
1808 // "Constraint++" is used to promote the string iterator
1809 // to the next constraint.
1810 return std::string("^") + std::string(Constraint++, 2);
1811 }
1812 [[fallthrough]];
1813 case 'j':
1814 switch (Constraint[1]) {
1815 default:
1816 // Break from inner switch and fall through (copy single char),
1817 // continue parsing after copying the current constraint into
1818 // the return string.
1819 break;
1820 case 'r':
1821 case 'R':
1822 // "^" hints llvm that this is a 2 letter constraint.
1823 // "Constraint++" is used to promote the string iterator
1824 // to the next constraint.
1825 return std::string("^") + std::string(Constraint++, 2);
1826 }
1827 [[fallthrough]];
1828 default:
1829 return std::string(1, *Constraint);
1830 }
1831}
1832
1833void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1834 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1835 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1836}
1837
1838void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1839 llvm::X86::fillValidTuneCPUList(Values);
1840}
1841
1845
1849
1850llvm::SmallVector<Builtin::InfosShard>
1851X86_32TargetInfo::getTargetBuiltins() const {
1852 return {
1853 {&X86::BuiltinStrings, X86::BuiltinInfos},
1854 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1855 };
1856}
1857
1858llvm::SmallVector<Builtin::InfosShard>
1859X86_64TargetInfo::getTargetBuiltins() const {
1860 return {
1861 {&X86::BuiltinStrings, X86::BuiltinInfos},
1862 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1863 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1864 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1865 "__builtin_ia32_"},
1866 };
1867}
1868
1869unsigned
1870MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1871 bool HasNonWeakDef) const {
1872 unsigned Align =
1873 WindowsX86_64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1874
1875 return std::max(Align, Microsoft64BitMinGlobalAlign(TypeSize));
1876}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1559
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:232
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1335
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:233
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1580
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:327
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1323
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1452
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:760
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:568
clang::targets::MicrosoftX86_64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition X86.cpp:1870
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:238
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1568
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1433
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1346
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1842
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1372
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1764
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:513
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1376
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1388
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1691
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1706
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1838
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1368
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1327
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1076
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1197
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:219
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:186
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1833
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1846
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1700
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1851
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1859
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Microsoft64BitMinGlobalAlign
unsigned Microsoft64BitMinGlobalAlign(uint64_t TypeSize)
Definition TargetInfo.cpp:1121
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:80
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1234
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1198
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:144
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