clang  9.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/TargetBuiltins.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
25 const Builtin::Info BuiltinInfoX86[] = {
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65 };
66 
67 const TargetInfo::AddlRegName AddlRegNames[] = {
68  {{"al", "ah", "eax", "rax"}, 0},
69  {{"bl", "bh", "ebx", "rbx"}, 3},
70  {{"cl", "ch", "ecx", "rcx"}, 2},
71  {{"dl", "dh", "edx", "rdx"}, 1},
72  {{"esi", "rsi"}, 4},
73  {{"edi", "rdi"}, 5},
74  {{"esp", "rsp"}, 7},
75  {{"ebp", "rbp"}, 6},
76  {{"r8d", "r8w", "r8b"}, 38},
77  {{"r9d", "r9w", "r9b"}, 39},
78  {{"r10d", "r10w", "r10b"}, 40},
79  {{"r11d", "r11w", "r11b"}, 41},
80  {{"r12d", "r12w", "r12b"}, 42},
81  {{"r13d", "r13w", "r13b"}, 43},
82  {{"r14d", "r14w", "r14b"}, 44},
83  {{"r15d", "r15w", "r15b"}, 45},
84 };
85 
86 } // namespace targets
87 } // namespace clang
88 
89 using namespace clang;
90 using namespace clang::targets;
91 
92 bool X86TargetInfo::setFPMath(StringRef Name) {
93  if (Name == "387") {
94  FPMath = FP_387;
95  return true;
96  }
97  if (Name == "sse") {
98  FPMath = FP_SSE;
99  return true;
100  }
101  return false;
102 }
103 
104 bool X86TargetInfo::initFeatureMap(
105  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106  const std::vector<std::string> &FeaturesVec) const {
107  // FIXME: This *really* should not be here.
108  // X86_64 always has SSE2.
109  if (getTriple().getArch() == llvm::Triple::x86_64)
110  setFeatureEnabledImpl(Features, "sse2", true);
111 
112  const CPUKind Kind = getCPUKind(CPU);
113 
114  // Enable X87 for all X86 processors but Lakemont.
115  if (Kind != CK_Lakemont)
116  setFeatureEnabledImpl(Features, "x87", true);
117 
118  // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
119  // compatibility.
120  if (Kind >= CK_i586 || Kind == CK_Generic)
121  setFeatureEnabledImpl(Features, "cx8", true);
122 
123  switch (Kind) {
124  case CK_Generic:
125  case CK_i386:
126  case CK_i486:
127  case CK_i586:
128  case CK_Pentium:
129  case CK_PentiumPro:
130  case CK_i686:
131  case CK_Lakemont:
132  break;
133 
134  case CK_PentiumMMX:
135  case CK_Pentium2:
136  case CK_K6:
137  case CK_WinChipC6:
138  setFeatureEnabledImpl(Features, "mmx", true);
139  break;
140 
141  case CK_IcelakeServer:
142  setFeatureEnabledImpl(Features, "pconfig", true);
143  setFeatureEnabledImpl(Features, "wbnoinvd", true);
144  LLVM_FALLTHROUGH;
145  case CK_IcelakeClient:
146  setFeatureEnabledImpl(Features, "vaes", true);
147  setFeatureEnabledImpl(Features, "gfni", true);
148  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
149  setFeatureEnabledImpl(Features, "avx512bitalg", true);
150  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
151  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
152  setFeatureEnabledImpl(Features, "rdpid", true);
153  LLVM_FALLTHROUGH;
154  case CK_Cannonlake:
155  setFeatureEnabledImpl(Features, "avx512ifma", true);
156  setFeatureEnabledImpl(Features, "avx512vbmi", true);
157  setFeatureEnabledImpl(Features, "sha", true);
158  LLVM_FALLTHROUGH;
159  case CK_Cascadelake:
160  //Cannonlake has no VNNI feature inside while Icelake has
161  if (Kind != CK_Cannonlake)
162  // CLK inherits all SKX features plus AVX512_VNNI
163  setFeatureEnabledImpl(Features, "avx512vnni", true);
164  LLVM_FALLTHROUGH;
165  case CK_SkylakeServer:
166  setFeatureEnabledImpl(Features, "avx512f", true);
167  setFeatureEnabledImpl(Features, "avx512cd", true);
168  setFeatureEnabledImpl(Features, "avx512dq", true);
169  setFeatureEnabledImpl(Features, "avx512bw", true);
170  setFeatureEnabledImpl(Features, "avx512vl", true);
171  setFeatureEnabledImpl(Features, "pku", true);
172  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
173  setFeatureEnabledImpl(Features, "clwb", true);
174  LLVM_FALLTHROUGH;
175  case CK_SkylakeClient:
176  setFeatureEnabledImpl(Features, "xsavec", true);
177  setFeatureEnabledImpl(Features, "xsaves", true);
178  setFeatureEnabledImpl(Features, "mpx", true);
179  if (Kind != CK_SkylakeServer
180  && Kind != CK_Cascadelake)
181  // SKX/CLX inherits all SKL features, except SGX
182  setFeatureEnabledImpl(Features, "sgx", true);
183  setFeatureEnabledImpl(Features, "clflushopt", true);
184  setFeatureEnabledImpl(Features, "aes", true);
185  LLVM_FALLTHROUGH;
186  case CK_Broadwell:
187  setFeatureEnabledImpl(Features, "rdseed", true);
188  setFeatureEnabledImpl(Features, "adx", true);
189  setFeatureEnabledImpl(Features, "prfchw", true);
190  LLVM_FALLTHROUGH;
191  case CK_Haswell:
192  setFeatureEnabledImpl(Features, "avx2", true);
193  setFeatureEnabledImpl(Features, "lzcnt", true);
194  setFeatureEnabledImpl(Features, "bmi", true);
195  setFeatureEnabledImpl(Features, "bmi2", true);
196  setFeatureEnabledImpl(Features, "fma", true);
197  setFeatureEnabledImpl(Features, "invpcid", true);
198  setFeatureEnabledImpl(Features, "movbe", true);
199  LLVM_FALLTHROUGH;
200  case CK_IvyBridge:
201  setFeatureEnabledImpl(Features, "rdrnd", true);
202  setFeatureEnabledImpl(Features, "f16c", true);
203  setFeatureEnabledImpl(Features, "fsgsbase", true);
204  LLVM_FALLTHROUGH;
205  case CK_SandyBridge:
206  setFeatureEnabledImpl(Features, "avx", true);
207  setFeatureEnabledImpl(Features, "xsave", true);
208  setFeatureEnabledImpl(Features, "xsaveopt", true);
209  LLVM_FALLTHROUGH;
210  case CK_Westmere:
211  setFeatureEnabledImpl(Features, "pclmul", true);
212  LLVM_FALLTHROUGH;
213  case CK_Nehalem:
214  setFeatureEnabledImpl(Features, "sse4.2", true);
215  LLVM_FALLTHROUGH;
216  case CK_Penryn:
217  setFeatureEnabledImpl(Features, "sse4.1", true);
218  LLVM_FALLTHROUGH;
219  case CK_Core2:
220  setFeatureEnabledImpl(Features, "ssse3", true);
221  setFeatureEnabledImpl(Features, "sahf", true);
222  LLVM_FALLTHROUGH;
223  case CK_Nocona:
224  setFeatureEnabledImpl(Features, "cx16", true);
225  LLVM_FALLTHROUGH;
226  case CK_Yonah:
227  case CK_Prescott:
228  setFeatureEnabledImpl(Features, "sse3", true);
229  LLVM_FALLTHROUGH;
230  case CK_PentiumM:
231  case CK_Pentium4:
232  case CK_x86_64:
233  setFeatureEnabledImpl(Features, "sse2", true);
234  LLVM_FALLTHROUGH;
235  case CK_Pentium3:
236  case CK_C3_2:
237  setFeatureEnabledImpl(Features, "sse", true);
238  setFeatureEnabledImpl(Features, "fxsr", true);
239  break;
240 
241  case CK_Tremont:
242  setFeatureEnabledImpl(Features, "cldemote", true);
243  setFeatureEnabledImpl(Features, "movdiri", true);
244  setFeatureEnabledImpl(Features, "movdir64b", true);
245  setFeatureEnabledImpl(Features, "gfni", true);
246  setFeatureEnabledImpl(Features, "waitpkg", true);
247  LLVM_FALLTHROUGH;
248  case CK_GoldmontPlus:
249  setFeatureEnabledImpl(Features, "ptwrite", true);
250  setFeatureEnabledImpl(Features, "rdpid", true);
251  setFeatureEnabledImpl(Features, "sgx", true);
252  LLVM_FALLTHROUGH;
253  case CK_Goldmont:
254  setFeatureEnabledImpl(Features, "sha", true);
255  setFeatureEnabledImpl(Features, "rdseed", true);
256  setFeatureEnabledImpl(Features, "xsave", true);
257  setFeatureEnabledImpl(Features, "xsaveopt", true);
258  setFeatureEnabledImpl(Features, "xsavec", true);
259  setFeatureEnabledImpl(Features, "xsaves", true);
260  setFeatureEnabledImpl(Features, "clflushopt", true);
261  setFeatureEnabledImpl(Features, "mpx", true);
262  setFeatureEnabledImpl(Features, "fsgsbase", true);
263  setFeatureEnabledImpl(Features, "aes", true);
264  LLVM_FALLTHROUGH;
265  case CK_Silvermont:
266  setFeatureEnabledImpl(Features, "rdrnd", true);
267  setFeatureEnabledImpl(Features, "pclmul", true);
268  setFeatureEnabledImpl(Features, "sse4.2", true);
269  setFeatureEnabledImpl(Features, "prfchw", true);
270  LLVM_FALLTHROUGH;
271  case CK_Bonnell:
272  setFeatureEnabledImpl(Features, "movbe", true);
273  setFeatureEnabledImpl(Features, "ssse3", true);
274  setFeatureEnabledImpl(Features, "fxsr", true);
275  setFeatureEnabledImpl(Features, "cx16", true);
276  setFeatureEnabledImpl(Features, "sahf", true);
277  break;
278 
279  case CK_KNM:
280  // TODO: Add avx5124fmaps/avx5124vnniw.
281  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
282  LLVM_FALLTHROUGH;
283  case CK_KNL:
284  setFeatureEnabledImpl(Features, "avx512f", true);
285  setFeatureEnabledImpl(Features, "avx512cd", true);
286  setFeatureEnabledImpl(Features, "avx512er", true);
287  setFeatureEnabledImpl(Features, "avx512pf", true);
288  setFeatureEnabledImpl(Features, "prfchw", true);
289  setFeatureEnabledImpl(Features, "prefetchwt1", true);
290  setFeatureEnabledImpl(Features, "fxsr", true);
291  setFeatureEnabledImpl(Features, "rdseed", true);
292  setFeatureEnabledImpl(Features, "adx", true);
293  setFeatureEnabledImpl(Features, "lzcnt", true);
294  setFeatureEnabledImpl(Features, "bmi", true);
295  setFeatureEnabledImpl(Features, "bmi2", true);
296  setFeatureEnabledImpl(Features, "fma", true);
297  setFeatureEnabledImpl(Features, "rdrnd", true);
298  setFeatureEnabledImpl(Features, "f16c", true);
299  setFeatureEnabledImpl(Features, "fsgsbase", true);
300  setFeatureEnabledImpl(Features, "aes", true);
301  setFeatureEnabledImpl(Features, "pclmul", true);
302  setFeatureEnabledImpl(Features, "cx16", true);
303  setFeatureEnabledImpl(Features, "xsaveopt", true);
304  setFeatureEnabledImpl(Features, "xsave", true);
305  setFeatureEnabledImpl(Features, "movbe", true);
306  setFeatureEnabledImpl(Features, "sahf", true);
307  break;
308 
309  case CK_K6_2:
310  case CK_K6_3:
311  case CK_WinChip2:
312  case CK_C3:
313  setFeatureEnabledImpl(Features, "3dnow", true);
314  break;
315 
316  case CK_AMDFAM10:
317  setFeatureEnabledImpl(Features, "sse4a", true);
318  setFeatureEnabledImpl(Features, "lzcnt", true);
319  setFeatureEnabledImpl(Features, "popcnt", true);
320  setFeatureEnabledImpl(Features, "sahf", true);
321  LLVM_FALLTHROUGH;
322  case CK_K8SSE3:
323  setFeatureEnabledImpl(Features, "sse3", true);
324  LLVM_FALLTHROUGH;
325  case CK_K8:
326  setFeatureEnabledImpl(Features, "sse2", true);
327  LLVM_FALLTHROUGH;
328  case CK_AthlonXP:
329  setFeatureEnabledImpl(Features, "sse", true);
330  setFeatureEnabledImpl(Features, "fxsr", true);
331  LLVM_FALLTHROUGH;
332  case CK_Athlon:
333  case CK_Geode:
334  setFeatureEnabledImpl(Features, "3dnowa", true);
335  break;
336 
337  case CK_BTVER2:
338  setFeatureEnabledImpl(Features, "avx", true);
339  setFeatureEnabledImpl(Features, "aes", true);
340  setFeatureEnabledImpl(Features, "pclmul", true);
341  setFeatureEnabledImpl(Features, "bmi", true);
342  setFeatureEnabledImpl(Features, "f16c", true);
343  setFeatureEnabledImpl(Features, "xsaveopt", true);
344  setFeatureEnabledImpl(Features, "movbe", true);
345  LLVM_FALLTHROUGH;
346  case CK_BTVER1:
347  setFeatureEnabledImpl(Features, "ssse3", true);
348  setFeatureEnabledImpl(Features, "sse4a", true);
349  setFeatureEnabledImpl(Features, "lzcnt", true);
350  setFeatureEnabledImpl(Features, "popcnt", true);
351  setFeatureEnabledImpl(Features, "prfchw", true);
352  setFeatureEnabledImpl(Features, "cx16", true);
353  setFeatureEnabledImpl(Features, "fxsr", true);
354  setFeatureEnabledImpl(Features, "sahf", true);
355  break;
356 
357  case CK_ZNVER2:
358  setFeatureEnabledImpl(Features, "clwb", true);
359  setFeatureEnabledImpl(Features, "rdpid", true);
360  setFeatureEnabledImpl(Features, "wbnoinvd", true);
361  LLVM_FALLTHROUGH;
362  case CK_ZNVER1:
363  setFeatureEnabledImpl(Features, "adx", true);
364  setFeatureEnabledImpl(Features, "aes", true);
365  setFeatureEnabledImpl(Features, "avx2", true);
366  setFeatureEnabledImpl(Features, "bmi", true);
367  setFeatureEnabledImpl(Features, "bmi2", true);
368  setFeatureEnabledImpl(Features, "clflushopt", true);
369  setFeatureEnabledImpl(Features, "clzero", true);
370  setFeatureEnabledImpl(Features, "cx16", true);
371  setFeatureEnabledImpl(Features, "f16c", true);
372  setFeatureEnabledImpl(Features, "fma", true);
373  setFeatureEnabledImpl(Features, "fsgsbase", true);
374  setFeatureEnabledImpl(Features, "fxsr", true);
375  setFeatureEnabledImpl(Features, "lzcnt", true);
376  setFeatureEnabledImpl(Features, "mwaitx", true);
377  setFeatureEnabledImpl(Features, "movbe", true);
378  setFeatureEnabledImpl(Features, "pclmul", true);
379  setFeatureEnabledImpl(Features, "popcnt", true);
380  setFeatureEnabledImpl(Features, "prfchw", true);
381  setFeatureEnabledImpl(Features, "rdrnd", true);
382  setFeatureEnabledImpl(Features, "rdseed", true);
383  setFeatureEnabledImpl(Features, "sahf", true);
384  setFeatureEnabledImpl(Features, "sha", true);
385  setFeatureEnabledImpl(Features, "sse4a", true);
386  setFeatureEnabledImpl(Features, "xsave", true);
387  setFeatureEnabledImpl(Features, "xsavec", true);
388  setFeatureEnabledImpl(Features, "xsaveopt", true);
389  setFeatureEnabledImpl(Features, "xsaves", true);
390  break;
391 
392  case CK_BDVER4:
393  setFeatureEnabledImpl(Features, "avx2", true);
394  setFeatureEnabledImpl(Features, "bmi2", true);
395  setFeatureEnabledImpl(Features, "mwaitx", true);
396  LLVM_FALLTHROUGH;
397  case CK_BDVER3:
398  setFeatureEnabledImpl(Features, "fsgsbase", true);
399  setFeatureEnabledImpl(Features, "xsaveopt", true);
400  LLVM_FALLTHROUGH;
401  case CK_BDVER2:
402  setFeatureEnabledImpl(Features, "bmi", true);
403  setFeatureEnabledImpl(Features, "fma", true);
404  setFeatureEnabledImpl(Features, "f16c", true);
405  setFeatureEnabledImpl(Features, "tbm", true);
406  LLVM_FALLTHROUGH;
407  case CK_BDVER1:
408  // xop implies avx, sse4a and fma4.
409  setFeatureEnabledImpl(Features, "xop", true);
410  setFeatureEnabledImpl(Features, "lwp", true);
411  setFeatureEnabledImpl(Features, "lzcnt", true);
412  setFeatureEnabledImpl(Features, "aes", true);
413  setFeatureEnabledImpl(Features, "pclmul", true);
414  setFeatureEnabledImpl(Features, "prfchw", true);
415  setFeatureEnabledImpl(Features, "cx16", true);
416  setFeatureEnabledImpl(Features, "fxsr", true);
417  setFeatureEnabledImpl(Features, "xsave", true);
418  setFeatureEnabledImpl(Features, "sahf", true);
419  break;
420  }
421  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
422  return false;
423 
424  // Can't do this earlier because we need to be able to explicitly enable
425  // or disable these features and the things that they depend upon.
426 
427  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
428  auto I = Features.find("sse4.2");
429  if (I != Features.end() && I->getValue() &&
430  llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
431  Features["popcnt"] = true;
432 
433  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
434  I = Features.find("3dnow");
435  if (I != Features.end() && I->getValue() &&
436  llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end())
437  Features["prfchw"] = true;
438 
439  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
440  // then enable MMX.
441  I = Features.find("sse");
442  if (I != Features.end() && I->getValue() &&
443  llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
444  Features["mmx"] = true;
445 
446  return true;
447 }
448 
449 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
450  X86SSEEnum Level, bool Enabled) {
451  if (Enabled) {
452  switch (Level) {
453  case AVX512F:
454  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
455  LLVM_FALLTHROUGH;
456  case AVX2:
457  Features["avx2"] = true;
458  LLVM_FALLTHROUGH;
459  case AVX:
460  Features["avx"] = true;
461  Features["xsave"] = true;
462  LLVM_FALLTHROUGH;
463  case SSE42:
464  Features["sse4.2"] = true;
465  LLVM_FALLTHROUGH;
466  case SSE41:
467  Features["sse4.1"] = true;
468  LLVM_FALLTHROUGH;
469  case SSSE3:
470  Features["ssse3"] = true;
471  LLVM_FALLTHROUGH;
472  case SSE3:
473  Features["sse3"] = true;
474  LLVM_FALLTHROUGH;
475  case SSE2:
476  Features["sse2"] = true;
477  LLVM_FALLTHROUGH;
478  case SSE1:
479  Features["sse"] = true;
480  LLVM_FALLTHROUGH;
481  case NoSSE:
482  break;
483  }
484  return;
485  }
486 
487  switch (Level) {
488  case NoSSE:
489  case SSE1:
490  Features["sse"] = false;
491  LLVM_FALLTHROUGH;
492  case SSE2:
493  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
494  Features["gfni"] = false;
495  LLVM_FALLTHROUGH;
496  case SSE3:
497  Features["sse3"] = false;
498  setXOPLevel(Features, NoXOP, false);
499  LLVM_FALLTHROUGH;
500  case SSSE3:
501  Features["ssse3"] = false;
502  LLVM_FALLTHROUGH;
503  case SSE41:
504  Features["sse4.1"] = false;
505  LLVM_FALLTHROUGH;
506  case SSE42:
507  Features["sse4.2"] = false;
508  LLVM_FALLTHROUGH;
509  case AVX:
510  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
511  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
512  setXOPLevel(Features, FMA4, false);
513  LLVM_FALLTHROUGH;
514  case AVX2:
515  Features["avx2"] = false;
516  LLVM_FALLTHROUGH;
517  case AVX512F:
518  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
519  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
520  Features["avx512vl"] = Features["avx512vbmi"] =
521  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
522  Features["avx512bitalg"] = Features["avx512vnni"] =
523  Features["avx512vbmi2"] = false;
524  Features["avx512bf16"] = false;
525  break;
526  }
527 }
528 
529 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
530  MMX3DNowEnum Level, bool Enabled) {
531  if (Enabled) {
532  switch (Level) {
533  case AMD3DNowAthlon:
534  Features["3dnowa"] = true;
535  LLVM_FALLTHROUGH;
536  case AMD3DNow:
537  Features["3dnow"] = true;
538  LLVM_FALLTHROUGH;
539  case MMX:
540  Features["mmx"] = true;
541  LLVM_FALLTHROUGH;
542  case NoMMX3DNow:
543  break;
544  }
545  return;
546  }
547 
548  switch (Level) {
549  case NoMMX3DNow:
550  case MMX:
551  Features["mmx"] = false;
552  LLVM_FALLTHROUGH;
553  case AMD3DNow:
554  Features["3dnow"] = false;
555  LLVM_FALLTHROUGH;
556  case AMD3DNowAthlon:
557  Features["3dnowa"] = false;
558  break;
559  }
560 }
561 
562 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
563  bool Enabled) {
564  if (Enabled) {
565  switch (Level) {
566  case XOP:
567  Features["xop"] = true;
568  LLVM_FALLTHROUGH;
569  case FMA4:
570  Features["fma4"] = true;
571  setSSELevel(Features, AVX, true);
572  LLVM_FALLTHROUGH;
573  case SSE4A:
574  Features["sse4a"] = true;
575  setSSELevel(Features, SSE3, true);
576  LLVM_FALLTHROUGH;
577  case NoXOP:
578  break;
579  }
580  return;
581  }
582 
583  switch (Level) {
584  case NoXOP:
585  case SSE4A:
586  Features["sse4a"] = false;
587  LLVM_FALLTHROUGH;
588  case FMA4:
589  Features["fma4"] = false;
590  LLVM_FALLTHROUGH;
591  case XOP:
592  Features["xop"] = false;
593  break;
594  }
595 }
596 
597 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
598  StringRef Name, bool Enabled) {
599  // This is a bit of a hack to deal with the sse4 target feature when used
600  // as part of the target attribute. We handle sse4 correctly everywhere
601  // else. See below for more information on how we handle the sse4 options.
602  if (Name != "sse4")
603  Features[Name] = Enabled;
604 
605  if (Name == "mmx") {
606  setMMXLevel(Features, MMX, Enabled);
607  } else if (Name == "sse") {
608  setSSELevel(Features, SSE1, Enabled);
609  } else if (Name == "sse2") {
610  setSSELevel(Features, SSE2, Enabled);
611  } else if (Name == "sse3") {
612  setSSELevel(Features, SSE3, Enabled);
613  } else if (Name == "ssse3") {
614  setSSELevel(Features, SSSE3, Enabled);
615  } else if (Name == "sse4.2") {
616  setSSELevel(Features, SSE42, Enabled);
617  } else if (Name == "sse4.1") {
618  setSSELevel(Features, SSE41, Enabled);
619  } else if (Name == "3dnow") {
620  setMMXLevel(Features, AMD3DNow, Enabled);
621  } else if (Name == "3dnowa") {
622  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
623  } else if (Name == "aes") {
624  if (Enabled)
625  setSSELevel(Features, SSE2, Enabled);
626  else
627  Features["vaes"] = false;
628  } else if (Name == "vaes") {
629  if (Enabled) {
630  setSSELevel(Features, AVX, Enabled);
631  Features["aes"] = true;
632  }
633  } else if (Name == "pclmul") {
634  if (Enabled)
635  setSSELevel(Features, SSE2, Enabled);
636  else
637  Features["vpclmulqdq"] = false;
638  } else if (Name == "vpclmulqdq") {
639  if (Enabled) {
640  setSSELevel(Features, AVX, Enabled);
641  Features["pclmul"] = true;
642  }
643  } else if (Name == "gfni") {
644  if (Enabled)
645  setSSELevel(Features, SSE2, Enabled);
646  } else if (Name == "avx") {
647  setSSELevel(Features, AVX, Enabled);
648  } else if (Name == "avx2") {
649  setSSELevel(Features, AVX2, Enabled);
650  } else if (Name == "avx512f") {
651  setSSELevel(Features, AVX512F, Enabled);
652  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
653  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
654  Name == "avx512vbmi" || Name == "avx512ifma" ||
655  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
656  Name == "avx512bf16" ||
657  Name == "avx512vnni" || Name == "avx512vbmi2") {
658  if (Enabled)
659  setSSELevel(Features, AVX512F, Enabled);
660  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
661  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
662  Features["avx512bw"] = true;
663  if (Name == "avx512bf16" && Enabled)
664  Features["avx512bw"] = true;
665  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
666  if (Name == "avx512bw" && !Enabled)
667  Features["avx512vbmi"] = Features["avx512vbmi2"] =
668  Features["avx512bf16"] =
669  Features["avx512bitalg"] = false;
670  } else if (Name == "fma") {
671  if (Enabled)
672  setSSELevel(Features, AVX, Enabled);
673  else
674  setSSELevel(Features, AVX512F, Enabled);
675  } else if (Name == "fma4") {
676  setXOPLevel(Features, FMA4, Enabled);
677  } else if (Name == "xop") {
678  setXOPLevel(Features, XOP, Enabled);
679  } else if (Name == "sse4a") {
680  setXOPLevel(Features, SSE4A, Enabled);
681  } else if (Name == "f16c") {
682  if (Enabled)
683  setSSELevel(Features, AVX, Enabled);
684  else
685  setSSELevel(Features, AVX512F, Enabled);
686  } else if (Name == "sha") {
687  if (Enabled)
688  setSSELevel(Features, SSE2, Enabled);
689  } else if (Name == "sse4") {
690  // We can get here via the __target__ attribute since that's not controlled
691  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
692  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
693  // disabled.
694  if (Enabled)
695  setSSELevel(Features, SSE42, Enabled);
696  else
697  setSSELevel(Features, SSE41, Enabled);
698  } else if (Name == "xsave") {
699  if (!Enabled)
700  Features["xsaveopt"] = false;
701  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
702  if (Enabled)
703  Features["xsave"] = true;
704  }
705 }
706 
707 /// handleTargetFeatures - Perform initialization based on the user
708 /// configured set of features.
709 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
710  DiagnosticsEngine &Diags) {
711  for (const auto &Feature : Features) {
712  if (Feature[0] != '+')
713  continue;
714 
715  if (Feature == "+aes") {
716  HasAES = true;
717  } else if (Feature == "+vaes") {
718  HasVAES = true;
719  } else if (Feature == "+pclmul") {
720  HasPCLMUL = true;
721  } else if (Feature == "+vpclmulqdq") {
722  HasVPCLMULQDQ = true;
723  } else if (Feature == "+lzcnt") {
724  HasLZCNT = true;
725  } else if (Feature == "+rdrnd") {
726  HasRDRND = true;
727  } else if (Feature == "+fsgsbase") {
728  HasFSGSBASE = true;
729  } else if (Feature == "+bmi") {
730  HasBMI = true;
731  } else if (Feature == "+bmi2") {
732  HasBMI2 = true;
733  } else if (Feature == "+popcnt") {
734  HasPOPCNT = true;
735  } else if (Feature == "+rtm") {
736  HasRTM = true;
737  } else if (Feature == "+prfchw") {
738  HasPRFCHW = true;
739  } else if (Feature == "+rdseed") {
740  HasRDSEED = true;
741  } else if (Feature == "+adx") {
742  HasADX = true;
743  } else if (Feature == "+tbm") {
744  HasTBM = true;
745  } else if (Feature == "+lwp") {
746  HasLWP = true;
747  } else if (Feature == "+fma") {
748  HasFMA = true;
749  } else if (Feature == "+f16c") {
750  HasF16C = true;
751  } else if (Feature == "+gfni") {
752  HasGFNI = true;
753  } else if (Feature == "+avx512cd") {
754  HasAVX512CD = true;
755  } else if (Feature == "+avx512vpopcntdq") {
756  HasAVX512VPOPCNTDQ = true;
757  } else if (Feature == "+avx512vnni") {
758  HasAVX512VNNI = true;
759  } else if (Feature == "+avx512bf16") {
760  HasAVX512BF16 = true;
761  } else if (Feature == "+avx512er") {
762  HasAVX512ER = true;
763  } else if (Feature == "+avx512pf") {
764  HasAVX512PF = true;
765  } else if (Feature == "+avx512dq") {
766  HasAVX512DQ = true;
767  } else if (Feature == "+avx512bitalg") {
768  HasAVX512BITALG = true;
769  } else if (Feature == "+avx512bw") {
770  HasAVX512BW = true;
771  } else if (Feature == "+avx512vl") {
772  HasAVX512VL = true;
773  } else if (Feature == "+avx512vbmi") {
774  HasAVX512VBMI = true;
775  } else if (Feature == "+avx512vbmi2") {
776  HasAVX512VBMI2 = true;
777  } else if (Feature == "+avx512ifma") {
778  HasAVX512IFMA = true;
779  } else if (Feature == "+sha") {
780  HasSHA = true;
781  } else if (Feature == "+mpx") {
782  HasMPX = true;
783  } else if (Feature == "+shstk") {
784  HasSHSTK = true;
785  } else if (Feature == "+movbe") {
786  HasMOVBE = true;
787  } else if (Feature == "+sgx") {
788  HasSGX = true;
789  } else if (Feature == "+cx8") {
790  HasCX8 = true;
791  } else if (Feature == "+cx16") {
792  HasCX16 = true;
793  } else if (Feature == "+fxsr") {
794  HasFXSR = true;
795  } else if (Feature == "+xsave") {
796  HasXSAVE = true;
797  } else if (Feature == "+xsaveopt") {
798  HasXSAVEOPT = true;
799  } else if (Feature == "+xsavec") {
800  HasXSAVEC = true;
801  } else if (Feature == "+xsaves") {
802  HasXSAVES = true;
803  } else if (Feature == "+mwaitx") {
804  HasMWAITX = true;
805  } else if (Feature == "+pku") {
806  HasPKU = true;
807  } else if (Feature == "+clflushopt") {
808  HasCLFLUSHOPT = true;
809  } else if (Feature == "+clwb") {
810  HasCLWB = true;
811  } else if (Feature == "+wbnoinvd") {
812  HasWBNOINVD = true;
813  } else if (Feature == "+prefetchwt1") {
814  HasPREFETCHWT1 = true;
815  } else if (Feature == "+clzero") {
816  HasCLZERO = true;
817  } else if (Feature == "+cldemote") {
818  HasCLDEMOTE = true;
819  } else if (Feature == "+rdpid") {
820  HasRDPID = true;
821  } else if (Feature == "+retpoline-external-thunk") {
822  HasRetpolineExternalThunk = true;
823  } else if (Feature == "+sahf") {
824  HasLAHFSAHF = true;
825  } else if (Feature == "+waitpkg") {
826  HasWAITPKG = true;
827  } else if (Feature == "+movdiri") {
828  HasMOVDIRI = true;
829  } else if (Feature == "+movdir64b") {
830  HasMOVDIR64B = true;
831  } else if (Feature == "+pconfig") {
832  HasPCONFIG = true;
833  } else if (Feature == "+ptwrite") {
834  HasPTWRITE = true;
835  } else if (Feature == "+invpcid") {
836  HasINVPCID = true;
837  }
838 
839  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
840  .Case("+avx512f", AVX512F)
841  .Case("+avx2", AVX2)
842  .Case("+avx", AVX)
843  .Case("+sse4.2", SSE42)
844  .Case("+sse4.1", SSE41)
845  .Case("+ssse3", SSSE3)
846  .Case("+sse3", SSE3)
847  .Case("+sse2", SSE2)
848  .Case("+sse", SSE1)
849  .Default(NoSSE);
850  SSELevel = std::max(SSELevel, Level);
851 
852  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
853  .Case("+3dnowa", AMD3DNowAthlon)
854  .Case("+3dnow", AMD3DNow)
855  .Case("+mmx", MMX)
856  .Default(NoMMX3DNow);
857  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
858 
859  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
860  .Case("+xop", XOP)
861  .Case("+fma4", FMA4)
862  .Case("+sse4a", SSE4A)
863  .Default(NoXOP);
864  XOPLevel = std::max(XOPLevel, XLevel);
865  }
866 
867  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
868  // matches the selected sse level.
869  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
870  (FPMath == FP_387 && SSELevel >= SSE1)) {
871  Diags.Report(diag::err_target_unsupported_fpmath)
872  << (FPMath == FP_SSE ? "sse" : "387");
873  return false;
874  }
875 
876  SimdDefaultAlign =
877  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
878  return true;
879 }
880 
881 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
882 /// definitions for this particular subtarget.
883 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
884  MacroBuilder &Builder) const {
885  // Inline assembly supports X86 flag outputs.
886  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
887 
888  std::string CodeModel = getTargetOpts().CodeModel;
889  if (CodeModel == "default")
890  CodeModel = "small";
891  Builder.defineMacro("__code_model_" + CodeModel + "_");
892 
893  // Target identification.
894  if (getTriple().getArch() == llvm::Triple::x86_64) {
895  Builder.defineMacro("__amd64__");
896  Builder.defineMacro("__amd64");
897  Builder.defineMacro("__x86_64");
898  Builder.defineMacro("__x86_64__");
899  if (getTriple().getArchName() == "x86_64h") {
900  Builder.defineMacro("__x86_64h");
901  Builder.defineMacro("__x86_64h__");
902  }
903  } else {
904  DefineStd(Builder, "i386", Opts);
905  }
906 
907  // Subtarget options.
908  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
909  // truly should be based on -mtune options.
910  switch (CPU) {
911  case CK_Generic:
912  break;
913  case CK_i386:
914  // The rest are coming from the i386 define above.
915  Builder.defineMacro("__tune_i386__");
916  break;
917  case CK_i486:
918  case CK_WinChipC6:
919  case CK_WinChip2:
920  case CK_C3:
921  defineCPUMacros(Builder, "i486");
922  break;
923  case CK_PentiumMMX:
924  Builder.defineMacro("__pentium_mmx__");
925  Builder.defineMacro("__tune_pentium_mmx__");
926  LLVM_FALLTHROUGH;
927  case CK_i586:
928  case CK_Pentium:
929  defineCPUMacros(Builder, "i586");
930  defineCPUMacros(Builder, "pentium");
931  break;
932  case CK_Pentium3:
933  case CK_PentiumM:
934  Builder.defineMacro("__tune_pentium3__");
935  LLVM_FALLTHROUGH;
936  case CK_Pentium2:
937  case CK_C3_2:
938  Builder.defineMacro("__tune_pentium2__");
939  LLVM_FALLTHROUGH;
940  case CK_PentiumPro:
941  case CK_i686:
942  defineCPUMacros(Builder, "i686");
943  defineCPUMacros(Builder, "pentiumpro");
944  break;
945  case CK_Pentium4:
946  defineCPUMacros(Builder, "pentium4");
947  break;
948  case CK_Yonah:
949  case CK_Prescott:
950  case CK_Nocona:
951  defineCPUMacros(Builder, "nocona");
952  break;
953  case CK_Core2:
954  case CK_Penryn:
955  defineCPUMacros(Builder, "core2");
956  break;
957  case CK_Bonnell:
958  defineCPUMacros(Builder, "atom");
959  break;
960  case CK_Silvermont:
961  defineCPUMacros(Builder, "slm");
962  break;
963  case CK_Goldmont:
964  defineCPUMacros(Builder, "goldmont");
965  break;
966  case CK_GoldmontPlus:
967  defineCPUMacros(Builder, "goldmont_plus");
968  break;
969  case CK_Tremont:
970  defineCPUMacros(Builder, "tremont");
971  break;
972  case CK_Nehalem:
973  case CK_Westmere:
974  case CK_SandyBridge:
975  case CK_IvyBridge:
976  case CK_Haswell:
977  case CK_Broadwell:
978  case CK_SkylakeClient:
979  case CK_SkylakeServer:
980  case CK_Cascadelake:
981  case CK_Cannonlake:
982  case CK_IcelakeClient:
983  case CK_IcelakeServer:
984  // FIXME: Historically, we defined this legacy name, it would be nice to
985  // remove it at some point. We've never exposed fine-grained names for
986  // recent primary x86 CPUs, and we should keep it that way.
987  defineCPUMacros(Builder, "corei7");
988  break;
989  case CK_KNL:
990  defineCPUMacros(Builder, "knl");
991  break;
992  case CK_KNM:
993  break;
994  case CK_Lakemont:
995  defineCPUMacros(Builder, "i586", /*Tuning*/false);
996  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
997  Builder.defineMacro("__tune_lakemont__");
998  break;
999  case CK_K6_2:
1000  Builder.defineMacro("__k6_2__");
1001  Builder.defineMacro("__tune_k6_2__");
1002  LLVM_FALLTHROUGH;
1003  case CK_K6_3:
1004  if (CPU != CK_K6_2) { // In case of fallthrough
1005  // FIXME: GCC may be enabling these in cases where some other k6
1006  // architecture is specified but -m3dnow is explicitly provided. The
1007  // exact semantics need to be determined and emulated here.
1008  Builder.defineMacro("__k6_3__");
1009  Builder.defineMacro("__tune_k6_3__");
1010  }
1011  LLVM_FALLTHROUGH;
1012  case CK_K6:
1013  defineCPUMacros(Builder, "k6");
1014  break;
1015  case CK_Athlon:
1016  case CK_AthlonXP:
1017  defineCPUMacros(Builder, "athlon");
1018  if (SSELevel != NoSSE) {
1019  Builder.defineMacro("__athlon_sse__");
1020  Builder.defineMacro("__tune_athlon_sse__");
1021  }
1022  break;
1023  case CK_K8:
1024  case CK_K8SSE3:
1025  case CK_x86_64:
1026  defineCPUMacros(Builder, "k8");
1027  break;
1028  case CK_AMDFAM10:
1029  defineCPUMacros(Builder, "amdfam10");
1030  break;
1031  case CK_BTVER1:
1032  defineCPUMacros(Builder, "btver1");
1033  break;
1034  case CK_BTVER2:
1035  defineCPUMacros(Builder, "btver2");
1036  break;
1037  case CK_BDVER1:
1038  defineCPUMacros(Builder, "bdver1");
1039  break;
1040  case CK_BDVER2:
1041  defineCPUMacros(Builder, "bdver2");
1042  break;
1043  case CK_BDVER3:
1044  defineCPUMacros(Builder, "bdver3");
1045  break;
1046  case CK_BDVER4:
1047  defineCPUMacros(Builder, "bdver4");
1048  break;
1049  case CK_ZNVER1:
1050  defineCPUMacros(Builder, "znver1");
1051  break;
1052  case CK_ZNVER2:
1053  defineCPUMacros(Builder, "znver2");
1054  break;
1055  case CK_Geode:
1056  defineCPUMacros(Builder, "geode");
1057  break;
1058  }
1059 
1060  // Target properties.
1061  Builder.defineMacro("__REGISTER_PREFIX__", "");
1062 
1063  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1064  // functions in glibc header files that use FP Stack inline asm which the
1065  // backend can't deal with (PR879).
1066  Builder.defineMacro("__NO_MATH_INLINES");
1067 
1068  if (HasAES)
1069  Builder.defineMacro("__AES__");
1070 
1071  if (HasVAES)
1072  Builder.defineMacro("__VAES__");
1073 
1074  if (HasPCLMUL)
1075  Builder.defineMacro("__PCLMUL__");
1076 
1077  if (HasVPCLMULQDQ)
1078  Builder.defineMacro("__VPCLMULQDQ__");
1079 
1080  if (HasLZCNT)
1081  Builder.defineMacro("__LZCNT__");
1082 
1083  if (HasRDRND)
1084  Builder.defineMacro("__RDRND__");
1085 
1086  if (HasFSGSBASE)
1087  Builder.defineMacro("__FSGSBASE__");
1088 
1089  if (HasBMI)
1090  Builder.defineMacro("__BMI__");
1091 
1092  if (HasBMI2)
1093  Builder.defineMacro("__BMI2__");
1094 
1095  if (HasPOPCNT)
1096  Builder.defineMacro("__POPCNT__");
1097 
1098  if (HasRTM)
1099  Builder.defineMacro("__RTM__");
1100 
1101  if (HasPRFCHW)
1102  Builder.defineMacro("__PRFCHW__");
1103 
1104  if (HasRDSEED)
1105  Builder.defineMacro("__RDSEED__");
1106 
1107  if (HasADX)
1108  Builder.defineMacro("__ADX__");
1109 
1110  if (HasTBM)
1111  Builder.defineMacro("__TBM__");
1112 
1113  if (HasLWP)
1114  Builder.defineMacro("__LWP__");
1115 
1116  if (HasMWAITX)
1117  Builder.defineMacro("__MWAITX__");
1118 
1119  if (HasMOVBE)
1120  Builder.defineMacro("__MOVBE__");
1121 
1122  switch (XOPLevel) {
1123  case XOP:
1124  Builder.defineMacro("__XOP__");
1125  LLVM_FALLTHROUGH;
1126  case FMA4:
1127  Builder.defineMacro("__FMA4__");
1128  LLVM_FALLTHROUGH;
1129  case SSE4A:
1130  Builder.defineMacro("__SSE4A__");
1131  LLVM_FALLTHROUGH;
1132  case NoXOP:
1133  break;
1134  }
1135 
1136  if (HasFMA)
1137  Builder.defineMacro("__FMA__");
1138 
1139  if (HasF16C)
1140  Builder.defineMacro("__F16C__");
1141 
1142  if (HasGFNI)
1143  Builder.defineMacro("__GFNI__");
1144 
1145  if (HasAVX512CD)
1146  Builder.defineMacro("__AVX512CD__");
1147  if (HasAVX512VPOPCNTDQ)
1148  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1149  if (HasAVX512VNNI)
1150  Builder.defineMacro("__AVX512VNNI__");
1151  if (HasAVX512BF16)
1152  Builder.defineMacro("__AVX512BF16__");
1153  if (HasAVX512ER)
1154  Builder.defineMacro("__AVX512ER__");
1155  if (HasAVX512PF)
1156  Builder.defineMacro("__AVX512PF__");
1157  if (HasAVX512DQ)
1158  Builder.defineMacro("__AVX512DQ__");
1159  if (HasAVX512BITALG)
1160  Builder.defineMacro("__AVX512BITALG__");
1161  if (HasAVX512BW)
1162  Builder.defineMacro("__AVX512BW__");
1163  if (HasAVX512VL)
1164  Builder.defineMacro("__AVX512VL__");
1165  if (HasAVX512VBMI)
1166  Builder.defineMacro("__AVX512VBMI__");
1167  if (HasAVX512VBMI2)
1168  Builder.defineMacro("__AVX512VBMI2__");
1169  if (HasAVX512IFMA)
1170  Builder.defineMacro("__AVX512IFMA__");
1171 
1172  if (HasSHA)
1173  Builder.defineMacro("__SHA__");
1174 
1175  if (HasFXSR)
1176  Builder.defineMacro("__FXSR__");
1177  if (HasXSAVE)
1178  Builder.defineMacro("__XSAVE__");
1179  if (HasXSAVEOPT)
1180  Builder.defineMacro("__XSAVEOPT__");
1181  if (HasXSAVEC)
1182  Builder.defineMacro("__XSAVEC__");
1183  if (HasXSAVES)
1184  Builder.defineMacro("__XSAVES__");
1185  if (HasPKU)
1186  Builder.defineMacro("__PKU__");
1187  if (HasCLFLUSHOPT)
1188  Builder.defineMacro("__CLFLUSHOPT__");
1189  if (HasCLWB)
1190  Builder.defineMacro("__CLWB__");
1191  if (HasWBNOINVD)
1192  Builder.defineMacro("__WBNOINVD__");
1193  if (HasMPX)
1194  Builder.defineMacro("__MPX__");
1195  if (HasSHSTK)
1196  Builder.defineMacro("__SHSTK__");
1197  if (HasSGX)
1198  Builder.defineMacro("__SGX__");
1199  if (HasPREFETCHWT1)
1200  Builder.defineMacro("__PREFETCHWT1__");
1201  if (HasCLZERO)
1202  Builder.defineMacro("__CLZERO__");
1203  if (HasRDPID)
1204  Builder.defineMacro("__RDPID__");
1205  if (HasCLDEMOTE)
1206  Builder.defineMacro("__CLDEMOTE__");
1207  if (HasWAITPKG)
1208  Builder.defineMacro("__WAITPKG__");
1209  if (HasMOVDIRI)
1210  Builder.defineMacro("__MOVDIRI__");
1211  if (HasMOVDIR64B)
1212  Builder.defineMacro("__MOVDIR64B__");
1213  if (HasPCONFIG)
1214  Builder.defineMacro("__PCONFIG__");
1215  if (HasPTWRITE)
1216  Builder.defineMacro("__PTWRITE__");
1217  if (HasINVPCID)
1218  Builder.defineMacro("__INVPCID__");
1219 
1220  // Each case falls through to the previous one here.
1221  switch (SSELevel) {
1222  case AVX512F:
1223  Builder.defineMacro("__AVX512F__");
1224  LLVM_FALLTHROUGH;
1225  case AVX2:
1226  Builder.defineMacro("__AVX2__");
1227  LLVM_FALLTHROUGH;
1228  case AVX:
1229  Builder.defineMacro("__AVX__");
1230  LLVM_FALLTHROUGH;
1231  case SSE42:
1232  Builder.defineMacro("__SSE4_2__");
1233  LLVM_FALLTHROUGH;
1234  case SSE41:
1235  Builder.defineMacro("__SSE4_1__");
1236  LLVM_FALLTHROUGH;
1237  case SSSE3:
1238  Builder.defineMacro("__SSSE3__");
1239  LLVM_FALLTHROUGH;
1240  case SSE3:
1241  Builder.defineMacro("__SSE3__");
1242  LLVM_FALLTHROUGH;
1243  case SSE2:
1244  Builder.defineMacro("__SSE2__");
1245  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1246  LLVM_FALLTHROUGH;
1247  case SSE1:
1248  Builder.defineMacro("__SSE__");
1249  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1250  LLVM_FALLTHROUGH;
1251  case NoSSE:
1252  break;
1253  }
1254 
1255  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1256  switch (SSELevel) {
1257  case AVX512F:
1258  case AVX2:
1259  case AVX:
1260  case SSE42:
1261  case SSE41:
1262  case SSSE3:
1263  case SSE3:
1264  case SSE2:
1265  Builder.defineMacro("_M_IX86_FP", Twine(2));
1266  break;
1267  case SSE1:
1268  Builder.defineMacro("_M_IX86_FP", Twine(1));
1269  break;
1270  default:
1271  Builder.defineMacro("_M_IX86_FP", Twine(0));
1272  break;
1273  }
1274  }
1275 
1276  // Each case falls through to the previous one here.
1277  switch (MMX3DNowLevel) {
1278  case AMD3DNowAthlon:
1279  Builder.defineMacro("__3dNOW_A__");
1280  LLVM_FALLTHROUGH;
1281  case AMD3DNow:
1282  Builder.defineMacro("__3dNOW__");
1283  LLVM_FALLTHROUGH;
1284  case MMX:
1285  Builder.defineMacro("__MMX__");
1286  LLVM_FALLTHROUGH;
1287  case NoMMX3DNow:
1288  break;
1289  }
1290 
1291  if (CPU >= CK_i486 || CPU == CK_Generic) {
1292  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1293  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1294  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1295  }
1296  if (HasCX8)
1297  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1298  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1299  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1300 
1301  if (HasFloat128)
1302  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1303 }
1304 
1305 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1306  return llvm::StringSwitch<bool>(Name)
1307  .Case("3dnow", true)
1308  .Case("3dnowa", true)
1309  .Case("adx", true)
1310  .Case("aes", true)
1311  .Case("avx", true)
1312  .Case("avx2", true)
1313  .Case("avx512f", true)
1314  .Case("avx512cd", true)
1315  .Case("avx512vpopcntdq", true)
1316  .Case("avx512vnni", true)
1317  .Case("avx512bf16", true)
1318  .Case("avx512er", true)
1319  .Case("avx512pf", true)
1320  .Case("avx512dq", true)
1321  .Case("avx512bitalg", true)
1322  .Case("avx512bw", true)
1323  .Case("avx512vl", true)
1324  .Case("avx512vbmi", true)
1325  .Case("avx512vbmi2", true)
1326  .Case("avx512ifma", true)
1327  .Case("bmi", true)
1328  .Case("bmi2", true)
1329  .Case("cldemote", true)
1330  .Case("clflushopt", true)
1331  .Case("clwb", true)
1332  .Case("clzero", true)
1333  .Case("cx16", true)
1334  .Case("f16c", true)
1335  .Case("fma", true)
1336  .Case("fma4", true)
1337  .Case("fsgsbase", true)
1338  .Case("fxsr", true)
1339  .Case("gfni", true)
1340  .Case("invpcid", true)
1341  .Case("lwp", true)
1342  .Case("lzcnt", true)
1343  .Case("mmx", true)
1344  .Case("movbe", true)
1345  .Case("movdiri", true)
1346  .Case("movdir64b", true)
1347  .Case("mpx", true)
1348  .Case("mwaitx", true)
1349  .Case("pclmul", true)
1350  .Case("pconfig", true)
1351  .Case("pku", true)
1352  .Case("popcnt", true)
1353  .Case("prefetchwt1", true)
1354  .Case("prfchw", true)
1355  .Case("ptwrite", true)
1356  .Case("rdpid", true)
1357  .Case("rdrnd", true)
1358  .Case("rdseed", true)
1359  .Case("rtm", true)
1360  .Case("sahf", true)
1361  .Case("sgx", true)
1362  .Case("sha", true)
1363  .Case("shstk", true)
1364  .Case("sse", true)
1365  .Case("sse2", true)
1366  .Case("sse3", true)
1367  .Case("ssse3", true)
1368  .Case("sse4", true)
1369  .Case("sse4.1", true)
1370  .Case("sse4.2", true)
1371  .Case("sse4a", true)
1372  .Case("tbm", true)
1373  .Case("vaes", true)
1374  .Case("vpclmulqdq", true)
1375  .Case("wbnoinvd", true)
1376  .Case("waitpkg", true)
1377  .Case("x87", true)
1378  .Case("xop", true)
1379  .Case("xsave", true)
1380  .Case("xsavec", true)
1381  .Case("xsaves", true)
1382  .Case("xsaveopt", true)
1383  .Default(false);
1384 }
1385 
1386 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1387  return llvm::StringSwitch<bool>(Feature)
1388  .Case("adx", HasADX)
1389  .Case("aes", HasAES)
1390  .Case("avx", SSELevel >= AVX)
1391  .Case("avx2", SSELevel >= AVX2)
1392  .Case("avx512f", SSELevel >= AVX512F)
1393  .Case("avx512cd", HasAVX512CD)
1394  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1395  .Case("avx512vnni", HasAVX512VNNI)
1396  .Case("avx512bf16", HasAVX512BF16)
1397  .Case("avx512er", HasAVX512ER)
1398  .Case("avx512pf", HasAVX512PF)
1399  .Case("avx512dq", HasAVX512DQ)
1400  .Case("avx512bitalg", HasAVX512BITALG)
1401  .Case("avx512bw", HasAVX512BW)
1402  .Case("avx512vl", HasAVX512VL)
1403  .Case("avx512vbmi", HasAVX512VBMI)
1404  .Case("avx512vbmi2", HasAVX512VBMI2)
1405  .Case("avx512ifma", HasAVX512IFMA)
1406  .Case("bmi", HasBMI)
1407  .Case("bmi2", HasBMI2)
1408  .Case("cldemote", HasCLDEMOTE)
1409  .Case("clflushopt", HasCLFLUSHOPT)
1410  .Case("clwb", HasCLWB)
1411  .Case("clzero", HasCLZERO)
1412  .Case("cx8", HasCX8)
1413  .Case("cx16", HasCX16)
1414  .Case("f16c", HasF16C)
1415  .Case("fma", HasFMA)
1416  .Case("fma4", XOPLevel >= FMA4)
1417  .Case("fsgsbase", HasFSGSBASE)
1418  .Case("fxsr", HasFXSR)
1419  .Case("gfni", HasGFNI)
1420  .Case("invpcid", HasINVPCID)
1421  .Case("lwp", HasLWP)
1422  .Case("lzcnt", HasLZCNT)
1423  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1424  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1425  .Case("mmx", MMX3DNowLevel >= MMX)
1426  .Case("movbe", HasMOVBE)
1427  .Case("movdiri", HasMOVDIRI)
1428  .Case("movdir64b", HasMOVDIR64B)
1429  .Case("mpx", HasMPX)
1430  .Case("mwaitx", HasMWAITX)
1431  .Case("pclmul", HasPCLMUL)
1432  .Case("pconfig", HasPCONFIG)
1433  .Case("pku", HasPKU)
1434  .Case("popcnt", HasPOPCNT)
1435  .Case("prefetchwt1", HasPREFETCHWT1)
1436  .Case("prfchw", HasPRFCHW)
1437  .Case("ptwrite", HasPTWRITE)
1438  .Case("rdpid", HasRDPID)
1439  .Case("rdrnd", HasRDRND)
1440  .Case("rdseed", HasRDSEED)
1441  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1442  .Case("rtm", HasRTM)
1443  .Case("sahf", HasLAHFSAHF)
1444  .Case("sgx", HasSGX)
1445  .Case("sha", HasSHA)
1446  .Case("shstk", HasSHSTK)
1447  .Case("sse", SSELevel >= SSE1)
1448  .Case("sse2", SSELevel >= SSE2)
1449  .Case("sse3", SSELevel >= SSE3)
1450  .Case("ssse3", SSELevel >= SSSE3)
1451  .Case("sse4.1", SSELevel >= SSE41)
1452  .Case("sse4.2", SSELevel >= SSE42)
1453  .Case("sse4a", XOPLevel >= SSE4A)
1454  .Case("tbm", HasTBM)
1455  .Case("vaes", HasVAES)
1456  .Case("vpclmulqdq", HasVPCLMULQDQ)
1457  .Case("wbnoinvd", HasWBNOINVD)
1458  .Case("waitpkg", HasWAITPKG)
1459  .Case("x86", true)
1460  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1461  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1462  .Case("xop", XOPLevel >= XOP)
1463  .Case("xsave", HasXSAVE)
1464  .Case("xsavec", HasXSAVEC)
1465  .Case("xsaves", HasXSAVES)
1466  .Case("xsaveopt", HasXSAVEOPT)
1467  .Default(false);
1468 }
1469 
1470 // We can't use a generic validation scheme for the features accepted here
1471 // versus subtarget features accepted in the target attribute because the
1472 // bitfield structure that's initialized in the runtime only supports the
1473 // below currently rather than the full range of subtarget features. (See
1474 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1475 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1476  return llvm::StringSwitch<bool>(FeatureStr)
1477 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1478 #include "llvm/Support/X86TargetParser.def"
1479  .Default(false);
1480 }
1481 
1482 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1483  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1484 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1485 #include "llvm/Support/X86TargetParser.def"
1486  ;
1487  // Note, this function should only be used after ensuring the value is
1488  // correct, so it asserts if the value is out of range.
1489 }
1490 
1491 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1492  enum class FeatPriority {
1493 #define FEATURE(FEAT) FEAT,
1494 #include "clang/Basic/X86Target.def"
1495  };
1496  switch (Feat) {
1497 #define FEATURE(FEAT) \
1498  case llvm::X86::FEAT: \
1499  return static_cast<unsigned>(FeatPriority::FEAT);
1500 #include "clang/Basic/X86Target.def"
1501  default:
1502  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1503  }
1504 }
1505 
1506 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1507  // Valid CPUs have a 'key feature' that compares just better than its key
1508  // feature.
1509  CPUKind Kind = getCPUKind(Name);
1510  if (Kind != CK_Generic) {
1511  switch (Kind) {
1512  default:
1513  llvm_unreachable(
1514  "CPU Type without a key feature used in 'target' attribute");
1515 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1516  case CK_##ENUM: \
1517  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1518 #include "clang/Basic/X86Target.def"
1519  }
1520  }
1521 
1522  // Now we know we have a feature, so get its priority and shift it a few so
1523  // that we have sufficient room for the CPUs (above).
1524  return getFeaturePriority(getFeature(Name)) << 1;
1525 }
1526 
1527 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1528  return llvm::StringSwitch<bool>(Name)
1529 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1530 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1531 #include "clang/Basic/X86Target.def"
1532  .Default(false);
1533 }
1534 
1535 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1536  return llvm::StringSwitch<StringRef>(Name)
1537 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1538 #include "clang/Basic/X86Target.def"
1539  .Default(Name);
1540 }
1541 
1542 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1543  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1544 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1545 #include "clang/Basic/X86Target.def"
1546  .Default(0);
1547 }
1548 
1549 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1550  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1551  StringRef WholeList =
1552  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1553 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1554 #include "clang/Basic/X86Target.def"
1555  .Default("");
1556  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1557 }
1558 
1559 // We can't use a generic validation scheme for the cpus accepted here
1560 // versus subtarget cpus accepted in the target attribute because the
1561 // variables intitialized by the runtime only support the below currently
1562 // rather than the full range of cpus.
1563 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1564  return llvm::StringSwitch<bool>(FeatureStr)
1565 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1566 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1567  .Cases(STR, ALIAS, true)
1568 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1569 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1570 #include "llvm/Support/X86TargetParser.def"
1571  .Default(false);
1572 }
1573 
1574 static unsigned matchAsmCCConstraint(const char *&Name) {
1575  auto RV = llvm::StringSwitch<unsigned>(Name)
1576  .Case("@cca", 4)
1577  .Case("@ccae", 5)
1578  .Case("@ccb", 4)
1579  .Case("@ccbe", 5)
1580  .Case("@ccc", 4)
1581  .Case("@cce", 4)
1582  .Case("@ccz", 4)
1583  .Case("@ccg", 4)
1584  .Case("@ccge", 5)
1585  .Case("@ccl", 4)
1586  .Case("@ccle", 5)
1587  .Case("@ccna", 5)
1588  .Case("@ccnae", 6)
1589  .Case("@ccnb", 5)
1590  .Case("@ccnbe", 6)
1591  .Case("@ccnc", 5)
1592  .Case("@ccne", 5)
1593  .Case("@ccnz", 5)
1594  .Case("@ccng", 5)
1595  .Case("@ccnge", 6)
1596  .Case("@ccnl", 5)
1597  .Case("@ccnle", 6)
1598  .Case("@ccno", 5)
1599  .Case("@ccnp", 5)
1600  .Case("@ccns", 5)
1601  .Case("@cco", 4)
1602  .Case("@ccp", 4)
1603  .Case("@ccs", 4)
1604  .Default(0);
1605  return RV;
1606 }
1607 
1608 bool X86TargetInfo::validateAsmConstraint(
1609  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1610  switch (*Name) {
1611  default:
1612  return false;
1613  // Constant constraints.
1614  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1615  // instructions.
1616  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1617  // x86_64 instructions.
1618  case 's':
1619  Info.setRequiresImmediate();
1620  return true;
1621  case 'I':
1622  Info.setRequiresImmediate(0, 31);
1623  return true;
1624  case 'J':
1625  Info.setRequiresImmediate(0, 63);
1626  return true;
1627  case 'K':
1628  Info.setRequiresImmediate(-128, 127);
1629  return true;
1630  case 'L':
1631  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1632  return true;
1633  case 'M':
1634  Info.setRequiresImmediate(0, 3);
1635  return true;
1636  case 'N':
1637  Info.setRequiresImmediate(0, 255);
1638  return true;
1639  case 'O':
1640  Info.setRequiresImmediate(0, 127);
1641  return true;
1642  // Register constraints.
1643  case 'Y': // 'Y' is the first character for several 2-character constraints.
1644  // Shift the pointer to the second character of the constraint.
1645  Name++;
1646  switch (*Name) {
1647  default:
1648  return false;
1649  case 'z':
1650  case '0': // First SSE register.
1651  case '2':
1652  case 't': // Any SSE register, when SSE2 is enabled.
1653  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1654  case 'm': // Any MMX register, when inter-unit moves enabled.
1655  case 'k': // AVX512 arch mask registers: k1-k7.
1656  Info.setAllowsRegister();
1657  return true;
1658  }
1659  case 'f': // Any x87 floating point stack register.
1660  // Constraint 'f' cannot be used for output operands.
1661  if (Info.ConstraintStr[0] == '=')
1662  return false;
1663  Info.setAllowsRegister();
1664  return true;
1665  case 'a': // eax.
1666  case 'b': // ebx.
1667  case 'c': // ecx.
1668  case 'd': // edx.
1669  case 'S': // esi.
1670  case 'D': // edi.
1671  case 'A': // edx:eax.
1672  case 't': // Top of floating point stack.
1673  case 'u': // Second from top of floating point stack.
1674  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1675  case 'y': // Any MMX register.
1676  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1677  case 'x': // Any SSE register.
1678  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1679  // for intermideate k reg operations).
1680  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1681  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1682  case 'l': // "Index" registers: any general register that can be used as an
1683  // index in a base+index memory access.
1684  Info.setAllowsRegister();
1685  return true;
1686  // Floating point constant constraints.
1687  case 'C': // SSE floating point constant.
1688  case 'G': // x87 floating point constant.
1689  return true;
1690  case '@':
1691  // CC condition changes.
1692  if (auto Len = matchAsmCCConstraint(Name)) {
1693  Name += Len - 1;
1694  Info.setAllowsRegister();
1695  return true;
1696  }
1697  return false;
1698  }
1699 }
1700 
1701 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1702  unsigned Size) const {
1703  // Strip off constraint modifiers.
1704  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1705  Constraint = Constraint.substr(1);
1706 
1707  return validateOperandSize(Constraint, Size);
1708 }
1709 
1710 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1711  unsigned Size) const {
1712  return validateOperandSize(Constraint, Size);
1713 }
1714 
1715 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1716  unsigned Size) const {
1717  switch (Constraint[0]) {
1718  default:
1719  break;
1720  case 'k':
1721  // Registers k0-k7 (AVX512) size limit is 64 bit.
1722  case 'y':
1723  return Size <= 64;
1724  case 'f':
1725  case 't':
1726  case 'u':
1727  return Size <= 128;
1728  case 'Y':
1729  // 'Y' is the first character for several 2-character constraints.
1730  switch (Constraint[1]) {
1731  default:
1732  return false;
1733  case 'm':
1734  // 'Ym' is synonymous with 'y'.
1735  case 'k':
1736  return Size <= 64;
1737  case 'z':
1738  case '0':
1739  // XMM0
1740  if (SSELevel >= SSE1)
1741  return Size <= 128U;
1742  return false;
1743  case 'i':
1744  case 't':
1745  case '2':
1746  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1747  if (SSELevel < SSE2)
1748  return false;
1749  break;
1750  }
1751  LLVM_FALLTHROUGH;
1752  case 'v':
1753  case 'x':
1754  if (SSELevel >= AVX512F)
1755  // 512-bit zmm registers can be used if target supports AVX512F.
1756  return Size <= 512U;
1757  else if (SSELevel >= AVX)
1758  // 256-bit ymm registers can be used if target supports AVX.
1759  return Size <= 256U;
1760  return Size <= 128U;
1761 
1762  }
1763 
1764  return true;
1765 }
1766 
1767 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1768  switch (*Constraint) {
1769  case '@':
1770  if (auto Len = matchAsmCCConstraint(Constraint)) {
1771  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1772  Constraint += Len - 1;
1773  return Converted;
1774  }
1775  return std::string(1, *Constraint);
1776  case 'a':
1777  return std::string("{ax}");
1778  case 'b':
1779  return std::string("{bx}");
1780  case 'c':
1781  return std::string("{cx}");
1782  case 'd':
1783  return std::string("{dx}");
1784  case 'S':
1785  return std::string("{si}");
1786  case 'D':
1787  return std::string("{di}");
1788  case 'p': // address
1789  return std::string("im");
1790  case 't': // top of floating point stack.
1791  return std::string("{st}");
1792  case 'u': // second from top of floating point stack.
1793  return std::string("{st(1)}"); // second from top of floating point stack.
1794  case 'Y':
1795  switch (Constraint[1]) {
1796  default:
1797  // Break from inner switch and fall through (copy single char),
1798  // continue parsing after copying the current constraint into
1799  // the return string.
1800  break;
1801  case 'k':
1802  case 'm':
1803  case 'i':
1804  case 't':
1805  case 'z':
1806  case '0':
1807  case '2':
1808  // "^" hints llvm that this is a 2 letter constraint.
1809  // "Constraint++" is used to promote the string iterator
1810  // to the next constraint.
1811  return std::string("^") + std::string(Constraint++, 2);
1812  }
1813  LLVM_FALLTHROUGH;
1814  default:
1815  return std::string(1, *Constraint);
1816  }
1817 }
1818 
1819 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1820  // Perform any per-CPU checks necessary to determine if this CPU is
1821  // acceptable.
1822  switch (Kind) {
1823  case CK_Generic:
1824  // No processor selected!
1825  return false;
1826 #define PROC(ENUM, STRING, IS64BIT) \
1827  case CK_##ENUM: \
1828  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1829 #include "clang/Basic/X86Target.def"
1830  }
1831  llvm_unreachable("Unhandled CPU kind");
1832 }
1833 
1834 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1835 #define PROC(ENUM, STRING, IS64BIT) \
1836  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1837  Values.emplace_back(STRING);
1838  // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
1839 #define PROC_ALIAS(ENUM, ALIAS) \
1840  if (checkCPUKind(CK_##ENUM)) \
1841  Values.emplace_back(ALIAS);
1842 #include "clang/Basic/X86Target.def"
1843 }
1844 
1845 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1846  return llvm::StringSwitch<CPUKind>(CPU)
1847 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1848 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1849 #include "clang/Basic/X86Target.def"
1850  .Default(CK_Generic);
1851 }
1852 
1853 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1854  return llvm::makeArrayRef(GCCRegNames);
1855 }
1856 
1857 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1858  return llvm::makeArrayRef(AddlRegNames);
1859 }
1860 
1861 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1862  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1863  Builtin::FirstTSBuiltin + 1);
1864 }
1865 
1866 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1867  return llvm::makeArrayRef(BuiltinInfoX86,
1868  X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1869 }
clang::targets::DefineStd
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:54
hasFeature
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:92
clang::targets::BuiltinInfoX86
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
clang::targets::X86TargetInfo::setMMXLevel
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:529
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1296
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1701
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1857
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void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:888
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1715
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1834
clang::targets::X86TargetInfo::setXOPLevel
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:562
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *&Name)
Definition: X86.cpp:1574
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const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:67
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:49
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1475
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1549
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#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
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Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:148
Diagnostic.h
Defines the Diagnostic-related interfaces.
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1482
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#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1608
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition: X86.cpp:43
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1527
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1305
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#define X86_VENDOR(ENUM, STRING)
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:385
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static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1535
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CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1845
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1386
clang::targets::X86TargetInfo::setSSELevel
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:449
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
clang::targets::X86TargetInfo::CPUKind
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:116
clang::targets::X86_64TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1866
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Kind
Definition: ChrootChecker.cpp:28
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static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1491
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std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1767
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ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1861
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char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1542
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Dataflow Directional Tag Classes.
Definition: CFGReachabilityAnalysis.h:21
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unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1506
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#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:709
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1710
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:883
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#define PROC(ENUM, STRING, IS64BIT)
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__DEVICE__ int max(int __a, int __b)
Definition: __clang_cuda_device_functions.h:1628
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bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1819
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void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:70
clang::MacroBuilder::defineMacro
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:29
clang::targets::X86TargetInfo::setFeatureEnabledImpl
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:597
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bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1563
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1853
Builtins.h
Defines enum values for all the target-independent builtin functions.
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:104
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