clang  15.0.0git
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/X86TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65  "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabled(Features, "sse2", true);
112 
113  using namespace llvm::X86;
114 
115  SmallVector<StringRef, 16> CPUFeatures;
116  getFeaturesForCPU(CPU, CPUFeatures);
117  for (auto &F : CPUFeatures)
118  setFeatureEnabled(Features, F, true);
119 
120  std::vector<std::string> UpdatedFeaturesVec;
121  for (const auto &Feature : FeaturesVec) {
122  // Expand general-regs-only to -x86, -mmx and -sse
123  if (Feature == "+general-regs-only") {
124  UpdatedFeaturesVec.push_back("-x87");
125  UpdatedFeaturesVec.push_back("-mmx");
126  UpdatedFeaturesVec.push_back("-sse");
127  continue;
128  }
129 
130  UpdatedFeaturesVec.push_back(Feature);
131  }
132 
133  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134  return false;
135 
136  // Can't do this earlier because we need to be able to explicitly enable
137  // or disable these features and the things that they depend upon.
138 
139  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140  auto I = Features.find("sse4.2");
141  if (I != Features.end() && I->getValue() &&
142  !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
143  Features["popcnt"] = true;
144 
145  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146  // then enable MMX.
147  I = Features.find("sse");
148  if (I != Features.end() && I->getValue() &&
149  !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
150  Features["mmx"] = true;
151 
152  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153  I = Features.find("avx");
154  if (I != Features.end() && I->getValue() &&
155  !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
156  Features["xsave"] = true;
157 
158  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
159  I = Features.find("sse4.2");
160  if (I != Features.end() && I->getValue() &&
161  !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
162  Features["crc32"] = true;
163 
164  return true;
165 }
166 
167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
168  StringRef Name, bool Enabled) const {
169  if (Name == "sse4") {
170  // We can get here via the __target__ attribute since that's not controlled
171  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
172  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
173  // disabled.
174  if (Enabled)
175  Name = "sse4.2";
176  else
177  Name = "sse4.1";
178  }
179 
180  Features[Name] = Enabled;
181  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
182 }
183 
184 /// handleTargetFeatures - Perform initialization based on the user
185 /// configured set of features.
186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
187  DiagnosticsEngine &Diags) {
188  for (const auto &Feature : Features) {
189  if (Feature[0] != '+')
190  continue;
191 
192  if (Feature == "+aes") {
193  HasAES = true;
194  } else if (Feature == "+vaes") {
195  HasVAES = true;
196  } else if (Feature == "+pclmul") {
197  HasPCLMUL = true;
198  } else if (Feature == "+vpclmulqdq") {
199  HasVPCLMULQDQ = true;
200  } else if (Feature == "+lzcnt") {
201  HasLZCNT = true;
202  } else if (Feature == "+rdrnd") {
203  HasRDRND = true;
204  } else if (Feature == "+fsgsbase") {
205  HasFSGSBASE = true;
206  } else if (Feature == "+bmi") {
207  HasBMI = true;
208  } else if (Feature == "+bmi2") {
209  HasBMI2 = true;
210  } else if (Feature == "+popcnt") {
211  HasPOPCNT = true;
212  } else if (Feature == "+rtm") {
213  HasRTM = true;
214  } else if (Feature == "+prfchw") {
215  HasPRFCHW = true;
216  } else if (Feature == "+rdseed") {
217  HasRDSEED = true;
218  } else if (Feature == "+adx") {
219  HasADX = true;
220  } else if (Feature == "+tbm") {
221  HasTBM = true;
222  } else if (Feature == "+lwp") {
223  HasLWP = true;
224  } else if (Feature == "+fma") {
225  HasFMA = true;
226  } else if (Feature == "+f16c") {
227  HasF16C = true;
228  } else if (Feature == "+gfni") {
229  HasGFNI = true;
230  } else if (Feature == "+avx512cd") {
231  HasAVX512CD = true;
232  } else if (Feature == "+avx512vpopcntdq") {
233  HasAVX512VPOPCNTDQ = true;
234  } else if (Feature == "+avx512vnni") {
235  HasAVX512VNNI = true;
236  } else if (Feature == "+avx512bf16") {
237  HasAVX512BF16 = true;
238  } else if (Feature == "+avx512er") {
239  HasAVX512ER = true;
240  } else if (Feature == "+avx512fp16") {
241  HasAVX512FP16 = true;
242  HasFloat16 = true;
243  } else if (Feature == "+avx512pf") {
244  HasAVX512PF = true;
245  } else if (Feature == "+avx512dq") {
246  HasAVX512DQ = true;
247  } else if (Feature == "+avx512bitalg") {
248  HasAVX512BITALG = true;
249  } else if (Feature == "+avx512bw") {
250  HasAVX512BW = true;
251  } else if (Feature == "+avx512vl") {
252  HasAVX512VL = true;
253  } else if (Feature == "+avx512vbmi") {
254  HasAVX512VBMI = true;
255  } else if (Feature == "+avx512vbmi2") {
256  HasAVX512VBMI2 = true;
257  } else if (Feature == "+avx512ifma") {
258  HasAVX512IFMA = true;
259  } else if (Feature == "+avx512vp2intersect") {
260  HasAVX512VP2INTERSECT = true;
261  } else if (Feature == "+sha") {
262  HasSHA = true;
263  } else if (Feature == "+shstk") {
264  HasSHSTK = true;
265  } else if (Feature == "+movbe") {
266  HasMOVBE = true;
267  } else if (Feature == "+sgx") {
268  HasSGX = true;
269  } else if (Feature == "+cx8") {
270  HasCX8 = true;
271  } else if (Feature == "+cx16") {
272  HasCX16 = true;
273  } else if (Feature == "+fxsr") {
274  HasFXSR = true;
275  } else if (Feature == "+xsave") {
276  HasXSAVE = true;
277  } else if (Feature == "+xsaveopt") {
278  HasXSAVEOPT = true;
279  } else if (Feature == "+xsavec") {
280  HasXSAVEC = true;
281  } else if (Feature == "+xsaves") {
282  HasXSAVES = true;
283  } else if (Feature == "+mwaitx") {
284  HasMWAITX = true;
285  } else if (Feature == "+pku") {
286  HasPKU = true;
287  } else if (Feature == "+clflushopt") {
288  HasCLFLUSHOPT = true;
289  } else if (Feature == "+clwb") {
290  HasCLWB = true;
291  } else if (Feature == "+wbnoinvd") {
292  HasWBNOINVD = true;
293  } else if (Feature == "+prefetchwt1") {
294  HasPREFETCHWT1 = true;
295  } else if (Feature == "+clzero") {
296  HasCLZERO = true;
297  } else if (Feature == "+cldemote") {
298  HasCLDEMOTE = true;
299  } else if (Feature == "+rdpid") {
300  HasRDPID = true;
301  } else if (Feature == "+kl") {
302  HasKL = true;
303  } else if (Feature == "+widekl") {
304  HasWIDEKL = true;
305  } else if (Feature == "+retpoline-external-thunk") {
306  HasRetpolineExternalThunk = true;
307  } else if (Feature == "+sahf") {
308  HasLAHFSAHF = true;
309  } else if (Feature == "+waitpkg") {
310  HasWAITPKG = true;
311  } else if (Feature == "+movdiri") {
312  HasMOVDIRI = true;
313  } else if (Feature == "+movdir64b") {
314  HasMOVDIR64B = true;
315  } else if (Feature == "+pconfig") {
316  HasPCONFIG = true;
317  } else if (Feature == "+ptwrite") {
318  HasPTWRITE = true;
319  } else if (Feature == "+invpcid") {
320  HasINVPCID = true;
321  } else if (Feature == "+enqcmd") {
322  HasENQCMD = true;
323  } else if (Feature == "+hreset") {
324  HasHRESET = true;
325  } else if (Feature == "+amx-bf16") {
326  HasAMXBF16 = true;
327  } else if (Feature == "+amx-int8") {
328  HasAMXINT8 = true;
329  } else if (Feature == "+amx-tile") {
330  HasAMXTILE = true;
331  } else if (Feature == "+avxvnni") {
332  HasAVXVNNI = true;
333  } else if (Feature == "+serialize") {
334  HasSERIALIZE = true;
335  } else if (Feature == "+tsxldtrk") {
336  HasTSXLDTRK = true;
337  } else if (Feature == "+uintr") {
338  HasUINTR = true;
339  } else if (Feature == "+crc32") {
340  HasCRC32 = true;
341  } else if (Feature == "+x87") {
342  HasX87 = true;
343  }
344 
345  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
346  .Case("+avx512f", AVX512F)
347  .Case("+avx2", AVX2)
348  .Case("+avx", AVX)
349  .Case("+sse4.2", SSE42)
350  .Case("+sse4.1", SSE41)
351  .Case("+ssse3", SSSE3)
352  .Case("+sse3", SSE3)
353  .Case("+sse2", SSE2)
354  .Case("+sse", SSE1)
355  .Default(NoSSE);
356  SSELevel = std::max(SSELevel, Level);
357 
358  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
359  .Case("+3dnowa", AMD3DNowAthlon)
360  .Case("+3dnow", AMD3DNow)
361  .Case("+mmx", MMX)
362  .Default(NoMMX3DNow);
363  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
364 
365  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
366  .Case("+xop", XOP)
367  .Case("+fma4", FMA4)
368  .Case("+sse4a", SSE4A)
369  .Default(NoXOP);
370  XOPLevel = std::max(XOPLevel, XLevel);
371  }
372 
373  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
374  // matches the selected sse level.
375  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
376  (FPMath == FP_387 && SSELevel >= SSE1)) {
377  Diags.Report(diag::err_target_unsupported_fpmath)
378  << (FPMath == FP_SSE ? "sse" : "387");
379  return false;
380  }
381 
383  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
384 
385  // FIXME: We should allow long double type on 32-bits to match with GCC.
386  // This requires backend to be able to lower f80 without x87 first.
387  if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
388  HasLongDouble = false;
389 
390  return true;
391 }
392 
393 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
394 /// definitions for this particular subtarget.
396  MacroBuilder &Builder) const {
397  // Inline assembly supports X86 flag outputs.
398  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
399 
400  std::string CodeModel = getTargetOpts().CodeModel;
401  if (CodeModel == "default")
402  CodeModel = "small";
403  Builder.defineMacro("__code_model_" + CodeModel + "__");
404 
405  // Target identification.
406  if (getTriple().getArch() == llvm::Triple::x86_64) {
407  Builder.defineMacro("__amd64__");
408  Builder.defineMacro("__amd64");
409  Builder.defineMacro("__x86_64");
410  Builder.defineMacro("__x86_64__");
411  if (getTriple().getArchName() == "x86_64h") {
412  Builder.defineMacro("__x86_64h");
413  Builder.defineMacro("__x86_64h__");
414  }
415  } else {
416  DefineStd(Builder, "i386", Opts);
417  }
418 
419  Builder.defineMacro("__SEG_GS");
420  Builder.defineMacro("__SEG_FS");
421  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
422  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
423 
424  // Subtarget options.
425  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
426  // truly should be based on -mtune options.
427  using namespace llvm::X86;
428  switch (CPU) {
429  case CK_None:
430  break;
431  case CK_i386:
432  // The rest are coming from the i386 define above.
433  Builder.defineMacro("__tune_i386__");
434  break;
435  case CK_i486:
436  case CK_WinChipC6:
437  case CK_WinChip2:
438  case CK_C3:
439  defineCPUMacros(Builder, "i486");
440  break;
441  case CK_PentiumMMX:
442  Builder.defineMacro("__pentium_mmx__");
443  Builder.defineMacro("__tune_pentium_mmx__");
444  LLVM_FALLTHROUGH;
445  case CK_i586:
446  case CK_Pentium:
447  defineCPUMacros(Builder, "i586");
448  defineCPUMacros(Builder, "pentium");
449  break;
450  case CK_Pentium3:
451  case CK_PentiumM:
452  Builder.defineMacro("__tune_pentium3__");
453  LLVM_FALLTHROUGH;
454  case CK_Pentium2:
455  case CK_C3_2:
456  Builder.defineMacro("__tune_pentium2__");
457  LLVM_FALLTHROUGH;
458  case CK_PentiumPro:
459  case CK_i686:
460  defineCPUMacros(Builder, "i686");
461  defineCPUMacros(Builder, "pentiumpro");
462  break;
463  case CK_Pentium4:
464  defineCPUMacros(Builder, "pentium4");
465  break;
466  case CK_Yonah:
467  case CK_Prescott:
468  case CK_Nocona:
469  defineCPUMacros(Builder, "nocona");
470  break;
471  case CK_Core2:
472  case CK_Penryn:
473  defineCPUMacros(Builder, "core2");
474  break;
475  case CK_Bonnell:
476  defineCPUMacros(Builder, "atom");
477  break;
478  case CK_Silvermont:
479  defineCPUMacros(Builder, "slm");
480  break;
481  case CK_Goldmont:
482  defineCPUMacros(Builder, "goldmont");
483  break;
484  case CK_GoldmontPlus:
485  defineCPUMacros(Builder, "goldmont_plus");
486  break;
487  case CK_Tremont:
488  defineCPUMacros(Builder, "tremont");
489  break;
490  case CK_Nehalem:
491  case CK_Westmere:
492  case CK_SandyBridge:
493  case CK_IvyBridge:
494  case CK_Haswell:
495  case CK_Broadwell:
496  case CK_SkylakeClient:
497  case CK_SkylakeServer:
498  case CK_Cascadelake:
499  case CK_Cooperlake:
500  case CK_Cannonlake:
501  case CK_IcelakeClient:
502  case CK_Rocketlake:
503  case CK_IcelakeServer:
504  case CK_Tigerlake:
505  case CK_SapphireRapids:
506  case CK_Alderlake:
507  // FIXME: Historically, we defined this legacy name, it would be nice to
508  // remove it at some point. We've never exposed fine-grained names for
509  // recent primary x86 CPUs, and we should keep it that way.
510  defineCPUMacros(Builder, "corei7");
511  break;
512  case CK_KNL:
513  defineCPUMacros(Builder, "knl");
514  break;
515  case CK_KNM:
516  break;
517  case CK_Lakemont:
518  defineCPUMacros(Builder, "i586", /*Tuning*/false);
519  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
520  Builder.defineMacro("__tune_lakemont__");
521  break;
522  case CK_K6_2:
523  Builder.defineMacro("__k6_2__");
524  Builder.defineMacro("__tune_k6_2__");
525  LLVM_FALLTHROUGH;
526  case CK_K6_3:
527  if (CPU != CK_K6_2) { // In case of fallthrough
528  // FIXME: GCC may be enabling these in cases where some other k6
529  // architecture is specified but -m3dnow is explicitly provided. The
530  // exact semantics need to be determined and emulated here.
531  Builder.defineMacro("__k6_3__");
532  Builder.defineMacro("__tune_k6_3__");
533  }
534  LLVM_FALLTHROUGH;
535  case CK_K6:
536  defineCPUMacros(Builder, "k6");
537  break;
538  case CK_Athlon:
539  case CK_AthlonXP:
540  defineCPUMacros(Builder, "athlon");
541  if (SSELevel != NoSSE) {
542  Builder.defineMacro("__athlon_sse__");
543  Builder.defineMacro("__tune_athlon_sse__");
544  }
545  break;
546  case CK_K8:
547  case CK_K8SSE3:
548  case CK_x86_64:
549  defineCPUMacros(Builder, "k8");
550  break;
551  case CK_x86_64_v2:
552  case CK_x86_64_v3:
553  case CK_x86_64_v4:
554  break;
555  case CK_AMDFAM10:
556  defineCPUMacros(Builder, "amdfam10");
557  break;
558  case CK_BTVER1:
559  defineCPUMacros(Builder, "btver1");
560  break;
561  case CK_BTVER2:
562  defineCPUMacros(Builder, "btver2");
563  break;
564  case CK_BDVER1:
565  defineCPUMacros(Builder, "bdver1");
566  break;
567  case CK_BDVER2:
568  defineCPUMacros(Builder, "bdver2");
569  break;
570  case CK_BDVER3:
571  defineCPUMacros(Builder, "bdver3");
572  break;
573  case CK_BDVER4:
574  defineCPUMacros(Builder, "bdver4");
575  break;
576  case CK_ZNVER1:
577  defineCPUMacros(Builder, "znver1");
578  break;
579  case CK_ZNVER2:
580  defineCPUMacros(Builder, "znver2");
581  break;
582  case CK_ZNVER3:
583  defineCPUMacros(Builder, "znver3");
584  break;
585  case CK_Geode:
586  defineCPUMacros(Builder, "geode");
587  break;
588  }
589 
590  // Target properties.
591  Builder.defineMacro("__REGISTER_PREFIX__", "");
592 
593  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
594  // functions in glibc header files that use FP Stack inline asm which the
595  // backend can't deal with (PR879).
596  Builder.defineMacro("__NO_MATH_INLINES");
597 
598  if (HasAES)
599  Builder.defineMacro("__AES__");
600 
601  if (HasVAES)
602  Builder.defineMacro("__VAES__");
603 
604  if (HasPCLMUL)
605  Builder.defineMacro("__PCLMUL__");
606 
607  if (HasVPCLMULQDQ)
608  Builder.defineMacro("__VPCLMULQDQ__");
609 
610  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
611  // the feature flag only applies to 64-bit mode.
612  if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
613  Builder.defineMacro("__LAHF_SAHF__");
614 
615  if (HasLZCNT)
616  Builder.defineMacro("__LZCNT__");
617 
618  if (HasRDRND)
619  Builder.defineMacro("__RDRND__");
620 
621  if (HasFSGSBASE)
622  Builder.defineMacro("__FSGSBASE__");
623 
624  if (HasBMI)
625  Builder.defineMacro("__BMI__");
626 
627  if (HasBMI2)
628  Builder.defineMacro("__BMI2__");
629 
630  if (HasPOPCNT)
631  Builder.defineMacro("__POPCNT__");
632 
633  if (HasRTM)
634  Builder.defineMacro("__RTM__");
635 
636  if (HasPRFCHW)
637  Builder.defineMacro("__PRFCHW__");
638 
639  if (HasRDSEED)
640  Builder.defineMacro("__RDSEED__");
641 
642  if (HasADX)
643  Builder.defineMacro("__ADX__");
644 
645  if (HasTBM)
646  Builder.defineMacro("__TBM__");
647 
648  if (HasLWP)
649  Builder.defineMacro("__LWP__");
650 
651  if (HasMWAITX)
652  Builder.defineMacro("__MWAITX__");
653 
654  if (HasMOVBE)
655  Builder.defineMacro("__MOVBE__");
656 
657  switch (XOPLevel) {
658  case XOP:
659  Builder.defineMacro("__XOP__");
660  LLVM_FALLTHROUGH;
661  case FMA4:
662  Builder.defineMacro("__FMA4__");
663  LLVM_FALLTHROUGH;
664  case SSE4A:
665  Builder.defineMacro("__SSE4A__");
666  LLVM_FALLTHROUGH;
667  case NoXOP:
668  break;
669  }
670 
671  if (HasFMA)
672  Builder.defineMacro("__FMA__");
673 
674  if (HasF16C)
675  Builder.defineMacro("__F16C__");
676 
677  if (HasGFNI)
678  Builder.defineMacro("__GFNI__");
679 
680  if (HasAVX512CD)
681  Builder.defineMacro("__AVX512CD__");
682  if (HasAVX512VPOPCNTDQ)
683  Builder.defineMacro("__AVX512VPOPCNTDQ__");
684  if (HasAVX512VNNI)
685  Builder.defineMacro("__AVX512VNNI__");
686  if (HasAVX512BF16)
687  Builder.defineMacro("__AVX512BF16__");
688  if (HasAVX512ER)
689  Builder.defineMacro("__AVX512ER__");
690  if (HasAVX512FP16)
691  Builder.defineMacro("__AVX512FP16__");
692  if (HasAVX512PF)
693  Builder.defineMacro("__AVX512PF__");
694  if (HasAVX512DQ)
695  Builder.defineMacro("__AVX512DQ__");
696  if (HasAVX512BITALG)
697  Builder.defineMacro("__AVX512BITALG__");
698  if (HasAVX512BW)
699  Builder.defineMacro("__AVX512BW__");
700  if (HasAVX512VL)
701  Builder.defineMacro("__AVX512VL__");
702  if (HasAVX512VBMI)
703  Builder.defineMacro("__AVX512VBMI__");
704  if (HasAVX512VBMI2)
705  Builder.defineMacro("__AVX512VBMI2__");
706  if (HasAVX512IFMA)
707  Builder.defineMacro("__AVX512IFMA__");
708  if (HasAVX512VP2INTERSECT)
709  Builder.defineMacro("__AVX512VP2INTERSECT__");
710  if (HasSHA)
711  Builder.defineMacro("__SHA__");
712 
713  if (HasFXSR)
714  Builder.defineMacro("__FXSR__");
715  if (HasXSAVE)
716  Builder.defineMacro("__XSAVE__");
717  if (HasXSAVEOPT)
718  Builder.defineMacro("__XSAVEOPT__");
719  if (HasXSAVEC)
720  Builder.defineMacro("__XSAVEC__");
721  if (HasXSAVES)
722  Builder.defineMacro("__XSAVES__");
723  if (HasPKU)
724  Builder.defineMacro("__PKU__");
725  if (HasCLFLUSHOPT)
726  Builder.defineMacro("__CLFLUSHOPT__");
727  if (HasCLWB)
728  Builder.defineMacro("__CLWB__");
729  if (HasWBNOINVD)
730  Builder.defineMacro("__WBNOINVD__");
731  if (HasSHSTK)
732  Builder.defineMacro("__SHSTK__");
733  if (HasSGX)
734  Builder.defineMacro("__SGX__");
735  if (HasPREFETCHWT1)
736  Builder.defineMacro("__PREFETCHWT1__");
737  if (HasCLZERO)
738  Builder.defineMacro("__CLZERO__");
739  if (HasKL)
740  Builder.defineMacro("__KL__");
741  if (HasWIDEKL)
742  Builder.defineMacro("__WIDEKL__");
743  if (HasRDPID)
744  Builder.defineMacro("__RDPID__");
745  if (HasCLDEMOTE)
746  Builder.defineMacro("__CLDEMOTE__");
747  if (HasWAITPKG)
748  Builder.defineMacro("__WAITPKG__");
749  if (HasMOVDIRI)
750  Builder.defineMacro("__MOVDIRI__");
751  if (HasMOVDIR64B)
752  Builder.defineMacro("__MOVDIR64B__");
753  if (HasPCONFIG)
754  Builder.defineMacro("__PCONFIG__");
755  if (HasPTWRITE)
756  Builder.defineMacro("__PTWRITE__");
757  if (HasINVPCID)
758  Builder.defineMacro("__INVPCID__");
759  if (HasENQCMD)
760  Builder.defineMacro("__ENQCMD__");
761  if (HasHRESET)
762  Builder.defineMacro("__HRESET__");
763  if (HasAMXTILE)
764  Builder.defineMacro("__AMXTILE__");
765  if (HasAMXINT8)
766  Builder.defineMacro("__AMXINT8__");
767  if (HasAMXBF16)
768  Builder.defineMacro("__AMXBF16__");
769  if (HasAVXVNNI)
770  Builder.defineMacro("__AVXVNNI__");
771  if (HasSERIALIZE)
772  Builder.defineMacro("__SERIALIZE__");
773  if (HasTSXLDTRK)
774  Builder.defineMacro("__TSXLDTRK__");
775  if (HasUINTR)
776  Builder.defineMacro("__UINTR__");
777  if (HasCRC32)
778  Builder.defineMacro("__CRC32__");
779 
780  // Each case falls through to the previous one here.
781  switch (SSELevel) {
782  case AVX512F:
783  Builder.defineMacro("__AVX512F__");
784  LLVM_FALLTHROUGH;
785  case AVX2:
786  Builder.defineMacro("__AVX2__");
787  LLVM_FALLTHROUGH;
788  case AVX:
789  Builder.defineMacro("__AVX__");
790  LLVM_FALLTHROUGH;
791  case SSE42:
792  Builder.defineMacro("__SSE4_2__");
793  LLVM_FALLTHROUGH;
794  case SSE41:
795  Builder.defineMacro("__SSE4_1__");
796  LLVM_FALLTHROUGH;
797  case SSSE3:
798  Builder.defineMacro("__SSSE3__");
799  LLVM_FALLTHROUGH;
800  case SSE3:
801  Builder.defineMacro("__SSE3__");
802  LLVM_FALLTHROUGH;
803  case SSE2:
804  Builder.defineMacro("__SSE2__");
805  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
806  LLVM_FALLTHROUGH;
807  case SSE1:
808  Builder.defineMacro("__SSE__");
809  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
810  LLVM_FALLTHROUGH;
811  case NoSSE:
812  break;
813  }
814 
815  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
816  switch (SSELevel) {
817  case AVX512F:
818  case AVX2:
819  case AVX:
820  case SSE42:
821  case SSE41:
822  case SSSE3:
823  case SSE3:
824  case SSE2:
825  Builder.defineMacro("_M_IX86_FP", Twine(2));
826  break;
827  case SSE1:
828  Builder.defineMacro("_M_IX86_FP", Twine(1));
829  break;
830  default:
831  Builder.defineMacro("_M_IX86_FP", Twine(0));
832  break;
833  }
834  }
835 
836  // Each case falls through to the previous one here.
837  switch (MMX3DNowLevel) {
838  case AMD3DNowAthlon:
839  Builder.defineMacro("__3dNOW_A__");
840  LLVM_FALLTHROUGH;
841  case AMD3DNow:
842  Builder.defineMacro("__3dNOW__");
843  LLVM_FALLTHROUGH;
844  case MMX:
845  Builder.defineMacro("__MMX__");
846  LLVM_FALLTHROUGH;
847  case NoMMX3DNow:
848  break;
849  }
850 
851  if (CPU >= CK_i486 || CPU == CK_None) {
852  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
853  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
854  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
855  }
856  if (HasCX8)
857  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
858  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
859  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
860 
861  if (HasFloat128)
862  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
863 }
864 
865 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
866  return llvm::StringSwitch<bool>(Name)
867  .Case("3dnow", true)
868  .Case("3dnowa", true)
869  .Case("adx", true)
870  .Case("aes", true)
871  .Case("amx-bf16", true)
872  .Case("amx-int8", true)
873  .Case("amx-tile", true)
874  .Case("avx", true)
875  .Case("avx2", true)
876  .Case("avx512f", true)
877  .Case("avx512cd", true)
878  .Case("avx512vpopcntdq", true)
879  .Case("avx512vnni", true)
880  .Case("avx512bf16", true)
881  .Case("avx512er", true)
882  .Case("avx512fp16", true)
883  .Case("avx512pf", true)
884  .Case("avx512dq", true)
885  .Case("avx512bitalg", true)
886  .Case("avx512bw", true)
887  .Case("avx512vl", true)
888  .Case("avx512vbmi", true)
889  .Case("avx512vbmi2", true)
890  .Case("avx512ifma", true)
891  .Case("avx512vp2intersect", true)
892  .Case("avxvnni", true)
893  .Case("bmi", true)
894  .Case("bmi2", true)
895  .Case("cldemote", true)
896  .Case("clflushopt", true)
897  .Case("clwb", true)
898  .Case("clzero", true)
899  .Case("crc32", true)
900  .Case("cx16", true)
901  .Case("enqcmd", true)
902  .Case("f16c", true)
903  .Case("fma", true)
904  .Case("fma4", true)
905  .Case("fsgsbase", true)
906  .Case("fxsr", true)
907  .Case("general-regs-only", true)
908  .Case("gfni", true)
909  .Case("hreset", true)
910  .Case("invpcid", true)
911  .Case("kl", true)
912  .Case("widekl", true)
913  .Case("lwp", true)
914  .Case("lzcnt", true)
915  .Case("mmx", true)
916  .Case("movbe", true)
917  .Case("movdiri", true)
918  .Case("movdir64b", true)
919  .Case("mwaitx", true)
920  .Case("pclmul", true)
921  .Case("pconfig", true)
922  .Case("pku", true)
923  .Case("popcnt", true)
924  .Case("prefetchwt1", true)
925  .Case("prfchw", true)
926  .Case("ptwrite", true)
927  .Case("rdpid", true)
928  .Case("rdrnd", true)
929  .Case("rdseed", true)
930  .Case("rtm", true)
931  .Case("sahf", true)
932  .Case("serialize", true)
933  .Case("sgx", true)
934  .Case("sha", true)
935  .Case("shstk", true)
936  .Case("sse", true)
937  .Case("sse2", true)
938  .Case("sse3", true)
939  .Case("ssse3", true)
940  .Case("sse4", true)
941  .Case("sse4.1", true)
942  .Case("sse4.2", true)
943  .Case("sse4a", true)
944  .Case("tbm", true)
945  .Case("tsxldtrk", true)
946  .Case("uintr", true)
947  .Case("vaes", true)
948  .Case("vpclmulqdq", true)
949  .Case("wbnoinvd", true)
950  .Case("waitpkg", true)
951  .Case("x87", true)
952  .Case("xop", true)
953  .Case("xsave", true)
954  .Case("xsavec", true)
955  .Case("xsaves", true)
956  .Case("xsaveopt", true)
957  .Default(false);
958 }
959 
960 bool X86TargetInfo::hasFeature(StringRef Feature) const {
961  return llvm::StringSwitch<bool>(Feature)
962  .Case("adx", HasADX)
963  .Case("aes", HasAES)
964  .Case("amx-bf16", HasAMXBF16)
965  .Case("amx-int8", HasAMXINT8)
966  .Case("amx-tile", HasAMXTILE)
967  .Case("avxvnni", HasAVXVNNI)
968  .Case("avx", SSELevel >= AVX)
969  .Case("avx2", SSELevel >= AVX2)
970  .Case("avx512f", SSELevel >= AVX512F)
971  .Case("avx512cd", HasAVX512CD)
972  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
973  .Case("avx512vnni", HasAVX512VNNI)
974  .Case("avx512bf16", HasAVX512BF16)
975  .Case("avx512er", HasAVX512ER)
976  .Case("avx512fp16", HasAVX512FP16)
977  .Case("avx512pf", HasAVX512PF)
978  .Case("avx512dq", HasAVX512DQ)
979  .Case("avx512bitalg", HasAVX512BITALG)
980  .Case("avx512bw", HasAVX512BW)
981  .Case("avx512vl", HasAVX512VL)
982  .Case("avx512vbmi", HasAVX512VBMI)
983  .Case("avx512vbmi2", HasAVX512VBMI2)
984  .Case("avx512ifma", HasAVX512IFMA)
985  .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
986  .Case("bmi", HasBMI)
987  .Case("bmi2", HasBMI2)
988  .Case("cldemote", HasCLDEMOTE)
989  .Case("clflushopt", HasCLFLUSHOPT)
990  .Case("clwb", HasCLWB)
991  .Case("clzero", HasCLZERO)
992  .Case("crc32", HasCRC32)
993  .Case("cx8", HasCX8)
994  .Case("cx16", HasCX16)
995  .Case("enqcmd", HasENQCMD)
996  .Case("f16c", HasF16C)
997  .Case("fma", HasFMA)
998  .Case("fma4", XOPLevel >= FMA4)
999  .Case("fsgsbase", HasFSGSBASE)
1000  .Case("fxsr", HasFXSR)
1001  .Case("gfni", HasGFNI)
1002  .Case("hreset", HasHRESET)
1003  .Case("invpcid", HasINVPCID)
1004  .Case("kl", HasKL)
1005  .Case("widekl", HasWIDEKL)
1006  .Case("lwp", HasLWP)
1007  .Case("lzcnt", HasLZCNT)
1008  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1009  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1010  .Case("mmx", MMX3DNowLevel >= MMX)
1011  .Case("movbe", HasMOVBE)
1012  .Case("movdiri", HasMOVDIRI)
1013  .Case("movdir64b", HasMOVDIR64B)
1014  .Case("mwaitx", HasMWAITX)
1015  .Case("pclmul", HasPCLMUL)
1016  .Case("pconfig", HasPCONFIG)
1017  .Case("pku", HasPKU)
1018  .Case("popcnt", HasPOPCNT)
1019  .Case("prefetchwt1", HasPREFETCHWT1)
1020  .Case("prfchw", HasPRFCHW)
1021  .Case("ptwrite", HasPTWRITE)
1022  .Case("rdpid", HasRDPID)
1023  .Case("rdrnd", HasRDRND)
1024  .Case("rdseed", HasRDSEED)
1025  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1026  .Case("rtm", HasRTM)
1027  .Case("sahf", HasLAHFSAHF)
1028  .Case("serialize", HasSERIALIZE)
1029  .Case("sgx", HasSGX)
1030  .Case("sha", HasSHA)
1031  .Case("shstk", HasSHSTK)
1032  .Case("sse", SSELevel >= SSE1)
1033  .Case("sse2", SSELevel >= SSE2)
1034  .Case("sse3", SSELevel >= SSE3)
1035  .Case("ssse3", SSELevel >= SSSE3)
1036  .Case("sse4.1", SSELevel >= SSE41)
1037  .Case("sse4.2", SSELevel >= SSE42)
1038  .Case("sse4a", XOPLevel >= SSE4A)
1039  .Case("tbm", HasTBM)
1040  .Case("tsxldtrk", HasTSXLDTRK)
1041  .Case("uintr", HasUINTR)
1042  .Case("vaes", HasVAES)
1043  .Case("vpclmulqdq", HasVPCLMULQDQ)
1044  .Case("wbnoinvd", HasWBNOINVD)
1045  .Case("waitpkg", HasWAITPKG)
1046  .Case("x86", true)
1047  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1048  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1049  .Case("x87", HasX87)
1050  .Case("xop", XOPLevel >= XOP)
1051  .Case("xsave", HasXSAVE)
1052  .Case("xsavec", HasXSAVEC)
1053  .Case("xsaves", HasXSAVES)
1054  .Case("xsaveopt", HasXSAVEOPT)
1055  .Default(false);
1056 }
1057 
1058 // We can't use a generic validation scheme for the features accepted here
1059 // versus subtarget features accepted in the target attribute because the
1060 // bitfield structure that's initialized in the runtime only supports the
1061 // below currently rather than the full range of subtarget features. (See
1062 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1063 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1064  return llvm::StringSwitch<bool>(FeatureStr)
1065 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1066 #include "llvm/Support/X86TargetParser.def"
1067  .Default(false);
1068 }
1069 
1070 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1071  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1072 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1073  .Case(STR, llvm::X86::FEATURE_##ENUM)
1074 
1075 #include "llvm/Support/X86TargetParser.def"
1076  ;
1077  // Note, this function should only be used after ensuring the value is
1078  // correct, so it asserts if the value is out of range.
1079 }
1080 
1081 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1082  // Valid CPUs have a 'key feature' that compares just better than its key
1083  // feature.
1084  using namespace llvm::X86;
1085  CPUKind Kind = parseArchX86(Name);
1086  if (Kind != CK_None) {
1087  ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1088  return (getFeaturePriority(KeyFeature) << 1) + 1;
1089  }
1090 
1091  // Now we know we have a feature, so get its priority and shift it a few so
1092  // that we have sufficient room for the CPUs (above).
1093  return getFeaturePriority(getFeature(Name)) << 1;
1094 }
1095 
1097  return llvm::StringSwitch<bool>(Name)
1098 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1099 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1100 #include "llvm/Support/X86TargetParser.def"
1101  .Default(false);
1102 }
1103 
1104 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1105  return llvm::StringSwitch<StringRef>(Name)
1106 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1107 #include "llvm/Support/X86TargetParser.def"
1108  .Default(Name);
1109 }
1110 
1112  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1113 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1114 #include "llvm/Support/X86TargetParser.def"
1115  .Default(0);
1116 }
1117 
1119  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1120  StringRef WholeList =
1121  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1122 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1123 #include "llvm/Support/X86TargetParser.def"
1124  .Default("");
1125  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1126 }
1127 
1128 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const {
1129  return llvm::StringSwitch<StringRef>(Name)
1130 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1131 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1132 #include "llvm/Support/X86TargetParser.def"
1133  .Default("");
1134 }
1135 
1136 // We can't use a generic validation scheme for the cpus accepted here
1137 // versus subtarget cpus accepted in the target attribute because the
1138 // variables intitialized by the runtime only support the below currently
1139 // rather than the full range of cpus.
1140 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1141  return llvm::StringSwitch<bool>(FeatureStr)
1142 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1143 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1144 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1145 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1146 #include "llvm/Support/X86TargetParser.def"
1147  .Default(false);
1148 }
1149 
1150 static unsigned matchAsmCCConstraint(const char *&Name) {
1151  auto RV = llvm::StringSwitch<unsigned>(Name)
1152  .Case("@cca", 4)
1153  .Case("@ccae", 5)
1154  .Case("@ccb", 4)
1155  .Case("@ccbe", 5)
1156  .Case("@ccc", 4)
1157  .Case("@cce", 4)
1158  .Case("@ccz", 4)
1159  .Case("@ccg", 4)
1160  .Case("@ccge", 5)
1161  .Case("@ccl", 4)
1162  .Case("@ccle", 5)
1163  .Case("@ccna", 5)
1164  .Case("@ccnae", 6)
1165  .Case("@ccnb", 5)
1166  .Case("@ccnbe", 6)
1167  .Case("@ccnc", 5)
1168  .Case("@ccne", 5)
1169  .Case("@ccnz", 5)
1170  .Case("@ccng", 5)
1171  .Case("@ccnge", 6)
1172  .Case("@ccnl", 5)
1173  .Case("@ccnle", 6)
1174  .Case("@ccno", 5)
1175  .Case("@ccnp", 5)
1176  .Case("@ccns", 5)
1177  .Case("@cco", 4)
1178  .Case("@ccp", 4)
1179  .Case("@ccs", 4)
1180  .Default(0);
1181  return RV;
1182 }
1183 
1185  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1186  switch (*Name) {
1187  default:
1188  return false;
1189  // Constant constraints.
1190  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1191  // instructions.
1192  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1193  // x86_64 instructions.
1194  case 's':
1195  Info.setRequiresImmediate();
1196  return true;
1197  case 'I':
1198  Info.setRequiresImmediate(0, 31);
1199  return true;
1200  case 'J':
1201  Info.setRequiresImmediate(0, 63);
1202  return true;
1203  case 'K':
1204  Info.setRequiresImmediate(-128, 127);
1205  return true;
1206  case 'L':
1207  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1208  return true;
1209  case 'M':
1210  Info.setRequiresImmediate(0, 3);
1211  return true;
1212  case 'N':
1213  Info.setRequiresImmediate(0, 255);
1214  return true;
1215  case 'O':
1216  Info.setRequiresImmediate(0, 127);
1217  return true;
1218  // Register constraints.
1219  case 'Y': // 'Y' is the first character for several 2-character constraints.
1220  // Shift the pointer to the second character of the constraint.
1221  Name++;
1222  switch (*Name) {
1223  default:
1224  return false;
1225  case 'z': // First SSE register.
1226  case '2':
1227  case 't': // Any SSE register, when SSE2 is enabled.
1228  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1229  case 'm': // Any MMX register, when inter-unit moves enabled.
1230  case 'k': // AVX512 arch mask registers: k1-k7.
1231  Info.setAllowsRegister();
1232  return true;
1233  }
1234  case 'f': // Any x87 floating point stack register.
1235  // Constraint 'f' cannot be used for output operands.
1236  if (Info.ConstraintStr[0] == '=')
1237  return false;
1238  Info.setAllowsRegister();
1239  return true;
1240  case 'a': // eax.
1241  case 'b': // ebx.
1242  case 'c': // ecx.
1243  case 'd': // edx.
1244  case 'S': // esi.
1245  case 'D': // edi.
1246  case 'A': // edx:eax.
1247  case 't': // Top of floating point stack.
1248  case 'u': // Second from top of floating point stack.
1249  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1250  case 'y': // Any MMX register.
1251  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1252  case 'x': // Any SSE register.
1253  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1254  // for intermideate k reg operations).
1255  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1256  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1257  case 'l': // "Index" registers: any general register that can be used as an
1258  // index in a base+index memory access.
1259  Info.setAllowsRegister();
1260  return true;
1261  // Floating point constant constraints.
1262  case 'C': // SSE floating point constant.
1263  case 'G': // x87 floating point constant.
1264  return true;
1265  case '@':
1266  // CC condition changes.
1267  if (auto Len = matchAsmCCConstraint(Name)) {
1268  Name += Len - 1;
1269  Info.setAllowsRegister();
1270  return true;
1271  }
1272  return false;
1273  }
1274 }
1275 
1276 // Below is based on the following information:
1277 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1278 // | Processor Name | Cache Line Size (Bytes) | Source |
1279 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1280 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1281 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1282 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1283 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1284 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1285 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1286 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1287 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1288 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1289 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1290 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1291 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1292 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1293 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1294 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1295 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1296 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1297 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1299  using namespace llvm::X86;
1300  switch (CPU) {
1301  // i386
1302  case CK_i386:
1303  // i486
1304  case CK_i486:
1305  case CK_WinChipC6:
1306  case CK_WinChip2:
1307  case CK_C3:
1308  // Lakemont
1309  case CK_Lakemont:
1310  return 16;
1311 
1312  // i586
1313  case CK_i586:
1314  case CK_Pentium:
1315  case CK_PentiumMMX:
1316  // i686
1317  case CK_PentiumPro:
1318  case CK_i686:
1319  case CK_Pentium2:
1320  case CK_Pentium3:
1321  case CK_PentiumM:
1322  case CK_C3_2:
1323  // K6
1324  case CK_K6:
1325  case CK_K6_2:
1326  case CK_K6_3:
1327  // Geode
1328  case CK_Geode:
1329  return 32;
1330 
1331  // Netburst
1332  case CK_Pentium4:
1333  case CK_Prescott:
1334  case CK_Nocona:
1335  // Atom
1336  case CK_Bonnell:
1337  case CK_Silvermont:
1338  case CK_Goldmont:
1339  case CK_GoldmontPlus:
1340  case CK_Tremont:
1341 
1342  case CK_Westmere:
1343  case CK_SandyBridge:
1344  case CK_IvyBridge:
1345  case CK_Haswell:
1346  case CK_Broadwell:
1347  case CK_SkylakeClient:
1348  case CK_SkylakeServer:
1349  case CK_Cascadelake:
1350  case CK_Nehalem:
1351  case CK_Cooperlake:
1352  case CK_Cannonlake:
1353  case CK_Tigerlake:
1354  case CK_SapphireRapids:
1355  case CK_IcelakeClient:
1356  case CK_Rocketlake:
1357  case CK_IcelakeServer:
1358  case CK_Alderlake:
1359  case CK_KNL:
1360  case CK_KNM:
1361  // K7
1362  case CK_Athlon:
1363  case CK_AthlonXP:
1364  // K8
1365  case CK_K8:
1366  case CK_K8SSE3:
1367  case CK_AMDFAM10:
1368  // Bobcat
1369  case CK_BTVER1:
1370  case CK_BTVER2:
1371  // Bulldozer
1372  case CK_BDVER1:
1373  case CK_BDVER2:
1374  case CK_BDVER3:
1375  case CK_BDVER4:
1376  // Zen
1377  case CK_ZNVER1:
1378  case CK_ZNVER2:
1379  case CK_ZNVER3:
1380  // Deprecated
1381  case CK_x86_64:
1382  case CK_x86_64_v2:
1383  case CK_x86_64_v3:
1384  case CK_x86_64_v4:
1385  case CK_Yonah:
1386  case CK_Penryn:
1387  case CK_Core2:
1388  return 64;
1389 
1390  // The following currently have unknown cache line sizes (but they are probably all 64):
1391  // Core
1392  case CK_None:
1393  return None;
1394  }
1395  llvm_unreachable("Unknown CPU kind");
1396 }
1397 
1398 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1399  StringRef Constraint,
1400  unsigned Size) const {
1401  // Strip off constraint modifiers.
1402  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1403  Constraint = Constraint.substr(1);
1404 
1405  return validateOperandSize(FeatureMap, Constraint, Size);
1406 }
1407 
1408 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1409  StringRef Constraint,
1410  unsigned Size) const {
1411  return validateOperandSize(FeatureMap, Constraint, Size);
1412 }
1413 
1414 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1415  StringRef Constraint,
1416  unsigned Size) const {
1417  switch (Constraint[0]) {
1418  default:
1419  break;
1420  case 'k':
1421  // Registers k0-k7 (AVX512) size limit is 64 bit.
1422  case 'y':
1423  return Size <= 64;
1424  case 'f':
1425  case 't':
1426  case 'u':
1427  return Size <= 128;
1428  case 'Y':
1429  // 'Y' is the first character for several 2-character constraints.
1430  switch (Constraint[1]) {
1431  default:
1432  return false;
1433  case 'm':
1434  // 'Ym' is synonymous with 'y'.
1435  case 'k':
1436  return Size <= 64;
1437  case 'z':
1438  // XMM0/YMM/ZMM0
1439  if (hasFeatureEnabled(FeatureMap, "avx512f"))
1440  // ZMM0 can be used if target supports AVX512F.
1441  return Size <= 512U;
1442  else if (hasFeatureEnabled(FeatureMap, "avx"))
1443  // YMM0 can be used if target supports AVX.
1444  return Size <= 256U;
1445  else if (hasFeatureEnabled(FeatureMap, "sse"))
1446  return Size <= 128U;
1447  return false;
1448  case 'i':
1449  case 't':
1450  case '2':
1451  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1452  if (SSELevel < SSE2)
1453  return false;
1454  break;
1455  }
1456  break;
1457  case 'v':
1458  case 'x':
1459  if (hasFeatureEnabled(FeatureMap, "avx512f"))
1460  // 512-bit zmm registers can be used if target supports AVX512F.
1461  return Size <= 512U;
1462  else if (hasFeatureEnabled(FeatureMap, "avx"))
1463  // 256-bit ymm registers can be used if target supports AVX.
1464  return Size <= 256U;
1465  return Size <= 128U;
1466 
1467  }
1468 
1469  return true;
1470 }
1471 
1472 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1473  switch (*Constraint) {
1474  case '@':
1475  if (auto Len = matchAsmCCConstraint(Constraint)) {
1476  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1477  Constraint += Len - 1;
1478  return Converted;
1479  }
1480  return std::string(1, *Constraint);
1481  case 'a':
1482  return std::string("{ax}");
1483  case 'b':
1484  return std::string("{bx}");
1485  case 'c':
1486  return std::string("{cx}");
1487  case 'd':
1488  return std::string("{dx}");
1489  case 'S':
1490  return std::string("{si}");
1491  case 'D':
1492  return std::string("{di}");
1493  case 'p': // Keep 'p' constraint (address).
1494  return std::string("p");
1495  case 't': // top of floating point stack.
1496  return std::string("{st}");
1497  case 'u': // second from top of floating point stack.
1498  return std::string("{st(1)}"); // second from top of floating point stack.
1499  case 'Y':
1500  switch (Constraint[1]) {
1501  default:
1502  // Break from inner switch and fall through (copy single char),
1503  // continue parsing after copying the current constraint into
1504  // the return string.
1505  break;
1506  case 'k':
1507  case 'm':
1508  case 'i':
1509  case 't':
1510  case 'z':
1511  case '2':
1512  // "^" hints llvm that this is a 2 letter constraint.
1513  // "Constraint++" is used to promote the string iterator
1514  // to the next constraint.
1515  return std::string("^") + std::string(Constraint++, 2);
1516  }
1517  LLVM_FALLTHROUGH;
1518  default:
1519  return std::string(1, *Constraint);
1520  }
1521 }
1522 
1524  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1525  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1526 }
1527 
1529  llvm::X86::fillValidTuneCPUList(Values);
1530 }
1531 
1533  return llvm::makeArrayRef(GCCRegNames);
1534 }
1535 
1537  return llvm::makeArrayRef(AddlRegNames);
1538 }
1539 
1541  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1543 }
1544 
1546  return llvm::makeArrayRef(BuiltinInfoX86,
1548 }
Builtins.h
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Definition: __clang_cuda_math.h:196
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Definition: X86.cpp:1298
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Definition: X86.cpp:1536
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static unsigned matchAsmCCConstraint(const char *&Name)
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Definition: CMakeLists.txt:22
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:865
llvm::SmallVector< StringRef, 16 >
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Definition: X86.cpp:1118
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Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
int
__device__ int
Definition: __clang_hip_libdevice_declares.h:63
llvm::Optional< unsigned >
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bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1408
clang::TargetInfo::ConstraintInfo::setAllowsRegister
void setAllowsRegister()
Definition: TargetInfo.h:1067
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Definition: X86.h:152
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1140
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition: X86.h:150
U
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1523
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:1069
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ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1540
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@ LastX86CommonBuiltin
Definition: TargetBuiltins.h:115
clang::X86::LastTSBuiltin
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Definition: TargetBuiltins.h:118
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unsigned short SimdDefaultAlign
Definition: TargetInfo.h:211
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: X86.cpp:1528
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition: X86.cpp:167
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
Diagnostic.h
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virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:491
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Definition: X86.cpp:43
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DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:58
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unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1081
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Definition: X86.h:152
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bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1096
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Definition: TargetInfo.h:202
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bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105
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Definition: TargetInfo.h:1022
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Returns the target triple of the primary target.
Definition: TargetInfo.h:1172
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Determine whether the given target has the given feature.
Definition: X86.cpp:960
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Definition: TargetInfo.h:206
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Retrieve the target options.
Definition: TargetInfo.h:265
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition: X86.cpp:186
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Definition: X86.cpp:1070
llvm::ArrayRef< const char * >
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const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:116
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ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1545
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StringRef getCPUSpecificTuneName(StringRef Name) const override
Definition: X86.cpp:1128
TargetBuiltins.h
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1063
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bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1398
X86.h
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Definition: TargetInfo.h:1003
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Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:78
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Definition: X86.cpp:68
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Definition: DeclObjCCommon.h:22
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Definition: TargetInfo.h:203
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Definition: CalledOnceCheck.h:17
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Definition: AArch64.h:22
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Definition: Builtins.h:59
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std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1472
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition: TargetInfo.h:1295
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char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1111
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Definition: OperatorPrecedence.h:26
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Definition: X86.cpp:1414
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@ FirstTSBuiltin
Definition: Builtins.h:56
clang::targets::BuiltinInfoX86
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
llvm::SmallVectorImpl
Definition: Randstruct.h:18
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::defineCPUMacros
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:74
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1184
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1532
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:395
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1536
clang::TargetOptions::CodeModel
std::string CodeModel
Definition: TargetOptions.h:97
CPUSpecificCPUDispatchNameDealias
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1104