clang  13.0.0git
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/X86TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65  "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabled(Features, "sse2", true);
112 
113  using namespace llvm::X86;
114 
115  SmallVector<StringRef, 16> CPUFeatures;
116  getFeaturesForCPU(CPU, CPUFeatures);
117  for (auto &F : CPUFeatures)
118  setFeatureEnabled(Features, F, true);
119 
120  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
121  return false;
122 
123  // Can't do this earlier because we need to be able to explicitly enable
124  // or disable these features and the things that they depend upon.
125 
126  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
127  auto I = Features.find("sse4.2");
128  if (I != Features.end() && I->getValue() &&
129  llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
130  Features["popcnt"] = true;
131 
132  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
133  // then enable MMX.
134  I = Features.find("sse");
135  if (I != Features.end() && I->getValue() &&
136  llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
137  Features["mmx"] = true;
138 
139  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
140  I = Features.find("avx");
141  if (I != Features.end() && I->getValue() &&
142  llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end())
143  Features["xsave"] = true;
144 
145  return true;
146 }
147 
148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
149  StringRef Name, bool Enabled) const {
150  if (Name == "sse4") {
151  // We can get here via the __target__ attribute since that's not controlled
152  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
153  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
154  // disabled.
155  if (Enabled)
156  Name = "sse4.2";
157  else
158  Name = "sse4.1";
159  }
160 
161  Features[Name] = Enabled;
162  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
163 }
164 
165 /// handleTargetFeatures - Perform initialization based on the user
166 /// configured set of features.
167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
168  DiagnosticsEngine &Diags) {
169  for (const auto &Feature : Features) {
170  if (Feature[0] != '+')
171  continue;
172 
173  if (Feature == "+aes") {
174  HasAES = true;
175  } else if (Feature == "+vaes") {
176  HasVAES = true;
177  } else if (Feature == "+pclmul") {
178  HasPCLMUL = true;
179  } else if (Feature == "+vpclmulqdq") {
180  HasVPCLMULQDQ = true;
181  } else if (Feature == "+lzcnt") {
182  HasLZCNT = true;
183  } else if (Feature == "+rdrnd") {
184  HasRDRND = true;
185  } else if (Feature == "+fsgsbase") {
186  HasFSGSBASE = true;
187  } else if (Feature == "+bmi") {
188  HasBMI = true;
189  } else if (Feature == "+bmi2") {
190  HasBMI2 = true;
191  } else if (Feature == "+popcnt") {
192  HasPOPCNT = true;
193  } else if (Feature == "+rtm") {
194  HasRTM = true;
195  } else if (Feature == "+prfchw") {
196  HasPRFCHW = true;
197  } else if (Feature == "+rdseed") {
198  HasRDSEED = true;
199  } else if (Feature == "+adx") {
200  HasADX = true;
201  } else if (Feature == "+tbm") {
202  HasTBM = true;
203  } else if (Feature == "+lwp") {
204  HasLWP = true;
205  } else if (Feature == "+fma") {
206  HasFMA = true;
207  } else if (Feature == "+f16c") {
208  HasF16C = true;
209  } else if (Feature == "+gfni") {
210  HasGFNI = true;
211  } else if (Feature == "+avx512cd") {
212  HasAVX512CD = true;
213  } else if (Feature == "+avx512vpopcntdq") {
214  HasAVX512VPOPCNTDQ = true;
215  } else if (Feature == "+avx512vnni") {
216  HasAVX512VNNI = true;
217  } else if (Feature == "+avx512bf16") {
218  HasAVX512BF16 = true;
219  } else if (Feature == "+avx512er") {
220  HasAVX512ER = true;
221  } else if (Feature == "+avx512pf") {
222  HasAVX512PF = true;
223  } else if (Feature == "+avx512dq") {
224  HasAVX512DQ = true;
225  } else if (Feature == "+avx512bitalg") {
226  HasAVX512BITALG = true;
227  } else if (Feature == "+avx512bw") {
228  HasAVX512BW = true;
229  } else if (Feature == "+avx512vl") {
230  HasAVX512VL = true;
231  } else if (Feature == "+avx512vbmi") {
232  HasAVX512VBMI = true;
233  } else if (Feature == "+avx512vbmi2") {
234  HasAVX512VBMI2 = true;
235  } else if (Feature == "+avx512ifma") {
236  HasAVX512IFMA = true;
237  } else if (Feature == "+avx512vp2intersect") {
238  HasAVX512VP2INTERSECT = true;
239  } else if (Feature == "+sha") {
240  HasSHA = true;
241  } else if (Feature == "+shstk") {
242  HasSHSTK = true;
243  } else if (Feature == "+movbe") {
244  HasMOVBE = true;
245  } else if (Feature == "+sgx") {
246  HasSGX = true;
247  } else if (Feature == "+cx8") {
248  HasCX8 = true;
249  } else if (Feature == "+cx16") {
250  HasCX16 = true;
251  } else if (Feature == "+fxsr") {
252  HasFXSR = true;
253  } else if (Feature == "+xsave") {
254  HasXSAVE = true;
255  } else if (Feature == "+xsaveopt") {
256  HasXSAVEOPT = true;
257  } else if (Feature == "+xsavec") {
258  HasXSAVEC = true;
259  } else if (Feature == "+xsaves") {
260  HasXSAVES = true;
261  } else if (Feature == "+mwaitx") {
262  HasMWAITX = true;
263  } else if (Feature == "+pku") {
264  HasPKU = true;
265  } else if (Feature == "+clflushopt") {
266  HasCLFLUSHOPT = true;
267  } else if (Feature == "+clwb") {
268  HasCLWB = true;
269  } else if (Feature == "+wbnoinvd") {
270  HasWBNOINVD = true;
271  } else if (Feature == "+prefetchwt1") {
272  HasPREFETCHWT1 = true;
273  } else if (Feature == "+clzero") {
274  HasCLZERO = true;
275  } else if (Feature == "+cldemote") {
276  HasCLDEMOTE = true;
277  } else if (Feature == "+rdpid") {
278  HasRDPID = true;
279  } else if (Feature == "+kl") {
280  HasKL = true;
281  } else if (Feature == "+widekl") {
282  HasWIDEKL = true;
283  } else if (Feature == "+retpoline-external-thunk") {
284  HasRetpolineExternalThunk = true;
285  } else if (Feature == "+sahf") {
286  HasLAHFSAHF = true;
287  } else if (Feature == "+waitpkg") {
288  HasWAITPKG = true;
289  } else if (Feature == "+movdiri") {
290  HasMOVDIRI = true;
291  } else if (Feature == "+movdir64b") {
292  HasMOVDIR64B = true;
293  } else if (Feature == "+pconfig") {
294  HasPCONFIG = true;
295  } else if (Feature == "+ptwrite") {
296  HasPTWRITE = true;
297  } else if (Feature == "+invpcid") {
298  HasINVPCID = true;
299  } else if (Feature == "+enqcmd") {
300  HasENQCMD = true;
301  } else if (Feature == "+hreset") {
302  HasHRESET = true;
303  } else if (Feature == "+amx-bf16") {
304  HasAMXBF16 = true;
305  } else if (Feature == "+amx-int8") {
306  HasAMXINT8 = true;
307  } else if (Feature == "+amx-tile") {
308  HasAMXTILE = true;
309  } else if (Feature == "+avxvnni") {
310  HasAVXVNNI = true;
311  } else if (Feature == "+serialize") {
312  HasSERIALIZE = true;
313  } else if (Feature == "+tsxldtrk") {
314  HasTSXLDTRK = true;
315  } else if (Feature == "+uintr") {
316  HasUINTR = true;
317  }
318 
319  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
320  .Case("+avx512f", AVX512F)
321  .Case("+avx2", AVX2)
322  .Case("+avx", AVX)
323  .Case("+sse4.2", SSE42)
324  .Case("+sse4.1", SSE41)
325  .Case("+ssse3", SSSE3)
326  .Case("+sse3", SSE3)
327  .Case("+sse2", SSE2)
328  .Case("+sse", SSE1)
329  .Default(NoSSE);
330  SSELevel = std::max(SSELevel, Level);
331 
332  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
333  .Case("+3dnowa", AMD3DNowAthlon)
334  .Case("+3dnow", AMD3DNow)
335  .Case("+mmx", MMX)
336  .Default(NoMMX3DNow);
337  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
338 
339  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
340  .Case("+xop", XOP)
341  .Case("+fma4", FMA4)
342  .Case("+sse4a", SSE4A)
343  .Default(NoXOP);
344  XOPLevel = std::max(XOPLevel, XLevel);
345  }
346 
347  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
348  // matches the selected sse level.
349  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
350  (FPMath == FP_387 && SSELevel >= SSE1)) {
351  Diags.Report(diag::err_target_unsupported_fpmath)
352  << (FPMath == FP_SSE ? "sse" : "387");
353  return false;
354  }
355 
357  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
358  return true;
359 }
360 
361 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
362 /// definitions for this particular subtarget.
364  MacroBuilder &Builder) const {
365  // Inline assembly supports X86 flag outputs.
366  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
367 
368  std::string CodeModel = getTargetOpts().CodeModel;
369  if (CodeModel == "default")
370  CodeModel = "small";
371  Builder.defineMacro("__code_model_" + CodeModel + "__");
372 
373  // Target identification.
374  if (getTriple().getArch() == llvm::Triple::x86_64) {
375  Builder.defineMacro("__amd64__");
376  Builder.defineMacro("__amd64");
377  Builder.defineMacro("__x86_64");
378  Builder.defineMacro("__x86_64__");
379  if (getTriple().getArchName() == "x86_64h") {
380  Builder.defineMacro("__x86_64h");
381  Builder.defineMacro("__x86_64h__");
382  }
383  } else {
384  DefineStd(Builder, "i386", Opts);
385  }
386 
387  Builder.defineMacro("__SEG_GS");
388  Builder.defineMacro("__SEG_FS");
389  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
390  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
391 
392  // Subtarget options.
393  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
394  // truly should be based on -mtune options.
395  using namespace llvm::X86;
396  switch (CPU) {
397  case CK_None:
398  break;
399  case CK_i386:
400  // The rest are coming from the i386 define above.
401  Builder.defineMacro("__tune_i386__");
402  break;
403  case CK_i486:
404  case CK_WinChipC6:
405  case CK_WinChip2:
406  case CK_C3:
407  defineCPUMacros(Builder, "i486");
408  break;
409  case CK_PentiumMMX:
410  Builder.defineMacro("__pentium_mmx__");
411  Builder.defineMacro("__tune_pentium_mmx__");
412  LLVM_FALLTHROUGH;
413  case CK_i586:
414  case CK_Pentium:
415  defineCPUMacros(Builder, "i586");
416  defineCPUMacros(Builder, "pentium");
417  break;
418  case CK_Pentium3:
419  case CK_PentiumM:
420  Builder.defineMacro("__tune_pentium3__");
421  LLVM_FALLTHROUGH;
422  case CK_Pentium2:
423  case CK_C3_2:
424  Builder.defineMacro("__tune_pentium2__");
425  LLVM_FALLTHROUGH;
426  case CK_PentiumPro:
427  case CK_i686:
428  defineCPUMacros(Builder, "i686");
429  defineCPUMacros(Builder, "pentiumpro");
430  break;
431  case CK_Pentium4:
432  defineCPUMacros(Builder, "pentium4");
433  break;
434  case CK_Yonah:
435  case CK_Prescott:
436  case CK_Nocona:
437  defineCPUMacros(Builder, "nocona");
438  break;
439  case CK_Core2:
440  case CK_Penryn:
441  defineCPUMacros(Builder, "core2");
442  break;
443  case CK_Bonnell:
444  defineCPUMacros(Builder, "atom");
445  break;
446  case CK_Silvermont:
447  defineCPUMacros(Builder, "slm");
448  break;
449  case CK_Goldmont:
450  defineCPUMacros(Builder, "goldmont");
451  break;
452  case CK_GoldmontPlus:
453  defineCPUMacros(Builder, "goldmont_plus");
454  break;
455  case CK_Tremont:
456  defineCPUMacros(Builder, "tremont");
457  break;
458  case CK_Nehalem:
459  case CK_Westmere:
460  case CK_SandyBridge:
461  case CK_IvyBridge:
462  case CK_Haswell:
463  case CK_Broadwell:
464  case CK_SkylakeClient:
465  case CK_SkylakeServer:
466  case CK_Cascadelake:
467  case CK_Cooperlake:
468  case CK_Cannonlake:
469  case CK_IcelakeClient:
470  case CK_Rocketlake:
471  case CK_IcelakeServer:
472  case CK_Tigerlake:
473  case CK_SapphireRapids:
474  case CK_Alderlake:
475  // FIXME: Historically, we defined this legacy name, it would be nice to
476  // remove it at some point. We've never exposed fine-grained names for
477  // recent primary x86 CPUs, and we should keep it that way.
478  defineCPUMacros(Builder, "corei7");
479  break;
480  case CK_KNL:
481  defineCPUMacros(Builder, "knl");
482  break;
483  case CK_KNM:
484  break;
485  case CK_Lakemont:
486  defineCPUMacros(Builder, "i586", /*Tuning*/false);
487  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
488  Builder.defineMacro("__tune_lakemont__");
489  break;
490  case CK_K6_2:
491  Builder.defineMacro("__k6_2__");
492  Builder.defineMacro("__tune_k6_2__");
493  LLVM_FALLTHROUGH;
494  case CK_K6_3:
495  if (CPU != CK_K6_2) { // In case of fallthrough
496  // FIXME: GCC may be enabling these in cases where some other k6
497  // architecture is specified but -m3dnow is explicitly provided. The
498  // exact semantics need to be determined and emulated here.
499  Builder.defineMacro("__k6_3__");
500  Builder.defineMacro("__tune_k6_3__");
501  }
502  LLVM_FALLTHROUGH;
503  case CK_K6:
504  defineCPUMacros(Builder, "k6");
505  break;
506  case CK_Athlon:
507  case CK_AthlonXP:
508  defineCPUMacros(Builder, "athlon");
509  if (SSELevel != NoSSE) {
510  Builder.defineMacro("__athlon_sse__");
511  Builder.defineMacro("__tune_athlon_sse__");
512  }
513  break;
514  case CK_K8:
515  case CK_K8SSE3:
516  case CK_x86_64:
517  case CK_x86_64_v2:
518  case CK_x86_64_v3:
519  case CK_x86_64_v4:
520  defineCPUMacros(Builder, "k8");
521  break;
522  case CK_AMDFAM10:
523  defineCPUMacros(Builder, "amdfam10");
524  break;
525  case CK_BTVER1:
526  defineCPUMacros(Builder, "btver1");
527  break;
528  case CK_BTVER2:
529  defineCPUMacros(Builder, "btver2");
530  break;
531  case CK_BDVER1:
532  defineCPUMacros(Builder, "bdver1");
533  break;
534  case CK_BDVER2:
535  defineCPUMacros(Builder, "bdver2");
536  break;
537  case CK_BDVER3:
538  defineCPUMacros(Builder, "bdver3");
539  break;
540  case CK_BDVER4:
541  defineCPUMacros(Builder, "bdver4");
542  break;
543  case CK_ZNVER1:
544  defineCPUMacros(Builder, "znver1");
545  break;
546  case CK_ZNVER2:
547  defineCPUMacros(Builder, "znver2");
548  break;
549  case CK_ZNVER3:
550  defineCPUMacros(Builder, "znver3");
551  break;
552  case CK_Geode:
553  defineCPUMacros(Builder, "geode");
554  break;
555  }
556 
557  // Target properties.
558  Builder.defineMacro("__REGISTER_PREFIX__", "");
559 
560  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
561  // functions in glibc header files that use FP Stack inline asm which the
562  // backend can't deal with (PR879).
563  Builder.defineMacro("__NO_MATH_INLINES");
564 
565  if (HasAES)
566  Builder.defineMacro("__AES__");
567 
568  if (HasVAES)
569  Builder.defineMacro("__VAES__");
570 
571  if (HasPCLMUL)
572  Builder.defineMacro("__PCLMUL__");
573 
574  if (HasVPCLMULQDQ)
575  Builder.defineMacro("__VPCLMULQDQ__");
576 
577  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
578  // the feature flag only applies to 64-bit mode.
579  if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
580  Builder.defineMacro("__LAHF_SAHF__");
581 
582  if (HasLZCNT)
583  Builder.defineMacro("__LZCNT__");
584 
585  if (HasRDRND)
586  Builder.defineMacro("__RDRND__");
587 
588  if (HasFSGSBASE)
589  Builder.defineMacro("__FSGSBASE__");
590 
591  if (HasBMI)
592  Builder.defineMacro("__BMI__");
593 
594  if (HasBMI2)
595  Builder.defineMacro("__BMI2__");
596 
597  if (HasPOPCNT)
598  Builder.defineMacro("__POPCNT__");
599 
600  if (HasRTM)
601  Builder.defineMacro("__RTM__");
602 
603  if (HasPRFCHW)
604  Builder.defineMacro("__PRFCHW__");
605 
606  if (HasRDSEED)
607  Builder.defineMacro("__RDSEED__");
608 
609  if (HasADX)
610  Builder.defineMacro("__ADX__");
611 
612  if (HasTBM)
613  Builder.defineMacro("__TBM__");
614 
615  if (HasLWP)
616  Builder.defineMacro("__LWP__");
617 
618  if (HasMWAITX)
619  Builder.defineMacro("__MWAITX__");
620 
621  if (HasMOVBE)
622  Builder.defineMacro("__MOVBE__");
623 
624  switch (XOPLevel) {
625  case XOP:
626  Builder.defineMacro("__XOP__");
627  LLVM_FALLTHROUGH;
628  case FMA4:
629  Builder.defineMacro("__FMA4__");
630  LLVM_FALLTHROUGH;
631  case SSE4A:
632  Builder.defineMacro("__SSE4A__");
633  LLVM_FALLTHROUGH;
634  case NoXOP:
635  break;
636  }
637 
638  if (HasFMA)
639  Builder.defineMacro("__FMA__");
640 
641  if (HasF16C)
642  Builder.defineMacro("__F16C__");
643 
644  if (HasGFNI)
645  Builder.defineMacro("__GFNI__");
646 
647  if (HasAVX512CD)
648  Builder.defineMacro("__AVX512CD__");
649  if (HasAVX512VPOPCNTDQ)
650  Builder.defineMacro("__AVX512VPOPCNTDQ__");
651  if (HasAVX512VNNI)
652  Builder.defineMacro("__AVX512VNNI__");
653  if (HasAVX512BF16)
654  Builder.defineMacro("__AVX512BF16__");
655  if (HasAVX512ER)
656  Builder.defineMacro("__AVX512ER__");
657  if (HasAVX512PF)
658  Builder.defineMacro("__AVX512PF__");
659  if (HasAVX512DQ)
660  Builder.defineMacro("__AVX512DQ__");
661  if (HasAVX512BITALG)
662  Builder.defineMacro("__AVX512BITALG__");
663  if (HasAVX512BW)
664  Builder.defineMacro("__AVX512BW__");
665  if (HasAVX512VL)
666  Builder.defineMacro("__AVX512VL__");
667  if (HasAVX512VBMI)
668  Builder.defineMacro("__AVX512VBMI__");
669  if (HasAVX512VBMI2)
670  Builder.defineMacro("__AVX512VBMI2__");
671  if (HasAVX512IFMA)
672  Builder.defineMacro("__AVX512IFMA__");
673  if (HasAVX512VP2INTERSECT)
674  Builder.defineMacro("__AVX512VP2INTERSECT__");
675  if (HasSHA)
676  Builder.defineMacro("__SHA__");
677 
678  if (HasFXSR)
679  Builder.defineMacro("__FXSR__");
680  if (HasXSAVE)
681  Builder.defineMacro("__XSAVE__");
682  if (HasXSAVEOPT)
683  Builder.defineMacro("__XSAVEOPT__");
684  if (HasXSAVEC)
685  Builder.defineMacro("__XSAVEC__");
686  if (HasXSAVES)
687  Builder.defineMacro("__XSAVES__");
688  if (HasPKU)
689  Builder.defineMacro("__PKU__");
690  if (HasCLFLUSHOPT)
691  Builder.defineMacro("__CLFLUSHOPT__");
692  if (HasCLWB)
693  Builder.defineMacro("__CLWB__");
694  if (HasWBNOINVD)
695  Builder.defineMacro("__WBNOINVD__");
696  if (HasSHSTK)
697  Builder.defineMacro("__SHSTK__");
698  if (HasSGX)
699  Builder.defineMacro("__SGX__");
700  if (HasPREFETCHWT1)
701  Builder.defineMacro("__PREFETCHWT1__");
702  if (HasCLZERO)
703  Builder.defineMacro("__CLZERO__");
704  if (HasKL)
705  Builder.defineMacro("__KL__");
706  if (HasWIDEKL)
707  Builder.defineMacro("__WIDEKL__");
708  if (HasRDPID)
709  Builder.defineMacro("__RDPID__");
710  if (HasCLDEMOTE)
711  Builder.defineMacro("__CLDEMOTE__");
712  if (HasWAITPKG)
713  Builder.defineMacro("__WAITPKG__");
714  if (HasMOVDIRI)
715  Builder.defineMacro("__MOVDIRI__");
716  if (HasMOVDIR64B)
717  Builder.defineMacro("__MOVDIR64B__");
718  if (HasPCONFIG)
719  Builder.defineMacro("__PCONFIG__");
720  if (HasPTWRITE)
721  Builder.defineMacro("__PTWRITE__");
722  if (HasINVPCID)
723  Builder.defineMacro("__INVPCID__");
724  if (HasENQCMD)
725  Builder.defineMacro("__ENQCMD__");
726  if (HasHRESET)
727  Builder.defineMacro("__HRESET__");
728  if (HasAMXTILE)
729  Builder.defineMacro("__AMXTILE__");
730  if (HasAMXINT8)
731  Builder.defineMacro("__AMXINT8__");
732  if (HasAMXBF16)
733  Builder.defineMacro("__AMXBF16__");
734  if (HasAVXVNNI)
735  Builder.defineMacro("__AVXVNNI__");
736  if (HasSERIALIZE)
737  Builder.defineMacro("__SERIALIZE__");
738  if (HasTSXLDTRK)
739  Builder.defineMacro("__TSXLDTRK__");
740  if (HasUINTR)
741  Builder.defineMacro("__UINTR__");
742 
743  // Each case falls through to the previous one here.
744  switch (SSELevel) {
745  case AVX512F:
746  Builder.defineMacro("__AVX512F__");
747  LLVM_FALLTHROUGH;
748  case AVX2:
749  Builder.defineMacro("__AVX2__");
750  LLVM_FALLTHROUGH;
751  case AVX:
752  Builder.defineMacro("__AVX__");
753  LLVM_FALLTHROUGH;
754  case SSE42:
755  Builder.defineMacro("__SSE4_2__");
756  LLVM_FALLTHROUGH;
757  case SSE41:
758  Builder.defineMacro("__SSE4_1__");
759  LLVM_FALLTHROUGH;
760  case SSSE3:
761  Builder.defineMacro("__SSSE3__");
762  LLVM_FALLTHROUGH;
763  case SSE3:
764  Builder.defineMacro("__SSE3__");
765  LLVM_FALLTHROUGH;
766  case SSE2:
767  Builder.defineMacro("__SSE2__");
768  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
769  LLVM_FALLTHROUGH;
770  case SSE1:
771  Builder.defineMacro("__SSE__");
772  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
773  LLVM_FALLTHROUGH;
774  case NoSSE:
775  break;
776  }
777 
778  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
779  switch (SSELevel) {
780  case AVX512F:
781  case AVX2:
782  case AVX:
783  case SSE42:
784  case SSE41:
785  case SSSE3:
786  case SSE3:
787  case SSE2:
788  Builder.defineMacro("_M_IX86_FP", Twine(2));
789  break;
790  case SSE1:
791  Builder.defineMacro("_M_IX86_FP", Twine(1));
792  break;
793  default:
794  Builder.defineMacro("_M_IX86_FP", Twine(0));
795  break;
796  }
797  }
798 
799  // Each case falls through to the previous one here.
800  switch (MMX3DNowLevel) {
801  case AMD3DNowAthlon:
802  Builder.defineMacro("__3dNOW_A__");
803  LLVM_FALLTHROUGH;
804  case AMD3DNow:
805  Builder.defineMacro("__3dNOW__");
806  LLVM_FALLTHROUGH;
807  case MMX:
808  Builder.defineMacro("__MMX__");
809  LLVM_FALLTHROUGH;
810  case NoMMX3DNow:
811  break;
812  }
813 
814  if (CPU >= CK_i486 || CPU == CK_None) {
815  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
816  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
817  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
818  }
819  if (HasCX8)
820  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
821  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
822  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
823 
824  if (HasFloat128)
825  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
826 }
827 
828 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
829  return llvm::StringSwitch<bool>(Name)
830  .Case("3dnow", true)
831  .Case("3dnowa", true)
832  .Case("adx", true)
833  .Case("aes", true)
834  .Case("amx-bf16", true)
835  .Case("amx-int8", true)
836  .Case("amx-tile", true)
837  .Case("avx", true)
838  .Case("avx2", true)
839  .Case("avx512f", true)
840  .Case("avx512cd", true)
841  .Case("avx512vpopcntdq", true)
842  .Case("avx512vnni", true)
843  .Case("avx512bf16", true)
844  .Case("avx512er", true)
845  .Case("avx512pf", true)
846  .Case("avx512dq", true)
847  .Case("avx512bitalg", true)
848  .Case("avx512bw", true)
849  .Case("avx512vl", true)
850  .Case("avx512vbmi", true)
851  .Case("avx512vbmi2", true)
852  .Case("avx512ifma", true)
853  .Case("avx512vp2intersect", true)
854  .Case("avxvnni", true)
855  .Case("bmi", true)
856  .Case("bmi2", true)
857  .Case("cldemote", true)
858  .Case("clflushopt", true)
859  .Case("clwb", true)
860  .Case("clzero", true)
861  .Case("cx16", true)
862  .Case("enqcmd", true)
863  .Case("f16c", true)
864  .Case("fma", true)
865  .Case("fma4", true)
866  .Case("fsgsbase", true)
867  .Case("fxsr", true)
868  .Case("gfni", true)
869  .Case("hreset", true)
870  .Case("invpcid", true)
871  .Case("kl", true)
872  .Case("widekl", true)
873  .Case("lwp", true)
874  .Case("lzcnt", true)
875  .Case("mmx", true)
876  .Case("movbe", true)
877  .Case("movdiri", true)
878  .Case("movdir64b", true)
879  .Case("mwaitx", true)
880  .Case("pclmul", true)
881  .Case("pconfig", true)
882  .Case("pku", true)
883  .Case("popcnt", true)
884  .Case("prefetchwt1", true)
885  .Case("prfchw", true)
886  .Case("ptwrite", true)
887  .Case("rdpid", true)
888  .Case("rdrnd", true)
889  .Case("rdseed", true)
890  .Case("rtm", true)
891  .Case("sahf", true)
892  .Case("serialize", true)
893  .Case("sgx", true)
894  .Case("sha", true)
895  .Case("shstk", true)
896  .Case("sse", true)
897  .Case("sse2", true)
898  .Case("sse3", true)
899  .Case("ssse3", true)
900  .Case("sse4", true)
901  .Case("sse4.1", true)
902  .Case("sse4.2", true)
903  .Case("sse4a", true)
904  .Case("tbm", true)
905  .Case("tsxldtrk", true)
906  .Case("uintr", true)
907  .Case("vaes", true)
908  .Case("vpclmulqdq", true)
909  .Case("wbnoinvd", true)
910  .Case("waitpkg", true)
911  .Case("x87", true)
912  .Case("xop", true)
913  .Case("xsave", true)
914  .Case("xsavec", true)
915  .Case("xsaves", true)
916  .Case("xsaveopt", true)
917  .Default(false);
918 }
919 
920 bool X86TargetInfo::hasFeature(StringRef Feature) const {
921  return llvm::StringSwitch<bool>(Feature)
922  .Case("adx", HasADX)
923  .Case("aes", HasAES)
924  .Case("amx-bf16", HasAMXBF16)
925  .Case("amx-int8", HasAMXINT8)
926  .Case("amx-tile", HasAMXTILE)
927  .Case("avxvnni", HasAVXVNNI)
928  .Case("avx", SSELevel >= AVX)
929  .Case("avx2", SSELevel >= AVX2)
930  .Case("avx512f", SSELevel >= AVX512F)
931  .Case("avx512cd", HasAVX512CD)
932  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
933  .Case("avx512vnni", HasAVX512VNNI)
934  .Case("avx512bf16", HasAVX512BF16)
935  .Case("avx512er", HasAVX512ER)
936  .Case("avx512pf", HasAVX512PF)
937  .Case("avx512dq", HasAVX512DQ)
938  .Case("avx512bitalg", HasAVX512BITALG)
939  .Case("avx512bw", HasAVX512BW)
940  .Case("avx512vl", HasAVX512VL)
941  .Case("avx512vbmi", HasAVX512VBMI)
942  .Case("avx512vbmi2", HasAVX512VBMI2)
943  .Case("avx512ifma", HasAVX512IFMA)
944  .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
945  .Case("bmi", HasBMI)
946  .Case("bmi2", HasBMI2)
947  .Case("cldemote", HasCLDEMOTE)
948  .Case("clflushopt", HasCLFLUSHOPT)
949  .Case("clwb", HasCLWB)
950  .Case("clzero", HasCLZERO)
951  .Case("cx8", HasCX8)
952  .Case("cx16", HasCX16)
953  .Case("enqcmd", HasENQCMD)
954  .Case("f16c", HasF16C)
955  .Case("fma", HasFMA)
956  .Case("fma4", XOPLevel >= FMA4)
957  .Case("fsgsbase", HasFSGSBASE)
958  .Case("fxsr", HasFXSR)
959  .Case("gfni", HasGFNI)
960  .Case("hreset", HasHRESET)
961  .Case("invpcid", HasINVPCID)
962  .Case("kl", HasKL)
963  .Case("widekl", HasWIDEKL)
964  .Case("lwp", HasLWP)
965  .Case("lzcnt", HasLZCNT)
966  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
967  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
968  .Case("mmx", MMX3DNowLevel >= MMX)
969  .Case("movbe", HasMOVBE)
970  .Case("movdiri", HasMOVDIRI)
971  .Case("movdir64b", HasMOVDIR64B)
972  .Case("mwaitx", HasMWAITX)
973  .Case("pclmul", HasPCLMUL)
974  .Case("pconfig", HasPCONFIG)
975  .Case("pku", HasPKU)
976  .Case("popcnt", HasPOPCNT)
977  .Case("prefetchwt1", HasPREFETCHWT1)
978  .Case("prfchw", HasPRFCHW)
979  .Case("ptwrite", HasPTWRITE)
980  .Case("rdpid", HasRDPID)
981  .Case("rdrnd", HasRDRND)
982  .Case("rdseed", HasRDSEED)
983  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
984  .Case("rtm", HasRTM)
985  .Case("sahf", HasLAHFSAHF)
986  .Case("serialize", HasSERIALIZE)
987  .Case("sgx", HasSGX)
988  .Case("sha", HasSHA)
989  .Case("shstk", HasSHSTK)
990  .Case("sse", SSELevel >= SSE1)
991  .Case("sse2", SSELevel >= SSE2)
992  .Case("sse3", SSELevel >= SSE3)
993  .Case("ssse3", SSELevel >= SSSE3)
994  .Case("sse4.1", SSELevel >= SSE41)
995  .Case("sse4.2", SSELevel >= SSE42)
996  .Case("sse4a", XOPLevel >= SSE4A)
997  .Case("tbm", HasTBM)
998  .Case("tsxldtrk", HasTSXLDTRK)
999  .Case("uintr", HasUINTR)
1000  .Case("vaes", HasVAES)
1001  .Case("vpclmulqdq", HasVPCLMULQDQ)
1002  .Case("wbnoinvd", HasWBNOINVD)
1003  .Case("waitpkg", HasWAITPKG)
1004  .Case("x86", true)
1005  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1006  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1007  .Case("xop", XOPLevel >= XOP)
1008  .Case("xsave", HasXSAVE)
1009  .Case("xsavec", HasXSAVEC)
1010  .Case("xsaves", HasXSAVES)
1011  .Case("xsaveopt", HasXSAVEOPT)
1012  .Default(false);
1013 }
1014 
1015 // We can't use a generic validation scheme for the features accepted here
1016 // versus subtarget features accepted in the target attribute because the
1017 // bitfield structure that's initialized in the runtime only supports the
1018 // below currently rather than the full range of subtarget features. (See
1019 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1020 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1021  return llvm::StringSwitch<bool>(FeatureStr)
1022 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true)
1023 #include "llvm/Support/X86TargetParser.def"
1024  .Default(false);
1025 }
1026 
1027 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1028  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1029 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM)
1030 #include "llvm/Support/X86TargetParser.def"
1031  ;
1032  // Note, this function should only be used after ensuring the value is
1033  // correct, so it asserts if the value is out of range.
1034 }
1035 
1036 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1037  enum class FeatPriority {
1038 #define FEATURE(FEAT) FEAT,
1039 #include "clang/Basic/X86Target.def"
1040  };
1041  switch (Feat) {
1042 #define FEATURE(FEAT) \
1043  case llvm::X86::FEAT: \
1044  return static_cast<unsigned>(FeatPriority::FEAT);
1045 #include "clang/Basic/X86Target.def"
1046  default:
1047  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1048  }
1049 }
1050 
1051 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1052  // Valid CPUs have a 'key feature' that compares just better than its key
1053  // feature.
1054  using namespace llvm::X86;
1055  CPUKind Kind = parseArchX86(Name);
1056  if (Kind != CK_None) {
1057  ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1058  return (getFeaturePriority(KeyFeature) << 1) + 1;
1059  }
1060 
1061  // Now we know we have a feature, so get its priority and shift it a few so
1062  // that we have sufficient room for the CPUs (above).
1063  return getFeaturePriority(getFeature(Name)) << 1;
1064 }
1065 
1067  return llvm::StringSwitch<bool>(Name)
1068 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1069 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1070 #include "clang/Basic/X86Target.def"
1071  .Default(false);
1072 }
1073 
1074 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1075  return llvm::StringSwitch<StringRef>(Name)
1076 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1077 #include "clang/Basic/X86Target.def"
1078  .Default(Name);
1079 }
1080 
1082  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1083 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1084 #include "clang/Basic/X86Target.def"
1085  .Default(0);
1086 }
1087 
1089  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1090  StringRef WholeList =
1091  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1092 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1093 #include "clang/Basic/X86Target.def"
1094  .Default("");
1095  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1096 }
1097 
1098 // We can't use a generic validation scheme for the cpus accepted here
1099 // versus subtarget cpus accepted in the target attribute because the
1100 // variables intitialized by the runtime only support the below currently
1101 // rather than the full range of cpus.
1102 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1103  return llvm::StringSwitch<bool>(FeatureStr)
1104 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1105 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1106 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1107 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1108 #include "llvm/Support/X86TargetParser.def"
1109  .Default(false);
1110 }
1111 
1112 static unsigned matchAsmCCConstraint(const char *&Name) {
1113  auto RV = llvm::StringSwitch<unsigned>(Name)
1114  .Case("@cca", 4)
1115  .Case("@ccae", 5)
1116  .Case("@ccb", 4)
1117  .Case("@ccbe", 5)
1118  .Case("@ccc", 4)
1119  .Case("@cce", 4)
1120  .Case("@ccz", 4)
1121  .Case("@ccg", 4)
1122  .Case("@ccge", 5)
1123  .Case("@ccl", 4)
1124  .Case("@ccle", 5)
1125  .Case("@ccna", 5)
1126  .Case("@ccnae", 6)
1127  .Case("@ccnb", 5)
1128  .Case("@ccnbe", 6)
1129  .Case("@ccnc", 5)
1130  .Case("@ccne", 5)
1131  .Case("@ccnz", 5)
1132  .Case("@ccng", 5)
1133  .Case("@ccnge", 6)
1134  .Case("@ccnl", 5)
1135  .Case("@ccnle", 6)
1136  .Case("@ccno", 5)
1137  .Case("@ccnp", 5)
1138  .Case("@ccns", 5)
1139  .Case("@cco", 4)
1140  .Case("@ccp", 4)
1141  .Case("@ccs", 4)
1142  .Default(0);
1143  return RV;
1144 }
1145 
1147  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1148  switch (*Name) {
1149  default:
1150  return false;
1151  // Constant constraints.
1152  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1153  // instructions.
1154  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1155  // x86_64 instructions.
1156  case 's':
1157  Info.setRequiresImmediate();
1158  return true;
1159  case 'I':
1160  Info.setRequiresImmediate(0, 31);
1161  return true;
1162  case 'J':
1163  Info.setRequiresImmediate(0, 63);
1164  return true;
1165  case 'K':
1166  Info.setRequiresImmediate(-128, 127);
1167  return true;
1168  case 'L':
1169  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1170  return true;
1171  case 'M':
1172  Info.setRequiresImmediate(0, 3);
1173  return true;
1174  case 'N':
1175  Info.setRequiresImmediate(0, 255);
1176  return true;
1177  case 'O':
1178  Info.setRequiresImmediate(0, 127);
1179  return true;
1180  // Register constraints.
1181  case 'Y': // 'Y' is the first character for several 2-character constraints.
1182  // Shift the pointer to the second character of the constraint.
1183  Name++;
1184  switch (*Name) {
1185  default:
1186  return false;
1187  case 'z': // First SSE register.
1188  case '2':
1189  case 't': // Any SSE register, when SSE2 is enabled.
1190  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1191  case 'm': // Any MMX register, when inter-unit moves enabled.
1192  case 'k': // AVX512 arch mask registers: k1-k7.
1193  Info.setAllowsRegister();
1194  return true;
1195  }
1196  case 'f': // Any x87 floating point stack register.
1197  // Constraint 'f' cannot be used for output operands.
1198  if (Info.ConstraintStr[0] == '=')
1199  return false;
1200  Info.setAllowsRegister();
1201  return true;
1202  case 'a': // eax.
1203  case 'b': // ebx.
1204  case 'c': // ecx.
1205  case 'd': // edx.
1206  case 'S': // esi.
1207  case 'D': // edi.
1208  case 'A': // edx:eax.
1209  case 't': // Top of floating point stack.
1210  case 'u': // Second from top of floating point stack.
1211  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1212  case 'y': // Any MMX register.
1213  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1214  case 'x': // Any SSE register.
1215  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1216  // for intermideate k reg operations).
1217  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1218  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1219  case 'l': // "Index" registers: any general register that can be used as an
1220  // index in a base+index memory access.
1221  Info.setAllowsRegister();
1222  return true;
1223  // Floating point constant constraints.
1224  case 'C': // SSE floating point constant.
1225  case 'G': // x87 floating point constant.
1226  return true;
1227  case '@':
1228  // CC condition changes.
1229  if (auto Len = matchAsmCCConstraint(Name)) {
1230  Name += Len - 1;
1231  Info.setAllowsRegister();
1232  return true;
1233  }
1234  return false;
1235  }
1236 }
1237 
1238 // Below is based on the following information:
1239 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1240 // | Processor Name | Cache Line Size (Bytes) | Source |
1241 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1242 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1243 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1244 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1245 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1246 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1247 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1248 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1249 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1250 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1251 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1252 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1253 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1254 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1255 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1256 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1257 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1258 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1259 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1261  using namespace llvm::X86;
1262  switch (CPU) {
1263  // i386
1264  case CK_i386:
1265  // i486
1266  case CK_i486:
1267  case CK_WinChipC6:
1268  case CK_WinChip2:
1269  case CK_C3:
1270  // Lakemont
1271  case CK_Lakemont:
1272  return 16;
1273 
1274  // i586
1275  case CK_i586:
1276  case CK_Pentium:
1277  case CK_PentiumMMX:
1278  // i686
1279  case CK_PentiumPro:
1280  case CK_i686:
1281  case CK_Pentium2:
1282  case CK_Pentium3:
1283  case CK_PentiumM:
1284  case CK_C3_2:
1285  // K6
1286  case CK_K6:
1287  case CK_K6_2:
1288  case CK_K6_3:
1289  // Geode
1290  case CK_Geode:
1291  return 32;
1292 
1293  // Netburst
1294  case CK_Pentium4:
1295  case CK_Prescott:
1296  case CK_Nocona:
1297  // Atom
1298  case CK_Bonnell:
1299  case CK_Silvermont:
1300  case CK_Goldmont:
1301  case CK_GoldmontPlus:
1302  case CK_Tremont:
1303 
1304  case CK_Westmere:
1305  case CK_SandyBridge:
1306  case CK_IvyBridge:
1307  case CK_Haswell:
1308  case CK_Broadwell:
1309  case CK_SkylakeClient:
1310  case CK_SkylakeServer:
1311  case CK_Cascadelake:
1312  case CK_Nehalem:
1313  case CK_Cooperlake:
1314  case CK_Cannonlake:
1315  case CK_Tigerlake:
1316  case CK_SapphireRapids:
1317  case CK_IcelakeClient:
1318  case CK_Rocketlake:
1319  case CK_IcelakeServer:
1320  case CK_Alderlake:
1321  case CK_KNL:
1322  case CK_KNM:
1323  // K7
1324  case CK_Athlon:
1325  case CK_AthlonXP:
1326  // K8
1327  case CK_K8:
1328  case CK_K8SSE3:
1329  case CK_AMDFAM10:
1330  // Bobcat
1331  case CK_BTVER1:
1332  case CK_BTVER2:
1333  // Bulldozer
1334  case CK_BDVER1:
1335  case CK_BDVER2:
1336  case CK_BDVER3:
1337  case CK_BDVER4:
1338  // Zen
1339  case CK_ZNVER1:
1340  case CK_ZNVER2:
1341  case CK_ZNVER3:
1342  // Deprecated
1343  case CK_x86_64:
1344  case CK_x86_64_v2:
1345  case CK_x86_64_v3:
1346  case CK_x86_64_v4:
1347  case CK_Yonah:
1348  case CK_Penryn:
1349  case CK_Core2:
1350  return 64;
1351 
1352  // The following currently have unknown cache line sizes (but they are probably all 64):
1353  // Core
1354  case CK_None:
1355  return None;
1356  }
1357  llvm_unreachable("Unknown CPU kind");
1358 }
1359 
1360 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1361  StringRef Constraint,
1362  unsigned Size) const {
1363  // Strip off constraint modifiers.
1364  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1365  Constraint = Constraint.substr(1);
1366 
1367  return validateOperandSize(FeatureMap, Constraint, Size);
1368 }
1369 
1370 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1371  StringRef Constraint,
1372  unsigned Size) const {
1373  return validateOperandSize(FeatureMap, Constraint, Size);
1374 }
1375 
1376 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1377  StringRef Constraint,
1378  unsigned Size) const {
1379  switch (Constraint[0]) {
1380  default:
1381  break;
1382  case 'k':
1383  // Registers k0-k7 (AVX512) size limit is 64 bit.
1384  case 'y':
1385  return Size <= 64;
1386  case 'f':
1387  case 't':
1388  case 'u':
1389  return Size <= 128;
1390  case 'Y':
1391  // 'Y' is the first character for several 2-character constraints.
1392  switch (Constraint[1]) {
1393  default:
1394  return false;
1395  case 'm':
1396  // 'Ym' is synonymous with 'y'.
1397  case 'k':
1398  return Size <= 64;
1399  case 'z':
1400  // XMM0/YMM/ZMM0
1401  if (FeatureMap.lookup("avx512f"))
1402  // ZMM0 can be used if target supports AVX512F.
1403  return Size <= 512U;
1404  else if (FeatureMap.lookup("avx"))
1405  // YMM0 can be used if target supports AVX.
1406  return Size <= 256U;
1407  else if (FeatureMap.lookup("sse"))
1408  return Size <= 128U;
1409  return false;
1410  case 'i':
1411  case 't':
1412  case '2':
1413  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1414  if (SSELevel < SSE2)
1415  return false;
1416  break;
1417  }
1418  break;
1419  case 'v':
1420  case 'x':
1421  if (FeatureMap.lookup("avx512f"))
1422  // 512-bit zmm registers can be used if target supports AVX512F.
1423  return Size <= 512U;
1424  else if (FeatureMap.lookup("avx"))
1425  // 256-bit ymm registers can be used if target supports AVX.
1426  return Size <= 256U;
1427  return Size <= 128U;
1428 
1429  }
1430 
1431  return true;
1432 }
1433 
1434 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1435  switch (*Constraint) {
1436  case '@':
1437  if (auto Len = matchAsmCCConstraint(Constraint)) {
1438  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1439  Constraint += Len - 1;
1440  return Converted;
1441  }
1442  return std::string(1, *Constraint);
1443  case 'a':
1444  return std::string("{ax}");
1445  case 'b':
1446  return std::string("{bx}");
1447  case 'c':
1448  return std::string("{cx}");
1449  case 'd':
1450  return std::string("{dx}");
1451  case 'S':
1452  return std::string("{si}");
1453  case 'D':
1454  return std::string("{di}");
1455  case 'p': // address
1456  return std::string("im");
1457  case 't': // top of floating point stack.
1458  return std::string("{st}");
1459  case 'u': // second from top of floating point stack.
1460  return std::string("{st(1)}"); // second from top of floating point stack.
1461  case 'Y':
1462  switch (Constraint[1]) {
1463  default:
1464  // Break from inner switch and fall through (copy single char),
1465  // continue parsing after copying the current constraint into
1466  // the return string.
1467  break;
1468  case 'k':
1469  case 'm':
1470  case 'i':
1471  case 't':
1472  case 'z':
1473  case '2':
1474  // "^" hints llvm that this is a 2 letter constraint.
1475  // "Constraint++" is used to promote the string iterator
1476  // to the next constraint.
1477  return std::string("^") + std::string(Constraint++, 2);
1478  }
1479  LLVM_FALLTHROUGH;
1480  default:
1481  return std::string(1, *Constraint);
1482  }
1483 }
1484 
1486  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1487  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1488 }
1489 
1491  llvm::X86::fillValidTuneCPUList(Values);
1492 }
1493 
1495  return llvm::makeArrayRef(GCCRegNames);
1496 }
1497 
1499  return llvm::makeArrayRef(AddlRegNames);
1500 }
1501 
1503  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1505 }
1506 
1508  return llvm::makeArrayRef(BuiltinInfoX86,
1510 }
Builtins.h
max
__DEVICE__ int max(int __a, int __b)
Definition: __clang_cuda_math.h:194
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::getCPUCacheLineSize
Optional< unsigned > getCPUCacheLineSize() const override
Definition: X86.cpp:1260
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1498
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *&Name)
Definition: X86.cpp:1112
string
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Definition: CMakeLists.txt:22
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:828
llvm::SmallVector< StringRef, 16 >
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1088
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:191
int
__device__ int
Definition: __clang_hip_libdevice_declares.h:63
llvm::Optional< unsigned >
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1370
clang::TargetInfo::ConstraintInfo::setAllowsRegister
void setAllowsRegister()
Definition: TargetInfo.h:993
clang::targets::X86TargetInfo::FP_387
@ FP_387
Definition: X86.h:144
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1102
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition: X86.h:142
U
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1485
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:995
clang::targets::X86_32TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1502
clang::X86::LastX86CommonBuiltin
@ LastX86CommonBuiltin
Definition: TargetBuiltins.h:115
clang::X86::LastTSBuiltin
@ LastTSBuiltin
Definition: TargetBuiltins.h:118
clang::TargetInfo::SimdDefaultAlign
unsigned short SimdDefaultAlign
Definition: TargetInfo.h:207
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: X86.cpp:1490
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition: X86.cpp:148
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
getFeaturePriority
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1036
Diagnostic.h
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:433
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition: X86.cpp:43
clang::targets::DefineStd
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:56
clang::targets::X86TargetInfo::multiVersionSortPriority
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1051
clang::targets::X86TargetInfo::FP_SSE
@ FP_SSE
Definition: X86.h:144
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1066
clang::TargetInfo::HasFloat128
bool HasFloat128
Definition: TargetInfo.h:201
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105
clang::TargetInfo::ConstraintInfo::ConstraintStr
std::string ConstraintStr
Definition: TargetInfo.h:947
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1092
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition: X86.cpp:920
clang::TargetInfo::AddlRegName
Definition: TargetInfo.h:1109
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition: TargetInfo.h:256
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition: X86.cpp:167
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1027
llvm::ArrayRef< const char * >
clang::targets::X86_64TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1507
TargetBuiltins.h
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1020
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1360
X86.h
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:928
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:58
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
clang::ObjCPropertyAttribute::Kind
Kind
Definition: DeclObjCCommon.h:22
clang
Dataflow Directional Tag Classes.
Definition: CalledOnceCheck.h:17
clang::targets
Definition: AArch64.h:21
clang::Builtin::Info
Definition: Builtins.h:54
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1434
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1081
clang::prec::Level
Level
Definition: OperatorPrecedence.h:26
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1376
clang::Builtin::FirstTSBuiltin
@ FirstTSBuiltin
Definition: Builtins.h:51
clang::targets::BuiltinInfoX86
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
llvm::SmallVectorImpl
Definition: LLVM.h:39
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::defineCPUMacros
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:72
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1146
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1494
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:363
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1508
clang::TargetOptions::CodeModel
std::string CodeModel
Definition: TargetOptions.h:85
CPUSpecificCPUDispatchNameDealias
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1074