clang 24.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 if (Feature == "+apxf" || Feature == "-apxf") {
178 char Sign = Feature[0];
179 for (const char *Sub :
180 {"egpr", "push2pop2", "ppx", "ndd", "ccmp", "nf", "zu", "jmpabs"})
181 UpdatedFeaturesVec.push_back(Sign + std::string(Sub));
182 continue;
183 }
184
185 UpdatedFeaturesVec.push_back(Feature);
186 }
187
188 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
189 return false;
190
191 // Can't do this earlier because we need to be able to explicitly enable
192 // or disable these features and the things that they depend upon.
193
194 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
195 auto I = Features.find("sse4.2");
196 if (I != Features.end() && I->getValue() &&
197 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
198 Features["popcnt"] = true;
199
200 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
201 // then enable MMX.
202 I = Features.find("sse");
203 if (I != Features.end() && I->getValue() &&
204 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
205 Features["mmx"] = true;
206
207 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
208 I = Features.find("avx");
209 if (I != Features.end() && I->getValue() &&
210 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
211 Features["xsave"] = true;
212
213 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
214 I = Features.find("sse4.2");
215 if (I != Features.end() && I->getValue() &&
216 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
217 Features["crc32"] = true;
218
219 return true;
220}
221
222void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
223 StringRef Name, bool Enabled) const {
224 if (Name == "sse4") {
225 // We can get here via the __target__ attribute since that's not controlled
226 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
227 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
228 // disabled.
229 if (Enabled)
230 Name = "sse4.2";
231 else
232 Name = "sse4.1";
233 }
234
235 Features[Name] = Enabled;
236 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
237}
238
239/// handleTargetFeatures - Perform initialization based on the user
240/// configured set of features.
241bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
242 DiagnosticsEngine &Diags) {
243 for (const auto &Feature : Features) {
244 if (Feature[0] != '+')
245 continue;
246
247 if (Feature == "+mmx") {
248 HasMMX = true;
249 } else if (Feature == "+aes") {
250 HasAES = true;
251 } else if (Feature == "+vaes") {
252 HasVAES = true;
253 } else if (Feature == "+pclmul") {
254 HasPCLMUL = true;
255 } else if (Feature == "+vpclmulqdq") {
256 HasVPCLMULQDQ = true;
257 } else if (Feature == "+lzcnt") {
258 HasLZCNT = true;
259 } else if (Feature == "+rdrnd") {
260 HasRDRND = true;
261 } else if (Feature == "+fsgsbase") {
262 HasFSGSBASE = true;
263 } else if (Feature == "+bmi") {
264 HasBMI = true;
265 } else if (Feature == "+bmi2") {
266 HasBMI2 = true;
267 } else if (Feature == "+popcnt") {
268 HasPOPCNT = true;
269 } else if (Feature == "+rtm") {
270 HasRTM = true;
271 } else if (Feature == "+prfchw") {
272 HasPRFCHW = true;
273 } else if (Feature == "+rdseed") {
274 HasRDSEED = true;
275 } else if (Feature == "+adx") {
276 HasADX = true;
277 } else if (Feature == "+tbm") {
278 HasTBM = true;
279 } else if (Feature == "+lwp") {
280 HasLWP = true;
281 } else if (Feature == "+fma") {
282 HasFMA = true;
283 } else if (Feature == "+f16c") {
284 HasF16C = true;
285 } else if (Feature == "+gfni") {
286 HasGFNI = true;
287 } else if (Feature == "+avx10.1") {
288 HasAVX10_1 = true;
289 } else if (Feature == "+avx10.2") {
290 HasAVX10_2 = true;
291 HasFullBFloat16 = true;
292 } else if (Feature == "+avx10v2aux") {
293 HasAVX10_V2_AUX = true;
294 } else if (Feature == "+avx512cd") {
295 HasAVX512CD = true;
296 } else if (Feature == "+avx512vpopcntdq") {
297 HasAVX512VPOPCNTDQ = true;
298 } else if (Feature == "+avx512vnni") {
299 HasAVX512VNNI = true;
300 } else if (Feature == "+avx512bf16") {
301 HasAVX512BF16 = true;
302 } else if (Feature == "+avx512fp16") {
303 HasAVX512FP16 = true;
304 HasFastHalfType = true;
305 } else if (Feature == "+avx512dq") {
306 HasAVX512DQ = true;
307 } else if (Feature == "+avx512bitalg") {
308 HasAVX512BITALG = true;
309 } else if (Feature == "+avx512bmm") {
310 HasAVX512BMM = true;
311 } else if (Feature == "+avx512bw") {
312 HasAVX512BW = true;
313 } else if (Feature == "+avx512vl") {
314 HasAVX512VL = true;
315 } else if (Feature == "+avx512vbmi") {
316 HasAVX512VBMI = true;
317 } else if (Feature == "+avx512vbmi2") {
318 HasAVX512VBMI2 = true;
319 } else if (Feature == "+avx512ifma") {
320 HasAVX512IFMA = true;
321 } else if (Feature == "+avx512vp2intersect") {
322 HasAVX512VP2INTERSECT = true;
323 } else if (Feature == "+sha") {
324 HasSHA = true;
325 } else if (Feature == "+sha512") {
326 HasSHA512 = true;
327 } else if (Feature == "+shstk") {
328 HasSHSTK = true;
329 } else if (Feature == "+sm3") {
330 HasSM3 = true;
331 } else if (Feature == "+sm4") {
332 HasSM4 = true;
333 } else if (Feature == "+movbe") {
334 HasMOVBE = true;
335 } else if (Feature == "+movrs") {
336 HasMOVRS = true;
337 } else if (Feature == "+sgx") {
338 HasSGX = true;
339 } else if (Feature == "+cx8") {
340 HasCX8 = true;
341 } else if (Feature == "+cx16") {
342 HasCX16 = true;
343 } else if (Feature == "+fxsr") {
344 HasFXSR = true;
345 } else if (Feature == "+xsave") {
346 HasXSAVE = true;
347 } else if (Feature == "+xsaveopt") {
348 HasXSAVEOPT = true;
349 } else if (Feature == "+xsavec") {
350 HasXSAVEC = true;
351 } else if (Feature == "+xsaves") {
352 HasXSAVES = true;
353 } else if (Feature == "+mwaitx") {
354 HasMWAITX = true;
355 } else if (Feature == "+pku") {
356 HasPKU = true;
357 } else if (Feature == "+clflushopt") {
358 HasCLFLUSHOPT = true;
359 } else if (Feature == "+clwb") {
360 HasCLWB = true;
361 } else if (Feature == "+wbnoinvd") {
362 HasWBNOINVD = true;
363 } else if (Feature == "+prefetchi") {
364 HasPREFETCHI = true;
365 } else if (Feature == "+clzero") {
366 HasCLZERO = true;
367 } else if (Feature == "+cldemote") {
368 HasCLDEMOTE = true;
369 } else if (Feature == "+rdpid") {
370 HasRDPID = true;
371 } else if (Feature == "+rdpru") {
372 HasRDPRU = true;
373 } else if (Feature == "+kl") {
374 HasKL = true;
375 } else if (Feature == "+widekl") {
376 HasWIDEKL = true;
377 } else if (Feature == "+retpoline-external-thunk") {
378 HasRetpolineExternalThunk = true;
379 } else if (Feature == "+sahf") {
380 HasLAHFSAHF = true;
381 } else if (Feature == "+waitpkg") {
382 HasWAITPKG = true;
383 } else if (Feature == "+movdiri") {
384 HasMOVDIRI = true;
385 } else if (Feature == "+movdir64b") {
386 HasMOVDIR64B = true;
387 } else if (Feature == "+pconfig") {
388 HasPCONFIG = true;
389 } else if (Feature == "+ptwrite") {
390 HasPTWRITE = true;
391 } else if (Feature == "+invpcid") {
392 HasINVPCID = true;
393 } else if (Feature == "+enqcmd") {
394 HasENQCMD = true;
395 } else if (Feature == "+hreset") {
396 HasHRESET = true;
397 } else if (Feature == "+amx-bf16") {
398 HasAMXBF16 = true;
399 } else if (Feature == "+amx-fp16") {
400 HasAMXFP16 = true;
401 } else if (Feature == "+amx-int8") {
402 HasAMXINT8 = true;
403 } else if (Feature == "+amx-tile") {
404 HasAMXTILE = true;
405 } else if (Feature == "+amx-complex") {
406 HasAMXCOMPLEX = true;
407 } else if (Feature == "+amx-fp8") {
408 HasAMXFP8 = true;
409 } else if (Feature == "+amx-movrs") {
410 HasAMXMOVRS = true;
411 } else if (Feature == "+amx-avx512") {
412 HasAMXAVX512 = true;
413 } else if (Feature == "+cmpccxadd") {
414 HasCMPCCXADD = true;
415 } else if (Feature == "+raoint") {
416 HasRAOINT = true;
417 } else if (Feature == "+avxifma") {
418 HasAVXIFMA = true;
419 } else if (Feature == "+avxneconvert") {
420 HasAVXNECONVERT= true;
421 } else if (Feature == "+avxvnni") {
422 HasAVXVNNI = true;
423 } else if (Feature == "+avxvnniint16") {
424 HasAVXVNNIINT16 = true;
425 } else if (Feature == "+avxvnniint8") {
426 HasAVXVNNIINT8 = true;
427 } else if (Feature == "+serialize") {
428 HasSERIALIZE = true;
429 } else if (Feature == "+tsxldtrk") {
430 HasTSXLDTRK = true;
431 } else if (Feature == "+uintr") {
432 HasUINTR = true;
433 } else if (Feature == "+usermsr") {
434 HasUSERMSR = true;
435 } else if (Feature == "+crc32") {
436 HasCRC32 = true;
437 } else if (Feature == "+x87") {
438 HasX87 = true;
439 } else if (Feature == "+fullbf16") {
440 HasFullBFloat16 = true;
441 } else if (Feature == "+egpr") {
442 HasEGPR = true;
443 } else if (Feature == "+inline-asm-use-gpr32") {
444 HasInlineAsmUseGPR32 = true;
445 } else if (Feature == "+push2pop2") {
446 HasPush2Pop2 = true;
447 } else if (Feature == "+ppx") {
448 HasPPX = true;
449 } else if (Feature == "+ndd") {
450 HasNDD = true;
451 } else if (Feature == "+ccmp") {
452 HasCCMP = true;
453 } else if (Feature == "+nf") {
454 HasNF = true;
455 } else if (Feature == "+cf") {
456 HasCF = true;
457 } else if (Feature == "+zu") {
458 HasZU = true;
459 } else if (Feature == "+jmpabs") {
460 HasJMPABS = true;
461 } else if (Feature == "+branch-hint") {
462 HasBranchHint = true;
463 }
464
465 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
466 .Case("+avx512f", AVX512F)
467 .Case("+avx2", AVX2)
468 .Case("+avx", AVX)
469 .Case("+sse4.2", SSE42)
470 .Case("+sse4.1", SSE41)
471 .Case("+ssse3", SSSE3)
472 .Case("+sse3", SSE3)
473 .Case("+sse2", SSE2)
474 .Case("+sse", SSE1)
475 .Default(NoSSE);
476 SSELevel = std::max(SSELevel, Level);
477
478 HasFloat16 = SSELevel >= SSE2;
479
480 // X86 target has bfloat16 emulation support in the backend, where
481 // bfloat16 is treated as a 32-bit float, arithmetic operations are
482 // performed in 32-bit, and the result is converted back to bfloat16.
483 // Truncation and extension between bfloat16 and 32-bit float are supported
484 // by the compiler-rt library. However, native bfloat16 support is currently
485 // not available in the X86 target. Hence, HasFullBFloat16 will be false
486 // until native bfloat16 support is available. HasFullBFloat16 is used to
487 // determine whether to automatically use excess floating point precision
488 // for bfloat16 arithmetic operations in the front-end.
489 HasBFloat16 = SSELevel >= SSE2;
490
491 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
492 .Case("+xop", XOP)
493 .Case("+fma4", FMA4)
494 .Case("+sse4a", SSE4A)
495 .Default(NoXOP);
496 XOPLevel = std::max(XOPLevel, XLevel);
497 }
498
499 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
500 // matches the selected sse level.
501 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
502 (FPMath == FP_387 && SSELevel >= SSE1)) {
503 Diags.Report(diag::err_target_unsupported_fpmath)
504 << (FPMath == FP_SSE ? "sse" : "387");
505 return false;
506 }
507
508 // FIXME: We should allow long double type on 32-bits to match with GCC.
509 // This requires backend to be able to lower f80 without x87 first.
510 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
511 HasLongDouble = false;
512
513 return true;
514}
515
516/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
517/// definitions for this particular subtarget.
518void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
519 MacroBuilder &Builder) const {
520 // Inline assembly supports X86 flag outputs.
521 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
522
523 std::string CodeModel = getTargetOpts().CodeModel;
524 if (CodeModel == "default")
525 CodeModel = "small";
526 Builder.defineMacro("__code_model_" + CodeModel + "__");
527
528 // Target identification.
529 if (getTriple().getArch() == llvm::Triple::x86_64) {
530 Builder.defineMacro("__amd64__");
531 Builder.defineMacro("__amd64");
532 Builder.defineMacro("__x86_64");
533 Builder.defineMacro("__x86_64__");
534 if (getTriple().getArchName() == "x86_64h") {
535 Builder.defineMacro("__x86_64h");
536 Builder.defineMacro("__x86_64h__");
537 }
538 } else {
539 DefineStd(Builder, "i386", Opts);
540 }
541
542 if (getTriple().isLFI()) {
543 Builder.defineMacro("__LFI__");
544 }
545
546 Builder.defineMacro("__SEG_GS");
547 Builder.defineMacro("__SEG_FS");
548 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
549 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
550
551 // Subtarget options.
552 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
553 // truly should be based on -mtune options.
554 using namespace llvm::X86;
555 switch (CPU) {
556 case CK_None:
557 break;
558 case CK_i386:
559 // The rest are coming from the i386 define above.
560 Builder.defineMacro("__tune_i386__");
561 break;
562 case CK_i486:
563 case CK_WinChipC6:
564 case CK_WinChip2:
565 case CK_C3:
566 defineCPUMacros(Builder, "i486");
567 break;
568 case CK_PentiumMMX:
569 Builder.defineMacro("__pentium_mmx__");
570 Builder.defineMacro("__tune_pentium_mmx__");
571 [[fallthrough]];
572 case CK_i586:
573 case CK_Pentium:
574 defineCPUMacros(Builder, "i586");
575 defineCPUMacros(Builder, "pentium");
576 break;
577 case CK_Pentium3:
578 case CK_PentiumM:
579 Builder.defineMacro("__tune_pentium3__");
580 [[fallthrough]];
581 case CK_Pentium2:
582 case CK_C3_2:
583 Builder.defineMacro("__tune_pentium2__");
584 [[fallthrough]];
585 case CK_PentiumPro:
586 case CK_i686:
587 defineCPUMacros(Builder, "i686");
588 defineCPUMacros(Builder, "pentiumpro");
589 break;
590 case CK_Pentium4:
591 defineCPUMacros(Builder, "pentium4");
592 break;
593 case CK_Yonah:
594 case CK_Prescott:
595 case CK_Nocona:
596 defineCPUMacros(Builder, "nocona");
597 break;
598 case CK_Core2:
599 case CK_Penryn:
600 defineCPUMacros(Builder, "core2");
601 break;
602 case CK_Bonnell:
603 defineCPUMacros(Builder, "atom");
604 break;
605 case CK_Silvermont:
606 defineCPUMacros(Builder, "slm");
607 break;
608 case CK_Goldmont:
609 defineCPUMacros(Builder, "goldmont");
610 break;
611 case CK_GoldmontPlus:
612 defineCPUMacros(Builder, "goldmont_plus");
613 break;
614 case CK_Tremont:
615 defineCPUMacros(Builder, "tremont");
616 break;
617 // Gracemont and later atom-cores use P-core cpu macros.
618 case CK_Gracemont:
619 case CK_Nehalem:
620 case CK_Westmere:
621 case CK_SandyBridge:
622 case CK_IvyBridge:
623 case CK_Haswell:
624 case CK_Broadwell:
625 case CK_SkylakeClient:
626 case CK_SkylakeServer:
627 case CK_Cascadelake:
628 case CK_Cooperlake:
629 case CK_Cannonlake:
630 case CK_IcelakeClient:
631 case CK_Rocketlake:
632 case CK_IcelakeServer:
633 case CK_Tigerlake:
634 case CK_SapphireRapids:
635 case CK_Alderlake:
636 case CK_Raptorlake:
637 case CK_Meteorlake:
638 case CK_Arrowlake:
639 case CK_ArrowlakeS:
640 case CK_Lunarlake:
641 case CK_Pantherlake:
642 case CK_Wildcatlake:
643 case CK_Novalake:
644 case CK_Sierraforest:
645 case CK_Grandridge:
646 case CK_Graniterapids:
647 case CK_GraniterapidsD:
648 case CK_Emeraldrapids:
649 case CK_Clearwaterforest:
650 case CK_Diamondrapids:
651 // FIXME: Historically, we defined this legacy name, it would be nice to
652 // remove it at some point. We've never exposed fine-grained names for
653 // recent primary x86 CPUs, and we should keep it that way.
654 defineCPUMacros(Builder, "corei7");
655 break;
656 case CK_KNL:
657 defineCPUMacros(Builder, "knl");
658 break;
659 case CK_KNM:
660 break;
661 case CK_Lakemont:
662 defineCPUMacros(Builder, "i586", /*Tuning*/false);
663 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
664 Builder.defineMacro("__tune_lakemont__");
665 break;
666 case CK_K6_2:
667 Builder.defineMacro("__k6_2__");
668 Builder.defineMacro("__tune_k6_2__");
669 [[fallthrough]];
670 case CK_K6_3:
671 if (CPU != CK_K6_2) { // In case of fallthrough
672 // FIXME: GCC may be enabling these in cases where some other k6
673 // architecture is specified but -m3dnow is explicitly provided. The
674 // exact semantics need to be determined and emulated here.
675 Builder.defineMacro("__k6_3__");
676 Builder.defineMacro("__tune_k6_3__");
677 }
678 [[fallthrough]];
679 case CK_K6:
680 defineCPUMacros(Builder, "k6");
681 break;
682 case CK_Athlon:
683 case CK_AthlonXP:
684 defineCPUMacros(Builder, "athlon");
685 if (SSELevel != NoSSE) {
686 Builder.defineMacro("__athlon_sse__");
687 Builder.defineMacro("__tune_athlon_sse__");
688 }
689 break;
690 case CK_K8:
691 case CK_K8SSE3:
692 case CK_x86_64:
693 defineCPUMacros(Builder, "k8");
694 break;
695 case CK_x86_64_v2:
696 case CK_x86_64_v3:
697 case CK_x86_64_v4:
698 break;
699 case CK_AMDFAM10:
700 defineCPUMacros(Builder, "amdfam10");
701 break;
702 case CK_BTVER1:
703 defineCPUMacros(Builder, "btver1");
704 break;
705 case CK_BTVER2:
706 defineCPUMacros(Builder, "btver2");
707 break;
708 case CK_BDVER1:
709 defineCPUMacros(Builder, "bdver1");
710 break;
711 case CK_BDVER2:
712 defineCPUMacros(Builder, "bdver2");
713 break;
714 case CK_BDVER3:
715 defineCPUMacros(Builder, "bdver3");
716 break;
717 case CK_BDVER4:
718 defineCPUMacros(Builder, "bdver4");
719 break;
720 case CK_ZNVER1:
721 defineCPUMacros(Builder, "znver1");
722 break;
723 case CK_ZNVER2:
724 defineCPUMacros(Builder, "znver2");
725 break;
726 case CK_ZNVER3:
727 defineCPUMacros(Builder, "znver3");
728 break;
729 case CK_ZNVER4:
730 defineCPUMacros(Builder, "znver4");
731 break;
732 case CK_ZNVER5:
733 defineCPUMacros(Builder, "znver5");
734 break;
735 case CK_ZNVER6:
736 defineCPUMacros(Builder, "znver6");
737 break;
738 case CK_Geode:
739 defineCPUMacros(Builder, "geode");
740 break;
741 case CK_C86_4G_M4:
742 defineCPUMacros(Builder, "c86_4g_m4");
743 break;
744 case CK_C86_4G_M6:
745 defineCPUMacros(Builder, "c86_4g_m6");
746 break;
747 case CK_C86_4G_M7:
748 defineCPUMacros(Builder, "c86_4g_m7");
749 break;
750 case CK_C86_4G_M8:
751 defineCPUMacros(Builder, "c86_4g_m8");
752 break;
753 }
754
755 // Target properties.
756 Builder.defineMacro("__REGISTER_PREFIX__", "");
757
758 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
759 // functions in glibc header files that use FP Stack inline asm which the
760 // backend can't deal with (PR879).
761 Builder.defineMacro("__NO_MATH_INLINES");
762
763 if (HasAES)
764 Builder.defineMacro("__AES__");
765
766 if (HasVAES)
767 Builder.defineMacro("__VAES__");
768
769 if (HasPCLMUL)
770 Builder.defineMacro("__PCLMUL__");
771
772 if (HasVPCLMULQDQ)
773 Builder.defineMacro("__VPCLMULQDQ__");
774
775 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
776 // the feature flag only applies to 64-bit mode.
777 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
778 Builder.defineMacro("__LAHF_SAHF__");
779
780 if (HasLZCNT)
781 Builder.defineMacro("__LZCNT__");
782
783 if (HasRDRND)
784 Builder.defineMacro("__RDRND__");
785
786 if (HasFSGSBASE)
787 Builder.defineMacro("__FSGSBASE__");
788
789 if (HasBMI)
790 Builder.defineMacro("__BMI__");
791
792 if (HasBMI2)
793 Builder.defineMacro("__BMI2__");
794
795 if (HasPOPCNT)
796 Builder.defineMacro("__POPCNT__");
797
798 if (HasRTM)
799 Builder.defineMacro("__RTM__");
800
801 if (HasPRFCHW)
802 Builder.defineMacro("__PRFCHW__");
803
804 if (HasRDSEED)
805 Builder.defineMacro("__RDSEED__");
806
807 if (HasADX)
808 Builder.defineMacro("__ADX__");
809
810 if (HasTBM)
811 Builder.defineMacro("__TBM__");
812
813 if (HasLWP)
814 Builder.defineMacro("__LWP__");
815
816 if (HasMWAITX)
817 Builder.defineMacro("__MWAITX__");
818
819 if (HasMOVBE)
820 Builder.defineMacro("__MOVBE__");
821
822 switch (XOPLevel) {
823 case XOP:
824 Builder.defineMacro("__XOP__");
825 [[fallthrough]];
826 case FMA4:
827 Builder.defineMacro("__FMA4__");
828 [[fallthrough]];
829 case SSE4A:
830 Builder.defineMacro("__SSE4A__");
831 [[fallthrough]];
832 case NoXOP:
833 break;
834 }
835
836 if (HasFMA)
837 Builder.defineMacro("__FMA__");
838
839 if (HasF16C)
840 Builder.defineMacro("__F16C__");
841
842 if (HasGFNI)
843 Builder.defineMacro("__GFNI__");
844
845 if (HasAVX10_1) {
846 Builder.defineMacro("__AVX10_1__");
847 Builder.defineMacro("__AVX10_1_512__");
848 }
849 if (HasAVX10_2) {
850 Builder.defineMacro("__AVX10_2__");
851 Builder.defineMacro("__AVX10_2_512__");
852 }
853 if (HasAVX10_V2_AUX)
854 Builder.defineMacro("__AVX10_V2_AUX__");
855 if (HasAVX512CD)
856 Builder.defineMacro("__AVX512CD__");
857 if (HasAVX512VPOPCNTDQ)
858 Builder.defineMacro("__AVX512VPOPCNTDQ__");
859 if (HasAVX512VNNI)
860 Builder.defineMacro("__AVX512VNNI__");
861 if (HasAVX512BF16)
862 Builder.defineMacro("__AVX512BF16__");
863 if (HasAVX512FP16)
864 Builder.defineMacro("__AVX512FP16__");
865 if (HasAVX512DQ)
866 Builder.defineMacro("__AVX512DQ__");
867 if (HasAVX512BITALG)
868 Builder.defineMacro("__AVX512BITALG__");
869 if (HasAVX512BMM)
870 Builder.defineMacro("__AVX512BMM__");
871 if (HasAVX512BW)
872 Builder.defineMacro("__AVX512BW__");
873 if (HasAVX512VL) {
874 Builder.defineMacro("__AVX512VL__");
875 }
876 if (HasAVX512VBMI)
877 Builder.defineMacro("__AVX512VBMI__");
878 if (HasAVX512VBMI2)
879 Builder.defineMacro("__AVX512VBMI2__");
880 if (HasAVX512IFMA)
881 Builder.defineMacro("__AVX512IFMA__");
882 if (HasAVX512VP2INTERSECT)
883 Builder.defineMacro("__AVX512VP2INTERSECT__");
884 if (HasSHA)
885 Builder.defineMacro("__SHA__");
886 if (HasSHA512)
887 Builder.defineMacro("__SHA512__");
888
889 if (HasFXSR)
890 Builder.defineMacro("__FXSR__");
891 if (HasXSAVE)
892 Builder.defineMacro("__XSAVE__");
893 if (HasXSAVEOPT)
894 Builder.defineMacro("__XSAVEOPT__");
895 if (HasXSAVEC)
896 Builder.defineMacro("__XSAVEC__");
897 if (HasXSAVES)
898 Builder.defineMacro("__XSAVES__");
899 if (HasPKU)
900 Builder.defineMacro("__PKU__");
901 if (HasCLFLUSHOPT)
902 Builder.defineMacro("__CLFLUSHOPT__");
903 if (HasCLWB)
904 Builder.defineMacro("__CLWB__");
905 if (HasWBNOINVD)
906 Builder.defineMacro("__WBNOINVD__");
907 if (HasSHSTK)
908 Builder.defineMacro("__SHSTK__");
909 if (HasSGX)
910 Builder.defineMacro("__SGX__");
911 if (HasSM3)
912 Builder.defineMacro("__SM3__");
913 if (HasSM4)
914 Builder.defineMacro("__SM4__");
915 if (HasPREFETCHI)
916 Builder.defineMacro("__PREFETCHI__");
917 if (HasCLZERO)
918 Builder.defineMacro("__CLZERO__");
919 if (HasKL)
920 Builder.defineMacro("__KL__");
921 if (HasWIDEKL)
922 Builder.defineMacro("__WIDEKL__");
923 if (HasRDPID)
924 Builder.defineMacro("__RDPID__");
925 if (HasRDPRU)
926 Builder.defineMacro("__RDPRU__");
927 if (HasCLDEMOTE)
928 Builder.defineMacro("__CLDEMOTE__");
929 if (HasWAITPKG)
930 Builder.defineMacro("__WAITPKG__");
931 if (HasMOVDIRI)
932 Builder.defineMacro("__MOVDIRI__");
933 if (HasMOVDIR64B)
934 Builder.defineMacro("__MOVDIR64B__");
935 if (HasMOVRS)
936 Builder.defineMacro("__MOVRS__");
937 if (HasPCONFIG)
938 Builder.defineMacro("__PCONFIG__");
939 if (HasPTWRITE)
940 Builder.defineMacro("__PTWRITE__");
941 if (HasINVPCID)
942 Builder.defineMacro("__INVPCID__");
943 if (HasENQCMD)
944 Builder.defineMacro("__ENQCMD__");
945 if (HasHRESET)
946 Builder.defineMacro("__HRESET__");
947 if (HasAMXTILE)
948 Builder.defineMacro("__AMX_TILE__");
949 if (HasAMXINT8)
950 Builder.defineMacro("__AMX_INT8__");
951 if (HasAMXBF16)
952 Builder.defineMacro("__AMX_BF16__");
953 if (HasAMXFP16)
954 Builder.defineMacro("__AMX_FP16__");
955 if (HasAMXCOMPLEX)
956 Builder.defineMacro("__AMX_COMPLEX__");
957 if (HasAMXFP8)
958 Builder.defineMacro("__AMX_FP8__");
959 if (HasAMXMOVRS)
960 Builder.defineMacro("__AMX_MOVRS__");
961 if (HasAMXAVX512)
962 Builder.defineMacro("__AMX_AVX512__");
963 if (HasCMPCCXADD)
964 Builder.defineMacro("__CMPCCXADD__");
965 if (HasRAOINT)
966 Builder.defineMacro("__RAOINT__");
967 if (HasAVXIFMA)
968 Builder.defineMacro("__AVXIFMA__");
969 if (HasAVXNECONVERT)
970 Builder.defineMacro("__AVXNECONVERT__");
971 if (HasAVXVNNI)
972 Builder.defineMacro("__AVXVNNI__");
973 if (HasAVXVNNIINT16)
974 Builder.defineMacro("__AVXVNNIINT16__");
975 if (HasAVXVNNIINT8)
976 Builder.defineMacro("__AVXVNNIINT8__");
977 if (HasSERIALIZE)
978 Builder.defineMacro("__SERIALIZE__");
979 if (HasTSXLDTRK)
980 Builder.defineMacro("__TSXLDTRK__");
981 if (HasUINTR)
982 Builder.defineMacro("__UINTR__");
983 if (HasUSERMSR)
984 Builder.defineMacro("__USERMSR__");
985 if (HasCRC32)
986 Builder.defineMacro("__CRC32__");
987 if (HasEGPR)
988 Builder.defineMacro("__EGPR__");
989 if (HasPush2Pop2)
990 Builder.defineMacro("__PUSH2POP2__");
991 if (HasPPX)
992 Builder.defineMacro("__PPX__");
993 if (HasNDD)
994 Builder.defineMacro("__NDD__");
995 if (HasCCMP)
996 Builder.defineMacro("__CCMP__");
997 if (HasNF)
998 Builder.defineMacro("__NF__");
999 if (HasCF)
1000 Builder.defineMacro("__CF__");
1001 if (HasZU)
1002 Builder.defineMacro("__ZU__");
1003 if (HasJMPABS)
1004 Builder.defineMacro("__JMPABS__");
1005 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
1006 HasZU && HasJMPABS)
1007 Builder.defineMacro("__APX_F__");
1008 if (HasEGPR && HasInlineAsmUseGPR32)
1009 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
1010
1011 // Each case falls through to the previous one here.
1012 switch (SSELevel) {
1013 case AVX512F:
1014 Builder.defineMacro("__AVX512F__");
1015 [[fallthrough]];
1016 case AVX2:
1017 Builder.defineMacro("__AVX2__");
1018 [[fallthrough]];
1019 case AVX:
1020 Builder.defineMacro("__AVX__");
1021 [[fallthrough]];
1022 case SSE42:
1023 Builder.defineMacro("__SSE4_2__");
1024 [[fallthrough]];
1025 case SSE41:
1026 Builder.defineMacro("__SSE4_1__");
1027 [[fallthrough]];
1028 case SSSE3:
1029 Builder.defineMacro("__SSSE3__");
1030 [[fallthrough]];
1031 case SSE3:
1032 Builder.defineMacro("__SSE3__");
1033 [[fallthrough]];
1034 case SSE2:
1035 Builder.defineMacro("__SSE2__");
1036 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1037 [[fallthrough]];
1038 case SSE1:
1039 Builder.defineMacro("__SSE__");
1040 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1041 [[fallthrough]];
1042 case NoSSE:
1043 break;
1044 }
1045
1046 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1047 switch (SSELevel) {
1048 case AVX512F:
1049 case AVX2:
1050 case AVX:
1051 case SSE42:
1052 case SSE41:
1053 case SSSE3:
1054 case SSE3:
1055 case SSE2:
1056 Builder.defineMacro("_M_IX86_FP", Twine(2));
1057 break;
1058 case SSE1:
1059 Builder.defineMacro("_M_IX86_FP", Twine(1));
1060 break;
1061 default:
1062 Builder.defineMacro("_M_IX86_FP", Twine(0));
1063 break;
1064 }
1065 }
1066
1067 // Each case falls through to the previous one here.
1068 if (HasMMX) {
1069 Builder.defineMacro("__MMX__");
1070 }
1071
1072 if (CPU >= CK_i486 || CPU == CK_None) {
1073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1074 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1075 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1076 }
1077 if (HasCX8)
1078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1079 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1081
1082 if (HasFloat128)
1083 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1084
1085 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1086 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1087 Opts.CFProtectionBranch});
1088}
1089
1090bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1091 return llvm::StringSwitch<bool>(Name)
1092 .Case("adx", true)
1093 .Case("aes", true)
1094 .Case("amx-avx512", true)
1095 .Case("amx-bf16", true)
1096 .Case("amx-complex", true)
1097 .Case("amx-fp16", true)
1098 .Case("amx-fp8", true)
1099 .Case("amx-int8", true)
1100 .Case("amx-movrs", true)
1101 .Case("amx-tile", true)
1102 .Case("avx", true)
1103 .Case("avx10.1", true)
1104 .Case("avx10.2", true)
1105 .Case("avx10v2aux", true)
1106 .Case("avx2", true)
1107 .Case("avx512f", true)
1108 .Case("avx512cd", true)
1109 .Case("avx512vpopcntdq", true)
1110 .Case("avx512vnni", true)
1111 .Case("avx512bf16", true)
1112 .Case("avx512fp16", true)
1113 .Case("avx512dq", true)
1114 .Case("avx512bitalg", true)
1115 .Case("avx512bmm", true)
1116 .Case("avx512bw", true)
1117 .Case("avx512vl", true)
1118 .Case("avx512vbmi", true)
1119 .Case("avx512vbmi2", true)
1120 .Case("avx512ifma", true)
1121 .Case("avx512vp2intersect", true)
1122 .Case("avxifma", true)
1123 .Case("avxneconvert", true)
1124 .Case("avxvnni", true)
1125 .Case("avxvnniint16", true)
1126 .Case("avxvnniint8", true)
1127 .Case("bmi", true)
1128 .Case("bmi2", true)
1129 .Case("cldemote", true)
1130 .Case("clflushopt", true)
1131 .Case("clwb", true)
1132 .Case("clzero", true)
1133 .Case("cmpccxadd", true)
1134 .Case("crc32", true)
1135 .Case("cx16", true)
1136 .Case("enqcmd", true)
1137 .Case("f16c", true)
1138 .Case("fma", true)
1139 .Case("fma4", true)
1140 .Case("fsgsbase", true)
1141 .Case("fxsr", true)
1142 .Case("general-regs-only", true)
1143 .Case("gfni", true)
1144 .Case("hreset", true)
1145 .Case("invpcid", true)
1146 .Case("kl", true)
1147 .Case("widekl", true)
1148 .Case("lwp", true)
1149 .Case("lzcnt", true)
1150 .Case("mmx", true)
1151 .Case("movbe", true)
1152 .Case("movrs", true)
1153 .Case("movdiri", true)
1154 .Case("movdir64b", true)
1155 .Case("mwaitx", true)
1156 .Case("pclmul", true)
1157 .Case("pconfig", true)
1158 .Case("pku", true)
1159 .Case("popcnt", true)
1160 .Case("prefer-256-bit", true)
1161 .Case("prefetchi", true)
1162 .Case("prfchw", true)
1163 .Case("ptwrite", true)
1164 .Case("raoint", true)
1165 .Case("rdpid", true)
1166 .Case("rdpru", true)
1167 .Case("rdrnd", true)
1168 .Case("rdseed", true)
1169 .Case("rtm", true)
1170 .Case("sahf", true)
1171 .Case("serialize", true)
1172 .Case("sgx", true)
1173 .Case("sha", true)
1174 .Case("sha512", true)
1175 .Case("shstk", true)
1176 .Case("sm3", true)
1177 .Case("sm4", true)
1178 .Case("sse", true)
1179 .Case("sse2", true)
1180 .Case("sse3", true)
1181 .Case("ssse3", true)
1182 .Case("sse4", true)
1183 .Case("sse4.1", true)
1184 .Case("sse4.2", true)
1185 .Case("sse4a", true)
1186 .Case("tbm", true)
1187 .Case("tsxldtrk", true)
1188 .Case("uintr", true)
1189 .Case("usermsr", true)
1190 .Case("vaes", true)
1191 .Case("vpclmulqdq", true)
1192 .Case("wbnoinvd", true)
1193 .Case("waitpkg", true)
1194 .Case("x87", true)
1195 .Case("xop", true)
1196 .Case("xsave", true)
1197 .Case("xsavec", true)
1198 .Case("xsaves", true)
1199 .Case("xsaveopt", true)
1200 .Case("apxf", true)
1201 .Case("egpr", true)
1202 .Case("push2pop2", true)
1203 .Case("ppx", true)
1204 .Case("ndd", true)
1205 .Case("ccmp", true)
1206 .Case("nf", true)
1207 .Case("cf", true)
1208 .Case("zu", true)
1209 .Case("jmpabs", true)
1210 .Default(false);
1211}
1212
1213bool X86TargetInfo::hasFeature(StringRef Feature) const {
1214 return llvm::StringSwitch<bool>(Feature)
1215 .Case("adx", HasADX)
1216 .Case("aes", HasAES)
1217 .Case("amx-avx512", HasAMXAVX512)
1218 .Case("amx-bf16", HasAMXBF16)
1219 .Case("amx-complex", HasAMXCOMPLEX)
1220 .Case("amx-fp16", HasAMXFP16)
1221 .Case("amx-fp8", HasAMXFP8)
1222 .Case("amx-int8", HasAMXINT8)
1223 .Case("amx-movrs", HasAMXMOVRS)
1224 .Case("amx-tile", HasAMXTILE)
1225 .Case("avx", SSELevel >= AVX)
1226 .Case("avx10.1", HasAVX10_1)
1227 .Case("avx10.2", HasAVX10_2)
1228 .Case("avx10v2aux", HasAVX10_V2_AUX)
1229 .Case("avx2", SSELevel >= AVX2)
1230 .Case("avx512f", SSELevel >= AVX512F)
1231 .Case("avx512cd", HasAVX512CD)
1232 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1233 .Case("avx512vnni", HasAVX512VNNI)
1234 .Case("avx512bf16", HasAVX512BF16)
1235 .Case("avx512fp16", HasAVX512FP16)
1236 .Case("avx512dq", HasAVX512DQ)
1237 .Case("avx512bitalg", HasAVX512BITALG)
1238 .Case("avx512bmm", HasAVX512BMM)
1239 .Case("avx512bw", HasAVX512BW)
1240 .Case("avx512vl", HasAVX512VL)
1241 .Case("avx512vbmi", HasAVX512VBMI)
1242 .Case("avx512vbmi2", HasAVX512VBMI2)
1243 .Case("avx512ifma", HasAVX512IFMA)
1244 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1245 .Case("avxifma", HasAVXIFMA)
1246 .Case("avxneconvert", HasAVXNECONVERT)
1247 .Case("avxvnni", HasAVXVNNI)
1248 .Case("avxvnniint16", HasAVXVNNIINT16)
1249 .Case("avxvnniint8", HasAVXVNNIINT8)
1250 .Case("bmi", HasBMI)
1251 .Case("bmi2", HasBMI2)
1252 .Case("cldemote", HasCLDEMOTE)
1253 .Case("clflushopt", HasCLFLUSHOPT)
1254 .Case("clwb", HasCLWB)
1255 .Case("clzero", HasCLZERO)
1256 .Case("cmpccxadd", HasCMPCCXADD)
1257 .Case("crc32", HasCRC32)
1258 .Case("cx8", HasCX8)
1259 .Case("cx16", HasCX16)
1260 .Case("enqcmd", HasENQCMD)
1261 .Case("f16c", HasF16C)
1262 .Case("fma", HasFMA)
1263 .Case("fma4", XOPLevel >= FMA4)
1264 .Case("fsgsbase", HasFSGSBASE)
1265 .Case("fxsr", HasFXSR)
1266 .Case("gfni", HasGFNI)
1267 .Case("hreset", HasHRESET)
1268 .Case("invpcid", HasINVPCID)
1269 .Case("kl", HasKL)
1270 .Case("widekl", HasWIDEKL)
1271 .Case("lwp", HasLWP)
1272 .Case("lzcnt", HasLZCNT)
1273 .Case("mmx", HasMMX)
1274 .Case("movbe", HasMOVBE)
1275 .Case("movrs", HasMOVRS)
1276 .Case("movdiri", HasMOVDIRI)
1277 .Case("movdir64b", HasMOVDIR64B)
1278 .Case("mwaitx", HasMWAITX)
1279 .Case("pclmul", HasPCLMUL)
1280 .Case("pconfig", HasPCONFIG)
1281 .Case("pku", HasPKU)
1282 .Case("popcnt", HasPOPCNT)
1283 .Case("prefetchi", HasPREFETCHI)
1284 .Case("prfchw", HasPRFCHW)
1285 .Case("ptwrite", HasPTWRITE)
1286 .Case("raoint", HasRAOINT)
1287 .Case("rdpid", HasRDPID)
1288 .Case("rdpru", HasRDPRU)
1289 .Case("rdrnd", HasRDRND)
1290 .Case("rdseed", HasRDSEED)
1291 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1292 .Case("rtm", HasRTM)
1293 .Case("sahf", HasLAHFSAHF)
1294 .Case("serialize", HasSERIALIZE)
1295 .Case("sgx", HasSGX)
1296 .Case("sha", HasSHA)
1297 .Case("sha512", HasSHA512)
1298 .Case("shstk", HasSHSTK)
1299 .Case("sm3", HasSM3)
1300 .Case("sm4", HasSM4)
1301 .Case("sse", SSELevel >= SSE1)
1302 .Case("sse2", SSELevel >= SSE2)
1303 .Case("sse3", SSELevel >= SSE3)
1304 .Case("ssse3", SSELevel >= SSSE3)
1305 .Case("sse4.1", SSELevel >= SSE41)
1306 .Case("sse4.2", SSELevel >= SSE42)
1307 .Case("sse4a", XOPLevel >= SSE4A)
1308 .Case("tbm", HasTBM)
1309 .Case("tsxldtrk", HasTSXLDTRK)
1310 .Case("uintr", HasUINTR)
1311 .Case("usermsr", HasUSERMSR)
1312 .Case("vaes", HasVAES)
1313 .Case("vpclmulqdq", HasVPCLMULQDQ)
1314 .Case("wbnoinvd", HasWBNOINVD)
1315 .Case("waitpkg", HasWAITPKG)
1316 .Case("x86", true)
1317 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1318 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1319 .Case("x87", HasX87)
1320 .Case("xop", XOPLevel >= XOP)
1321 .Case("xsave", HasXSAVE)
1322 .Case("xsavec", HasXSAVEC)
1323 .Case("xsaves", HasXSAVES)
1324 .Case("xsaveopt", HasXSAVEOPT)
1325 .Case("fullbf16", HasFullBFloat16)
1326 .Case("egpr", HasEGPR)
1327 .Case("push2pop2", HasPush2Pop2)
1328 .Case("ppx", HasPPX)
1329 .Case("ndd", HasNDD)
1330 .Case("ccmp", HasCCMP)
1331 .Case("nf", HasNF)
1332 .Case("cf", HasCF)
1333 .Case("zu", HasZU)
1334 .Case("jmpabs", HasJMPABS)
1335 .Case("branch-hint", HasBranchHint)
1336 .Default(false);
1337}
1338
1339// We can't use a generic validation scheme for the features accepted here
1340// versus subtarget features accepted in the target attribute because the
1341// bitfield structure that's initialized in the runtime only supports the
1342// below currently rather than the full range of subtarget features. (See
1343// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1344bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1345 return llvm::StringSwitch<bool>(FeatureStr)
1346#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1347#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1348#include "llvm/TargetParser/X86TargetParser.def"
1349 .Default(false);
1350}
1351
1352static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1353 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1354#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1355 .Case(STR, llvm::X86::FEATURE_##ENUM)
1356
1357#include "llvm/TargetParser/X86TargetParser.def"
1358 ;
1359 // Note, this function should only be used after ensuring the value is
1360 // correct, so it asserts if the value is out of range.
1361}
1362
1363llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1364 auto getPriority = [](StringRef Feature) -> unsigned {
1365 // Valid CPUs have a 'key feature' that compares just better than its key
1366 // feature.
1367 using namespace llvm::X86;
1368 CPUKind Kind = parseArchX86(Feature);
1369 if (Kind != CK_None) {
1370 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1371 return (getFeaturePriority(KeyFeature) << 1) + 1;
1372 }
1373 // Now we know we have a feature, so get its priority and shift it a few so
1374 // that we have sufficient room for the CPUs (above).
1375 return getFeaturePriority(getFeature(Feature)) << 1;
1376 };
1377
1378 unsigned Priority = 0;
1379 for (StringRef Feature : Features)
1380 if (!Feature.empty())
1381 Priority = std::max(Priority, getPriority(Feature));
1382 return llvm::APInt(32, Priority);
1383}
1384
1385bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1386 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1387}
1388
1389char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1390 return llvm::X86::getCPUDispatchMangling(Name);
1391}
1392
1393void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1394 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1395 SmallVector<StringRef, 32> TargetCPUFeatures;
1396 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1397 for (auto &F : TargetCPUFeatures)
1398 Features.push_back(F);
1399}
1400
1401// We can't use a generic validation scheme for the cpus accepted here
1402// versus subtarget cpus accepted in the target attribute because the
1403// variables intitialized by the runtime only support the below currently
1404// rather than the full range of cpus.
1405bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1406 return llvm::StringSwitch<bool>(FeatureStr)
1407#define X86_VENDOR(ENUM, STRING, ABI_VALUE) .Case(STRING, true)
1408#define X86_CPU_TYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1409#define X86_CPU_SUBTYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1410#include "llvm/TargetParser/X86TargetParser.def"
1411 .Default(false);
1412}
1413
1414static unsigned matchAsmCCConstraint(const char *Name) {
1415 auto RV = llvm::StringSwitch<unsigned>(Name)
1416 .Case("@cca", 4)
1417 .Case("@ccae", 5)
1418 .Case("@ccb", 4)
1419 .Case("@ccbe", 5)
1420 .Case("@ccc", 4)
1421 .Case("@cce", 4)
1422 .Case("@ccz", 4)
1423 .Case("@ccg", 4)
1424 .Case("@ccge", 5)
1425 .Case("@ccl", 4)
1426 .Case("@ccle", 5)
1427 .Case("@ccna", 5)
1428 .Case("@ccnae", 6)
1429 .Case("@ccnb", 5)
1430 .Case("@ccnbe", 6)
1431 .Case("@ccnc", 5)
1432 .Case("@ccne", 5)
1433 .Case("@ccnz", 5)
1434 .Case("@ccng", 5)
1435 .Case("@ccnge", 6)
1436 .Case("@ccnl", 5)
1437 .Case("@ccnle", 6)
1438 .Case("@ccno", 5)
1439 .Case("@ccnp", 5)
1440 .Case("@ccns", 5)
1441 .Case("@cco", 4)
1442 .Case("@ccp", 4)
1443 .Case("@ccs", 4)
1444 .Default(0);
1445 return RV;
1446}
1447
1448bool X86TargetInfo::validateAsmConstraint(
1449 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1450 switch (*Name) {
1451 default:
1452 return false;
1453 // Constant constraints.
1454 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1455 // instructions.
1456 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1457 // x86_64 instructions.
1458 case 's':
1459 Info.setRequiresImmediate();
1460 return true;
1461 case 'I':
1462 Info.setRequiresImmediate(0, 31);
1463 return true;
1464 case 'J':
1465 Info.setRequiresImmediate(0, 63);
1466 return true;
1467 case 'K':
1468 Info.setRequiresImmediate(-128, 127);
1469 return true;
1470 case 'L':
1471 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1472 return true;
1473 case 'M':
1474 Info.setRequiresImmediate(0, 3);
1475 return true;
1476 case 'N':
1477 Info.setRequiresImmediate(0, 255);
1478 return true;
1479 case 'O':
1480 Info.setRequiresImmediate(0, 127);
1481 return true;
1482 case 'W':
1483 switch (*++Name) {
1484 default:
1485 return false;
1486 case 's':
1487 Info.setAllowsRegister();
1488 return true;
1489 }
1490 // Register constraints.
1491 case 'Y': // 'Y' is the first character for several 2-character constraints.
1492 // Shift the pointer to the second character of the constraint.
1493 Name++;
1494 switch (*Name) {
1495 default:
1496 return false;
1497 case 'z': // First SSE register.
1498 case '2':
1499 case 't': // Any SSE register, when SSE2 is enabled.
1500 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1501 case 'm': // Any MMX register, when inter-unit moves enabled.
1502 case 'k': // AVX512 arch mask registers: k1-k7.
1503 Info.setAllowsRegister();
1504 return true;
1505 }
1506 case 'f': // Any x87 floating point stack register.
1507 // Constraint 'f' cannot be used for output operands.
1508 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1509 return false;
1510 Info.setAllowsRegister();
1511 return true;
1512 case 'a': // eax.
1513 case 'b': // ebx.
1514 case 'c': // ecx.
1515 case 'd': // edx.
1516 case 'S': // esi.
1517 case 'D': // edi.
1518 case 'A': // edx:eax.
1519 case 't': // Top of floating point stack.
1520 case 'u': // Second from top of floating point stack.
1521 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1522 case 'y': // Any MMX register.
1523 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1524 case 'x': // Any SSE register.
1525 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1526 // for intermideate k reg operations).
1527 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1528 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1529 case 'l': // "Index" registers: any general register that can be used as an
1530 // index in a base+index memory access.
1531 Info.setAllowsRegister();
1532 return true;
1533 // Floating point constant constraints.
1534 case 'C': // SSE floating point constant.
1535 case 'G': // x87 floating point constant.
1536 return true;
1537 case 'j':
1538 Name++;
1539 switch (*Name) {
1540 default:
1541 return false;
1542 case 'r':
1543 Info.setAllowsRegister();
1544 return true;
1545 case 'R':
1546 Info.setAllowsRegister();
1547 return true;
1548 }
1549 case '@':
1550 // CC condition changes.
1551 if (auto Len = matchAsmCCConstraint(Name)) {
1552 Name += Len - 1;
1553 Info.setAllowsRegister();
1554 Info.setOutputOperandBounds(0, 2);
1555 return true;
1556 }
1557 return false;
1558 }
1559}
1560
1561// Below is based on the following information:
1562// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1563// | Processor Name | Cache Line Size (Bytes) | Source |
1564// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1565// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1566// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1567// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1568// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1569// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1570// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1571// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1572// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1573// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1574// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1575// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1576// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1577// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1578// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1579// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1580// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1581// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1582// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1583std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1584 using namespace llvm::X86;
1585 switch (CPU) {
1586 // i386
1587 case CK_i386:
1588 // i486
1589 case CK_i486:
1590 case CK_WinChipC6:
1591 case CK_WinChip2:
1592 case CK_C3:
1593 // Lakemont
1594 case CK_Lakemont:
1595 return 16;
1596
1597 // i586
1598 case CK_i586:
1599 case CK_Pentium:
1600 case CK_PentiumMMX:
1601 // i686
1602 case CK_PentiumPro:
1603 case CK_i686:
1604 case CK_Pentium2:
1605 case CK_Pentium3:
1606 case CK_PentiumM:
1607 case CK_C3_2:
1608 // K6
1609 case CK_K6:
1610 case CK_K6_2:
1611 case CK_K6_3:
1612 // Geode
1613 case CK_Geode:
1614 return 32;
1615
1616 // Netburst
1617 case CK_Pentium4:
1618 case CK_Prescott:
1619 case CK_Nocona:
1620 // Atom
1621 case CK_Bonnell:
1622 case CK_Silvermont:
1623 case CK_Goldmont:
1624 case CK_GoldmontPlus:
1625 case CK_Tremont:
1626 case CK_Gracemont:
1627
1628 case CK_Westmere:
1629 case CK_SandyBridge:
1630 case CK_IvyBridge:
1631 case CK_Haswell:
1632 case CK_Broadwell:
1633 case CK_SkylakeClient:
1634 case CK_SkylakeServer:
1635 case CK_Cascadelake:
1636 case CK_Nehalem:
1637 case CK_Cooperlake:
1638 case CK_Cannonlake:
1639 case CK_Tigerlake:
1640 case CK_SapphireRapids:
1641 case CK_IcelakeClient:
1642 case CK_Rocketlake:
1643 case CK_IcelakeServer:
1644 case CK_Alderlake:
1645 case CK_Raptorlake:
1646 case CK_Meteorlake:
1647 case CK_Arrowlake:
1648 case CK_ArrowlakeS:
1649 case CK_Lunarlake:
1650 case CK_Pantherlake:
1651 case CK_Wildcatlake:
1652 case CK_Novalake:
1653 case CK_Sierraforest:
1654 case CK_Grandridge:
1655 case CK_Graniterapids:
1656 case CK_GraniterapidsD:
1657 case CK_Emeraldrapids:
1658 case CK_Clearwaterforest:
1659 case CK_Diamondrapids:
1660 case CK_KNL:
1661 case CK_KNM:
1662 // K7
1663 case CK_Athlon:
1664 case CK_AthlonXP:
1665 // K8
1666 case CK_K8:
1667 case CK_K8SSE3:
1668 case CK_AMDFAM10:
1669 // Bobcat
1670 case CK_BTVER1:
1671 case CK_BTVER2:
1672 // Bulldozer
1673 case CK_BDVER1:
1674 case CK_BDVER2:
1675 case CK_BDVER3:
1676 case CK_BDVER4:
1677 // Zen
1678 case CK_ZNVER1:
1679 case CK_ZNVER2:
1680 case CK_ZNVER3:
1681 case CK_ZNVER4:
1682 case CK_ZNVER5:
1683 case CK_ZNVER6:
1684 // Hygon
1685 case CK_C86_4G_M4:
1686 case CK_C86_4G_M6:
1687 case CK_C86_4G_M7:
1688 case CK_C86_4G_M8:
1689 // Deprecated
1690 case CK_x86_64:
1691 case CK_x86_64_v2:
1692 case CK_x86_64_v3:
1693 case CK_x86_64_v4:
1694 case CK_Yonah:
1695 case CK_Penryn:
1696 case CK_Core2:
1697 return 64;
1698
1699 // The following currently have unknown cache line sizes (but they are probably all 64):
1700 // Core
1701 case CK_None:
1702 return std::nullopt;
1703 }
1704 llvm_unreachable("Unknown CPU kind");
1705}
1706
1707bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1708 StringRef Constraint,
1709 unsigned Size) const {
1710 // Strip off constraint modifiers.
1711 Constraint = Constraint.ltrim("=+&");
1712
1713 return validateOperandSize(FeatureMap, Constraint, Size);
1714}
1715
1716bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1717 StringRef Constraint,
1718 unsigned Size) const {
1719 return validateOperandSize(FeatureMap, Constraint, Size);
1720}
1721
1722bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1723 StringRef Constraint,
1724 unsigned Size) const {
1725 switch (Constraint[0]) {
1726 default:
1727 break;
1728 case 'k':
1729 // Registers k0-k7 (AVX512) size limit is 64 bit.
1730 case 'y':
1731 return Size <= 64;
1732 case 'f':
1733 case 't':
1734 case 'u':
1735 return Size <= 128;
1736 case 'Y':
1737 // 'Y' is the first character for several 2-character constraints.
1738 switch (Constraint[1]) {
1739 default:
1740 return false;
1741 case 'm':
1742 // 'Ym' is synonymous with 'y'.
1743 case 'k':
1744 return Size <= 64;
1745 case 'z':
1746 // XMM0/YMM/ZMM0
1747 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1748 // ZMM0 can be used if target supports AVX512F.
1749 return Size <= 512U;
1750 else if (hasFeatureEnabled(FeatureMap, "avx"))
1751 // YMM0 can be used if target supports AVX.
1752 return Size <= 256U;
1753 else if (hasFeatureEnabled(FeatureMap, "sse"))
1754 return Size <= 128U;
1755 return false;
1756 case 'i':
1757 case 't':
1758 case '2':
1759 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1760 if (SSELevel < SSE2)
1761 return false;
1762 break;
1763 }
1764 break;
1765 case 'v':
1766 case 'x':
1767 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1768 // 512-bit zmm registers can be used if target supports AVX512F.
1769 return Size <= 512U;
1770 else if (hasFeatureEnabled(FeatureMap, "avx"))
1771 // 256-bit ymm registers can be used if target supports AVX.
1772 return Size <= 256U;
1773 return Size <= 128U;
1774
1775 }
1776
1777 return true;
1778}
1779
1780std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1781 switch (*Constraint) {
1782 case '@':
1783 if (auto Len = matchAsmCCConstraint(Constraint)) {
1784 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1785 Constraint += Len - 1;
1786 return Converted;
1787 }
1788 return std::string(1, *Constraint);
1789 case 'a':
1790 return std::string("{ax}");
1791 case 'b':
1792 return std::string("{bx}");
1793 case 'c':
1794 return std::string("{cx}");
1795 case 'd':
1796 return std::string("{dx}");
1797 case 'S':
1798 return std::string("{si}");
1799 case 'D':
1800 return std::string("{di}");
1801 case 'p': // Keep 'p' constraint (address).
1802 return std::string("p");
1803 case 't': // top of floating point stack.
1804 return std::string("{st}");
1805 case 'u': // second from top of floating point stack.
1806 return std::string("{st(1)}"); // second from top of floating point stack.
1807 case 'W':
1808 assert(Constraint[1] == 's');
1809 return '^' + std::string(Constraint++, 2);
1810 case 'Y':
1811 switch (Constraint[1]) {
1812 default:
1813 // Break from inner switch and fall through (copy single char),
1814 // continue parsing after copying the current constraint into
1815 // the return string.
1816 break;
1817 case 'k':
1818 case 'm':
1819 case 'i':
1820 case 't':
1821 case 'z':
1822 case '2':
1823 // "^" hints llvm that this is a 2 letter constraint.
1824 // "Constraint++" is used to promote the string iterator
1825 // to the next constraint.
1826 return std::string("^") + std::string(Constraint++, 2);
1827 }
1828 [[fallthrough]];
1829 case 'j':
1830 switch (Constraint[1]) {
1831 default:
1832 // Break from inner switch and fall through (copy single char),
1833 // continue parsing after copying the current constraint into
1834 // the return string.
1835 break;
1836 case 'r':
1837 case 'R':
1838 // "^" hints llvm that this is a 2 letter constraint.
1839 // "Constraint++" is used to promote the string iterator
1840 // to the next constraint.
1841 return std::string("^") + std::string(Constraint++, 2);
1842 }
1843 [[fallthrough]];
1844 default:
1845 return std::string(1, *Constraint);
1846 }
1847}
1848
1849void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1850 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1851 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1852}
1853
1854void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1855 llvm::X86::fillValidTuneCPUList(Values);
1856}
1857
1861
1865
1866llvm::SmallVector<Builtin::InfosShard>
1867X86_32TargetInfo::getTargetBuiltins() const {
1868 return {
1869 {&X86::BuiltinStrings, X86::BuiltinInfos},
1870 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1871 };
1872}
1873
1874llvm::SmallVector<Builtin::InfosShard>
1875X86_64TargetInfo::getTargetBuiltins() const {
1876 return {
1877 {&X86::BuiltinStrings, X86::BuiltinInfos},
1878 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1879 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1880 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1881 "__builtin_ia32_"},
1882 };
1883}
1884
1885unsigned
1886MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1887 bool HasNonWeakDef) const {
1888 unsigned Align =
1889 WindowsX86_64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1890
1891 // Skip the MSVC size-based global-alignment increase under
1892 // -fclang-abi-compat<=22.
1893 if (!UseMSVCCompatGlobalAlign)
1894 return Align;
1895
1896 return std::max(Align, Microsoft64BitMinGlobalAlign(TypeSize));
1897}
1898
1899void MicrosoftX86_64TargetInfo::adjust(DiagnosticsEngine &Diags,
1900 LangOptions &Opts,
1901 const TargetInfo *Aux) {
1902 WindowsX86_64TargetInfo::adjust(Diags, Opts, Aux);
1903 // Under -fclang-abi-compat<=22, restore the prior x86_64-windows-msvc
1904 // behavior: apply the Sys V "large array" alignment increase and skip the
1905 // MSVC size-based global-alignment increase.
1906 if (Opts.isCompatibleWith(LangOptions::ClangABI::Ver22)) {
1907 UseMSVCCompatGlobalAlign = false;
1908 LargeArrayMinWidth = 128;
1909 LargeArrayAlign = 128;
1910 }
1911}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1593
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:235
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1352
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:39
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:61
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:232
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1606
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:473
clang::LangOptions::isCompatibleWith
bool isCompatibleWith(ClangABI Version) const
Definition LangOptions.h:678
clang::TargetInfo
Exposes information about the current target.
Definition TargetInfo.h:226
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:332
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1314
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1441
clang::TargetInfo::adjust
virtual void adjust(DiagnosticsEngine &Diags, LangOptions &Opts, const TargetInfo *Aux)
Set forced language options.
Definition TargetInfo.cpp:442
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:753
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:589
clang::targets::MicrosoftX86_64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition X86.cpp:1886
clang::targets::MicrosoftX86_64TargetInfo::adjust
void adjust(DiagnosticsEngine &Diags, LangOptions &Opts, const TargetInfo *Aux) override
Set forced language options.
Definition X86.cpp:1899
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:241
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1583
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1448
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1363
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1858
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1389
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1780
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:518
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1393
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1405
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1707
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1722
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1854
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1385
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1344
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1090
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1213
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:222
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:162
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1849
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1862
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1716
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1867
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1875
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
Top level wrappers for InstallAPI frontend operations.
Definition CalledOnceCheck.h:17
clang::Microsoft64BitMinGlobalAlign
unsigned Microsoft64BitMinGlobalAlign(uint64_t TypeSize)
Definition TargetInfo.cpp:1146
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:80
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1225
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1189
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
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