clang  7.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements X86 TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 namespace clang {
24 namespace targets {
25 
27 #define BUILTIN(ID, TYPE, ATTRS) \
28  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
33 #include "clang/Basic/BuiltinsX86.def"
34 
35 #define BUILTIN(ID, TYPE, ATTRS) \
36  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
41 #include "clang/Basic/BuiltinsX86_64.def"
42 };
43 
44 static const char *const GCCRegNames[] = {
45  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62  "k2", "k3", "k4", "k5", "k6", "k7",
63  "cr0", "cr2", "cr3", "cr4", "cr8",
64  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65  "bnd0", "bnd1", "bnd2", "bnd3",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabledImpl(Features, "sse2", true);
112 
113  const CPUKind Kind = getCPUKind(CPU);
114 
115  // Enable X87 for all X86 processors but Lakemont.
116  if (Kind != CK_Lakemont)
117  setFeatureEnabledImpl(Features, "x87", true);
118 
119  switch (Kind) {
120  case CK_Generic:
121  case CK_i386:
122  case CK_i486:
123  case CK_i586:
124  case CK_Pentium:
125  case CK_PentiumPro:
126  case CK_Lakemont:
127  break;
128 
129  case CK_PentiumMMX:
130  case CK_Pentium2:
131  case CK_K6:
132  case CK_WinChipC6:
133  setFeatureEnabledImpl(Features, "mmx", true);
134  break;
135 
136  case CK_IcelakeServer:
137  setFeatureEnabledImpl(Features, "pconfig", true);
138  setFeatureEnabledImpl(Features, "wbnoinvd", true);
139  LLVM_FALLTHROUGH;
140  case CK_IcelakeClient:
141  setFeatureEnabledImpl(Features, "vaes", true);
142  setFeatureEnabledImpl(Features, "gfni", true);
143  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
144  setFeatureEnabledImpl(Features, "avx512bitalg", true);
145  setFeatureEnabledImpl(Features, "avx512vnni", true);
146  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
147  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
148  setFeatureEnabledImpl(Features, "rdpid", true);
149  LLVM_FALLTHROUGH;
150  case CK_Cannonlake:
151  setFeatureEnabledImpl(Features, "avx512ifma", true);
152  setFeatureEnabledImpl(Features, "avx512vbmi", true);
153  setFeatureEnabledImpl(Features, "sha", true);
154  LLVM_FALLTHROUGH;
155  case CK_SkylakeServer:
156  setFeatureEnabledImpl(Features, "avx512f", true);
157  setFeatureEnabledImpl(Features, "avx512cd", true);
158  setFeatureEnabledImpl(Features, "avx512dq", true);
159  setFeatureEnabledImpl(Features, "avx512bw", true);
160  setFeatureEnabledImpl(Features, "avx512vl", true);
161  setFeatureEnabledImpl(Features, "pku", true);
162  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
163  setFeatureEnabledImpl(Features, "clwb", true);
164  LLVM_FALLTHROUGH;
165  case CK_SkylakeClient:
166  setFeatureEnabledImpl(Features, "xsavec", true);
167  setFeatureEnabledImpl(Features, "xsaves", true);
168  setFeatureEnabledImpl(Features, "mpx", true);
169  if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX
170  setFeatureEnabledImpl(Features, "sgx", true);
171  setFeatureEnabledImpl(Features, "clflushopt", true);
172  setFeatureEnabledImpl(Features, "rtm", true);
173  LLVM_FALLTHROUGH;
174  case CK_Broadwell:
175  setFeatureEnabledImpl(Features, "rdseed", true);
176  setFeatureEnabledImpl(Features, "adx", true);
177  setFeatureEnabledImpl(Features, "prfchw", true);
178  LLVM_FALLTHROUGH;
179  case CK_Haswell:
180  setFeatureEnabledImpl(Features, "avx2", true);
181  setFeatureEnabledImpl(Features, "lzcnt", true);
182  setFeatureEnabledImpl(Features, "bmi", true);
183  setFeatureEnabledImpl(Features, "bmi2", true);
184  setFeatureEnabledImpl(Features, "fma", true);
185  setFeatureEnabledImpl(Features, "movbe", true);
186  LLVM_FALLTHROUGH;
187  case CK_IvyBridge:
188  setFeatureEnabledImpl(Features, "rdrnd", true);
189  setFeatureEnabledImpl(Features, "f16c", true);
190  setFeatureEnabledImpl(Features, "fsgsbase", true);
191  LLVM_FALLTHROUGH;
192  case CK_SandyBridge:
193  setFeatureEnabledImpl(Features, "avx", true);
194  setFeatureEnabledImpl(Features, "xsave", true);
195  setFeatureEnabledImpl(Features, "xsaveopt", true);
196  LLVM_FALLTHROUGH;
197  case CK_Westmere:
198  setFeatureEnabledImpl(Features, "aes", true);
199  setFeatureEnabledImpl(Features, "pclmul", true);
200  LLVM_FALLTHROUGH;
201  case CK_Nehalem:
202  setFeatureEnabledImpl(Features, "sse4.2", true);
203  LLVM_FALLTHROUGH;
204  case CK_Penryn:
205  setFeatureEnabledImpl(Features, "sse4.1", true);
206  LLVM_FALLTHROUGH;
207  case CK_Core2:
208  setFeatureEnabledImpl(Features, "ssse3", true);
209  setFeatureEnabledImpl(Features, "sahf", true);
210  LLVM_FALLTHROUGH;
211  case CK_Yonah:
212  case CK_Prescott:
213  case CK_Nocona:
214  setFeatureEnabledImpl(Features, "sse3", true);
215  setFeatureEnabledImpl(Features, "cx16", true);
216  LLVM_FALLTHROUGH;
217  case CK_PentiumM:
218  case CK_Pentium4:
219  case CK_x86_64:
220  setFeatureEnabledImpl(Features, "sse2", true);
221  LLVM_FALLTHROUGH;
222  case CK_Pentium3:
223  case CK_C3_2:
224  setFeatureEnabledImpl(Features, "sse", true);
225  setFeatureEnabledImpl(Features, "fxsr", true);
226  break;
227 
228  case CK_Tremont:
229  setFeatureEnabledImpl(Features, "cldemote", true);
230  setFeatureEnabledImpl(Features, "movdiri", true);
231  setFeatureEnabledImpl(Features, "movdir64b", true);
232  setFeatureEnabledImpl(Features, "gfni", true);
233  setFeatureEnabledImpl(Features, "waitpkg", true);
234  LLVM_FALLTHROUGH;
235  case CK_GoldmontPlus:
236  setFeatureEnabledImpl(Features, "ptwrite", true);
237  setFeatureEnabledImpl(Features, "rdpid", true);
238  setFeatureEnabledImpl(Features, "sgx", true);
239  LLVM_FALLTHROUGH;
240  case CK_Goldmont:
241  setFeatureEnabledImpl(Features, "sha", true);
242  setFeatureEnabledImpl(Features, "rdseed", true);
243  setFeatureEnabledImpl(Features, "xsave", true);
244  setFeatureEnabledImpl(Features, "xsaveopt", true);
245  setFeatureEnabledImpl(Features, "xsavec", true);
246  setFeatureEnabledImpl(Features, "xsaves", true);
247  setFeatureEnabledImpl(Features, "clflushopt", true);
248  setFeatureEnabledImpl(Features, "mpx", true);
249  setFeatureEnabledImpl(Features, "fsgsbase", true);
250  LLVM_FALLTHROUGH;
251  case CK_Silvermont:
252  setFeatureEnabledImpl(Features, "rdrnd", true);
253  setFeatureEnabledImpl(Features, "aes", true);
254  setFeatureEnabledImpl(Features, "pclmul", true);
255  setFeatureEnabledImpl(Features, "sse4.2", true);
256  setFeatureEnabledImpl(Features, "prfchw", true);
257  LLVM_FALLTHROUGH;
258  case CK_Bonnell:
259  setFeatureEnabledImpl(Features, "movbe", true);
260  setFeatureEnabledImpl(Features, "ssse3", true);
261  setFeatureEnabledImpl(Features, "fxsr", true);
262  setFeatureEnabledImpl(Features, "cx16", true);
263  setFeatureEnabledImpl(Features, "sahf", true);
264  break;
265 
266  case CK_KNM:
267  // TODO: Add avx5124fmaps/avx5124vnniw.
268  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
269  LLVM_FALLTHROUGH;
270  case CK_KNL:
271  setFeatureEnabledImpl(Features, "avx512f", true);
272  setFeatureEnabledImpl(Features, "avx512cd", true);
273  setFeatureEnabledImpl(Features, "avx512er", true);
274  setFeatureEnabledImpl(Features, "avx512pf", true);
275  setFeatureEnabledImpl(Features, "prfchw", true);
276  setFeatureEnabledImpl(Features, "prefetchwt1", true);
277  setFeatureEnabledImpl(Features, "fxsr", true);
278  setFeatureEnabledImpl(Features, "rdseed", true);
279  setFeatureEnabledImpl(Features, "adx", true);
280  setFeatureEnabledImpl(Features, "lzcnt", true);
281  setFeatureEnabledImpl(Features, "bmi", true);
282  setFeatureEnabledImpl(Features, "bmi2", true);
283  setFeatureEnabledImpl(Features, "rtm", true);
284  setFeatureEnabledImpl(Features, "fma", true);
285  setFeatureEnabledImpl(Features, "rdrnd", true);
286  setFeatureEnabledImpl(Features, "f16c", true);
287  setFeatureEnabledImpl(Features, "fsgsbase", true);
288  setFeatureEnabledImpl(Features, "aes", true);
289  setFeatureEnabledImpl(Features, "pclmul", true);
290  setFeatureEnabledImpl(Features, "cx16", true);
291  setFeatureEnabledImpl(Features, "xsaveopt", true);
292  setFeatureEnabledImpl(Features, "xsave", true);
293  setFeatureEnabledImpl(Features, "movbe", true);
294  setFeatureEnabledImpl(Features, "sahf", true);
295  break;
296 
297  case CK_K6_2:
298  case CK_K6_3:
299  case CK_WinChip2:
300  case CK_C3:
301  setFeatureEnabledImpl(Features, "3dnow", true);
302  break;
303 
304  case CK_AMDFAM10:
305  setFeatureEnabledImpl(Features, "sse4a", true);
306  setFeatureEnabledImpl(Features, "lzcnt", true);
307  setFeatureEnabledImpl(Features, "popcnt", true);
308  setFeatureEnabledImpl(Features, "sahf", true);
309  LLVM_FALLTHROUGH;
310  case CK_K8SSE3:
311  setFeatureEnabledImpl(Features, "sse3", true);
312  LLVM_FALLTHROUGH;
313  case CK_K8:
314  setFeatureEnabledImpl(Features, "sse2", true);
315  LLVM_FALLTHROUGH;
316  case CK_AthlonXP:
317  setFeatureEnabledImpl(Features, "sse", true);
318  setFeatureEnabledImpl(Features, "fxsr", true);
319  LLVM_FALLTHROUGH;
320  case CK_Athlon:
321  case CK_Geode:
322  setFeatureEnabledImpl(Features, "3dnowa", true);
323  break;
324 
325  case CK_BTVER2:
326  setFeatureEnabledImpl(Features, "avx", true);
327  setFeatureEnabledImpl(Features, "aes", true);
328  setFeatureEnabledImpl(Features, "pclmul", true);
329  setFeatureEnabledImpl(Features, "bmi", true);
330  setFeatureEnabledImpl(Features, "f16c", true);
331  setFeatureEnabledImpl(Features, "xsaveopt", true);
332  setFeatureEnabledImpl(Features, "movbe", true);
333  LLVM_FALLTHROUGH;
334  case CK_BTVER1:
335  setFeatureEnabledImpl(Features, "ssse3", true);
336  setFeatureEnabledImpl(Features, "sse4a", true);
337  setFeatureEnabledImpl(Features, "lzcnt", true);
338  setFeatureEnabledImpl(Features, "popcnt", true);
339  setFeatureEnabledImpl(Features, "prfchw", true);
340  setFeatureEnabledImpl(Features, "cx16", true);
341  setFeatureEnabledImpl(Features, "fxsr", true);
342  setFeatureEnabledImpl(Features, "sahf", true);
343  break;
344 
345  case CK_ZNVER1:
346  setFeatureEnabledImpl(Features, "adx", true);
347  setFeatureEnabledImpl(Features, "aes", true);
348  setFeatureEnabledImpl(Features, "avx2", true);
349  setFeatureEnabledImpl(Features, "bmi", true);
350  setFeatureEnabledImpl(Features, "bmi2", true);
351  setFeatureEnabledImpl(Features, "clflushopt", true);
352  setFeatureEnabledImpl(Features, "clzero", true);
353  setFeatureEnabledImpl(Features, "cx16", true);
354  setFeatureEnabledImpl(Features, "f16c", true);
355  setFeatureEnabledImpl(Features, "fma", true);
356  setFeatureEnabledImpl(Features, "fsgsbase", true);
357  setFeatureEnabledImpl(Features, "fxsr", true);
358  setFeatureEnabledImpl(Features, "lzcnt", true);
359  setFeatureEnabledImpl(Features, "mwaitx", true);
360  setFeatureEnabledImpl(Features, "movbe", true);
361  setFeatureEnabledImpl(Features, "pclmul", true);
362  setFeatureEnabledImpl(Features, "popcnt", true);
363  setFeatureEnabledImpl(Features, "prfchw", true);
364  setFeatureEnabledImpl(Features, "rdrnd", true);
365  setFeatureEnabledImpl(Features, "rdseed", true);
366  setFeatureEnabledImpl(Features, "sahf", true);
367  setFeatureEnabledImpl(Features, "sha", true);
368  setFeatureEnabledImpl(Features, "sse4a", true);
369  setFeatureEnabledImpl(Features, "xsave", true);
370  setFeatureEnabledImpl(Features, "xsavec", true);
371  setFeatureEnabledImpl(Features, "xsaveopt", true);
372  setFeatureEnabledImpl(Features, "xsaves", true);
373  break;
374 
375  case CK_BDVER4:
376  setFeatureEnabledImpl(Features, "avx2", true);
377  setFeatureEnabledImpl(Features, "bmi2", true);
378  setFeatureEnabledImpl(Features, "mwaitx", true);
379  LLVM_FALLTHROUGH;
380  case CK_BDVER3:
381  setFeatureEnabledImpl(Features, "fsgsbase", true);
382  setFeatureEnabledImpl(Features, "xsaveopt", true);
383  LLVM_FALLTHROUGH;
384  case CK_BDVER2:
385  setFeatureEnabledImpl(Features, "bmi", true);
386  setFeatureEnabledImpl(Features, "fma", true);
387  setFeatureEnabledImpl(Features, "f16c", true);
388  setFeatureEnabledImpl(Features, "tbm", true);
389  LLVM_FALLTHROUGH;
390  case CK_BDVER1:
391  // xop implies avx, sse4a and fma4.
392  setFeatureEnabledImpl(Features, "xop", true);
393  setFeatureEnabledImpl(Features, "lwp", true);
394  setFeatureEnabledImpl(Features, "lzcnt", true);
395  setFeatureEnabledImpl(Features, "aes", true);
396  setFeatureEnabledImpl(Features, "pclmul", true);
397  setFeatureEnabledImpl(Features, "prfchw", true);
398  setFeatureEnabledImpl(Features, "cx16", true);
399  setFeatureEnabledImpl(Features, "fxsr", true);
400  setFeatureEnabledImpl(Features, "xsave", true);
401  setFeatureEnabledImpl(Features, "sahf", true);
402  break;
403  }
404  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
405  return false;
406 
407  // Can't do this earlier because we need to be able to explicitly enable
408  // or disable these features and the things that they depend upon.
409 
410  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
411  auto I = Features.find("sse4.2");
412  if (I != Features.end() && I->getValue() &&
413  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
414  FeaturesVec.end())
415  Features["popcnt"] = true;
416 
417  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
418  I = Features.find("3dnow");
419  if (I != Features.end() && I->getValue() &&
420  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
421  FeaturesVec.end())
422  Features["prfchw"] = true;
423 
424  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
425  // then enable MMX.
426  I = Features.find("sse");
427  if (I != Features.end() && I->getValue() &&
428  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
429  FeaturesVec.end())
430  Features["mmx"] = true;
431 
432  return true;
433 }
434 
435 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
436  X86SSEEnum Level, bool Enabled) {
437  if (Enabled) {
438  switch (Level) {
439  case AVX512F:
440  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
441  LLVM_FALLTHROUGH;
442  case AVX2:
443  Features["avx2"] = true;
444  LLVM_FALLTHROUGH;
445  case AVX:
446  Features["avx"] = true;
447  Features["xsave"] = true;
448  LLVM_FALLTHROUGH;
449  case SSE42:
450  Features["sse4.2"] = true;
451  LLVM_FALLTHROUGH;
452  case SSE41:
453  Features["sse4.1"] = true;
454  LLVM_FALLTHROUGH;
455  case SSSE3:
456  Features["ssse3"] = true;
457  LLVM_FALLTHROUGH;
458  case SSE3:
459  Features["sse3"] = true;
460  LLVM_FALLTHROUGH;
461  case SSE2:
462  Features["sse2"] = true;
463  LLVM_FALLTHROUGH;
464  case SSE1:
465  Features["sse"] = true;
466  LLVM_FALLTHROUGH;
467  case NoSSE:
468  break;
469  }
470  return;
471  }
472 
473  switch (Level) {
474  case NoSSE:
475  case SSE1:
476  Features["sse"] = false;
477  LLVM_FALLTHROUGH;
478  case SSE2:
479  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
480  Features["gfni"] = false;
481  LLVM_FALLTHROUGH;
482  case SSE3:
483  Features["sse3"] = false;
484  setXOPLevel(Features, NoXOP, false);
485  LLVM_FALLTHROUGH;
486  case SSSE3:
487  Features["ssse3"] = false;
488  LLVM_FALLTHROUGH;
489  case SSE41:
490  Features["sse4.1"] = false;
491  LLVM_FALLTHROUGH;
492  case SSE42:
493  Features["sse4.2"] = false;
494  LLVM_FALLTHROUGH;
495  case AVX:
496  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
497  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
498  setXOPLevel(Features, FMA4, false);
499  LLVM_FALLTHROUGH;
500  case AVX2:
501  Features["avx2"] = false;
502  LLVM_FALLTHROUGH;
503  case AVX512F:
504  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
505  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
506  Features["avx512vl"] = Features["avx512vbmi"] =
507  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
508  Features["avx512bitalg"] = Features["avx512vnni"] =
509  Features["avx512vbmi2"] = false;
510  break;
511  }
512 }
513 
514 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
515  MMX3DNowEnum Level, bool Enabled) {
516  if (Enabled) {
517  switch (Level) {
518  case AMD3DNowAthlon:
519  Features["3dnowa"] = true;
520  LLVM_FALLTHROUGH;
521  case AMD3DNow:
522  Features["3dnow"] = true;
523  LLVM_FALLTHROUGH;
524  case MMX:
525  Features["mmx"] = true;
526  LLVM_FALLTHROUGH;
527  case NoMMX3DNow:
528  break;
529  }
530  return;
531  }
532 
533  switch (Level) {
534  case NoMMX3DNow:
535  case MMX:
536  Features["mmx"] = false;
537  LLVM_FALLTHROUGH;
538  case AMD3DNow:
539  Features["3dnow"] = false;
540  LLVM_FALLTHROUGH;
541  case AMD3DNowAthlon:
542  Features["3dnowa"] = false;
543  break;
544  }
545 }
546 
547 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
548  bool Enabled) {
549  if (Enabled) {
550  switch (Level) {
551  case XOP:
552  Features["xop"] = true;
553  LLVM_FALLTHROUGH;
554  case FMA4:
555  Features["fma4"] = true;
556  setSSELevel(Features, AVX, true);
557  LLVM_FALLTHROUGH;
558  case SSE4A:
559  Features["sse4a"] = true;
560  setSSELevel(Features, SSE3, true);
561  LLVM_FALLTHROUGH;
562  case NoXOP:
563  break;
564  }
565  return;
566  }
567 
568  switch (Level) {
569  case NoXOP:
570  case SSE4A:
571  Features["sse4a"] = false;
572  LLVM_FALLTHROUGH;
573  case FMA4:
574  Features["fma4"] = false;
575  LLVM_FALLTHROUGH;
576  case XOP:
577  Features["xop"] = false;
578  break;
579  }
580 }
581 
582 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
583  StringRef Name, bool Enabled) {
584  // This is a bit of a hack to deal with the sse4 target feature when used
585  // as part of the target attribute. We handle sse4 correctly everywhere
586  // else. See below for more information on how we handle the sse4 options.
587  if (Name != "sse4")
588  Features[Name] = Enabled;
589 
590  if (Name == "mmx") {
591  setMMXLevel(Features, MMX, Enabled);
592  } else if (Name == "sse") {
593  setSSELevel(Features, SSE1, Enabled);
594  } else if (Name == "sse2") {
595  setSSELevel(Features, SSE2, Enabled);
596  } else if (Name == "sse3") {
597  setSSELevel(Features, SSE3, Enabled);
598  } else if (Name == "ssse3") {
599  setSSELevel(Features, SSSE3, Enabled);
600  } else if (Name == "sse4.2") {
601  setSSELevel(Features, SSE42, Enabled);
602  } else if (Name == "sse4.1") {
603  setSSELevel(Features, SSE41, Enabled);
604  } else if (Name == "3dnow") {
605  setMMXLevel(Features, AMD3DNow, Enabled);
606  } else if (Name == "3dnowa") {
607  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
608  } else if (Name == "aes") {
609  if (Enabled)
610  setSSELevel(Features, SSE2, Enabled);
611  else
612  Features["vaes"] = false;
613  } else if (Name == "vaes") {
614  if (Enabled) {
615  setSSELevel(Features, AVX, Enabled);
616  Features["aes"] = true;
617  }
618  } else if (Name == "pclmul") {
619  if (Enabled)
620  setSSELevel(Features, SSE2, Enabled);
621  else
622  Features["vpclmulqdq"] = false;
623  } else if (Name == "vpclmulqdq") {
624  if (Enabled) {
625  setSSELevel(Features, AVX, Enabled);
626  Features["pclmul"] = true;
627  }
628  } else if (Name == "gfni") {
629  if (Enabled)
630  setSSELevel(Features, SSE2, Enabled);
631  } else if (Name == "avx") {
632  setSSELevel(Features, AVX, Enabled);
633  } else if (Name == "avx2") {
634  setSSELevel(Features, AVX2, Enabled);
635  } else if (Name == "avx512f") {
636  setSSELevel(Features, AVX512F, Enabled);
637  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
638  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
639  Name == "avx512vbmi" || Name == "avx512ifma" ||
640  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
641  Name == "avx512vnni" || Name == "avx512vbmi2") {
642  if (Enabled)
643  setSSELevel(Features, AVX512F, Enabled);
644  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
645  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
646  Features["avx512bw"] = true;
647  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
648  if (Name == "avx512bw" && !Enabled)
649  Features["avx512vbmi"] = Features["avx512vbmi2"] =
650  Features["avx512bitalg"] = false;
651  } else if (Name == "fma") {
652  if (Enabled)
653  setSSELevel(Features, AVX, Enabled);
654  else
655  setSSELevel(Features, AVX512F, Enabled);
656  } else if (Name == "fma4") {
657  setXOPLevel(Features, FMA4, Enabled);
658  } else if (Name == "xop") {
659  setXOPLevel(Features, XOP, Enabled);
660  } else if (Name == "sse4a") {
661  setXOPLevel(Features, SSE4A, Enabled);
662  } else if (Name == "f16c") {
663  if (Enabled)
664  setSSELevel(Features, AVX, Enabled);
665  else
666  setSSELevel(Features, AVX512F, Enabled);
667  } else if (Name == "sha") {
668  if (Enabled)
669  setSSELevel(Features, SSE2, Enabled);
670  } else if (Name == "sse4") {
671  // We can get here via the __target__ attribute since that's not controlled
672  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
673  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
674  // disabled.
675  if (Enabled)
676  setSSELevel(Features, SSE42, Enabled);
677  else
678  setSSELevel(Features, SSE41, Enabled);
679  } else if (Name == "xsave") {
680  if (!Enabled)
681  Features["xsaveopt"] = false;
682  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
683  if (Enabled)
684  Features["xsave"] = true;
685  }
686 }
687 
688 /// handleTargetFeatures - Perform initialization based on the user
689 /// configured set of features.
690 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
691  DiagnosticsEngine &Diags) {
692  for (const auto &Feature : Features) {
693  if (Feature[0] != '+')
694  continue;
695 
696  if (Feature == "+aes") {
697  HasAES = true;
698  } else if (Feature == "+vaes") {
699  HasVAES = true;
700  } else if (Feature == "+pclmul") {
701  HasPCLMUL = true;
702  } else if (Feature == "+vpclmulqdq") {
703  HasVPCLMULQDQ = true;
704  } else if (Feature == "+lzcnt") {
705  HasLZCNT = true;
706  } else if (Feature == "+rdrnd") {
707  HasRDRND = true;
708  } else if (Feature == "+fsgsbase") {
709  HasFSGSBASE = true;
710  } else if (Feature == "+bmi") {
711  HasBMI = true;
712  } else if (Feature == "+bmi2") {
713  HasBMI2 = true;
714  } else if (Feature == "+popcnt") {
715  HasPOPCNT = true;
716  } else if (Feature == "+rtm") {
717  HasRTM = true;
718  } else if (Feature == "+prfchw") {
719  HasPRFCHW = true;
720  } else if (Feature == "+rdseed") {
721  HasRDSEED = true;
722  } else if (Feature == "+adx") {
723  HasADX = true;
724  } else if (Feature == "+tbm") {
725  HasTBM = true;
726  } else if (Feature == "+lwp") {
727  HasLWP = true;
728  } else if (Feature == "+fma") {
729  HasFMA = true;
730  } else if (Feature == "+f16c") {
731  HasF16C = true;
732  } else if (Feature == "+gfni") {
733  HasGFNI = true;
734  } else if (Feature == "+avx512cd") {
735  HasAVX512CD = true;
736  } else if (Feature == "+avx512vpopcntdq") {
737  HasAVX512VPOPCNTDQ = true;
738  } else if (Feature == "+avx512vnni") {
739  HasAVX512VNNI = true;
740  } else if (Feature == "+avx512er") {
741  HasAVX512ER = true;
742  } else if (Feature == "+avx512pf") {
743  HasAVX512PF = true;
744  } else if (Feature == "+avx512dq") {
745  HasAVX512DQ = true;
746  } else if (Feature == "+avx512bitalg") {
747  HasAVX512BITALG = true;
748  } else if (Feature == "+avx512bw") {
749  HasAVX512BW = true;
750  } else if (Feature == "+avx512vl") {
751  HasAVX512VL = true;
752  } else if (Feature == "+avx512vbmi") {
753  HasAVX512VBMI = true;
754  } else if (Feature == "+avx512vbmi2") {
755  HasAVX512VBMI2 = true;
756  } else if (Feature == "+avx512ifma") {
757  HasAVX512IFMA = true;
758  } else if (Feature == "+sha") {
759  HasSHA = true;
760  } else if (Feature == "+mpx") {
761  HasMPX = true;
762  } else if (Feature == "+shstk") {
763  HasSHSTK = true;
764  } else if (Feature == "+movbe") {
765  HasMOVBE = true;
766  } else if (Feature == "+sgx") {
767  HasSGX = true;
768  } else if (Feature == "+cx16") {
769  HasCX16 = true;
770  } else if (Feature == "+fxsr") {
771  HasFXSR = true;
772  } else if (Feature == "+xsave") {
773  HasXSAVE = true;
774  } else if (Feature == "+xsaveopt") {
775  HasXSAVEOPT = true;
776  } else if (Feature == "+xsavec") {
777  HasXSAVEC = true;
778  } else if (Feature == "+xsaves") {
779  HasXSAVES = true;
780  } else if (Feature == "+mwaitx") {
781  HasMWAITX = true;
782  } else if (Feature == "+pku") {
783  HasPKU = true;
784  } else if (Feature == "+clflushopt") {
785  HasCLFLUSHOPT = true;
786  } else if (Feature == "+clwb") {
787  HasCLWB = true;
788  } else if (Feature == "+wbnoinvd") {
789  HasWBNOINVD = true;
790  } else if (Feature == "+prefetchwt1") {
791  HasPREFETCHWT1 = true;
792  } else if (Feature == "+clzero") {
793  HasCLZERO = true;
794  } else if (Feature == "+cldemote") {
795  HasCLDEMOTE = true;
796  } else if (Feature == "+rdpid") {
797  HasRDPID = true;
798  } else if (Feature == "+retpoline") {
799  HasRetpoline = true;
800  } else if (Feature == "+retpoline-external-thunk") {
801  HasRetpolineExternalThunk = true;
802  } else if (Feature == "+sahf") {
803  HasLAHFSAHF = true;
804  } else if (Feature == "+waitpkg") {
805  HasWAITPKG = true;
806  } else if (Feature == "+movdiri") {
807  HasMOVDIRI = true;
808  } else if (Feature == "+movdir64b") {
809  HasMOVDIR64B = true;
810  } else if (Feature == "+pconfig") {
811  HasPCONFIG = true;
812  } else if (Feature == "+ptwrite") {
813  HasPTWRITE = true;
814  }
815 
816  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
817  .Case("+avx512f", AVX512F)
818  .Case("+avx2", AVX2)
819  .Case("+avx", AVX)
820  .Case("+sse4.2", SSE42)
821  .Case("+sse4.1", SSE41)
822  .Case("+ssse3", SSSE3)
823  .Case("+sse3", SSE3)
824  .Case("+sse2", SSE2)
825  .Case("+sse", SSE1)
826  .Default(NoSSE);
827  SSELevel = std::max(SSELevel, Level);
828 
829  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
830  .Case("+3dnowa", AMD3DNowAthlon)
831  .Case("+3dnow", AMD3DNow)
832  .Case("+mmx", MMX)
833  .Default(NoMMX3DNow);
834  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
835 
836  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
837  .Case("+xop", XOP)
838  .Case("+fma4", FMA4)
839  .Case("+sse4a", SSE4A)
840  .Default(NoXOP);
841  XOPLevel = std::max(XOPLevel, XLevel);
842  }
843 
844  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
845  // matches the selected sse level.
846  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
847  (FPMath == FP_387 && SSELevel >= SSE1)) {
848  Diags.Report(diag::err_target_unsupported_fpmath)
849  << (FPMath == FP_SSE ? "sse" : "387");
850  return false;
851  }
852 
853  SimdDefaultAlign =
854  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
855  return true;
856 }
857 
858 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
859 /// definitions for this particular subtarget.
861  MacroBuilder &Builder) const {
862  // Target identification.
863  if (getTriple().getArch() == llvm::Triple::x86_64) {
864  Builder.defineMacro("__amd64__");
865  Builder.defineMacro("__amd64");
866  Builder.defineMacro("__x86_64");
867  Builder.defineMacro("__x86_64__");
868  if (getTriple().getArchName() == "x86_64h") {
869  Builder.defineMacro("__x86_64h");
870  Builder.defineMacro("__x86_64h__");
871  }
872  } else {
873  DefineStd(Builder, "i386", Opts);
874  }
875 
876  // Subtarget options.
877  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
878  // truly should be based on -mtune options.
879  switch (CPU) {
880  case CK_Generic:
881  break;
882  case CK_i386:
883  // The rest are coming from the i386 define above.
884  Builder.defineMacro("__tune_i386__");
885  break;
886  case CK_i486:
887  case CK_WinChipC6:
888  case CK_WinChip2:
889  case CK_C3:
890  defineCPUMacros(Builder, "i486");
891  break;
892  case CK_PentiumMMX:
893  Builder.defineMacro("__pentium_mmx__");
894  Builder.defineMacro("__tune_pentium_mmx__");
895  LLVM_FALLTHROUGH;
896  case CK_i586:
897  case CK_Pentium:
898  defineCPUMacros(Builder, "i586");
899  defineCPUMacros(Builder, "pentium");
900  break;
901  case CK_Pentium3:
902  case CK_PentiumM:
903  Builder.defineMacro("__tune_pentium3__");
904  LLVM_FALLTHROUGH;
905  case CK_Pentium2:
906  case CK_C3_2:
907  Builder.defineMacro("__tune_pentium2__");
908  LLVM_FALLTHROUGH;
909  case CK_PentiumPro:
910  defineCPUMacros(Builder, "i686");
911  defineCPUMacros(Builder, "pentiumpro");
912  break;
913  case CK_Pentium4:
914  defineCPUMacros(Builder, "pentium4");
915  break;
916  case CK_Yonah:
917  case CK_Prescott:
918  case CK_Nocona:
919  defineCPUMacros(Builder, "nocona");
920  break;
921  case CK_Core2:
922  case CK_Penryn:
923  defineCPUMacros(Builder, "core2");
924  break;
925  case CK_Bonnell:
926  defineCPUMacros(Builder, "atom");
927  break;
928  case CK_Silvermont:
929  defineCPUMacros(Builder, "slm");
930  break;
931  case CK_Goldmont:
932  defineCPUMacros(Builder, "goldmont");
933  break;
934  case CK_GoldmontPlus:
935  defineCPUMacros(Builder, "goldmont_plus");
936  break;
937  case CK_Tremont:
938  defineCPUMacros(Builder, "tremont");
939  break;
940  case CK_Nehalem:
941  case CK_Westmere:
942  case CK_SandyBridge:
943  case CK_IvyBridge:
944  case CK_Haswell:
945  case CK_Broadwell:
946  case CK_SkylakeClient:
947  case CK_SkylakeServer:
948  case CK_Cannonlake:
949  case CK_IcelakeClient:
950  case CK_IcelakeServer:
951  // FIXME: Historically, we defined this legacy name, it would be nice to
952  // remove it at some point. We've never exposed fine-grained names for
953  // recent primary x86 CPUs, and we should keep it that way.
954  defineCPUMacros(Builder, "corei7");
955  break;
956  case CK_KNL:
957  defineCPUMacros(Builder, "knl");
958  break;
959  case CK_KNM:
960  break;
961  case CK_Lakemont:
962  defineCPUMacros(Builder, "i586", /*Tuning*/false);
963  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
964  Builder.defineMacro("__tune_lakemont__");
965  break;
966  case CK_K6_2:
967  Builder.defineMacro("__k6_2__");
968  Builder.defineMacro("__tune_k6_2__");
969  LLVM_FALLTHROUGH;
970  case CK_K6_3:
971  if (CPU != CK_K6_2) { // In case of fallthrough
972  // FIXME: GCC may be enabling these in cases where some other k6
973  // architecture is specified but -m3dnow is explicitly provided. The
974  // exact semantics need to be determined and emulated here.
975  Builder.defineMacro("__k6_3__");
976  Builder.defineMacro("__tune_k6_3__");
977  }
978  LLVM_FALLTHROUGH;
979  case CK_K6:
980  defineCPUMacros(Builder, "k6");
981  break;
982  case CK_Athlon:
983  case CK_AthlonXP:
984  defineCPUMacros(Builder, "athlon");
985  if (SSELevel != NoSSE) {
986  Builder.defineMacro("__athlon_sse__");
987  Builder.defineMacro("__tune_athlon_sse__");
988  }
989  break;
990  case CK_K8:
991  case CK_K8SSE3:
992  case CK_x86_64:
993  defineCPUMacros(Builder, "k8");
994  break;
995  case CK_AMDFAM10:
996  defineCPUMacros(Builder, "amdfam10");
997  break;
998  case CK_BTVER1:
999  defineCPUMacros(Builder, "btver1");
1000  break;
1001  case CK_BTVER2:
1002  defineCPUMacros(Builder, "btver2");
1003  break;
1004  case CK_BDVER1:
1005  defineCPUMacros(Builder, "bdver1");
1006  break;
1007  case CK_BDVER2:
1008  defineCPUMacros(Builder, "bdver2");
1009  break;
1010  case CK_BDVER3:
1011  defineCPUMacros(Builder, "bdver3");
1012  break;
1013  case CK_BDVER4:
1014  defineCPUMacros(Builder, "bdver4");
1015  break;
1016  case CK_ZNVER1:
1017  defineCPUMacros(Builder, "znver1");
1018  break;
1019  case CK_Geode:
1020  defineCPUMacros(Builder, "geode");
1021  break;
1022  }
1023 
1024  // Target properties.
1025  Builder.defineMacro("__REGISTER_PREFIX__", "");
1026 
1027  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1028  // functions in glibc header files that use FP Stack inline asm which the
1029  // backend can't deal with (PR879).
1030  Builder.defineMacro("__NO_MATH_INLINES");
1031 
1032  if (HasAES)
1033  Builder.defineMacro("__AES__");
1034 
1035  if (HasVAES)
1036  Builder.defineMacro("__VAES__");
1037 
1038  if (HasPCLMUL)
1039  Builder.defineMacro("__PCLMUL__");
1040 
1041  if (HasVPCLMULQDQ)
1042  Builder.defineMacro("__VPCLMULQDQ__");
1043 
1044  if (HasLZCNT)
1045  Builder.defineMacro("__LZCNT__");
1046 
1047  if (HasRDRND)
1048  Builder.defineMacro("__RDRND__");
1049 
1050  if (HasFSGSBASE)
1051  Builder.defineMacro("__FSGSBASE__");
1052 
1053  if (HasBMI)
1054  Builder.defineMacro("__BMI__");
1055 
1056  if (HasBMI2)
1057  Builder.defineMacro("__BMI2__");
1058 
1059  if (HasPOPCNT)
1060  Builder.defineMacro("__POPCNT__");
1061 
1062  if (HasRTM)
1063  Builder.defineMacro("__RTM__");
1064 
1065  if (HasPRFCHW)
1066  Builder.defineMacro("__PRFCHW__");
1067 
1068  if (HasRDSEED)
1069  Builder.defineMacro("__RDSEED__");
1070 
1071  if (HasADX)
1072  Builder.defineMacro("__ADX__");
1073 
1074  if (HasTBM)
1075  Builder.defineMacro("__TBM__");
1076 
1077  if (HasLWP)
1078  Builder.defineMacro("__LWP__");
1079 
1080  if (HasMWAITX)
1081  Builder.defineMacro("__MWAITX__");
1082 
1083  switch (XOPLevel) {
1084  case XOP:
1085  Builder.defineMacro("__XOP__");
1086  LLVM_FALLTHROUGH;
1087  case FMA4:
1088  Builder.defineMacro("__FMA4__");
1089  LLVM_FALLTHROUGH;
1090  case SSE4A:
1091  Builder.defineMacro("__SSE4A__");
1092  LLVM_FALLTHROUGH;
1093  case NoXOP:
1094  break;
1095  }
1096 
1097  if (HasFMA)
1098  Builder.defineMacro("__FMA__");
1099 
1100  if (HasF16C)
1101  Builder.defineMacro("__F16C__");
1102 
1103  if (HasGFNI)
1104  Builder.defineMacro("__GFNI__");
1105 
1106  if (HasAVX512CD)
1107  Builder.defineMacro("__AVX512CD__");
1108  if (HasAVX512VPOPCNTDQ)
1109  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1110  if (HasAVX512VNNI)
1111  Builder.defineMacro("__AVX512VNNI__");
1112  if (HasAVX512ER)
1113  Builder.defineMacro("__AVX512ER__");
1114  if (HasAVX512PF)
1115  Builder.defineMacro("__AVX512PF__");
1116  if (HasAVX512DQ)
1117  Builder.defineMacro("__AVX512DQ__");
1118  if (HasAVX512BITALG)
1119  Builder.defineMacro("__AVX512BITALG__");
1120  if (HasAVX512BW)
1121  Builder.defineMacro("__AVX512BW__");
1122  if (HasAVX512VL)
1123  Builder.defineMacro("__AVX512VL__");
1124  if (HasAVX512VBMI)
1125  Builder.defineMacro("__AVX512VBMI__");
1126  if (HasAVX512VBMI2)
1127  Builder.defineMacro("__AVX512VBMI2__");
1128  if (HasAVX512IFMA)
1129  Builder.defineMacro("__AVX512IFMA__");
1130 
1131  if (HasSHA)
1132  Builder.defineMacro("__SHA__");
1133 
1134  if (HasFXSR)
1135  Builder.defineMacro("__FXSR__");
1136  if (HasXSAVE)
1137  Builder.defineMacro("__XSAVE__");
1138  if (HasXSAVEOPT)
1139  Builder.defineMacro("__XSAVEOPT__");
1140  if (HasXSAVEC)
1141  Builder.defineMacro("__XSAVEC__");
1142  if (HasXSAVES)
1143  Builder.defineMacro("__XSAVES__");
1144  if (HasPKU)
1145  Builder.defineMacro("__PKU__");
1146  if (HasCLFLUSHOPT)
1147  Builder.defineMacro("__CLFLUSHOPT__");
1148  if (HasCLWB)
1149  Builder.defineMacro("__CLWB__");
1150  if (HasWBNOINVD)
1151  Builder.defineMacro("__WBNOINVD__");
1152  if (HasMPX)
1153  Builder.defineMacro("__MPX__");
1154  if (HasSHSTK)
1155  Builder.defineMacro("__SHSTK__");
1156  if (HasSGX)
1157  Builder.defineMacro("__SGX__");
1158  if (HasPREFETCHWT1)
1159  Builder.defineMacro("__PREFETCHWT1__");
1160  if (HasCLZERO)
1161  Builder.defineMacro("__CLZERO__");
1162  if (HasRDPID)
1163  Builder.defineMacro("__RDPID__");
1164  if (HasCLDEMOTE)
1165  Builder.defineMacro("__CLDEMOTE__");
1166  if (HasWAITPKG)
1167  Builder.defineMacro("__WAITPKG__");
1168  if (HasMOVDIRI)
1169  Builder.defineMacro("__MOVDIRI__");
1170  if (HasMOVDIR64B)
1171  Builder.defineMacro("__MOVDIR64B__");
1172  if (HasPCONFIG)
1173  Builder.defineMacro("__PCONFIG__");
1174  if (HasPTWRITE)
1175  Builder.defineMacro("__PTWRITE__");
1176 
1177  // Each case falls through to the previous one here.
1178  switch (SSELevel) {
1179  case AVX512F:
1180  Builder.defineMacro("__AVX512F__");
1181  LLVM_FALLTHROUGH;
1182  case AVX2:
1183  Builder.defineMacro("__AVX2__");
1184  LLVM_FALLTHROUGH;
1185  case AVX:
1186  Builder.defineMacro("__AVX__");
1187  LLVM_FALLTHROUGH;
1188  case SSE42:
1189  Builder.defineMacro("__SSE4_2__");
1190  LLVM_FALLTHROUGH;
1191  case SSE41:
1192  Builder.defineMacro("__SSE4_1__");
1193  LLVM_FALLTHROUGH;
1194  case SSSE3:
1195  Builder.defineMacro("__SSSE3__");
1196  LLVM_FALLTHROUGH;
1197  case SSE3:
1198  Builder.defineMacro("__SSE3__");
1199  LLVM_FALLTHROUGH;
1200  case SSE2:
1201  Builder.defineMacro("__SSE2__");
1202  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1203  LLVM_FALLTHROUGH;
1204  case SSE1:
1205  Builder.defineMacro("__SSE__");
1206  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1207  LLVM_FALLTHROUGH;
1208  case NoSSE:
1209  break;
1210  }
1211 
1212  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1213  switch (SSELevel) {
1214  case AVX512F:
1215  case AVX2:
1216  case AVX:
1217  case SSE42:
1218  case SSE41:
1219  case SSSE3:
1220  case SSE3:
1221  case SSE2:
1222  Builder.defineMacro("_M_IX86_FP", Twine(2));
1223  break;
1224  case SSE1:
1225  Builder.defineMacro("_M_IX86_FP", Twine(1));
1226  break;
1227  default:
1228  Builder.defineMacro("_M_IX86_FP", Twine(0));
1229  break;
1230  }
1231  }
1232 
1233  // Each case falls through to the previous one here.
1234  switch (MMX3DNowLevel) {
1235  case AMD3DNowAthlon:
1236  Builder.defineMacro("__3dNOW_A__");
1237  LLVM_FALLTHROUGH;
1238  case AMD3DNow:
1239  Builder.defineMacro("__3dNOW__");
1240  LLVM_FALLTHROUGH;
1241  case MMX:
1242  Builder.defineMacro("__MMX__");
1243  LLVM_FALLTHROUGH;
1244  case NoMMX3DNow:
1245  break;
1246  }
1247 
1248  if (CPU >= CK_i486) {
1249  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1250  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1251  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1252  }
1253  if (CPU >= CK_i586)
1254  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1255  if (HasCX16)
1256  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1257 
1258  if (HasFloat128)
1259  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1260 }
1261 
1262 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1263  return llvm::StringSwitch<bool>(Name)
1264  .Case("3dnow", true)
1265  .Case("3dnowa", true)
1266  .Case("adx", true)
1267  .Case("aes", true)
1268  .Case("avx", true)
1269  .Case("avx2", true)
1270  .Case("avx512f", true)
1271  .Case("avx512cd", true)
1272  .Case("avx512vpopcntdq", true)
1273  .Case("avx512vnni", true)
1274  .Case("avx512er", true)
1275  .Case("avx512pf", true)
1276  .Case("avx512dq", true)
1277  .Case("avx512bitalg", true)
1278  .Case("avx512bw", true)
1279  .Case("avx512vl", true)
1280  .Case("avx512vbmi", true)
1281  .Case("avx512vbmi2", true)
1282  .Case("avx512ifma", true)
1283  .Case("bmi", true)
1284  .Case("bmi2", true)
1285  .Case("cldemote", true)
1286  .Case("clflushopt", true)
1287  .Case("clwb", true)
1288  .Case("clzero", true)
1289  .Case("cx16", true)
1290  .Case("f16c", true)
1291  .Case("fma", true)
1292  .Case("fma4", true)
1293  .Case("fsgsbase", true)
1294  .Case("fxsr", true)
1295  .Case("gfni", true)
1296  .Case("lwp", true)
1297  .Case("lzcnt", true)
1298  .Case("mmx", true)
1299  .Case("movbe", true)
1300  .Case("movdiri", true)
1301  .Case("movdir64b", true)
1302  .Case("mpx", true)
1303  .Case("mwaitx", true)
1304  .Case("pclmul", true)
1305  .Case("pconfig", true)
1306  .Case("pku", true)
1307  .Case("popcnt", true)
1308  .Case("prefetchwt1", true)
1309  .Case("prfchw", true)
1310  .Case("ptwrite", true)
1311  .Case("rdpid", true)
1312  .Case("rdrnd", true)
1313  .Case("rdseed", true)
1314  .Case("rtm", true)
1315  .Case("sahf", true)
1316  .Case("sgx", true)
1317  .Case("sha", true)
1318  .Case("shstk", true)
1319  .Case("sse", true)
1320  .Case("sse2", true)
1321  .Case("sse3", true)
1322  .Case("ssse3", true)
1323  .Case("sse4", true)
1324  .Case("sse4.1", true)
1325  .Case("sse4.2", true)
1326  .Case("sse4a", true)
1327  .Case("tbm", true)
1328  .Case("vaes", true)
1329  .Case("vpclmulqdq", true)
1330  .Case("wbnoinvd", true)
1331  .Case("waitpkg", true)
1332  .Case("x87", true)
1333  .Case("xop", true)
1334  .Case("xsave", true)
1335  .Case("xsavec", true)
1336  .Case("xsaves", true)
1337  .Case("xsaveopt", true)
1338  .Default(false);
1339 }
1340 
1341 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1342  return llvm::StringSwitch<bool>(Feature)
1343  .Case("adx", HasADX)
1344  .Case("aes", HasAES)
1345  .Case("avx", SSELevel >= AVX)
1346  .Case("avx2", SSELevel >= AVX2)
1347  .Case("avx512f", SSELevel >= AVX512F)
1348  .Case("avx512cd", HasAVX512CD)
1349  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1350  .Case("avx512vnni", HasAVX512VNNI)
1351  .Case("avx512er", HasAVX512ER)
1352  .Case("avx512pf", HasAVX512PF)
1353  .Case("avx512dq", HasAVX512DQ)
1354  .Case("avx512bitalg", HasAVX512BITALG)
1355  .Case("avx512bw", HasAVX512BW)
1356  .Case("avx512vl", HasAVX512VL)
1357  .Case("avx512vbmi", HasAVX512VBMI)
1358  .Case("avx512vbmi2", HasAVX512VBMI2)
1359  .Case("avx512ifma", HasAVX512IFMA)
1360  .Case("bmi", HasBMI)
1361  .Case("bmi2", HasBMI2)
1362  .Case("cldemote", HasCLDEMOTE)
1363  .Case("clflushopt", HasCLFLUSHOPT)
1364  .Case("clwb", HasCLWB)
1365  .Case("clzero", HasCLZERO)
1366  .Case("cx16", HasCX16)
1367  .Case("f16c", HasF16C)
1368  .Case("fma", HasFMA)
1369  .Case("fma4", XOPLevel >= FMA4)
1370  .Case("fsgsbase", HasFSGSBASE)
1371  .Case("fxsr", HasFXSR)
1372  .Case("gfni", HasGFNI)
1373  .Case("lwp", HasLWP)
1374  .Case("lzcnt", HasLZCNT)
1375  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1376  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1377  .Case("mmx", MMX3DNowLevel >= MMX)
1378  .Case("movbe", HasMOVBE)
1379  .Case("movdiri", HasMOVDIRI)
1380  .Case("movdir64b", HasMOVDIR64B)
1381  .Case("mpx", HasMPX)
1382  .Case("mwaitx", HasMWAITX)
1383  .Case("pclmul", HasPCLMUL)
1384  .Case("pconfig", HasPCONFIG)
1385  .Case("pku", HasPKU)
1386  .Case("popcnt", HasPOPCNT)
1387  .Case("prefetchwt1", HasPREFETCHWT1)
1388  .Case("prfchw", HasPRFCHW)
1389  .Case("ptwrite", HasPTWRITE)
1390  .Case("rdpid", HasRDPID)
1391  .Case("rdrnd", HasRDRND)
1392  .Case("rdseed", HasRDSEED)
1393  .Case("retpoline", HasRetpoline)
1394  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1395  .Case("rtm", HasRTM)
1396  .Case("sahf", HasLAHFSAHF)
1397  .Case("sgx", HasSGX)
1398  .Case("sha", HasSHA)
1399  .Case("shstk", HasSHSTK)
1400  .Case("sse", SSELevel >= SSE1)
1401  .Case("sse2", SSELevel >= SSE2)
1402  .Case("sse3", SSELevel >= SSE3)
1403  .Case("ssse3", SSELevel >= SSSE3)
1404  .Case("sse4.1", SSELevel >= SSE41)
1405  .Case("sse4.2", SSELevel >= SSE42)
1406  .Case("sse4a", XOPLevel >= SSE4A)
1407  .Case("tbm", HasTBM)
1408  .Case("vaes", HasVAES)
1409  .Case("vpclmulqdq", HasVPCLMULQDQ)
1410  .Case("wbnoinvd", HasWBNOINVD)
1411  .Case("waitpkg", HasWAITPKG)
1412  .Case("x86", true)
1413  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1414  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1415  .Case("xop", XOPLevel >= XOP)
1416  .Case("xsave", HasXSAVE)
1417  .Case("xsavec", HasXSAVEC)
1418  .Case("xsaves", HasXSAVES)
1419  .Case("xsaveopt", HasXSAVEOPT)
1420  .Default(false);
1421 }
1422 
1423 // We can't use a generic validation scheme for the features accepted here
1424 // versus subtarget features accepted in the target attribute because the
1425 // bitfield structure that's initialized in the runtime only supports the
1426 // below currently rather than the full range of subtarget features. (See
1427 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1428 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1429  return llvm::StringSwitch<bool>(FeatureStr)
1430 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1431 #include "llvm/Support/X86TargetParser.def"
1432  .Default(false);
1433 }
1434 
1435 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1436  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1437 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1438 #include "llvm/Support/X86TargetParser.def"
1439  ;
1440  // Note, this function should only be used after ensuring the value is
1441  // correct, so it asserts if the value is out of range.
1442 }
1443 
1444 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1445  enum class FeatPriority {
1446 #define FEATURE(FEAT) FEAT,
1447 #include "clang/Basic/X86Target.def"
1448  };
1449  switch (Feat) {
1450 #define FEATURE(FEAT) \
1451  case llvm::X86::FEAT: \
1452  return static_cast<unsigned>(FeatPriority::FEAT);
1453 #include "clang/Basic/X86Target.def"
1454  default:
1455  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1456  }
1457 }
1458 
1459 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1460  // Valid CPUs have a 'key feature' that compares just better than its key
1461  // feature.
1462  CPUKind Kind = getCPUKind(Name);
1463  if (Kind != CK_Generic) {
1464  switch (Kind) {
1465  default:
1466  llvm_unreachable(
1467  "CPU Type without a key feature used in 'target' attribute");
1468 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1469  case CK_##ENUM: \
1470  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1471 #include "clang/Basic/X86Target.def"
1472  }
1473  }
1474 
1475  // Now we know we have a feature, so get its priority and shift it a few so
1476  // that we have sufficient room for the CPUs (above).
1477  return getFeaturePriority(getFeature(Name)) << 1;
1478 }
1479 
1481  switch (Kind) {
1482  case CK_Generic:
1483  return "";
1484 #define PROC(ENUM, STRING, IS64BIT) \
1485  case CK_##ENUM: \
1486  return STRING;
1487 #include "clang/Basic/X86Target.def"
1488  }
1489  llvm_unreachable("Invalid CPUKind");
1490 }
1491 
1492 // We can't use a generic validation scheme for the cpus accepted here
1493 // versus subtarget cpus accepted in the target attribute because the
1494 // variables intitialized by the runtime only support the below currently
1495 // rather than the full range of cpus.
1496 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1497  return llvm::StringSwitch<bool>(FeatureStr)
1498 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1499 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1500  .Cases(STR, ALIAS, true)
1501 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1502 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1503 #include "llvm/Support/X86TargetParser.def"
1504  .Default(false);
1505 }
1506 
1508  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1509  switch (*Name) {
1510  default:
1511  return false;
1512  // Constant constraints.
1513  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1514  // instructions.
1515  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1516  // x86_64 instructions.
1517  case 's':
1518  Info.setRequiresImmediate();
1519  return true;
1520  case 'I':
1521  Info.setRequiresImmediate(0, 31);
1522  return true;
1523  case 'J':
1524  Info.setRequiresImmediate(0, 63);
1525  return true;
1526  case 'K':
1527  Info.setRequiresImmediate(-128, 127);
1528  return true;
1529  case 'L':
1530  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1531  return true;
1532  case 'M':
1533  Info.setRequiresImmediate(0, 3);
1534  return true;
1535  case 'N':
1536  Info.setRequiresImmediate(0, 255);
1537  return true;
1538  case 'O':
1539  Info.setRequiresImmediate(0, 127);
1540  return true;
1541  // Register constraints.
1542  case 'Y': // 'Y' is the first character for several 2-character constraints.
1543  // Shift the pointer to the second character of the constraint.
1544  Name++;
1545  switch (*Name) {
1546  default:
1547  return false;
1548  case 'z':
1549  case '0': // First SSE register.
1550  case '2':
1551  case 't': // Any SSE register, when SSE2 is enabled.
1552  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1553  case 'm': // Any MMX register, when inter-unit moves enabled.
1554  case 'k': // AVX512 arch mask registers: k1-k7.
1555  Info.setAllowsRegister();
1556  return true;
1557  }
1558  case 'f': // Any x87 floating point stack register.
1559  // Constraint 'f' cannot be used for output operands.
1560  if (Info.ConstraintStr[0] == '=')
1561  return false;
1562  Info.setAllowsRegister();
1563  return true;
1564  case 'a': // eax.
1565  case 'b': // ebx.
1566  case 'c': // ecx.
1567  case 'd': // edx.
1568  case 'S': // esi.
1569  case 'D': // edi.
1570  case 'A': // edx:eax.
1571  case 't': // Top of floating point stack.
1572  case 'u': // Second from top of floating point stack.
1573  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1574  case 'y': // Any MMX register.
1575  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1576  case 'x': // Any SSE register.
1577  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1578  // for intermideate k reg operations).
1579  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1580  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1581  case 'l': // "Index" registers: any general register that can be used as an
1582  // index in a base+index memory access.
1583  Info.setAllowsRegister();
1584  return true;
1585  // Floating point constant constraints.
1586  case 'C': // SSE floating point constant.
1587  case 'G': // x87 floating point constant.
1588  return true;
1589  }
1590 }
1591 
1592 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1593  unsigned Size) const {
1594  // Strip off constraint modifiers.
1595  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1596  Constraint = Constraint.substr(1);
1597 
1598  return validateOperandSize(Constraint, Size);
1599 }
1600 
1601 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1602  unsigned Size) const {
1603  return validateOperandSize(Constraint, Size);
1604 }
1605 
1606 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1607  unsigned Size) const {
1608  switch (Constraint[0]) {
1609  default:
1610  break;
1611  case 'k':
1612  // Registers k0-k7 (AVX512) size limit is 64 bit.
1613  case 'y':
1614  return Size <= 64;
1615  case 'f':
1616  case 't':
1617  case 'u':
1618  return Size <= 128;
1619  case 'Y':
1620  // 'Y' is the first character for several 2-character constraints.
1621  switch (Constraint[1]) {
1622  default:
1623  return false;
1624  case 'm':
1625  // 'Ym' is synonymous with 'y'.
1626  case 'k':
1627  return Size <= 64;
1628  case 'z':
1629  case '0':
1630  // XMM0
1631  if (SSELevel >= SSE1)
1632  return Size <= 128U;
1633  return false;
1634  case 'i':
1635  case 't':
1636  case '2':
1637  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1638  if (SSELevel < SSE2)
1639  return false;
1640  break;
1641  }
1642  case 'v':
1643  case 'x':
1644  if (SSELevel >= AVX512F)
1645  // 512-bit zmm registers can be used if target supports AVX512F.
1646  return Size <= 512U;
1647  else if (SSELevel >= AVX)
1648  // 256-bit ymm registers can be used if target supports AVX.
1649  return Size <= 256U;
1650  return Size <= 128U;
1651 
1652  }
1653 
1654  return true;
1655 }
1656 
1657 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1658  switch (*Constraint) {
1659  case 'a':
1660  return std::string("{ax}");
1661  case 'b':
1662  return std::string("{bx}");
1663  case 'c':
1664  return std::string("{cx}");
1665  case 'd':
1666  return std::string("{dx}");
1667  case 'S':
1668  return std::string("{si}");
1669  case 'D':
1670  return std::string("{di}");
1671  case 'p': // address
1672  return std::string("im");
1673  case 't': // top of floating point stack.
1674  return std::string("{st}");
1675  case 'u': // second from top of floating point stack.
1676  return std::string("{st(1)}"); // second from top of floating point stack.
1677  case 'Y':
1678  switch (Constraint[1]) {
1679  default:
1680  // Break from inner switch and fall through (copy single char),
1681  // continue parsing after copying the current constraint into
1682  // the return string.
1683  break;
1684  case 'k':
1685  case 'm':
1686  case 'i':
1687  case 't':
1688  case 'z':
1689  case '0':
1690  case '2':
1691  // "^" hints llvm that this is a 2 letter constraint.
1692  // "Constraint++" is used to promote the string iterator
1693  // to the next constraint.
1694  return std::string("^") + std::string(Constraint++, 2);
1695  }
1696  LLVM_FALLTHROUGH;
1697  default:
1698  return std::string(1, *Constraint);
1699  }
1700 }
1701 
1703  // Perform any per-CPU checks necessary to determine if this CPU is
1704  // acceptable.
1705  switch (Kind) {
1706  case CK_Generic:
1707  // No processor selected!
1708  return false;
1709 #define PROC(ENUM, STRING, IS64BIT) \
1710  case CK_##ENUM: \
1711  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1712 #include "clang/Basic/X86Target.def"
1713  }
1714  llvm_unreachable("Unhandled CPU kind");
1715 }
1716 
1718 #define PROC(ENUM, STRING, IS64BIT) \
1719  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1720  Values.emplace_back(STRING);
1721  // Go through CPUKind checking to ensure that the alias is de-aliased and
1722  // 64 bit-ness is checked.
1723 #define PROC_ALIAS(ENUM, ALIAS) \
1724  if (checkCPUKind(getCPUKind(ALIAS))) \
1725  Values.emplace_back(ALIAS);
1726 #include "clang/Basic/X86Target.def"
1727 }
1728 
1730  return llvm::StringSwitch<CPUKind>(CPU)
1731 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1732 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1733 #include "clang/Basic/X86Target.def"
1734  .Default(CK_Generic);
1735 }
1736 
1738  return llvm::makeArrayRef(GCCRegNames);
1739 }
1740 
1742  return llvm::makeArrayRef(AddlRegNames);
1743 }
1744 
1746  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1748 }
1749 
1751  return llvm::makeArrayRef(BuiltinInfoX86,
1753 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:55
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:76
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:26
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:514
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1294
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1592
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1741
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:705
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1606
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1717
std::string getCPUKindCanonicalName(CPUKind Kind) const
Definition: X86.cpp:1480
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:547
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:50
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1428
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
Defines the Diagnostic-related interfaces.
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1435
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1507
static const char *const GCCRegNames[]
Definition: X86.cpp:44
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1262
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:361
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1729
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1341
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:435
Enumerates target-specific builtins in their own namespaces within namespace clang.
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:115
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1750
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1444
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1657
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1745
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1459
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:690
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1601
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:860
#define PROC(ENUM, STRING, IS64BIT)
__DEVICE__ int max(int __a, int __b)
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1702
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:71
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:582
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1496
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1737
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105