clang  11.0.0git
X86.cpp
Go to the documentation of this file.
1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/X86TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65  "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabled(Features, "sse2", true);
112 
113  using namespace llvm::X86;
114 
115  SmallVector<StringRef, 16> CPUFeatures;
116  getFeaturesForCPU(CPU, CPUFeatures);
117  for (auto &F : CPUFeatures)
118  setFeatureEnabled(Features, F, true);
119 
120  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
121  return false;
122 
123  // Can't do this earlier because we need to be able to explicitly enable
124  // or disable these features and the things that they depend upon.
125 
126  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
127  auto I = Features.find("sse4.2");
128  if (I != Features.end() && I->getValue() &&
129  llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
130  Features["popcnt"] = true;
131 
132  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
133  // then enable MMX.
134  I = Features.find("sse");
135  if (I != Features.end() && I->getValue() &&
136  llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
137  Features["mmx"] = true;
138 
139  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
140  I = Features.find("avx");
141  if (I != Features.end() && I->getValue() &&
142  llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end())
143  Features["xsave"] = true;
144 
145  return true;
146 }
147 
148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
149  StringRef Name, bool Enabled) const {
150  if (Name == "sse4") {
151  // We can get here via the __target__ attribute since that's not controlled
152  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
153  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
154  // disabled.
155  if (Enabled)
156  Name = "sse4.2";
157  else
158  Name = "sse4.1";
159  }
160 
161  Features[Name] = Enabled;
162 
163  SmallVector<StringRef, 8> ImpliedFeatures;
164  llvm::X86::getImpliedFeatures(Name, Enabled, ImpliedFeatures);
165  for (const auto &F : ImpliedFeatures)
166  Features[F] = Enabled;
167 }
168 
169 /// handleTargetFeatures - Perform initialization based on the user
170 /// configured set of features.
171 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
172  DiagnosticsEngine &Diags) {
173  for (const auto &Feature : Features) {
174  if (Feature[0] != '+')
175  continue;
176 
177  if (Feature == "+aes") {
178  HasAES = true;
179  } else if (Feature == "+vaes") {
180  HasVAES = true;
181  } else if (Feature == "+pclmul") {
182  HasPCLMUL = true;
183  } else if (Feature == "+vpclmulqdq") {
184  HasVPCLMULQDQ = true;
185  } else if (Feature == "+lzcnt") {
186  HasLZCNT = true;
187  } else if (Feature == "+rdrnd") {
188  HasRDRND = true;
189  } else if (Feature == "+fsgsbase") {
190  HasFSGSBASE = true;
191  } else if (Feature == "+bmi") {
192  HasBMI = true;
193  } else if (Feature == "+bmi2") {
194  HasBMI2 = true;
195  } else if (Feature == "+popcnt") {
196  HasPOPCNT = true;
197  } else if (Feature == "+rtm") {
198  HasRTM = true;
199  } else if (Feature == "+prfchw") {
200  HasPRFCHW = true;
201  } else if (Feature == "+rdseed") {
202  HasRDSEED = true;
203  } else if (Feature == "+adx") {
204  HasADX = true;
205  } else if (Feature == "+tbm") {
206  HasTBM = true;
207  } else if (Feature == "+lwp") {
208  HasLWP = true;
209  } else if (Feature == "+fma") {
210  HasFMA = true;
211  } else if (Feature == "+f16c") {
212  HasF16C = true;
213  } else if (Feature == "+gfni") {
214  HasGFNI = true;
215  } else if (Feature == "+avx512cd") {
216  HasAVX512CD = true;
217  } else if (Feature == "+avx512vpopcntdq") {
218  HasAVX512VPOPCNTDQ = true;
219  } else if (Feature == "+avx512vnni") {
220  HasAVX512VNNI = true;
221  } else if (Feature == "+avx512bf16") {
222  HasAVX512BF16 = true;
223  } else if (Feature == "+avx512er") {
224  HasAVX512ER = true;
225  } else if (Feature == "+avx512pf") {
226  HasAVX512PF = true;
227  } else if (Feature == "+avx512dq") {
228  HasAVX512DQ = true;
229  } else if (Feature == "+avx512bitalg") {
230  HasAVX512BITALG = true;
231  } else if (Feature == "+avx512bw") {
232  HasAVX512BW = true;
233  } else if (Feature == "+avx512vl") {
234  HasAVX512VL = true;
235  } else if (Feature == "+avx512vbmi") {
236  HasAVX512VBMI = true;
237  } else if (Feature == "+avx512vbmi2") {
238  HasAVX512VBMI2 = true;
239  } else if (Feature == "+avx512ifma") {
240  HasAVX512IFMA = true;
241  } else if (Feature == "+avx512vp2intersect") {
242  HasAVX512VP2INTERSECT = true;
243  } else if (Feature == "+sha") {
244  HasSHA = true;
245  } else if (Feature == "+shstk") {
246  HasSHSTK = true;
247  } else if (Feature == "+movbe") {
248  HasMOVBE = true;
249  } else if (Feature == "+sgx") {
250  HasSGX = true;
251  } else if (Feature == "+cx8") {
252  HasCX8 = true;
253  } else if (Feature == "+cx16") {
254  HasCX16 = true;
255  } else if (Feature == "+fxsr") {
256  HasFXSR = true;
257  } else if (Feature == "+xsave") {
258  HasXSAVE = true;
259  } else if (Feature == "+xsaveopt") {
260  HasXSAVEOPT = true;
261  } else if (Feature == "+xsavec") {
262  HasXSAVEC = true;
263  } else if (Feature == "+xsaves") {
264  HasXSAVES = true;
265  } else if (Feature == "+mwaitx") {
266  HasMWAITX = true;
267  } else if (Feature == "+pku") {
268  HasPKU = true;
269  } else if (Feature == "+clflushopt") {
270  HasCLFLUSHOPT = true;
271  } else if (Feature == "+clwb") {
272  HasCLWB = true;
273  } else if (Feature == "+wbnoinvd") {
274  HasWBNOINVD = true;
275  } else if (Feature == "+prefetchwt1") {
276  HasPREFETCHWT1 = true;
277  } else if (Feature == "+clzero") {
278  HasCLZERO = true;
279  } else if (Feature == "+cldemote") {
280  HasCLDEMOTE = true;
281  } else if (Feature == "+rdpid") {
282  HasRDPID = true;
283  } else if (Feature == "+retpoline-external-thunk") {
284  HasRetpolineExternalThunk = true;
285  } else if (Feature == "+sahf") {
286  HasLAHFSAHF = true;
287  } else if (Feature == "+waitpkg") {
288  HasWAITPKG = true;
289  } else if (Feature == "+movdiri") {
290  HasMOVDIRI = true;
291  } else if (Feature == "+movdir64b") {
292  HasMOVDIR64B = true;
293  } else if (Feature == "+pconfig") {
294  HasPCONFIG = true;
295  } else if (Feature == "+ptwrite") {
296  HasPTWRITE = true;
297  } else if (Feature == "+invpcid") {
298  HasINVPCID = true;
299  } else if (Feature == "+enqcmd") {
300  HasENQCMD = true;
301  } else if (Feature == "+amx-bf16") {
302  HasAMXBF16 = true;
303  } else if (Feature == "+amx-int8") {
304  HasAMXINT8 = true;
305  } else if (Feature == "+amx-tile") {
306  HasAMXTILE = true;
307  } else if (Feature == "+serialize") {
308  HasSERIALIZE = true;
309  } else if (Feature == "+tsxldtrk") {
310  HasTSXLDTRK = true;
311  }
312 
313  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
314  .Case("+avx512f", AVX512F)
315  .Case("+avx2", AVX2)
316  .Case("+avx", AVX)
317  .Case("+sse4.2", SSE42)
318  .Case("+sse4.1", SSE41)
319  .Case("+ssse3", SSSE3)
320  .Case("+sse3", SSE3)
321  .Case("+sse2", SSE2)
322  .Case("+sse", SSE1)
323  .Default(NoSSE);
324  SSELevel = std::max(SSELevel, Level);
325 
326  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
327  .Case("+3dnowa", AMD3DNowAthlon)
328  .Case("+3dnow", AMD3DNow)
329  .Case("+mmx", MMX)
330  .Default(NoMMX3DNow);
331  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
332 
333  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
334  .Case("+xop", XOP)
335  .Case("+fma4", FMA4)
336  .Case("+sse4a", SSE4A)
337  .Default(NoXOP);
338  XOPLevel = std::max(XOPLevel, XLevel);
339  }
340 
341  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
342  // matches the selected sse level.
343  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
344  (FPMath == FP_387 && SSELevel >= SSE1)) {
345  Diags.Report(diag::err_target_unsupported_fpmath)
346  << (FPMath == FP_SSE ? "sse" : "387");
347  return false;
348  }
349 
350  SimdDefaultAlign =
351  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
352  return true;
353 }
354 
355 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
356 /// definitions for this particular subtarget.
358  MacroBuilder &Builder) const {
359  // Inline assembly supports X86 flag outputs.
360  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
361 
362  std::string CodeModel = getTargetOpts().CodeModel;
363  if (CodeModel == "default")
364  CodeModel = "small";
365  Builder.defineMacro("__code_model_" + CodeModel + "__");
366 
367  // Target identification.
368  if (getTriple().getArch() == llvm::Triple::x86_64) {
369  Builder.defineMacro("__amd64__");
370  Builder.defineMacro("__amd64");
371  Builder.defineMacro("__x86_64");
372  Builder.defineMacro("__x86_64__");
373  if (getTriple().getArchName() == "x86_64h") {
374  Builder.defineMacro("__x86_64h");
375  Builder.defineMacro("__x86_64h__");
376  }
377  } else {
378  DefineStd(Builder, "i386", Opts);
379  }
380 
381  Builder.defineMacro("__SEG_GS");
382  Builder.defineMacro("__SEG_FS");
383  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
384  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
385 
386  // Subtarget options.
387  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
388  // truly should be based on -mtune options.
389  using namespace llvm::X86;
390  switch (CPU) {
391  case CK_None:
392  break;
393  case CK_i386:
394  // The rest are coming from the i386 define above.
395  Builder.defineMacro("__tune_i386__");
396  break;
397  case CK_i486:
398  case CK_WinChipC6:
399  case CK_WinChip2:
400  case CK_C3:
401  defineCPUMacros(Builder, "i486");
402  break;
403  case CK_PentiumMMX:
404  Builder.defineMacro("__pentium_mmx__");
405  Builder.defineMacro("__tune_pentium_mmx__");
406  LLVM_FALLTHROUGH;
407  case CK_i586:
408  case CK_Pentium:
409  defineCPUMacros(Builder, "i586");
410  defineCPUMacros(Builder, "pentium");
411  break;
412  case CK_Pentium3:
413  case CK_PentiumM:
414  Builder.defineMacro("__tune_pentium3__");
415  LLVM_FALLTHROUGH;
416  case CK_Pentium2:
417  case CK_C3_2:
418  Builder.defineMacro("__tune_pentium2__");
419  LLVM_FALLTHROUGH;
420  case CK_PentiumPro:
421  case CK_i686:
422  defineCPUMacros(Builder, "i686");
423  defineCPUMacros(Builder, "pentiumpro");
424  break;
425  case CK_Pentium4:
426  defineCPUMacros(Builder, "pentium4");
427  break;
428  case CK_Yonah:
429  case CK_Prescott:
430  case CK_Nocona:
431  defineCPUMacros(Builder, "nocona");
432  break;
433  case CK_Core2:
434  case CK_Penryn:
435  defineCPUMacros(Builder, "core2");
436  break;
437  case CK_Bonnell:
438  defineCPUMacros(Builder, "atom");
439  break;
440  case CK_Silvermont:
441  defineCPUMacros(Builder, "slm");
442  break;
443  case CK_Goldmont:
444  defineCPUMacros(Builder, "goldmont");
445  break;
446  case CK_GoldmontPlus:
447  defineCPUMacros(Builder, "goldmont_plus");
448  break;
449  case CK_Tremont:
450  defineCPUMacros(Builder, "tremont");
451  break;
452  case CK_Nehalem:
453  case CK_Westmere:
454  case CK_SandyBridge:
455  case CK_IvyBridge:
456  case CK_Haswell:
457  case CK_Broadwell:
458  case CK_SkylakeClient:
459  case CK_SkylakeServer:
460  case CK_Cascadelake:
461  case CK_Cooperlake:
462  case CK_Cannonlake:
463  case CK_IcelakeClient:
464  case CK_IcelakeServer:
465  case CK_Tigerlake:
466  // FIXME: Historically, we defined this legacy name, it would be nice to
467  // remove it at some point. We've never exposed fine-grained names for
468  // recent primary x86 CPUs, and we should keep it that way.
469  defineCPUMacros(Builder, "corei7");
470  break;
471  case CK_KNL:
472  defineCPUMacros(Builder, "knl");
473  break;
474  case CK_KNM:
475  break;
476  case CK_Lakemont:
477  defineCPUMacros(Builder, "i586", /*Tuning*/false);
478  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
479  Builder.defineMacro("__tune_lakemont__");
480  break;
481  case CK_K6_2:
482  Builder.defineMacro("__k6_2__");
483  Builder.defineMacro("__tune_k6_2__");
484  LLVM_FALLTHROUGH;
485  case CK_K6_3:
486  if (CPU != CK_K6_2) { // In case of fallthrough
487  // FIXME: GCC may be enabling these in cases where some other k6
488  // architecture is specified but -m3dnow is explicitly provided. The
489  // exact semantics need to be determined and emulated here.
490  Builder.defineMacro("__k6_3__");
491  Builder.defineMacro("__tune_k6_3__");
492  }
493  LLVM_FALLTHROUGH;
494  case CK_K6:
495  defineCPUMacros(Builder, "k6");
496  break;
497  case CK_Athlon:
498  case CK_AthlonXP:
499  defineCPUMacros(Builder, "athlon");
500  if (SSELevel != NoSSE) {
501  Builder.defineMacro("__athlon_sse__");
502  Builder.defineMacro("__tune_athlon_sse__");
503  }
504  break;
505  case CK_K8:
506  case CK_K8SSE3:
507  case CK_x86_64:
508  defineCPUMacros(Builder, "k8");
509  break;
510  case CK_AMDFAM10:
511  defineCPUMacros(Builder, "amdfam10");
512  break;
513  case CK_BTVER1:
514  defineCPUMacros(Builder, "btver1");
515  break;
516  case CK_BTVER2:
517  defineCPUMacros(Builder, "btver2");
518  break;
519  case CK_BDVER1:
520  defineCPUMacros(Builder, "bdver1");
521  break;
522  case CK_BDVER2:
523  defineCPUMacros(Builder, "bdver2");
524  break;
525  case CK_BDVER3:
526  defineCPUMacros(Builder, "bdver3");
527  break;
528  case CK_BDVER4:
529  defineCPUMacros(Builder, "bdver4");
530  break;
531  case CK_ZNVER1:
532  defineCPUMacros(Builder, "znver1");
533  break;
534  case CK_ZNVER2:
535  defineCPUMacros(Builder, "znver2");
536  break;
537  case CK_Geode:
538  defineCPUMacros(Builder, "geode");
539  break;
540  }
541 
542  // Target properties.
543  Builder.defineMacro("__REGISTER_PREFIX__", "");
544 
545  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
546  // functions in glibc header files that use FP Stack inline asm which the
547  // backend can't deal with (PR879).
548  Builder.defineMacro("__NO_MATH_INLINES");
549 
550  if (HasAES)
551  Builder.defineMacro("__AES__");
552 
553  if (HasVAES)
554  Builder.defineMacro("__VAES__");
555 
556  if (HasPCLMUL)
557  Builder.defineMacro("__PCLMUL__");
558 
559  if (HasVPCLMULQDQ)
560  Builder.defineMacro("__VPCLMULQDQ__");
561 
562  if (HasLZCNT)
563  Builder.defineMacro("__LZCNT__");
564 
565  if (HasRDRND)
566  Builder.defineMacro("__RDRND__");
567 
568  if (HasFSGSBASE)
569  Builder.defineMacro("__FSGSBASE__");
570 
571  if (HasBMI)
572  Builder.defineMacro("__BMI__");
573 
574  if (HasBMI2)
575  Builder.defineMacro("__BMI2__");
576 
577  if (HasPOPCNT)
578  Builder.defineMacro("__POPCNT__");
579 
580  if (HasRTM)
581  Builder.defineMacro("__RTM__");
582 
583  if (HasPRFCHW)
584  Builder.defineMacro("__PRFCHW__");
585 
586  if (HasRDSEED)
587  Builder.defineMacro("__RDSEED__");
588 
589  if (HasADX)
590  Builder.defineMacro("__ADX__");
591 
592  if (HasTBM)
593  Builder.defineMacro("__TBM__");
594 
595  if (HasLWP)
596  Builder.defineMacro("__LWP__");
597 
598  if (HasMWAITX)
599  Builder.defineMacro("__MWAITX__");
600 
601  if (HasMOVBE)
602  Builder.defineMacro("__MOVBE__");
603 
604  switch (XOPLevel) {
605  case XOP:
606  Builder.defineMacro("__XOP__");
607  LLVM_FALLTHROUGH;
608  case FMA4:
609  Builder.defineMacro("__FMA4__");
610  LLVM_FALLTHROUGH;
611  case SSE4A:
612  Builder.defineMacro("__SSE4A__");
613  LLVM_FALLTHROUGH;
614  case NoXOP:
615  break;
616  }
617 
618  if (HasFMA)
619  Builder.defineMacro("__FMA__");
620 
621  if (HasF16C)
622  Builder.defineMacro("__F16C__");
623 
624  if (HasGFNI)
625  Builder.defineMacro("__GFNI__");
626 
627  if (HasAVX512CD)
628  Builder.defineMacro("__AVX512CD__");
629  if (HasAVX512VPOPCNTDQ)
630  Builder.defineMacro("__AVX512VPOPCNTDQ__");
631  if (HasAVX512VNNI)
632  Builder.defineMacro("__AVX512VNNI__");
633  if (HasAVX512BF16)
634  Builder.defineMacro("__AVX512BF16__");
635  if (HasAVX512ER)
636  Builder.defineMacro("__AVX512ER__");
637  if (HasAVX512PF)
638  Builder.defineMacro("__AVX512PF__");
639  if (HasAVX512DQ)
640  Builder.defineMacro("__AVX512DQ__");
641  if (HasAVX512BITALG)
642  Builder.defineMacro("__AVX512BITALG__");
643  if (HasAVX512BW)
644  Builder.defineMacro("__AVX512BW__");
645  if (HasAVX512VL)
646  Builder.defineMacro("__AVX512VL__");
647  if (HasAVX512VBMI)
648  Builder.defineMacro("__AVX512VBMI__");
649  if (HasAVX512VBMI2)
650  Builder.defineMacro("__AVX512VBMI2__");
651  if (HasAVX512IFMA)
652  Builder.defineMacro("__AVX512IFMA__");
653  if (HasAVX512VP2INTERSECT)
654  Builder.defineMacro("__AVX512VP2INTERSECT__");
655  if (HasSHA)
656  Builder.defineMacro("__SHA__");
657 
658  if (HasFXSR)
659  Builder.defineMacro("__FXSR__");
660  if (HasXSAVE)
661  Builder.defineMacro("__XSAVE__");
662  if (HasXSAVEOPT)
663  Builder.defineMacro("__XSAVEOPT__");
664  if (HasXSAVEC)
665  Builder.defineMacro("__XSAVEC__");
666  if (HasXSAVES)
667  Builder.defineMacro("__XSAVES__");
668  if (HasPKU)
669  Builder.defineMacro("__PKU__");
670  if (HasCLFLUSHOPT)
671  Builder.defineMacro("__CLFLUSHOPT__");
672  if (HasCLWB)
673  Builder.defineMacro("__CLWB__");
674  if (HasWBNOINVD)
675  Builder.defineMacro("__WBNOINVD__");
676  if (HasSHSTK)
677  Builder.defineMacro("__SHSTK__");
678  if (HasSGX)
679  Builder.defineMacro("__SGX__");
680  if (HasPREFETCHWT1)
681  Builder.defineMacro("__PREFETCHWT1__");
682  if (HasCLZERO)
683  Builder.defineMacro("__CLZERO__");
684  if (HasRDPID)
685  Builder.defineMacro("__RDPID__");
686  if (HasCLDEMOTE)
687  Builder.defineMacro("__CLDEMOTE__");
688  if (HasWAITPKG)
689  Builder.defineMacro("__WAITPKG__");
690  if (HasMOVDIRI)
691  Builder.defineMacro("__MOVDIRI__");
692  if (HasMOVDIR64B)
693  Builder.defineMacro("__MOVDIR64B__");
694  if (HasPCONFIG)
695  Builder.defineMacro("__PCONFIG__");
696  if (HasPTWRITE)
697  Builder.defineMacro("__PTWRITE__");
698  if (HasINVPCID)
699  Builder.defineMacro("__INVPCID__");
700  if (HasENQCMD)
701  Builder.defineMacro("__ENQCMD__");
702  if (HasAMXTILE)
703  Builder.defineMacro("__AMXTILE__");
704  if (HasAMXINT8)
705  Builder.defineMacro("__AMXINT8__");
706  if (HasAMXBF16)
707  Builder.defineMacro("__AMXBF16__");
708  if (HasSERIALIZE)
709  Builder.defineMacro("__SERIALIZE__");
710  if (HasTSXLDTRK)
711  Builder.defineMacro("__TSXLDTRK__");
712 
713  // Each case falls through to the previous one here.
714  switch (SSELevel) {
715  case AVX512F:
716  Builder.defineMacro("__AVX512F__");
717  LLVM_FALLTHROUGH;
718  case AVX2:
719  Builder.defineMacro("__AVX2__");
720  LLVM_FALLTHROUGH;
721  case AVX:
722  Builder.defineMacro("__AVX__");
723  LLVM_FALLTHROUGH;
724  case SSE42:
725  Builder.defineMacro("__SSE4_2__");
726  LLVM_FALLTHROUGH;
727  case SSE41:
728  Builder.defineMacro("__SSE4_1__");
729  LLVM_FALLTHROUGH;
730  case SSSE3:
731  Builder.defineMacro("__SSSE3__");
732  LLVM_FALLTHROUGH;
733  case SSE3:
734  Builder.defineMacro("__SSE3__");
735  LLVM_FALLTHROUGH;
736  case SSE2:
737  Builder.defineMacro("__SSE2__");
738  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
739  LLVM_FALLTHROUGH;
740  case SSE1:
741  Builder.defineMacro("__SSE__");
742  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
743  LLVM_FALLTHROUGH;
744  case NoSSE:
745  break;
746  }
747 
748  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
749  switch (SSELevel) {
750  case AVX512F:
751  case AVX2:
752  case AVX:
753  case SSE42:
754  case SSE41:
755  case SSSE3:
756  case SSE3:
757  case SSE2:
758  Builder.defineMacro("_M_IX86_FP", Twine(2));
759  break;
760  case SSE1:
761  Builder.defineMacro("_M_IX86_FP", Twine(1));
762  break;
763  default:
764  Builder.defineMacro("_M_IX86_FP", Twine(0));
765  break;
766  }
767  }
768 
769  // Each case falls through to the previous one here.
770  switch (MMX3DNowLevel) {
771  case AMD3DNowAthlon:
772  Builder.defineMacro("__3dNOW_A__");
773  LLVM_FALLTHROUGH;
774  case AMD3DNow:
775  Builder.defineMacro("__3dNOW__");
776  LLVM_FALLTHROUGH;
777  case MMX:
778  Builder.defineMacro("__MMX__");
779  LLVM_FALLTHROUGH;
780  case NoMMX3DNow:
781  break;
782  }
783 
784  if (CPU >= CK_i486 || CPU == CK_None) {
785  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
786  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
787  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
788  }
789  if (HasCX8)
790  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
791  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
792  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
793 
794  if (HasFloat128)
795  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
796 }
797 
798 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
799  return llvm::StringSwitch<bool>(Name)
800  .Case("3dnow", true)
801  .Case("3dnowa", true)
802  .Case("adx", true)
803  .Case("aes", true)
804  .Case("amx-bf16", true)
805  .Case("amx-int8", true)
806  .Case("amx-tile", true)
807  .Case("avx", true)
808  .Case("avx2", true)
809  .Case("avx512f", true)
810  .Case("avx512cd", true)
811  .Case("avx512vpopcntdq", true)
812  .Case("avx512vnni", true)
813  .Case("avx512bf16", true)
814  .Case("avx512er", true)
815  .Case("avx512pf", true)
816  .Case("avx512dq", true)
817  .Case("avx512bitalg", true)
818  .Case("avx512bw", true)
819  .Case("avx512vl", true)
820  .Case("avx512vbmi", true)
821  .Case("avx512vbmi2", true)
822  .Case("avx512ifma", true)
823  .Case("avx512vp2intersect", true)
824  .Case("bmi", true)
825  .Case("bmi2", true)
826  .Case("cldemote", true)
827  .Case("clflushopt", true)
828  .Case("clwb", true)
829  .Case("clzero", true)
830  .Case("cx16", true)
831  .Case("enqcmd", true)
832  .Case("f16c", true)
833  .Case("fma", true)
834  .Case("fma4", true)
835  .Case("fsgsbase", true)
836  .Case("fxsr", true)
837  .Case("gfni", true)
838  .Case("invpcid", true)
839  .Case("lwp", true)
840  .Case("lzcnt", true)
841  .Case("mmx", true)
842  .Case("movbe", true)
843  .Case("movdiri", true)
844  .Case("movdir64b", true)
845  .Case("mwaitx", true)
846  .Case("pclmul", true)
847  .Case("pconfig", true)
848  .Case("pku", true)
849  .Case("popcnt", true)
850  .Case("prefetchwt1", true)
851  .Case("prfchw", true)
852  .Case("ptwrite", true)
853  .Case("rdpid", true)
854  .Case("rdrnd", true)
855  .Case("rdseed", true)
856  .Case("rtm", true)
857  .Case("sahf", true)
858  .Case("serialize", true)
859  .Case("sgx", true)
860  .Case("sha", true)
861  .Case("shstk", true)
862  .Case("sse", true)
863  .Case("sse2", true)
864  .Case("sse3", true)
865  .Case("ssse3", true)
866  .Case("sse4", true)
867  .Case("sse4.1", true)
868  .Case("sse4.2", true)
869  .Case("sse4a", true)
870  .Case("tbm", true)
871  .Case("tsxldtrk", true)
872  .Case("vaes", true)
873  .Case("vpclmulqdq", true)
874  .Case("wbnoinvd", true)
875  .Case("waitpkg", true)
876  .Case("x87", true)
877  .Case("xop", true)
878  .Case("xsave", true)
879  .Case("xsavec", true)
880  .Case("xsaves", true)
881  .Case("xsaveopt", true)
882  .Default(false);
883 }
884 
885 bool X86TargetInfo::hasFeature(StringRef Feature) const {
886  return llvm::StringSwitch<bool>(Feature)
887  .Case("adx", HasADX)
888  .Case("aes", HasAES)
889  .Case("amx-bf16", HasAMXBF16)
890  .Case("amx-int8", HasAMXINT8)
891  .Case("amx-tile", HasAMXTILE)
892  .Case("avx", SSELevel >= AVX)
893  .Case("avx2", SSELevel >= AVX2)
894  .Case("avx512f", SSELevel >= AVX512F)
895  .Case("avx512cd", HasAVX512CD)
896  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
897  .Case("avx512vnni", HasAVX512VNNI)
898  .Case("avx512bf16", HasAVX512BF16)
899  .Case("avx512er", HasAVX512ER)
900  .Case("avx512pf", HasAVX512PF)
901  .Case("avx512dq", HasAVX512DQ)
902  .Case("avx512bitalg", HasAVX512BITALG)
903  .Case("avx512bw", HasAVX512BW)
904  .Case("avx512vl", HasAVX512VL)
905  .Case("avx512vbmi", HasAVX512VBMI)
906  .Case("avx512vbmi2", HasAVX512VBMI2)
907  .Case("avx512ifma", HasAVX512IFMA)
908  .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
909  .Case("bmi", HasBMI)
910  .Case("bmi2", HasBMI2)
911  .Case("cldemote", HasCLDEMOTE)
912  .Case("clflushopt", HasCLFLUSHOPT)
913  .Case("clwb", HasCLWB)
914  .Case("clzero", HasCLZERO)
915  .Case("cx8", HasCX8)
916  .Case("cx16", HasCX16)
917  .Case("enqcmd", HasENQCMD)
918  .Case("f16c", HasF16C)
919  .Case("fma", HasFMA)
920  .Case("fma4", XOPLevel >= FMA4)
921  .Case("fsgsbase", HasFSGSBASE)
922  .Case("fxsr", HasFXSR)
923  .Case("gfni", HasGFNI)
924  .Case("invpcid", HasINVPCID)
925  .Case("lwp", HasLWP)
926  .Case("lzcnt", HasLZCNT)
927  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
928  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
929  .Case("mmx", MMX3DNowLevel >= MMX)
930  .Case("movbe", HasMOVBE)
931  .Case("movdiri", HasMOVDIRI)
932  .Case("movdir64b", HasMOVDIR64B)
933  .Case("mwaitx", HasMWAITX)
934  .Case("pclmul", HasPCLMUL)
935  .Case("pconfig", HasPCONFIG)
936  .Case("pku", HasPKU)
937  .Case("popcnt", HasPOPCNT)
938  .Case("prefetchwt1", HasPREFETCHWT1)
939  .Case("prfchw", HasPRFCHW)
940  .Case("ptwrite", HasPTWRITE)
941  .Case("rdpid", HasRDPID)
942  .Case("rdrnd", HasRDRND)
943  .Case("rdseed", HasRDSEED)
944  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
945  .Case("rtm", HasRTM)
946  .Case("sahf", HasLAHFSAHF)
947  .Case("serialize", HasSERIALIZE)
948  .Case("sgx", HasSGX)
949  .Case("sha", HasSHA)
950  .Case("shstk", HasSHSTK)
951  .Case("sse", SSELevel >= SSE1)
952  .Case("sse2", SSELevel >= SSE2)
953  .Case("sse3", SSELevel >= SSE3)
954  .Case("ssse3", SSELevel >= SSSE3)
955  .Case("sse4.1", SSELevel >= SSE41)
956  .Case("sse4.2", SSELevel >= SSE42)
957  .Case("sse4a", XOPLevel >= SSE4A)
958  .Case("tbm", HasTBM)
959  .Case("tsxldtrk", HasTSXLDTRK)
960  .Case("vaes", HasVAES)
961  .Case("vpclmulqdq", HasVPCLMULQDQ)
962  .Case("wbnoinvd", HasWBNOINVD)
963  .Case("waitpkg", HasWAITPKG)
964  .Case("x86", true)
965  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
966  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
967  .Case("xop", XOPLevel >= XOP)
968  .Case("xsave", HasXSAVE)
969  .Case("xsavec", HasXSAVEC)
970  .Case("xsaves", HasXSAVES)
971  .Case("xsaveopt", HasXSAVEOPT)
972  .Default(false);
973 }
974 
975 // We can't use a generic validation scheme for the features accepted here
976 // versus subtarget features accepted in the target attribute because the
977 // bitfield structure that's initialized in the runtime only supports the
978 // below currently rather than the full range of subtarget features. (See
979 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
980 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
981  return llvm::StringSwitch<bool>(FeatureStr)
982 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true)
983 #include "llvm/Support/X86TargetParser.def"
984  .Default(false);
985 }
986 
987 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
988  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
989 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM)
990 #include "llvm/Support/X86TargetParser.def"
991  ;
992  // Note, this function should only be used after ensuring the value is
993  // correct, so it asserts if the value is out of range.
994 }
995 
996 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
997  enum class FeatPriority {
998 #define FEATURE(FEAT) FEAT,
999 #include "clang/Basic/X86Target.def"
1000  };
1001  switch (Feat) {
1002 #define FEATURE(FEAT) \
1003  case llvm::X86::FEAT: \
1004  return static_cast<unsigned>(FeatPriority::FEAT);
1005 #include "clang/Basic/X86Target.def"
1006  default:
1007  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1008  }
1009 }
1010 
1011 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1012  // Valid CPUs have a 'key feature' that compares just better than its key
1013  // feature.
1014  using namespace llvm::X86;
1015  CPUKind Kind = parseArchX86(Name);
1016  if (Kind != CK_None) {
1017  ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1018  return (getFeaturePriority(KeyFeature) << 1) + 1;
1019  }
1020 
1021  // Now we know we have a feature, so get its priority and shift it a few so
1022  // that we have sufficient room for the CPUs (above).
1023  return getFeaturePriority(getFeature(Name)) << 1;
1024 }
1025 
1027  return llvm::StringSwitch<bool>(Name)
1028 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1029 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1030 #include "clang/Basic/X86Target.def"
1031  .Default(false);
1032 }
1033 
1034 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1035  return llvm::StringSwitch<StringRef>(Name)
1036 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1037 #include "clang/Basic/X86Target.def"
1038  .Default(Name);
1039 }
1040 
1042  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1043 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1044 #include "clang/Basic/X86Target.def"
1045  .Default(0);
1046 }
1047 
1049  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1050  StringRef WholeList =
1051  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1052 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1053 #include "clang/Basic/X86Target.def"
1054  .Default("");
1055  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1056 }
1057 
1058 // We can't use a generic validation scheme for the cpus accepted here
1059 // versus subtarget cpus accepted in the target attribute because the
1060 // variables intitialized by the runtime only support the below currently
1061 // rather than the full range of cpus.
1062 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1063  return llvm::StringSwitch<bool>(FeatureStr)
1064 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1065 #define X86_CPU_TYPE_COMPAT_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1066 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1067 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1068 #include "llvm/Support/X86TargetParser.def"
1069  .Default(false);
1070 }
1071 
1072 static unsigned matchAsmCCConstraint(const char *&Name) {
1073  auto RV = llvm::StringSwitch<unsigned>(Name)
1074  .Case("@cca", 4)
1075  .Case("@ccae", 5)
1076  .Case("@ccb", 4)
1077  .Case("@ccbe", 5)
1078  .Case("@ccc", 4)
1079  .Case("@cce", 4)
1080  .Case("@ccz", 4)
1081  .Case("@ccg", 4)
1082  .Case("@ccge", 5)
1083  .Case("@ccl", 4)
1084  .Case("@ccle", 5)
1085  .Case("@ccna", 5)
1086  .Case("@ccnae", 6)
1087  .Case("@ccnb", 5)
1088  .Case("@ccnbe", 6)
1089  .Case("@ccnc", 5)
1090  .Case("@ccne", 5)
1091  .Case("@ccnz", 5)
1092  .Case("@ccng", 5)
1093  .Case("@ccnge", 6)
1094  .Case("@ccnl", 5)
1095  .Case("@ccnle", 6)
1096  .Case("@ccno", 5)
1097  .Case("@ccnp", 5)
1098  .Case("@ccns", 5)
1099  .Case("@cco", 4)
1100  .Case("@ccp", 4)
1101  .Case("@ccs", 4)
1102  .Default(0);
1103  return RV;
1104 }
1105 
1107  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1108  switch (*Name) {
1109  default:
1110  return false;
1111  // Constant constraints.
1112  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1113  // instructions.
1114  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1115  // x86_64 instructions.
1116  case 's':
1117  Info.setRequiresImmediate();
1118  return true;
1119  case 'I':
1120  Info.setRequiresImmediate(0, 31);
1121  return true;
1122  case 'J':
1123  Info.setRequiresImmediate(0, 63);
1124  return true;
1125  case 'K':
1126  Info.setRequiresImmediate(-128, 127);
1127  return true;
1128  case 'L':
1129  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1130  return true;
1131  case 'M':
1132  Info.setRequiresImmediate(0, 3);
1133  return true;
1134  case 'N':
1135  Info.setRequiresImmediate(0, 255);
1136  return true;
1137  case 'O':
1138  Info.setRequiresImmediate(0, 127);
1139  return true;
1140  // Register constraints.
1141  case 'Y': // 'Y' is the first character for several 2-character constraints.
1142  // Shift the pointer to the second character of the constraint.
1143  Name++;
1144  switch (*Name) {
1145  default:
1146  return false;
1147  case 'z': // First SSE register.
1148  case '2':
1149  case 't': // Any SSE register, when SSE2 is enabled.
1150  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1151  case 'm': // Any MMX register, when inter-unit moves enabled.
1152  case 'k': // AVX512 arch mask registers: k1-k7.
1153  Info.setAllowsRegister();
1154  return true;
1155  }
1156  case 'f': // Any x87 floating point stack register.
1157  // Constraint 'f' cannot be used for output operands.
1158  if (Info.ConstraintStr[0] == '=')
1159  return false;
1160  Info.setAllowsRegister();
1161  return true;
1162  case 'a': // eax.
1163  case 'b': // ebx.
1164  case 'c': // ecx.
1165  case 'd': // edx.
1166  case 'S': // esi.
1167  case 'D': // edi.
1168  case 'A': // edx:eax.
1169  case 't': // Top of floating point stack.
1170  case 'u': // Second from top of floating point stack.
1171  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1172  case 'y': // Any MMX register.
1173  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1174  case 'x': // Any SSE register.
1175  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1176  // for intermideate k reg operations).
1177  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1178  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1179  case 'l': // "Index" registers: any general register that can be used as an
1180  // index in a base+index memory access.
1181  Info.setAllowsRegister();
1182  return true;
1183  // Floating point constant constraints.
1184  case 'C': // SSE floating point constant.
1185  case 'G': // x87 floating point constant.
1186  return true;
1187  case '@':
1188  // CC condition changes.
1189  if (auto Len = matchAsmCCConstraint(Name)) {
1190  Name += Len - 1;
1191  Info.setAllowsRegister();
1192  return true;
1193  }
1194  return false;
1195  }
1196 }
1197 
1198 // Below is based on the following information:
1199 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1200 // | Processor Name | Cache Line Size (Bytes) | Source |
1201 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1202 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1203 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1204 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1205 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1206 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1207 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1208 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1209 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1210 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1211 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1212 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1213 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1214 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1215 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1216 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1217 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1218 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1219 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1221  using namespace llvm::X86;
1222  switch (CPU) {
1223  // i386
1224  case CK_i386:
1225  // i486
1226  case CK_i486:
1227  case CK_WinChipC6:
1228  case CK_WinChip2:
1229  case CK_C3:
1230  // Lakemont
1231  case CK_Lakemont:
1232  return 16;
1233 
1234  // i586
1235  case CK_i586:
1236  case CK_Pentium:
1237  case CK_PentiumMMX:
1238  // i686
1239  case CK_PentiumPro:
1240  case CK_i686:
1241  case CK_Pentium2:
1242  case CK_Pentium3:
1243  case CK_PentiumM:
1244  case CK_C3_2:
1245  // K6
1246  case CK_K6:
1247  case CK_K6_2:
1248  case CK_K6_3:
1249  // Geode
1250  case CK_Geode:
1251  return 32;
1252 
1253  // Netburst
1254  case CK_Pentium4:
1255  case CK_Prescott:
1256  case CK_Nocona:
1257  // Atom
1258  case CK_Bonnell:
1259  case CK_Silvermont:
1260  case CK_Goldmont:
1261  case CK_GoldmontPlus:
1262  case CK_Tremont:
1263 
1264  case CK_Westmere:
1265  case CK_SandyBridge:
1266  case CK_IvyBridge:
1267  case CK_Haswell:
1268  case CK_Broadwell:
1269  case CK_SkylakeClient:
1270  case CK_SkylakeServer:
1271  case CK_Cascadelake:
1272  case CK_Nehalem:
1273  case CK_Cooperlake:
1274  case CK_Cannonlake:
1275  case CK_Tigerlake:
1276  case CK_IcelakeClient:
1277  case CK_IcelakeServer:
1278  case CK_KNL:
1279  case CK_KNM:
1280  // K7
1281  case CK_Athlon:
1282  case CK_AthlonXP:
1283  // K8
1284  case CK_K8:
1285  case CK_K8SSE3:
1286  case CK_AMDFAM10:
1287  // Bobcat
1288  case CK_BTVER1:
1289  case CK_BTVER2:
1290  // Bulldozer
1291  case CK_BDVER1:
1292  case CK_BDVER2:
1293  case CK_BDVER3:
1294  case CK_BDVER4:
1295  // Zen
1296  case CK_ZNVER1:
1297  case CK_ZNVER2:
1298  // Deprecated
1299  case CK_x86_64:
1300  case CK_Yonah:
1301  case CK_Penryn:
1302  case CK_Core2:
1303  return 64;
1304 
1305  // The following currently have unknown cache line sizes (but they are probably all 64):
1306  // Core
1307  case CK_None:
1308  return None;
1309  }
1310  llvm_unreachable("Unknown CPU kind");
1311 }
1312 
1313 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1314  StringRef Constraint,
1315  unsigned Size) const {
1316  // Strip off constraint modifiers.
1317  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1318  Constraint = Constraint.substr(1);
1319 
1320  return validateOperandSize(FeatureMap, Constraint, Size);
1321 }
1322 
1323 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1324  StringRef Constraint,
1325  unsigned Size) const {
1326  return validateOperandSize(FeatureMap, Constraint, Size);
1327 }
1328 
1329 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1330  StringRef Constraint,
1331  unsigned Size) const {
1332  switch (Constraint[0]) {
1333  default:
1334  break;
1335  case 'k':
1336  // Registers k0-k7 (AVX512) size limit is 64 bit.
1337  case 'y':
1338  return Size <= 64;
1339  case 'f':
1340  case 't':
1341  case 'u':
1342  return Size <= 128;
1343  case 'Y':
1344  // 'Y' is the first character for several 2-character constraints.
1345  switch (Constraint[1]) {
1346  default:
1347  return false;
1348  case 'm':
1349  // 'Ym' is synonymous with 'y'.
1350  case 'k':
1351  return Size <= 64;
1352  case 'z':
1353  // XMM0/YMM/ZMM0
1354  if (FeatureMap.lookup("avx512f"))
1355  // ZMM0 can be used if target supports AVX512F.
1356  return Size <= 512U;
1357  else if (FeatureMap.lookup("avx"))
1358  // YMM0 can be used if target supports AVX.
1359  return Size <= 256U;
1360  else if (FeatureMap.lookup("sse"))
1361  return Size <= 128U;
1362  return false;
1363  case 'i':
1364  case 't':
1365  case '2':
1366  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1367  if (SSELevel < SSE2)
1368  return false;
1369  break;
1370  }
1371  break;
1372  case 'v':
1373  case 'x':
1374  if (FeatureMap.lookup("avx512f"))
1375  // 512-bit zmm registers can be used if target supports AVX512F.
1376  return Size <= 512U;
1377  else if (FeatureMap.lookup("avx"))
1378  // 256-bit ymm registers can be used if target supports AVX.
1379  return Size <= 256U;
1380  return Size <= 128U;
1381 
1382  }
1383 
1384  return true;
1385 }
1386 
1387 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1388  switch (*Constraint) {
1389  case '@':
1390  if (auto Len = matchAsmCCConstraint(Constraint)) {
1391  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1392  Constraint += Len - 1;
1393  return Converted;
1394  }
1395  return std::string(1, *Constraint);
1396  case 'a':
1397  return std::string("{ax}");
1398  case 'b':
1399  return std::string("{bx}");
1400  case 'c':
1401  return std::string("{cx}");
1402  case 'd':
1403  return std::string("{dx}");
1404  case 'S':
1405  return std::string("{si}");
1406  case 'D':
1407  return std::string("{di}");
1408  case 'p': // address
1409  return std::string("im");
1410  case 't': // top of floating point stack.
1411  return std::string("{st}");
1412  case 'u': // second from top of floating point stack.
1413  return std::string("{st(1)}"); // second from top of floating point stack.
1414  case 'Y':
1415  switch (Constraint[1]) {
1416  default:
1417  // Break from inner switch and fall through (copy single char),
1418  // continue parsing after copying the current constraint into
1419  // the return string.
1420  break;
1421  case 'k':
1422  case 'm':
1423  case 'i':
1424  case 't':
1425  case 'z':
1426  case '2':
1427  // "^" hints llvm that this is a 2 letter constraint.
1428  // "Constraint++" is used to promote the string iterator
1429  // to the next constraint.
1430  return std::string("^") + std::string(Constraint++, 2);
1431  }
1432  LLVM_FALLTHROUGH;
1433  default:
1434  return std::string(1, *Constraint);
1435  }
1436 }
1437 
1439  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1440  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1441 }
1442 
1444  return llvm::makeArrayRef(GCCRegNames);
1445 }
1446 
1448  return llvm::makeArrayRef(AddlRegNames);
1449 }
1450 
1452  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1454 }
1455 
1457  return llvm::makeArrayRef(BuiltinInfoX86,
1459 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:55
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1313
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1329
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1330
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition: X86.cpp:885
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1447
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:963
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1438
static unsigned matchAsmCCConstraint(const char *&Name)
Definition: X86.cpp:1072
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:54
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:980
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1048
__device__ int
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:153
Defines the Diagnostic-related interfaces.
Optional< unsigned > getCPUCacheLineSize() const override
Definition: X86.cpp:1220
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:987
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1106
static const char *const GCCRegNames[]
Definition: X86.cpp:43
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1026
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:798
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:426
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1034
#define X86_FEATURE_COMPAT(ENUM, STR)
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1323
Enumerates target-specific builtins in their own namespaces within namespace clang.
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1456
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:996
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1387
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1451
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1041
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1011
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:171
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:357
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition: X86.cpp:148
__DEVICE__ int max(int __a, int __b)
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:101
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:71
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:29
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1062
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1443
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105