clang 23.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 UpdatedFeaturesVec.push_back(Feature);
178 }
179
180 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
181 return false;
182
183 // Can't do this earlier because we need to be able to explicitly enable
184 // or disable these features and the things that they depend upon.
185
186 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
187 auto I = Features.find("sse4.2");
188 if (I != Features.end() && I->getValue() &&
189 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
190 Features["popcnt"] = true;
191
192 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
193 // then enable MMX.
194 I = Features.find("sse");
195 if (I != Features.end() && I->getValue() &&
196 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
197 Features["mmx"] = true;
198
199 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
200 I = Features.find("avx");
201 if (I != Features.end() && I->getValue() &&
202 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
203 Features["xsave"] = true;
204
205 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
206 I = Features.find("sse4.2");
207 if (I != Features.end() && I->getValue() &&
208 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
209 Features["crc32"] = true;
210
211 return true;
212}
213
214void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
215 StringRef Name, bool Enabled) const {
216 if (Name == "sse4") {
217 // We can get here via the __target__ attribute since that's not controlled
218 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
219 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
220 // disabled.
221 if (Enabled)
222 Name = "sse4.2";
223 else
224 Name = "sse4.1";
225 }
226
227 Features[Name] = Enabled;
228 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
229}
230
231/// handleTargetFeatures - Perform initialization based on the user
232/// configured set of features.
233bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
234 DiagnosticsEngine &Diags) {
235 for (const auto &Feature : Features) {
236 if (Feature[0] != '+')
237 continue;
238
239 if (Feature == "+mmx") {
240 HasMMX = true;
241 } else if (Feature == "+aes") {
242 HasAES = true;
243 } else if (Feature == "+vaes") {
244 HasVAES = true;
245 } else if (Feature == "+pclmul") {
246 HasPCLMUL = true;
247 } else if (Feature == "+vpclmulqdq") {
248 HasVPCLMULQDQ = true;
249 } else if (Feature == "+lzcnt") {
250 HasLZCNT = true;
251 } else if (Feature == "+rdrnd") {
252 HasRDRND = true;
253 } else if (Feature == "+fsgsbase") {
254 HasFSGSBASE = true;
255 } else if (Feature == "+bmi") {
256 HasBMI = true;
257 } else if (Feature == "+bmi2") {
258 HasBMI2 = true;
259 } else if (Feature == "+popcnt") {
260 HasPOPCNT = true;
261 } else if (Feature == "+rtm") {
262 HasRTM = true;
263 } else if (Feature == "+prfchw") {
264 HasPRFCHW = true;
265 } else if (Feature == "+rdseed") {
266 HasRDSEED = true;
267 } else if (Feature == "+adx") {
268 HasADX = true;
269 } else if (Feature == "+tbm") {
270 HasTBM = true;
271 } else if (Feature == "+lwp") {
272 HasLWP = true;
273 } else if (Feature == "+fma") {
274 HasFMA = true;
275 } else if (Feature == "+f16c") {
276 HasF16C = true;
277 } else if (Feature == "+gfni") {
278 HasGFNI = true;
279 } else if (Feature == "+avx10.1") {
280 HasAVX10_1 = true;
281 } else if (Feature == "+avx10.2") {
282 HasAVX10_2 = true;
283 HasFullBFloat16 = true;
284 } else if (Feature == "+avx512cd") {
285 HasAVX512CD = true;
286 } else if (Feature == "+avx512vpopcntdq") {
287 HasAVX512VPOPCNTDQ = true;
288 } else if (Feature == "+avx512vnni") {
289 HasAVX512VNNI = true;
290 } else if (Feature == "+avx512bf16") {
291 HasAVX512BF16 = true;
292 } else if (Feature == "+avx512fp16") {
293 HasAVX512FP16 = true;
294 HasFastHalfType = true;
295 } else if (Feature == "+avx512dq") {
296 HasAVX512DQ = true;
297 } else if (Feature == "+avx512bitalg") {
298 HasAVX512BITALG = true;
299 } else if (Feature == "+avx512bmm") {
300 HasAVX512BMM = true;
301 } else if (Feature == "+avx512bw") {
302 HasAVX512BW = true;
303 } else if (Feature == "+avx512vl") {
304 HasAVX512VL = true;
305 } else if (Feature == "+avx512vbmi") {
306 HasAVX512VBMI = true;
307 } else if (Feature == "+avx512vbmi2") {
308 HasAVX512VBMI2 = true;
309 } else if (Feature == "+avx512ifma") {
310 HasAVX512IFMA = true;
311 } else if (Feature == "+avx512vp2intersect") {
312 HasAVX512VP2INTERSECT = true;
313 } else if (Feature == "+sha") {
314 HasSHA = true;
315 } else if (Feature == "+sha512") {
316 HasSHA512 = true;
317 } else if (Feature == "+shstk") {
318 HasSHSTK = true;
319 } else if (Feature == "+sm3") {
320 HasSM3 = true;
321 } else if (Feature == "+sm4") {
322 HasSM4 = true;
323 } else if (Feature == "+movbe") {
324 HasMOVBE = true;
325 } else if (Feature == "+movrs") {
326 HasMOVRS = true;
327 } else if (Feature == "+sgx") {
328 HasSGX = true;
329 } else if (Feature == "+cx8") {
330 HasCX8 = true;
331 } else if (Feature == "+cx16") {
332 HasCX16 = true;
333 } else if (Feature == "+fxsr") {
334 HasFXSR = true;
335 } else if (Feature == "+xsave") {
336 HasXSAVE = true;
337 } else if (Feature == "+xsaveopt") {
338 HasXSAVEOPT = true;
339 } else if (Feature == "+xsavec") {
340 HasXSAVEC = true;
341 } else if (Feature == "+xsaves") {
342 HasXSAVES = true;
343 } else if (Feature == "+mwaitx") {
344 HasMWAITX = true;
345 } else if (Feature == "+pku") {
346 HasPKU = true;
347 } else if (Feature == "+clflushopt") {
348 HasCLFLUSHOPT = true;
349 } else if (Feature == "+clwb") {
350 HasCLWB = true;
351 } else if (Feature == "+wbnoinvd") {
352 HasWBNOINVD = true;
353 } else if (Feature == "+prefetchi") {
354 HasPREFETCHI = true;
355 } else if (Feature == "+clzero") {
356 HasCLZERO = true;
357 } else if (Feature == "+cldemote") {
358 HasCLDEMOTE = true;
359 } else if (Feature == "+rdpid") {
360 HasRDPID = true;
361 } else if (Feature == "+rdpru") {
362 HasRDPRU = true;
363 } else if (Feature == "+kl") {
364 HasKL = true;
365 } else if (Feature == "+widekl") {
366 HasWIDEKL = true;
367 } else if (Feature == "+retpoline-external-thunk") {
368 HasRetpolineExternalThunk = true;
369 } else if (Feature == "+sahf") {
370 HasLAHFSAHF = true;
371 } else if (Feature == "+waitpkg") {
372 HasWAITPKG = true;
373 } else if (Feature == "+movdiri") {
374 HasMOVDIRI = true;
375 } else if (Feature == "+movdir64b") {
376 HasMOVDIR64B = true;
377 } else if (Feature == "+pconfig") {
378 HasPCONFIG = true;
379 } else if (Feature == "+ptwrite") {
380 HasPTWRITE = true;
381 } else if (Feature == "+invpcid") {
382 HasINVPCID = true;
383 } else if (Feature == "+enqcmd") {
384 HasENQCMD = true;
385 } else if (Feature == "+hreset") {
386 HasHRESET = true;
387 } else if (Feature == "+amx-bf16") {
388 HasAMXBF16 = true;
389 } else if (Feature == "+amx-fp16") {
390 HasAMXFP16 = true;
391 } else if (Feature == "+amx-int8") {
392 HasAMXINT8 = true;
393 } else if (Feature == "+amx-tile") {
394 HasAMXTILE = true;
395 } else if (Feature == "+amx-complex") {
396 HasAMXCOMPLEX = true;
397 } else if (Feature == "+amx-fp8") {
398 HasAMXFP8 = true;
399 } else if (Feature == "+amx-movrs") {
400 HasAMXMOVRS = true;
401 } else if (Feature == "+amx-avx512") {
402 HasAMXAVX512 = true;
403 } else if (Feature == "+amx-tf32") {
404 HasAMXTF32 = true;
405 } else if (Feature == "+cmpccxadd") {
406 HasCMPCCXADD = true;
407 } else if (Feature == "+raoint") {
408 HasRAOINT = true;
409 } else if (Feature == "+avxifma") {
410 HasAVXIFMA = true;
411 } else if (Feature == "+avxneconvert") {
412 HasAVXNECONVERT= true;
413 } else if (Feature == "+avxvnni") {
414 HasAVXVNNI = true;
415 } else if (Feature == "+avxvnniint16") {
416 HasAVXVNNIINT16 = true;
417 } else if (Feature == "+avxvnniint8") {
418 HasAVXVNNIINT8 = true;
419 } else if (Feature == "+serialize") {
420 HasSERIALIZE = true;
421 } else if (Feature == "+tsxldtrk") {
422 HasTSXLDTRK = true;
423 } else if (Feature == "+uintr") {
424 HasUINTR = true;
425 } else if (Feature == "+usermsr") {
426 HasUSERMSR = true;
427 } else if (Feature == "+crc32") {
428 HasCRC32 = true;
429 } else if (Feature == "+x87") {
430 HasX87 = true;
431 } else if (Feature == "+fullbf16") {
432 HasFullBFloat16 = true;
433 } else if (Feature == "+egpr") {
434 HasEGPR = true;
435 } else if (Feature == "+inline-asm-use-gpr32") {
436 HasInlineAsmUseGPR32 = true;
437 } else if (Feature == "+push2pop2") {
438 HasPush2Pop2 = true;
439 } else if (Feature == "+ppx") {
440 HasPPX = true;
441 } else if (Feature == "+ndd") {
442 HasNDD = true;
443 } else if (Feature == "+ccmp") {
444 HasCCMP = true;
445 } else if (Feature == "+nf") {
446 HasNF = true;
447 } else if (Feature == "+cf") {
448 HasCF = true;
449 } else if (Feature == "+zu") {
450 HasZU = true;
451 } else if (Feature == "+jmpabs") {
452 HasJMPABS = true;
453 } else if (Feature == "+branch-hint") {
454 HasBranchHint = true;
455 }
456
457 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
458 .Case("+avx512f", AVX512F)
459 .Case("+avx2", AVX2)
460 .Case("+avx", AVX)
461 .Case("+sse4.2", SSE42)
462 .Case("+sse4.1", SSE41)
463 .Case("+ssse3", SSSE3)
464 .Case("+sse3", SSE3)
465 .Case("+sse2", SSE2)
466 .Case("+sse", SSE1)
467 .Default(NoSSE);
468 SSELevel = std::max(SSELevel, Level);
469
470 HasFloat16 = SSELevel >= SSE2;
471
472 // X86 target has bfloat16 emulation support in the backend, where
473 // bfloat16 is treated as a 32-bit float, arithmetic operations are
474 // performed in 32-bit, and the result is converted back to bfloat16.
475 // Truncation and extension between bfloat16 and 32-bit float are supported
476 // by the compiler-rt library. However, native bfloat16 support is currently
477 // not available in the X86 target. Hence, HasFullBFloat16 will be false
478 // until native bfloat16 support is available. HasFullBFloat16 is used to
479 // determine whether to automatically use excess floating point precision
480 // for bfloat16 arithmetic operations in the front-end.
481 HasBFloat16 = SSELevel >= SSE2;
482
483 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
484 .Case("+xop", XOP)
485 .Case("+fma4", FMA4)
486 .Case("+sse4a", SSE4A)
487 .Default(NoXOP);
488 XOPLevel = std::max(XOPLevel, XLevel);
489 }
490
491 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
492 // matches the selected sse level.
493 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
494 (FPMath == FP_387 && SSELevel >= SSE1)) {
495 Diags.Report(diag::err_target_unsupported_fpmath)
496 << (FPMath == FP_SSE ? "sse" : "387");
497 return false;
498 }
499
500 // FIXME: We should allow long double type on 32-bits to match with GCC.
501 // This requires backend to be able to lower f80 without x87 first.
502 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
503 HasLongDouble = false;
504
505 return true;
506}
507
508/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
509/// definitions for this particular subtarget.
510void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
511 MacroBuilder &Builder) const {
512 // Inline assembly supports X86 flag outputs.
513 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
514
515 std::string CodeModel = getTargetOpts().CodeModel;
516 if (CodeModel == "default")
517 CodeModel = "small";
518 Builder.defineMacro("__code_model_" + CodeModel + "__");
519
520 // Target identification.
521 if (getTriple().getArch() == llvm::Triple::x86_64) {
522 Builder.defineMacro("__amd64__");
523 Builder.defineMacro("__amd64");
524 Builder.defineMacro("__x86_64");
525 Builder.defineMacro("__x86_64__");
526 if (getTriple().getArchName() == "x86_64h") {
527 Builder.defineMacro("__x86_64h");
528 Builder.defineMacro("__x86_64h__");
529 }
530 } else {
531 DefineStd(Builder, "i386", Opts);
532 }
533
534 Builder.defineMacro("__SEG_GS");
535 Builder.defineMacro("__SEG_FS");
536 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
537 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
538
539 // Subtarget options.
540 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
541 // truly should be based on -mtune options.
542 using namespace llvm::X86;
543 switch (CPU) {
544 case CK_None:
545 break;
546 case CK_i386:
547 // The rest are coming from the i386 define above.
548 Builder.defineMacro("__tune_i386__");
549 break;
550 case CK_i486:
551 case CK_WinChipC6:
552 case CK_WinChip2:
553 case CK_C3:
554 defineCPUMacros(Builder, "i486");
555 break;
556 case CK_PentiumMMX:
557 Builder.defineMacro("__pentium_mmx__");
558 Builder.defineMacro("__tune_pentium_mmx__");
559 [[fallthrough]];
560 case CK_i586:
561 case CK_Pentium:
562 defineCPUMacros(Builder, "i586");
563 defineCPUMacros(Builder, "pentium");
564 break;
565 case CK_Pentium3:
566 case CK_PentiumM:
567 Builder.defineMacro("__tune_pentium3__");
568 [[fallthrough]];
569 case CK_Pentium2:
570 case CK_C3_2:
571 Builder.defineMacro("__tune_pentium2__");
572 [[fallthrough]];
573 case CK_PentiumPro:
574 case CK_i686:
575 defineCPUMacros(Builder, "i686");
576 defineCPUMacros(Builder, "pentiumpro");
577 break;
578 case CK_Pentium4:
579 defineCPUMacros(Builder, "pentium4");
580 break;
581 case CK_Yonah:
582 case CK_Prescott:
583 case CK_Nocona:
584 defineCPUMacros(Builder, "nocona");
585 break;
586 case CK_Core2:
587 case CK_Penryn:
588 defineCPUMacros(Builder, "core2");
589 break;
590 case CK_Bonnell:
591 defineCPUMacros(Builder, "atom");
592 break;
593 case CK_Silvermont:
594 defineCPUMacros(Builder, "slm");
595 break;
596 case CK_Goldmont:
597 defineCPUMacros(Builder, "goldmont");
598 break;
599 case CK_GoldmontPlus:
600 defineCPUMacros(Builder, "goldmont_plus");
601 break;
602 case CK_Tremont:
603 defineCPUMacros(Builder, "tremont");
604 break;
605 // Gracemont and later atom-cores use P-core cpu macros.
606 case CK_Gracemont:
607 case CK_Nehalem:
608 case CK_Westmere:
609 case CK_SandyBridge:
610 case CK_IvyBridge:
611 case CK_Haswell:
612 case CK_Broadwell:
613 case CK_SkylakeClient:
614 case CK_SkylakeServer:
615 case CK_Cascadelake:
616 case CK_Cooperlake:
617 case CK_Cannonlake:
618 case CK_IcelakeClient:
619 case CK_Rocketlake:
620 case CK_IcelakeServer:
621 case CK_Tigerlake:
622 case CK_SapphireRapids:
623 case CK_Alderlake:
624 case CK_Raptorlake:
625 case CK_Meteorlake:
626 case CK_Arrowlake:
627 case CK_ArrowlakeS:
628 case CK_Lunarlake:
629 case CK_Pantherlake:
630 case CK_Wildcatlake:
631 case CK_Novalake:
632 case CK_Sierraforest:
633 case CK_Grandridge:
634 case CK_Graniterapids:
635 case CK_GraniterapidsD:
636 case CK_Emeraldrapids:
637 case CK_Clearwaterforest:
638 case CK_Diamondrapids:
639 // FIXME: Historically, we defined this legacy name, it would be nice to
640 // remove it at some point. We've never exposed fine-grained names for
641 // recent primary x86 CPUs, and we should keep it that way.
642 defineCPUMacros(Builder, "corei7");
643 break;
644 case CK_KNL:
645 defineCPUMacros(Builder, "knl");
646 break;
647 case CK_KNM:
648 break;
649 case CK_Lakemont:
650 defineCPUMacros(Builder, "i586", /*Tuning*/false);
651 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
652 Builder.defineMacro("__tune_lakemont__");
653 break;
654 case CK_K6_2:
655 Builder.defineMacro("__k6_2__");
656 Builder.defineMacro("__tune_k6_2__");
657 [[fallthrough]];
658 case CK_K6_3:
659 if (CPU != CK_K6_2) { // In case of fallthrough
660 // FIXME: GCC may be enabling these in cases where some other k6
661 // architecture is specified but -m3dnow is explicitly provided. The
662 // exact semantics need to be determined and emulated here.
663 Builder.defineMacro("__k6_3__");
664 Builder.defineMacro("__tune_k6_3__");
665 }
666 [[fallthrough]];
667 case CK_K6:
668 defineCPUMacros(Builder, "k6");
669 break;
670 case CK_Athlon:
671 case CK_AthlonXP:
672 defineCPUMacros(Builder, "athlon");
673 if (SSELevel != NoSSE) {
674 Builder.defineMacro("__athlon_sse__");
675 Builder.defineMacro("__tune_athlon_sse__");
676 }
677 break;
678 case CK_K8:
679 case CK_K8SSE3:
680 case CK_x86_64:
681 defineCPUMacros(Builder, "k8");
682 break;
683 case CK_x86_64_v2:
684 case CK_x86_64_v3:
685 case CK_x86_64_v4:
686 break;
687 case CK_AMDFAM10:
688 defineCPUMacros(Builder, "amdfam10");
689 break;
690 case CK_BTVER1:
691 defineCPUMacros(Builder, "btver1");
692 break;
693 case CK_BTVER2:
694 defineCPUMacros(Builder, "btver2");
695 break;
696 case CK_BDVER1:
697 defineCPUMacros(Builder, "bdver1");
698 break;
699 case CK_BDVER2:
700 defineCPUMacros(Builder, "bdver2");
701 break;
702 case CK_BDVER3:
703 defineCPUMacros(Builder, "bdver3");
704 break;
705 case CK_BDVER4:
706 defineCPUMacros(Builder, "bdver4");
707 break;
708 case CK_ZNVER1:
709 defineCPUMacros(Builder, "znver1");
710 break;
711 case CK_ZNVER2:
712 defineCPUMacros(Builder, "znver2");
713 break;
714 case CK_ZNVER3:
715 defineCPUMacros(Builder, "znver3");
716 break;
717 case CK_ZNVER4:
718 defineCPUMacros(Builder, "znver4");
719 break;
720 case CK_ZNVER5:
721 defineCPUMacros(Builder, "znver5");
722 break;
723 case CK_ZNVER6:
724 defineCPUMacros(Builder, "znver6");
725 break;
726 case CK_Geode:
727 defineCPUMacros(Builder, "geode");
728 break;
729 case CK_C86_4G_M4:
730 defineCPUMacros(Builder, "c86_4g_m4");
731 break;
732 case CK_C86_4G_M6:
733 defineCPUMacros(Builder, "c86_4g_m6");
734 break;
735 case CK_C86_4G_M7:
736 defineCPUMacros(Builder, "c86_4g_m7");
737 break;
738 case CK_C86_4G_M8:
739 defineCPUMacros(Builder, "c86_4g_m8");
740 break;
741 }
742
743 // Target properties.
744 Builder.defineMacro("__REGISTER_PREFIX__", "");
745
746 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
747 // functions in glibc header files that use FP Stack inline asm which the
748 // backend can't deal with (PR879).
749 Builder.defineMacro("__NO_MATH_INLINES");
750
751 if (HasAES)
752 Builder.defineMacro("__AES__");
753
754 if (HasVAES)
755 Builder.defineMacro("__VAES__");
756
757 if (HasPCLMUL)
758 Builder.defineMacro("__PCLMUL__");
759
760 if (HasVPCLMULQDQ)
761 Builder.defineMacro("__VPCLMULQDQ__");
762
763 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
764 // the feature flag only applies to 64-bit mode.
765 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
766 Builder.defineMacro("__LAHF_SAHF__");
767
768 if (HasLZCNT)
769 Builder.defineMacro("__LZCNT__");
770
771 if (HasRDRND)
772 Builder.defineMacro("__RDRND__");
773
774 if (HasFSGSBASE)
775 Builder.defineMacro("__FSGSBASE__");
776
777 if (HasBMI)
778 Builder.defineMacro("__BMI__");
779
780 if (HasBMI2)
781 Builder.defineMacro("__BMI2__");
782
783 if (HasPOPCNT)
784 Builder.defineMacro("__POPCNT__");
785
786 if (HasRTM)
787 Builder.defineMacro("__RTM__");
788
789 if (HasPRFCHW)
790 Builder.defineMacro("__PRFCHW__");
791
792 if (HasRDSEED)
793 Builder.defineMacro("__RDSEED__");
794
795 if (HasADX)
796 Builder.defineMacro("__ADX__");
797
798 if (HasTBM)
799 Builder.defineMacro("__TBM__");
800
801 if (HasLWP)
802 Builder.defineMacro("__LWP__");
803
804 if (HasMWAITX)
805 Builder.defineMacro("__MWAITX__");
806
807 if (HasMOVBE)
808 Builder.defineMacro("__MOVBE__");
809
810 switch (XOPLevel) {
811 case XOP:
812 Builder.defineMacro("__XOP__");
813 [[fallthrough]];
814 case FMA4:
815 Builder.defineMacro("__FMA4__");
816 [[fallthrough]];
817 case SSE4A:
818 Builder.defineMacro("__SSE4A__");
819 [[fallthrough]];
820 case NoXOP:
821 break;
822 }
823
824 if (HasFMA)
825 Builder.defineMacro("__FMA__");
826
827 if (HasF16C)
828 Builder.defineMacro("__F16C__");
829
830 if (HasGFNI)
831 Builder.defineMacro("__GFNI__");
832
833 if (HasAVX10_1) {
834 Builder.defineMacro("__AVX10_1__");
835 Builder.defineMacro("__AVX10_1_512__");
836 }
837 if (HasAVX10_2) {
838 Builder.defineMacro("__AVX10_2__");
839 Builder.defineMacro("__AVX10_2_512__");
840 }
841 if (HasAVX512CD)
842 Builder.defineMacro("__AVX512CD__");
843 if (HasAVX512VPOPCNTDQ)
844 Builder.defineMacro("__AVX512VPOPCNTDQ__");
845 if (HasAVX512VNNI)
846 Builder.defineMacro("__AVX512VNNI__");
847 if (HasAVX512BF16)
848 Builder.defineMacro("__AVX512BF16__");
849 if (HasAVX512FP16)
850 Builder.defineMacro("__AVX512FP16__");
851 if (HasAVX512DQ)
852 Builder.defineMacro("__AVX512DQ__");
853 if (HasAVX512BITALG)
854 Builder.defineMacro("__AVX512BITALG__");
855 if (HasAVX512BMM)
856 Builder.defineMacro("__AVX512BMM__");
857 if (HasAVX512BW)
858 Builder.defineMacro("__AVX512BW__");
859 if (HasAVX512VL) {
860 Builder.defineMacro("__AVX512VL__");
861 }
862 if (HasAVX512VBMI)
863 Builder.defineMacro("__AVX512VBMI__");
864 if (HasAVX512VBMI2)
865 Builder.defineMacro("__AVX512VBMI2__");
866 if (HasAVX512IFMA)
867 Builder.defineMacro("__AVX512IFMA__");
868 if (HasAVX512VP2INTERSECT)
869 Builder.defineMacro("__AVX512VP2INTERSECT__");
870 if (HasSHA)
871 Builder.defineMacro("__SHA__");
872 if (HasSHA512)
873 Builder.defineMacro("__SHA512__");
874
875 if (HasFXSR)
876 Builder.defineMacro("__FXSR__");
877 if (HasXSAVE)
878 Builder.defineMacro("__XSAVE__");
879 if (HasXSAVEOPT)
880 Builder.defineMacro("__XSAVEOPT__");
881 if (HasXSAVEC)
882 Builder.defineMacro("__XSAVEC__");
883 if (HasXSAVES)
884 Builder.defineMacro("__XSAVES__");
885 if (HasPKU)
886 Builder.defineMacro("__PKU__");
887 if (HasCLFLUSHOPT)
888 Builder.defineMacro("__CLFLUSHOPT__");
889 if (HasCLWB)
890 Builder.defineMacro("__CLWB__");
891 if (HasWBNOINVD)
892 Builder.defineMacro("__WBNOINVD__");
893 if (HasSHSTK)
894 Builder.defineMacro("__SHSTK__");
895 if (HasSGX)
896 Builder.defineMacro("__SGX__");
897 if (HasSM3)
898 Builder.defineMacro("__SM3__");
899 if (HasSM4)
900 Builder.defineMacro("__SM4__");
901 if (HasPREFETCHI)
902 Builder.defineMacro("__PREFETCHI__");
903 if (HasCLZERO)
904 Builder.defineMacro("__CLZERO__");
905 if (HasKL)
906 Builder.defineMacro("__KL__");
907 if (HasWIDEKL)
908 Builder.defineMacro("__WIDEKL__");
909 if (HasRDPID)
910 Builder.defineMacro("__RDPID__");
911 if (HasRDPRU)
912 Builder.defineMacro("__RDPRU__");
913 if (HasCLDEMOTE)
914 Builder.defineMacro("__CLDEMOTE__");
915 if (HasWAITPKG)
916 Builder.defineMacro("__WAITPKG__");
917 if (HasMOVDIRI)
918 Builder.defineMacro("__MOVDIRI__");
919 if (HasMOVDIR64B)
920 Builder.defineMacro("__MOVDIR64B__");
921 if (HasMOVRS)
922 Builder.defineMacro("__MOVRS__");
923 if (HasPCONFIG)
924 Builder.defineMacro("__PCONFIG__");
925 if (HasPTWRITE)
926 Builder.defineMacro("__PTWRITE__");
927 if (HasINVPCID)
928 Builder.defineMacro("__INVPCID__");
929 if (HasENQCMD)
930 Builder.defineMacro("__ENQCMD__");
931 if (HasHRESET)
932 Builder.defineMacro("__HRESET__");
933 if (HasAMXTILE)
934 Builder.defineMacro("__AMX_TILE__");
935 if (HasAMXINT8)
936 Builder.defineMacro("__AMX_INT8__");
937 if (HasAMXBF16)
938 Builder.defineMacro("__AMX_BF16__");
939 if (HasAMXFP16)
940 Builder.defineMacro("__AMX_FP16__");
941 if (HasAMXCOMPLEX)
942 Builder.defineMacro("__AMX_COMPLEX__");
943 if (HasAMXFP8)
944 Builder.defineMacro("__AMX_FP8__");
945 if (HasAMXMOVRS)
946 Builder.defineMacro("__AMX_MOVRS__");
947 if (HasAMXAVX512)
948 Builder.defineMacro("__AMX_AVX512__");
949 if (HasAMXTF32)
950 Builder.defineMacro("__AMX_TF32__");
951 if (HasCMPCCXADD)
952 Builder.defineMacro("__CMPCCXADD__");
953 if (HasRAOINT)
954 Builder.defineMacro("__RAOINT__");
955 if (HasAVXIFMA)
956 Builder.defineMacro("__AVXIFMA__");
957 if (HasAVXNECONVERT)
958 Builder.defineMacro("__AVXNECONVERT__");
959 if (HasAVXVNNI)
960 Builder.defineMacro("__AVXVNNI__");
961 if (HasAVXVNNIINT16)
962 Builder.defineMacro("__AVXVNNIINT16__");
963 if (HasAVXVNNIINT8)
964 Builder.defineMacro("__AVXVNNIINT8__");
965 if (HasSERIALIZE)
966 Builder.defineMacro("__SERIALIZE__");
967 if (HasTSXLDTRK)
968 Builder.defineMacro("__TSXLDTRK__");
969 if (HasUINTR)
970 Builder.defineMacro("__UINTR__");
971 if (HasUSERMSR)
972 Builder.defineMacro("__USERMSR__");
973 if (HasCRC32)
974 Builder.defineMacro("__CRC32__");
975 if (HasEGPR)
976 Builder.defineMacro("__EGPR__");
977 if (HasPush2Pop2)
978 Builder.defineMacro("__PUSH2POP2__");
979 if (HasPPX)
980 Builder.defineMacro("__PPX__");
981 if (HasNDD)
982 Builder.defineMacro("__NDD__");
983 if (HasCCMP)
984 Builder.defineMacro("__CCMP__");
985 if (HasNF)
986 Builder.defineMacro("__NF__");
987 if (HasCF)
988 Builder.defineMacro("__CF__");
989 if (HasZU)
990 Builder.defineMacro("__ZU__");
991 if (HasJMPABS)
992 Builder.defineMacro("__JMPABS__");
993 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
994 HasZU && HasJMPABS)
995 Builder.defineMacro("__APX_F__");
996 if (HasEGPR && HasInlineAsmUseGPR32)
997 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
998
999 // Each case falls through to the previous one here.
1000 switch (SSELevel) {
1001 case AVX512F:
1002 Builder.defineMacro("__AVX512F__");
1003 [[fallthrough]];
1004 case AVX2:
1005 Builder.defineMacro("__AVX2__");
1006 [[fallthrough]];
1007 case AVX:
1008 Builder.defineMacro("__AVX__");
1009 [[fallthrough]];
1010 case SSE42:
1011 Builder.defineMacro("__SSE4_2__");
1012 [[fallthrough]];
1013 case SSE41:
1014 Builder.defineMacro("__SSE4_1__");
1015 [[fallthrough]];
1016 case SSSE3:
1017 Builder.defineMacro("__SSSE3__");
1018 [[fallthrough]];
1019 case SSE3:
1020 Builder.defineMacro("__SSE3__");
1021 [[fallthrough]];
1022 case SSE2:
1023 Builder.defineMacro("__SSE2__");
1024 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1025 [[fallthrough]];
1026 case SSE1:
1027 Builder.defineMacro("__SSE__");
1028 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1029 [[fallthrough]];
1030 case NoSSE:
1031 break;
1032 }
1033
1034 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1035 switch (SSELevel) {
1036 case AVX512F:
1037 case AVX2:
1038 case AVX:
1039 case SSE42:
1040 case SSE41:
1041 case SSSE3:
1042 case SSE3:
1043 case SSE2:
1044 Builder.defineMacro("_M_IX86_FP", Twine(2));
1045 break;
1046 case SSE1:
1047 Builder.defineMacro("_M_IX86_FP", Twine(1));
1048 break;
1049 default:
1050 Builder.defineMacro("_M_IX86_FP", Twine(0));
1051 break;
1052 }
1053 }
1054
1055 // Each case falls through to the previous one here.
1056 if (HasMMX) {
1057 Builder.defineMacro("__MMX__");
1058 }
1059
1060 if (CPU >= CK_i486 || CPU == CK_None) {
1061 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1062 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1063 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1064 }
1065 if (HasCX8)
1066 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1067 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1068 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1069
1070 if (HasFloat128)
1071 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1072
1073 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1074 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1075 Opts.CFProtectionBranch});
1076}
1077
1078bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1079 return llvm::StringSwitch<bool>(Name)
1080 .Case("adx", true)
1081 .Case("aes", true)
1082 .Case("amx-avx512", true)
1083 .Case("amx-bf16", true)
1084 .Case("amx-complex", true)
1085 .Case("amx-fp16", true)
1086 .Case("amx-fp8", true)
1087 .Case("amx-int8", true)
1088 .Case("amx-movrs", true)
1089 .Case("amx-tf32", true)
1090 .Case("amx-tile", true)
1091 .Case("avx", true)
1092 .Case("avx10.1", true)
1093 .Case("avx10.2", true)
1094 .Case("avx2", true)
1095 .Case("avx512f", true)
1096 .Case("avx512cd", true)
1097 .Case("avx512vpopcntdq", true)
1098 .Case("avx512vnni", true)
1099 .Case("avx512bf16", true)
1100 .Case("avx512fp16", true)
1101 .Case("avx512dq", true)
1102 .Case("avx512bitalg", true)
1103 .Case("avx512bmm", true)
1104 .Case("avx512bw", true)
1105 .Case("avx512vl", true)
1106 .Case("avx512vbmi", true)
1107 .Case("avx512vbmi2", true)
1108 .Case("avx512ifma", true)
1109 .Case("avx512vp2intersect", true)
1110 .Case("avxifma", true)
1111 .Case("avxneconvert", true)
1112 .Case("avxvnni", true)
1113 .Case("avxvnniint16", true)
1114 .Case("avxvnniint8", true)
1115 .Case("bmi", true)
1116 .Case("bmi2", true)
1117 .Case("cldemote", true)
1118 .Case("clflushopt", true)
1119 .Case("clwb", true)
1120 .Case("clzero", true)
1121 .Case("cmpccxadd", true)
1122 .Case("crc32", true)
1123 .Case("cx16", true)
1124 .Case("enqcmd", true)
1125 .Case("f16c", true)
1126 .Case("fma", true)
1127 .Case("fma4", true)
1128 .Case("fsgsbase", true)
1129 .Case("fxsr", true)
1130 .Case("general-regs-only", true)
1131 .Case("gfni", true)
1132 .Case("hreset", true)
1133 .Case("invpcid", true)
1134 .Case("kl", true)
1135 .Case("widekl", true)
1136 .Case("lwp", true)
1137 .Case("lzcnt", true)
1138 .Case("mmx", true)
1139 .Case("movbe", true)
1140 .Case("movrs", true)
1141 .Case("movdiri", true)
1142 .Case("movdir64b", true)
1143 .Case("mwaitx", true)
1144 .Case("pclmul", true)
1145 .Case("pconfig", true)
1146 .Case("pku", true)
1147 .Case("popcnt", true)
1148 .Case("prefer-256-bit", true)
1149 .Case("prefetchi", true)
1150 .Case("prfchw", true)
1151 .Case("ptwrite", true)
1152 .Case("raoint", true)
1153 .Case("rdpid", true)
1154 .Case("rdpru", true)
1155 .Case("rdrnd", true)
1156 .Case("rdseed", true)
1157 .Case("rtm", true)
1158 .Case("sahf", true)
1159 .Case("serialize", true)
1160 .Case("sgx", true)
1161 .Case("sha", true)
1162 .Case("sha512", true)
1163 .Case("shstk", true)
1164 .Case("sm3", true)
1165 .Case("sm4", true)
1166 .Case("sse", true)
1167 .Case("sse2", true)
1168 .Case("sse3", true)
1169 .Case("ssse3", true)
1170 .Case("sse4", true)
1171 .Case("sse4.1", true)
1172 .Case("sse4.2", true)
1173 .Case("sse4a", true)
1174 .Case("tbm", true)
1175 .Case("tsxldtrk", true)
1176 .Case("uintr", true)
1177 .Case("usermsr", true)
1178 .Case("vaes", true)
1179 .Case("vpclmulqdq", true)
1180 .Case("wbnoinvd", true)
1181 .Case("waitpkg", true)
1182 .Case("x87", true)
1183 .Case("xop", true)
1184 .Case("xsave", true)
1185 .Case("xsavec", true)
1186 .Case("xsaves", true)
1187 .Case("xsaveopt", true)
1188 .Case("egpr", true)
1189 .Case("push2pop2", true)
1190 .Case("ppx", true)
1191 .Case("ndd", true)
1192 .Case("ccmp", true)
1193 .Case("nf", true)
1194 .Case("cf", true)
1195 .Case("zu", true)
1196 .Case("jmpabs", true)
1197 .Default(false);
1198}
1199
1200bool X86TargetInfo::hasFeature(StringRef Feature) const {
1201 return llvm::StringSwitch<bool>(Feature)
1202 .Case("adx", HasADX)
1203 .Case("aes", HasAES)
1204 .Case("amx-avx512", HasAMXAVX512)
1205 .Case("amx-bf16", HasAMXBF16)
1206 .Case("amx-complex", HasAMXCOMPLEX)
1207 .Case("amx-fp16", HasAMXFP16)
1208 .Case("amx-fp8", HasAMXFP8)
1209 .Case("amx-int8", HasAMXINT8)
1210 .Case("amx-movrs", HasAMXMOVRS)
1211 .Case("amx-tf32", HasAMXTF32)
1212 .Case("amx-tile", HasAMXTILE)
1213 .Case("avx", SSELevel >= AVX)
1214 .Case("avx10.1", HasAVX10_1)
1215 .Case("avx10.2", HasAVX10_2)
1216 .Case("avx2", SSELevel >= AVX2)
1217 .Case("avx512f", SSELevel >= AVX512F)
1218 .Case("avx512cd", HasAVX512CD)
1219 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1220 .Case("avx512vnni", HasAVX512VNNI)
1221 .Case("avx512bf16", HasAVX512BF16)
1222 .Case("avx512fp16", HasAVX512FP16)
1223 .Case("avx512dq", HasAVX512DQ)
1224 .Case("avx512bitalg", HasAVX512BITALG)
1225 .Case("avx512bmm", HasAVX512BMM)
1226 .Case("avx512bw", HasAVX512BW)
1227 .Case("avx512vl", HasAVX512VL)
1228 .Case("avx512vbmi", HasAVX512VBMI)
1229 .Case("avx512vbmi2", HasAVX512VBMI2)
1230 .Case("avx512ifma", HasAVX512IFMA)
1231 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1232 .Case("avxifma", HasAVXIFMA)
1233 .Case("avxneconvert", HasAVXNECONVERT)
1234 .Case("avxvnni", HasAVXVNNI)
1235 .Case("avxvnniint16", HasAVXVNNIINT16)
1236 .Case("avxvnniint8", HasAVXVNNIINT8)
1237 .Case("bmi", HasBMI)
1238 .Case("bmi2", HasBMI2)
1239 .Case("cldemote", HasCLDEMOTE)
1240 .Case("clflushopt", HasCLFLUSHOPT)
1241 .Case("clwb", HasCLWB)
1242 .Case("clzero", HasCLZERO)
1243 .Case("cmpccxadd", HasCMPCCXADD)
1244 .Case("crc32", HasCRC32)
1245 .Case("cx8", HasCX8)
1246 .Case("cx16", HasCX16)
1247 .Case("enqcmd", HasENQCMD)
1248 .Case("f16c", HasF16C)
1249 .Case("fma", HasFMA)
1250 .Case("fma4", XOPLevel >= FMA4)
1251 .Case("fsgsbase", HasFSGSBASE)
1252 .Case("fxsr", HasFXSR)
1253 .Case("gfni", HasGFNI)
1254 .Case("hreset", HasHRESET)
1255 .Case("invpcid", HasINVPCID)
1256 .Case("kl", HasKL)
1257 .Case("widekl", HasWIDEKL)
1258 .Case("lwp", HasLWP)
1259 .Case("lzcnt", HasLZCNT)
1260 .Case("mmx", HasMMX)
1261 .Case("movbe", HasMOVBE)
1262 .Case("movrs", HasMOVRS)
1263 .Case("movdiri", HasMOVDIRI)
1264 .Case("movdir64b", HasMOVDIR64B)
1265 .Case("mwaitx", HasMWAITX)
1266 .Case("pclmul", HasPCLMUL)
1267 .Case("pconfig", HasPCONFIG)
1268 .Case("pku", HasPKU)
1269 .Case("popcnt", HasPOPCNT)
1270 .Case("prefetchi", HasPREFETCHI)
1271 .Case("prfchw", HasPRFCHW)
1272 .Case("ptwrite", HasPTWRITE)
1273 .Case("raoint", HasRAOINT)
1274 .Case("rdpid", HasRDPID)
1275 .Case("rdpru", HasRDPRU)
1276 .Case("rdrnd", HasRDRND)
1277 .Case("rdseed", HasRDSEED)
1278 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1279 .Case("rtm", HasRTM)
1280 .Case("sahf", HasLAHFSAHF)
1281 .Case("serialize", HasSERIALIZE)
1282 .Case("sgx", HasSGX)
1283 .Case("sha", HasSHA)
1284 .Case("sha512", HasSHA512)
1285 .Case("shstk", HasSHSTK)
1286 .Case("sm3", HasSM3)
1287 .Case("sm4", HasSM4)
1288 .Case("sse", SSELevel >= SSE1)
1289 .Case("sse2", SSELevel >= SSE2)
1290 .Case("sse3", SSELevel >= SSE3)
1291 .Case("ssse3", SSELevel >= SSSE3)
1292 .Case("sse4.1", SSELevel >= SSE41)
1293 .Case("sse4.2", SSELevel >= SSE42)
1294 .Case("sse4a", XOPLevel >= SSE4A)
1295 .Case("tbm", HasTBM)
1296 .Case("tsxldtrk", HasTSXLDTRK)
1297 .Case("uintr", HasUINTR)
1298 .Case("usermsr", HasUSERMSR)
1299 .Case("vaes", HasVAES)
1300 .Case("vpclmulqdq", HasVPCLMULQDQ)
1301 .Case("wbnoinvd", HasWBNOINVD)
1302 .Case("waitpkg", HasWAITPKG)
1303 .Case("x86", true)
1304 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1305 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1306 .Case("x87", HasX87)
1307 .Case("xop", XOPLevel >= XOP)
1308 .Case("xsave", HasXSAVE)
1309 .Case("xsavec", HasXSAVEC)
1310 .Case("xsaves", HasXSAVES)
1311 .Case("xsaveopt", HasXSAVEOPT)
1312 .Case("fullbf16", HasFullBFloat16)
1313 .Case("egpr", HasEGPR)
1314 .Case("push2pop2", HasPush2Pop2)
1315 .Case("ppx", HasPPX)
1316 .Case("ndd", HasNDD)
1317 .Case("ccmp", HasCCMP)
1318 .Case("nf", HasNF)
1319 .Case("cf", HasCF)
1320 .Case("zu", HasZU)
1321 .Case("jmpabs", HasJMPABS)
1322 .Case("branch-hint", HasBranchHint)
1323 .Default(false);
1324}
1325
1326// We can't use a generic validation scheme for the features accepted here
1327// versus subtarget features accepted in the target attribute because the
1328// bitfield structure that's initialized in the runtime only supports the
1329// below currently rather than the full range of subtarget features. (See
1330// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1331bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1332 return llvm::StringSwitch<bool>(FeatureStr)
1333#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1334#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1335#include "llvm/TargetParser/X86TargetParser.def"
1336 .Default(false);
1337}
1338
1339static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1340 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1341#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1342 .Case(STR, llvm::X86::FEATURE_##ENUM)
1343
1344#include "llvm/TargetParser/X86TargetParser.def"
1345 ;
1346 // Note, this function should only be used after ensuring the value is
1347 // correct, so it asserts if the value is out of range.
1348}
1349
1350llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1351 auto getPriority = [](StringRef Feature) -> unsigned {
1352 // Valid CPUs have a 'key feature' that compares just better than its key
1353 // feature.
1354 using namespace llvm::X86;
1355 CPUKind Kind = parseArchX86(Feature);
1356 if (Kind != CK_None) {
1357 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1358 return (getFeaturePriority(KeyFeature) << 1) + 1;
1359 }
1360 // Now we know we have a feature, so get its priority and shift it a few so
1361 // that we have sufficient room for the CPUs (above).
1362 return getFeaturePriority(getFeature(Feature)) << 1;
1363 };
1364
1365 unsigned Priority = 0;
1366 for (StringRef Feature : Features)
1367 if (!Feature.empty())
1368 Priority = std::max(Priority, getPriority(Feature));
1369 return llvm::APInt(32, Priority);
1370}
1371
1372bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1373 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1374}
1375
1376char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1377 return llvm::X86::getCPUDispatchMangling(Name);
1378}
1379
1380void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1381 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1382 SmallVector<StringRef, 32> TargetCPUFeatures;
1383 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1384 for (auto &F : TargetCPUFeatures)
1385 Features.push_back(F);
1386}
1387
1388// We can't use a generic validation scheme for the cpus accepted here
1389// versus subtarget cpus accepted in the target attribute because the
1390// variables intitialized by the runtime only support the below currently
1391// rather than the full range of cpus.
1392bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1393 return llvm::StringSwitch<bool>(FeatureStr)
1394#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1395#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1396#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1397#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1398#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1399#include "llvm/TargetParser/X86TargetParser.def"
1400 .Default(false);
1401}
1402
1403static unsigned matchAsmCCConstraint(const char *Name) {
1404 auto RV = llvm::StringSwitch<unsigned>(Name)
1405 .Case("@cca", 4)
1406 .Case("@ccae", 5)
1407 .Case("@ccb", 4)
1408 .Case("@ccbe", 5)
1409 .Case("@ccc", 4)
1410 .Case("@cce", 4)
1411 .Case("@ccz", 4)
1412 .Case("@ccg", 4)
1413 .Case("@ccge", 5)
1414 .Case("@ccl", 4)
1415 .Case("@ccle", 5)
1416 .Case("@ccna", 5)
1417 .Case("@ccnae", 6)
1418 .Case("@ccnb", 5)
1419 .Case("@ccnbe", 6)
1420 .Case("@ccnc", 5)
1421 .Case("@ccne", 5)
1422 .Case("@ccnz", 5)
1423 .Case("@ccng", 5)
1424 .Case("@ccnge", 6)
1425 .Case("@ccnl", 5)
1426 .Case("@ccnle", 6)
1427 .Case("@ccno", 5)
1428 .Case("@ccnp", 5)
1429 .Case("@ccns", 5)
1430 .Case("@cco", 4)
1431 .Case("@ccp", 4)
1432 .Case("@ccs", 4)
1433 .Default(0);
1434 return RV;
1435}
1436
1437bool X86TargetInfo::validateAsmConstraint(
1438 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1439 switch (*Name) {
1440 default:
1441 return false;
1442 // Constant constraints.
1443 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1444 // instructions.
1445 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1446 // x86_64 instructions.
1447 case 's':
1448 Info.setRequiresImmediate();
1449 return true;
1450 case 'I':
1451 Info.setRequiresImmediate(0, 31);
1452 return true;
1453 case 'J':
1454 Info.setRequiresImmediate(0, 63);
1455 return true;
1456 case 'K':
1457 Info.setRequiresImmediate(-128, 127);
1458 return true;
1459 case 'L':
1460 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1461 return true;
1462 case 'M':
1463 Info.setRequiresImmediate(0, 3);
1464 return true;
1465 case 'N':
1466 Info.setRequiresImmediate(0, 255);
1467 return true;
1468 case 'O':
1469 Info.setRequiresImmediate(0, 127);
1470 return true;
1471 case 'W':
1472 switch (*++Name) {
1473 default:
1474 return false;
1475 case 's':
1476 Info.setAllowsRegister();
1477 return true;
1478 }
1479 // Register constraints.
1480 case 'Y': // 'Y' is the first character for several 2-character constraints.
1481 // Shift the pointer to the second character of the constraint.
1482 Name++;
1483 switch (*Name) {
1484 default:
1485 return false;
1486 case 'z': // First SSE register.
1487 case '2':
1488 case 't': // Any SSE register, when SSE2 is enabled.
1489 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1490 case 'm': // Any MMX register, when inter-unit moves enabled.
1491 case 'k': // AVX512 arch mask registers: k1-k7.
1492 Info.setAllowsRegister();
1493 return true;
1494 }
1495 case 'f': // Any x87 floating point stack register.
1496 // Constraint 'f' cannot be used for output operands.
1497 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1498 return false;
1499 Info.setAllowsRegister();
1500 return true;
1501 case 'a': // eax.
1502 case 'b': // ebx.
1503 case 'c': // ecx.
1504 case 'd': // edx.
1505 case 'S': // esi.
1506 case 'D': // edi.
1507 case 'A': // edx:eax.
1508 case 't': // Top of floating point stack.
1509 case 'u': // Second from top of floating point stack.
1510 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1511 case 'y': // Any MMX register.
1512 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1513 case 'x': // Any SSE register.
1514 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1515 // for intermideate k reg operations).
1516 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1517 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1518 case 'l': // "Index" registers: any general register that can be used as an
1519 // index in a base+index memory access.
1520 Info.setAllowsRegister();
1521 return true;
1522 // Floating point constant constraints.
1523 case 'C': // SSE floating point constant.
1524 case 'G': // x87 floating point constant.
1525 return true;
1526 case 'j':
1527 Name++;
1528 switch (*Name) {
1529 default:
1530 return false;
1531 case 'r':
1532 Info.setAllowsRegister();
1533 return true;
1534 case 'R':
1535 Info.setAllowsRegister();
1536 return true;
1537 }
1538 case '@':
1539 // CC condition changes.
1540 if (auto Len = matchAsmCCConstraint(Name)) {
1541 Name += Len - 1;
1542 Info.setAllowsRegister();
1543 Info.setOutputOperandBounds(0, 2);
1544 return true;
1545 }
1546 return false;
1547 }
1548}
1549
1550// Below is based on the following information:
1551// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1552// | Processor Name | Cache Line Size (Bytes) | Source |
1553// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1554// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1555// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1556// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1557// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1558// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1559// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1560// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1561// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1562// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1563// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1564// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1565// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1566// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1567// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1568// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1569// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1570// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1571// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1572std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1573 using namespace llvm::X86;
1574 switch (CPU) {
1575 // i386
1576 case CK_i386:
1577 // i486
1578 case CK_i486:
1579 case CK_WinChipC6:
1580 case CK_WinChip2:
1581 case CK_C3:
1582 // Lakemont
1583 case CK_Lakemont:
1584 return 16;
1585
1586 // i586
1587 case CK_i586:
1588 case CK_Pentium:
1589 case CK_PentiumMMX:
1590 // i686
1591 case CK_PentiumPro:
1592 case CK_i686:
1593 case CK_Pentium2:
1594 case CK_Pentium3:
1595 case CK_PentiumM:
1596 case CK_C3_2:
1597 // K6
1598 case CK_K6:
1599 case CK_K6_2:
1600 case CK_K6_3:
1601 // Geode
1602 case CK_Geode:
1603 return 32;
1604
1605 // Netburst
1606 case CK_Pentium4:
1607 case CK_Prescott:
1608 case CK_Nocona:
1609 // Atom
1610 case CK_Bonnell:
1611 case CK_Silvermont:
1612 case CK_Goldmont:
1613 case CK_GoldmontPlus:
1614 case CK_Tremont:
1615 case CK_Gracemont:
1616
1617 case CK_Westmere:
1618 case CK_SandyBridge:
1619 case CK_IvyBridge:
1620 case CK_Haswell:
1621 case CK_Broadwell:
1622 case CK_SkylakeClient:
1623 case CK_SkylakeServer:
1624 case CK_Cascadelake:
1625 case CK_Nehalem:
1626 case CK_Cooperlake:
1627 case CK_Cannonlake:
1628 case CK_Tigerlake:
1629 case CK_SapphireRapids:
1630 case CK_IcelakeClient:
1631 case CK_Rocketlake:
1632 case CK_IcelakeServer:
1633 case CK_Alderlake:
1634 case CK_Raptorlake:
1635 case CK_Meteorlake:
1636 case CK_Arrowlake:
1637 case CK_ArrowlakeS:
1638 case CK_Lunarlake:
1639 case CK_Pantherlake:
1640 case CK_Wildcatlake:
1641 case CK_Novalake:
1642 case CK_Sierraforest:
1643 case CK_Grandridge:
1644 case CK_Graniterapids:
1645 case CK_GraniterapidsD:
1646 case CK_Emeraldrapids:
1647 case CK_Clearwaterforest:
1648 case CK_Diamondrapids:
1649 case CK_KNL:
1650 case CK_KNM:
1651 // K7
1652 case CK_Athlon:
1653 case CK_AthlonXP:
1654 // K8
1655 case CK_K8:
1656 case CK_K8SSE3:
1657 case CK_AMDFAM10:
1658 // Bobcat
1659 case CK_BTVER1:
1660 case CK_BTVER2:
1661 // Bulldozer
1662 case CK_BDVER1:
1663 case CK_BDVER2:
1664 case CK_BDVER3:
1665 case CK_BDVER4:
1666 // Zen
1667 case CK_ZNVER1:
1668 case CK_ZNVER2:
1669 case CK_ZNVER3:
1670 case CK_ZNVER4:
1671 case CK_ZNVER5:
1672 case CK_ZNVER6:
1673 // Hygon
1674 case CK_C86_4G_M4:
1675 case CK_C86_4G_M6:
1676 case CK_C86_4G_M7:
1677 case CK_C86_4G_M8:
1678 // Deprecated
1679 case CK_x86_64:
1680 case CK_x86_64_v2:
1681 case CK_x86_64_v3:
1682 case CK_x86_64_v4:
1683 case CK_Yonah:
1684 case CK_Penryn:
1685 case CK_Core2:
1686 return 64;
1687
1688 // The following currently have unknown cache line sizes (but they are probably all 64):
1689 // Core
1690 case CK_None:
1691 return std::nullopt;
1692 }
1693 llvm_unreachable("Unknown CPU kind");
1694}
1695
1696bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1697 StringRef Constraint,
1698 unsigned Size) const {
1699 // Strip off constraint modifiers.
1700 Constraint = Constraint.ltrim("=+&");
1701
1702 return validateOperandSize(FeatureMap, Constraint, Size);
1703}
1704
1705bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1706 StringRef Constraint,
1707 unsigned Size) const {
1708 return validateOperandSize(FeatureMap, Constraint, Size);
1709}
1710
1711bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1712 StringRef Constraint,
1713 unsigned Size) const {
1714 switch (Constraint[0]) {
1715 default:
1716 break;
1717 case 'k':
1718 // Registers k0-k7 (AVX512) size limit is 64 bit.
1719 case 'y':
1720 return Size <= 64;
1721 case 'f':
1722 case 't':
1723 case 'u':
1724 return Size <= 128;
1725 case 'Y':
1726 // 'Y' is the first character for several 2-character constraints.
1727 switch (Constraint[1]) {
1728 default:
1729 return false;
1730 case 'm':
1731 // 'Ym' is synonymous with 'y'.
1732 case 'k':
1733 return Size <= 64;
1734 case 'z':
1735 // XMM0/YMM/ZMM0
1736 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1737 // ZMM0 can be used if target supports AVX512F.
1738 return Size <= 512U;
1739 else if (hasFeatureEnabled(FeatureMap, "avx"))
1740 // YMM0 can be used if target supports AVX.
1741 return Size <= 256U;
1742 else if (hasFeatureEnabled(FeatureMap, "sse"))
1743 return Size <= 128U;
1744 return false;
1745 case 'i':
1746 case 't':
1747 case '2':
1748 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1749 if (SSELevel < SSE2)
1750 return false;
1751 break;
1752 }
1753 break;
1754 case 'v':
1755 case 'x':
1756 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1757 // 512-bit zmm registers can be used if target supports AVX512F.
1758 return Size <= 512U;
1759 else if (hasFeatureEnabled(FeatureMap, "avx"))
1760 // 256-bit ymm registers can be used if target supports AVX.
1761 return Size <= 256U;
1762 return Size <= 128U;
1763
1764 }
1765
1766 return true;
1767}
1768
1769std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1770 switch (*Constraint) {
1771 case '@':
1772 if (auto Len = matchAsmCCConstraint(Constraint)) {
1773 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1774 Constraint += Len - 1;
1775 return Converted;
1776 }
1777 return std::string(1, *Constraint);
1778 case 'a':
1779 return std::string("{ax}");
1780 case 'b':
1781 return std::string("{bx}");
1782 case 'c':
1783 return std::string("{cx}");
1784 case 'd':
1785 return std::string("{dx}");
1786 case 'S':
1787 return std::string("{si}");
1788 case 'D':
1789 return std::string("{di}");
1790 case 'p': // Keep 'p' constraint (address).
1791 return std::string("p");
1792 case 't': // top of floating point stack.
1793 return std::string("{st}");
1794 case 'u': // second from top of floating point stack.
1795 return std::string("{st(1)}"); // second from top of floating point stack.
1796 case 'W':
1797 assert(Constraint[1] == 's');
1798 return '^' + std::string(Constraint++, 2);
1799 case 'Y':
1800 switch (Constraint[1]) {
1801 default:
1802 // Break from inner switch and fall through (copy single char),
1803 // continue parsing after copying the current constraint into
1804 // the return string.
1805 break;
1806 case 'k':
1807 case 'm':
1808 case 'i':
1809 case 't':
1810 case 'z':
1811 case '2':
1812 // "^" hints llvm that this is a 2 letter constraint.
1813 // "Constraint++" is used to promote the string iterator
1814 // to the next constraint.
1815 return std::string("^") + std::string(Constraint++, 2);
1816 }
1817 [[fallthrough]];
1818 case 'j':
1819 switch (Constraint[1]) {
1820 default:
1821 // Break from inner switch and fall through (copy single char),
1822 // continue parsing after copying the current constraint into
1823 // the return string.
1824 break;
1825 case 'r':
1826 case 'R':
1827 // "^" hints llvm that this is a 2 letter constraint.
1828 // "Constraint++" is used to promote the string iterator
1829 // to the next constraint.
1830 return std::string("^") + std::string(Constraint++, 2);
1831 }
1832 [[fallthrough]];
1833 default:
1834 return std::string(1, *Constraint);
1835 }
1836}
1837
1838void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1839 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1840 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1841}
1842
1843void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1844 llvm::X86::fillValidTuneCPUList(Values);
1845}
1846
1850
1854
1855llvm::SmallVector<Builtin::InfosShard>
1856X86_32TargetInfo::getTargetBuiltins() const {
1857 return {
1858 {&X86::BuiltinStrings, X86::BuiltinInfos},
1859 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1860 };
1861}
1862
1863llvm::SmallVector<Builtin::InfosShard>
1864X86_64TargetInfo::getTargetBuiltins() const {
1865 return {
1866 {&X86::BuiltinStrings, X86::BuiltinInfos},
1867 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1868 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1869 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1870 "__builtin_ia32_"},
1871 };
1872}
1873
1874unsigned
1875MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1876 bool HasNonWeakDef) const {
1877 unsigned Align =
1878 WindowsX86_64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1879
1880 return std::max(Align, Microsoft64BitMinGlobalAlign(TypeSize));
1881}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1593
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:235
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1339
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:39
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:61
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:234
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1581
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:472
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:327
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1323
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1450
clang::TargetInfo::getMinGlobalAlign
virtual unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition TargetInfo.h:760
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:568
clang::targets::MicrosoftX86_64TargetInfo::getMinGlobalAlign
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
getMinGlobalAlign - Return the minimum alignment of a global variable, unless its alignment is explic...
Definition X86.cpp:1875
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:233
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1572
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1437
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1350
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1847
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1376
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1769
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:510
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1380
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1392
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1696
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1711
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1843
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1372
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1331
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1078
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1200
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:214
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:187
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1838
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1851
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1705
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1856
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1864
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Microsoft64BitMinGlobalAlign
unsigned Microsoft64BitMinGlobalAlign(uint64_t TypeSize)
Definition TargetInfo.cpp:1121
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:80
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1234
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1198
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:144
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