clang  9.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/TargetBuiltins.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
25 const Builtin::Info BuiltinInfoX86[] = {
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65 };
66 
67 const TargetInfo::AddlRegName AddlRegNames[] = {
68  {{"al", "ah", "eax", "rax"}, 0},
69  {{"bl", "bh", "ebx", "rbx"}, 3},
70  {{"cl", "ch", "ecx", "rcx"}, 2},
71  {{"dl", "dh", "edx", "rdx"}, 1},
72  {{"esi", "rsi"}, 4},
73  {{"edi", "rdi"}, 5},
74  {{"esp", "rsp"}, 7},
75  {{"ebp", "rbp"}, 6},
76  {{"r8d", "r8w", "r8b"}, 38},
77  {{"r9d", "r9w", "r9b"}, 39},
78  {{"r10d", "r10w", "r10b"}, 40},
79  {{"r11d", "r11w", "r11b"}, 41},
80  {{"r12d", "r12w", "r12b"}, 42},
81  {{"r13d", "r13w", "r13b"}, 43},
82  {{"r14d", "r14w", "r14b"}, 44},
83  {{"r15d", "r15w", "r15b"}, 45},
84 };
85 
86 } // namespace targets
87 } // namespace clang
88 
89 using namespace clang;
90 using namespace clang::targets;
91 
92 bool X86TargetInfo::setFPMath(StringRef Name) {
93  if (Name == "387") {
94  FPMath = FP_387;
95  return true;
96  }
97  if (Name == "sse") {
98  FPMath = FP_SSE;
99  return true;
100  }
101  return false;
102 }
103 
104 bool X86TargetInfo::initFeatureMap(
105  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106  const std::vector<std::string> &FeaturesVec) const {
107  // FIXME: This *really* should not be here.
108  // X86_64 always has SSE2.
109  if (getTriple().getArch() == llvm::Triple::x86_64)
110  setFeatureEnabledImpl(Features, "sse2", true);
111 
112  const CPUKind Kind = getCPUKind(CPU);
113 
114  // Enable X87 for all X86 processors but Lakemont.
115  if (Kind != CK_Lakemont)
116  setFeatureEnabledImpl(Features, "x87", true);
117 
118  switch (Kind) {
119  case CK_Generic:
120  case CK_i386:
121  case CK_i486:
122  case CK_i586:
123  case CK_Pentium:
124  case CK_PentiumPro:
125  case CK_Lakemont:
126  break;
127 
128  case CK_PentiumMMX:
129  case CK_Pentium2:
130  case CK_K6:
131  case CK_WinChipC6:
132  setFeatureEnabledImpl(Features, "mmx", true);
133  break;
134 
135  case CK_IcelakeServer:
136  setFeatureEnabledImpl(Features, "pconfig", true);
137  setFeatureEnabledImpl(Features, "wbnoinvd", true);
138  LLVM_FALLTHROUGH;
139  case CK_IcelakeClient:
140  setFeatureEnabledImpl(Features, "vaes", true);
141  setFeatureEnabledImpl(Features, "gfni", true);
142  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
143  setFeatureEnabledImpl(Features, "avx512bitalg", true);
144  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
145  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
146  setFeatureEnabledImpl(Features, "rdpid", true);
147  LLVM_FALLTHROUGH;
148  case CK_Cannonlake:
149  setFeatureEnabledImpl(Features, "avx512ifma", true);
150  setFeatureEnabledImpl(Features, "avx512vbmi", true);
151  setFeatureEnabledImpl(Features, "sha", true);
152  LLVM_FALLTHROUGH;
153  case CK_Cascadelake:
154  //Cannonlake has no VNNI feature inside while Icelake has
155  if (Kind != CK_Cannonlake)
156  // CLK inherits all SKX features plus AVX512_VNNI
157  setFeatureEnabledImpl(Features, "avx512vnni", true);
158  LLVM_FALLTHROUGH;
159  case CK_SkylakeServer:
160  setFeatureEnabledImpl(Features, "avx512f", true);
161  setFeatureEnabledImpl(Features, "avx512cd", true);
162  setFeatureEnabledImpl(Features, "avx512dq", true);
163  setFeatureEnabledImpl(Features, "avx512bw", true);
164  setFeatureEnabledImpl(Features, "avx512vl", true);
165  setFeatureEnabledImpl(Features, "pku", true);
166  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
167  setFeatureEnabledImpl(Features, "clwb", true);
168  LLVM_FALLTHROUGH;
169  case CK_SkylakeClient:
170  setFeatureEnabledImpl(Features, "xsavec", true);
171  setFeatureEnabledImpl(Features, "xsaves", true);
172  setFeatureEnabledImpl(Features, "mpx", true);
173  if (Kind != CK_SkylakeServer
174  && Kind != CK_Cascadelake)
175  // SKX/CLX inherits all SKL features, except SGX
176  setFeatureEnabledImpl(Features, "sgx", true);
177  setFeatureEnabledImpl(Features, "clflushopt", true);
178  setFeatureEnabledImpl(Features, "aes", true);
179  LLVM_FALLTHROUGH;
180  case CK_Broadwell:
181  setFeatureEnabledImpl(Features, "rdseed", true);
182  setFeatureEnabledImpl(Features, "adx", true);
183  setFeatureEnabledImpl(Features, "prfchw", true);
184  LLVM_FALLTHROUGH;
185  case CK_Haswell:
186  setFeatureEnabledImpl(Features, "avx2", true);
187  setFeatureEnabledImpl(Features, "lzcnt", true);
188  setFeatureEnabledImpl(Features, "bmi", true);
189  setFeatureEnabledImpl(Features, "bmi2", true);
190  setFeatureEnabledImpl(Features, "fma", true);
191  setFeatureEnabledImpl(Features, "invpcid", true);
192  setFeatureEnabledImpl(Features, "movbe", true);
193  LLVM_FALLTHROUGH;
194  case CK_IvyBridge:
195  setFeatureEnabledImpl(Features, "rdrnd", true);
196  setFeatureEnabledImpl(Features, "f16c", true);
197  setFeatureEnabledImpl(Features, "fsgsbase", true);
198  LLVM_FALLTHROUGH;
199  case CK_SandyBridge:
200  setFeatureEnabledImpl(Features, "avx", true);
201  setFeatureEnabledImpl(Features, "xsave", true);
202  setFeatureEnabledImpl(Features, "xsaveopt", true);
203  LLVM_FALLTHROUGH;
204  case CK_Westmere:
205  setFeatureEnabledImpl(Features, "pclmul", true);
206  LLVM_FALLTHROUGH;
207  case CK_Nehalem:
208  setFeatureEnabledImpl(Features, "sse4.2", true);
209  LLVM_FALLTHROUGH;
210  case CK_Penryn:
211  setFeatureEnabledImpl(Features, "sse4.1", true);
212  LLVM_FALLTHROUGH;
213  case CK_Core2:
214  setFeatureEnabledImpl(Features, "ssse3", true);
215  setFeatureEnabledImpl(Features, "sahf", true);
216  LLVM_FALLTHROUGH;
217  case CK_Yonah:
218  case CK_Prescott:
219  case CK_Nocona:
220  setFeatureEnabledImpl(Features, "sse3", true);
221  setFeatureEnabledImpl(Features, "cx16", true);
222  LLVM_FALLTHROUGH;
223  case CK_PentiumM:
224  case CK_Pentium4:
225  case CK_x86_64:
226  setFeatureEnabledImpl(Features, "sse2", true);
227  LLVM_FALLTHROUGH;
228  case CK_Pentium3:
229  case CK_C3_2:
230  setFeatureEnabledImpl(Features, "sse", true);
231  setFeatureEnabledImpl(Features, "fxsr", true);
232  break;
233 
234  case CK_Tremont:
235  setFeatureEnabledImpl(Features, "cldemote", true);
236  setFeatureEnabledImpl(Features, "movdiri", true);
237  setFeatureEnabledImpl(Features, "movdir64b", true);
238  setFeatureEnabledImpl(Features, "gfni", true);
239  setFeatureEnabledImpl(Features, "waitpkg", true);
240  LLVM_FALLTHROUGH;
241  case CK_GoldmontPlus:
242  setFeatureEnabledImpl(Features, "ptwrite", true);
243  setFeatureEnabledImpl(Features, "rdpid", true);
244  setFeatureEnabledImpl(Features, "sgx", true);
245  LLVM_FALLTHROUGH;
246  case CK_Goldmont:
247  setFeatureEnabledImpl(Features, "sha", true);
248  setFeatureEnabledImpl(Features, "rdseed", true);
249  setFeatureEnabledImpl(Features, "xsave", true);
250  setFeatureEnabledImpl(Features, "xsaveopt", true);
251  setFeatureEnabledImpl(Features, "xsavec", true);
252  setFeatureEnabledImpl(Features, "xsaves", true);
253  setFeatureEnabledImpl(Features, "clflushopt", true);
254  setFeatureEnabledImpl(Features, "mpx", true);
255  setFeatureEnabledImpl(Features, "fsgsbase", true);
256  setFeatureEnabledImpl(Features, "aes", true);
257  LLVM_FALLTHROUGH;
258  case CK_Silvermont:
259  setFeatureEnabledImpl(Features, "rdrnd", true);
260  setFeatureEnabledImpl(Features, "pclmul", true);
261  setFeatureEnabledImpl(Features, "sse4.2", true);
262  setFeatureEnabledImpl(Features, "prfchw", true);
263  LLVM_FALLTHROUGH;
264  case CK_Bonnell:
265  setFeatureEnabledImpl(Features, "movbe", true);
266  setFeatureEnabledImpl(Features, "ssse3", true);
267  setFeatureEnabledImpl(Features, "fxsr", true);
268  setFeatureEnabledImpl(Features, "cx16", true);
269  setFeatureEnabledImpl(Features, "sahf", true);
270  break;
271 
272  case CK_KNM:
273  // TODO: Add avx5124fmaps/avx5124vnniw.
274  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
275  LLVM_FALLTHROUGH;
276  case CK_KNL:
277  setFeatureEnabledImpl(Features, "avx512f", true);
278  setFeatureEnabledImpl(Features, "avx512cd", true);
279  setFeatureEnabledImpl(Features, "avx512er", true);
280  setFeatureEnabledImpl(Features, "avx512pf", true);
281  setFeatureEnabledImpl(Features, "prfchw", true);
282  setFeatureEnabledImpl(Features, "prefetchwt1", true);
283  setFeatureEnabledImpl(Features, "fxsr", true);
284  setFeatureEnabledImpl(Features, "rdseed", true);
285  setFeatureEnabledImpl(Features, "adx", true);
286  setFeatureEnabledImpl(Features, "lzcnt", true);
287  setFeatureEnabledImpl(Features, "bmi", true);
288  setFeatureEnabledImpl(Features, "bmi2", true);
289  setFeatureEnabledImpl(Features, "fma", true);
290  setFeatureEnabledImpl(Features, "rdrnd", true);
291  setFeatureEnabledImpl(Features, "f16c", true);
292  setFeatureEnabledImpl(Features, "fsgsbase", true);
293  setFeatureEnabledImpl(Features, "aes", true);
294  setFeatureEnabledImpl(Features, "pclmul", true);
295  setFeatureEnabledImpl(Features, "cx16", true);
296  setFeatureEnabledImpl(Features, "xsaveopt", true);
297  setFeatureEnabledImpl(Features, "xsave", true);
298  setFeatureEnabledImpl(Features, "movbe", true);
299  setFeatureEnabledImpl(Features, "sahf", true);
300  break;
301 
302  case CK_K6_2:
303  case CK_K6_3:
304  case CK_WinChip2:
305  case CK_C3:
306  setFeatureEnabledImpl(Features, "3dnow", true);
307  break;
308 
309  case CK_AMDFAM10:
310  setFeatureEnabledImpl(Features, "sse4a", true);
311  setFeatureEnabledImpl(Features, "lzcnt", true);
312  setFeatureEnabledImpl(Features, "popcnt", true);
313  setFeatureEnabledImpl(Features, "sahf", true);
314  LLVM_FALLTHROUGH;
315  case CK_K8SSE3:
316  setFeatureEnabledImpl(Features, "sse3", true);
317  LLVM_FALLTHROUGH;
318  case CK_K8:
319  setFeatureEnabledImpl(Features, "sse2", true);
320  LLVM_FALLTHROUGH;
321  case CK_AthlonXP:
322  setFeatureEnabledImpl(Features, "sse", true);
323  setFeatureEnabledImpl(Features, "fxsr", true);
324  LLVM_FALLTHROUGH;
325  case CK_Athlon:
326  case CK_Geode:
327  setFeatureEnabledImpl(Features, "3dnowa", true);
328  break;
329 
330  case CK_BTVER2:
331  setFeatureEnabledImpl(Features, "avx", true);
332  setFeatureEnabledImpl(Features, "aes", true);
333  setFeatureEnabledImpl(Features, "pclmul", true);
334  setFeatureEnabledImpl(Features, "bmi", true);
335  setFeatureEnabledImpl(Features, "f16c", true);
336  setFeatureEnabledImpl(Features, "xsaveopt", true);
337  setFeatureEnabledImpl(Features, "movbe", true);
338  LLVM_FALLTHROUGH;
339  case CK_BTVER1:
340  setFeatureEnabledImpl(Features, "ssse3", true);
341  setFeatureEnabledImpl(Features, "sse4a", true);
342  setFeatureEnabledImpl(Features, "lzcnt", true);
343  setFeatureEnabledImpl(Features, "popcnt", true);
344  setFeatureEnabledImpl(Features, "prfchw", true);
345  setFeatureEnabledImpl(Features, "cx16", true);
346  setFeatureEnabledImpl(Features, "fxsr", true);
347  setFeatureEnabledImpl(Features, "sahf", true);
348  break;
349 
350  case CK_ZNVER1:
351  setFeatureEnabledImpl(Features, "adx", true);
352  setFeatureEnabledImpl(Features, "aes", true);
353  setFeatureEnabledImpl(Features, "avx2", true);
354  setFeatureEnabledImpl(Features, "bmi", true);
355  setFeatureEnabledImpl(Features, "bmi2", true);
356  setFeatureEnabledImpl(Features, "clflushopt", true);
357  setFeatureEnabledImpl(Features, "clzero", true);
358  setFeatureEnabledImpl(Features, "cx16", true);
359  setFeatureEnabledImpl(Features, "f16c", true);
360  setFeatureEnabledImpl(Features, "fma", true);
361  setFeatureEnabledImpl(Features, "fsgsbase", true);
362  setFeatureEnabledImpl(Features, "fxsr", true);
363  setFeatureEnabledImpl(Features, "lzcnt", true);
364  setFeatureEnabledImpl(Features, "mwaitx", true);
365  setFeatureEnabledImpl(Features, "movbe", true);
366  setFeatureEnabledImpl(Features, "pclmul", true);
367  setFeatureEnabledImpl(Features, "popcnt", true);
368  setFeatureEnabledImpl(Features, "prfchw", true);
369  setFeatureEnabledImpl(Features, "rdrnd", true);
370  setFeatureEnabledImpl(Features, "rdseed", true);
371  setFeatureEnabledImpl(Features, "sahf", true);
372  setFeatureEnabledImpl(Features, "sha", true);
373  setFeatureEnabledImpl(Features, "sse4a", true);
374  setFeatureEnabledImpl(Features, "xsave", true);
375  setFeatureEnabledImpl(Features, "xsavec", true);
376  setFeatureEnabledImpl(Features, "xsaveopt", true);
377  setFeatureEnabledImpl(Features, "xsaves", true);
378  break;
379 
380  case CK_BDVER4:
381  setFeatureEnabledImpl(Features, "avx2", true);
382  setFeatureEnabledImpl(Features, "bmi2", true);
383  setFeatureEnabledImpl(Features, "mwaitx", true);
384  LLVM_FALLTHROUGH;
385  case CK_BDVER3:
386  setFeatureEnabledImpl(Features, "fsgsbase", true);
387  setFeatureEnabledImpl(Features, "xsaveopt", true);
388  LLVM_FALLTHROUGH;
389  case CK_BDVER2:
390  setFeatureEnabledImpl(Features, "bmi", true);
391  setFeatureEnabledImpl(Features, "fma", true);
392  setFeatureEnabledImpl(Features, "f16c", true);
393  setFeatureEnabledImpl(Features, "tbm", true);
394  LLVM_FALLTHROUGH;
395  case CK_BDVER1:
396  // xop implies avx, sse4a and fma4.
397  setFeatureEnabledImpl(Features, "xop", true);
398  setFeatureEnabledImpl(Features, "lwp", true);
399  setFeatureEnabledImpl(Features, "lzcnt", true);
400  setFeatureEnabledImpl(Features, "aes", true);
401  setFeatureEnabledImpl(Features, "pclmul", true);
402  setFeatureEnabledImpl(Features, "prfchw", true);
403  setFeatureEnabledImpl(Features, "cx16", true);
404  setFeatureEnabledImpl(Features, "fxsr", true);
405  setFeatureEnabledImpl(Features, "xsave", true);
406  setFeatureEnabledImpl(Features, "sahf", true);
407  break;
408  }
409  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
410  return false;
411 
412  // Can't do this earlier because we need to be able to explicitly enable
413  // or disable these features and the things that they depend upon.
414 
415  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
416  auto I = Features.find("sse4.2");
417  if (I != Features.end() && I->getValue() &&
418  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
419  FeaturesVec.end())
420  Features["popcnt"] = true;
421 
422  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
423  I = Features.find("3dnow");
424  if (I != Features.end() && I->getValue() &&
425  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
426  FeaturesVec.end())
427  Features["prfchw"] = true;
428 
429  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
430  // then enable MMX.
431  I = Features.find("sse");
432  if (I != Features.end() && I->getValue() &&
433  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
434  FeaturesVec.end())
435  Features["mmx"] = true;
436 
437  return true;
438 }
439 
440 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
441  X86SSEEnum Level, bool Enabled) {
442  if (Enabled) {
443  switch (Level) {
444  case AVX512F:
445  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
446  LLVM_FALLTHROUGH;
447  case AVX2:
448  Features["avx2"] = true;
449  LLVM_FALLTHROUGH;
450  case AVX:
451  Features["avx"] = true;
452  Features["xsave"] = true;
453  LLVM_FALLTHROUGH;
454  case SSE42:
455  Features["sse4.2"] = true;
456  LLVM_FALLTHROUGH;
457  case SSE41:
458  Features["sse4.1"] = true;
459  LLVM_FALLTHROUGH;
460  case SSSE3:
461  Features["ssse3"] = true;
462  LLVM_FALLTHROUGH;
463  case SSE3:
464  Features["sse3"] = true;
465  LLVM_FALLTHROUGH;
466  case SSE2:
467  Features["sse2"] = true;
468  LLVM_FALLTHROUGH;
469  case SSE1:
470  Features["sse"] = true;
471  LLVM_FALLTHROUGH;
472  case NoSSE:
473  break;
474  }
475  return;
476  }
477 
478  switch (Level) {
479  case NoSSE:
480  case SSE1:
481  Features["sse"] = false;
482  LLVM_FALLTHROUGH;
483  case SSE2:
484  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
485  Features["gfni"] = false;
486  LLVM_FALLTHROUGH;
487  case SSE3:
488  Features["sse3"] = false;
489  setXOPLevel(Features, NoXOP, false);
490  LLVM_FALLTHROUGH;
491  case SSSE3:
492  Features["ssse3"] = false;
493  LLVM_FALLTHROUGH;
494  case SSE41:
495  Features["sse4.1"] = false;
496  LLVM_FALLTHROUGH;
497  case SSE42:
498  Features["sse4.2"] = false;
499  LLVM_FALLTHROUGH;
500  case AVX:
501  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
502  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
503  setXOPLevel(Features, FMA4, false);
504  LLVM_FALLTHROUGH;
505  case AVX2:
506  Features["avx2"] = false;
507  LLVM_FALLTHROUGH;
508  case AVX512F:
509  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
510  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
511  Features["avx512vl"] = Features["avx512vbmi"] =
512  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
513  Features["avx512bitalg"] = Features["avx512vnni"] =
514  Features["avx512vbmi2"] = false;
515  break;
516  }
517 }
518 
519 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
520  MMX3DNowEnum Level, bool Enabled) {
521  if (Enabled) {
522  switch (Level) {
523  case AMD3DNowAthlon:
524  Features["3dnowa"] = true;
525  LLVM_FALLTHROUGH;
526  case AMD3DNow:
527  Features["3dnow"] = true;
528  LLVM_FALLTHROUGH;
529  case MMX:
530  Features["mmx"] = true;
531  LLVM_FALLTHROUGH;
532  case NoMMX3DNow:
533  break;
534  }
535  return;
536  }
537 
538  switch (Level) {
539  case NoMMX3DNow:
540  case MMX:
541  Features["mmx"] = false;
542  LLVM_FALLTHROUGH;
543  case AMD3DNow:
544  Features["3dnow"] = false;
545  LLVM_FALLTHROUGH;
546  case AMD3DNowAthlon:
547  Features["3dnowa"] = false;
548  break;
549  }
550 }
551 
552 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
553  bool Enabled) {
554  if (Enabled) {
555  switch (Level) {
556  case XOP:
557  Features["xop"] = true;
558  LLVM_FALLTHROUGH;
559  case FMA4:
560  Features["fma4"] = true;
561  setSSELevel(Features, AVX, true);
562  LLVM_FALLTHROUGH;
563  case SSE4A:
564  Features["sse4a"] = true;
565  setSSELevel(Features, SSE3, true);
566  LLVM_FALLTHROUGH;
567  case NoXOP:
568  break;
569  }
570  return;
571  }
572 
573  switch (Level) {
574  case NoXOP:
575  case SSE4A:
576  Features["sse4a"] = false;
577  LLVM_FALLTHROUGH;
578  case FMA4:
579  Features["fma4"] = false;
580  LLVM_FALLTHROUGH;
581  case XOP:
582  Features["xop"] = false;
583  break;
584  }
585 }
586 
587 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
588  StringRef Name, bool Enabled) {
589  // This is a bit of a hack to deal with the sse4 target feature when used
590  // as part of the target attribute. We handle sse4 correctly everywhere
591  // else. See below for more information on how we handle the sse4 options.
592  if (Name != "sse4")
593  Features[Name] = Enabled;
594 
595  if (Name == "mmx") {
596  setMMXLevel(Features, MMX, Enabled);
597  } else if (Name == "sse") {
598  setSSELevel(Features, SSE1, Enabled);
599  } else if (Name == "sse2") {
600  setSSELevel(Features, SSE2, Enabled);
601  } else if (Name == "sse3") {
602  setSSELevel(Features, SSE3, Enabled);
603  } else if (Name == "ssse3") {
604  setSSELevel(Features, SSSE3, Enabled);
605  } else if (Name == "sse4.2") {
606  setSSELevel(Features, SSE42, Enabled);
607  } else if (Name == "sse4.1") {
608  setSSELevel(Features, SSE41, Enabled);
609  } else if (Name == "3dnow") {
610  setMMXLevel(Features, AMD3DNow, Enabled);
611  } else if (Name == "3dnowa") {
612  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
613  } else if (Name == "aes") {
614  if (Enabled)
615  setSSELevel(Features, SSE2, Enabled);
616  else
617  Features["vaes"] = false;
618  } else if (Name == "vaes") {
619  if (Enabled) {
620  setSSELevel(Features, AVX, Enabled);
621  Features["aes"] = true;
622  }
623  } else if (Name == "pclmul") {
624  if (Enabled)
625  setSSELevel(Features, SSE2, Enabled);
626  else
627  Features["vpclmulqdq"] = false;
628  } else if (Name == "vpclmulqdq") {
629  if (Enabled) {
630  setSSELevel(Features, AVX, Enabled);
631  Features["pclmul"] = true;
632  }
633  } else if (Name == "gfni") {
634  if (Enabled)
635  setSSELevel(Features, SSE2, Enabled);
636  } else if (Name == "avx") {
637  setSSELevel(Features, AVX, Enabled);
638  } else if (Name == "avx2") {
639  setSSELevel(Features, AVX2, Enabled);
640  } else if (Name == "avx512f") {
641  setSSELevel(Features, AVX512F, Enabled);
642  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
643  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
644  Name == "avx512vbmi" || Name == "avx512ifma" ||
645  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
646  Name == "avx512vnni" || Name == "avx512vbmi2") {
647  if (Enabled)
648  setSSELevel(Features, AVX512F, Enabled);
649  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
650  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
651  Features["avx512bw"] = true;
652  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
653  if (Name == "avx512bw" && !Enabled)
654  Features["avx512vbmi"] = Features["avx512vbmi2"] =
655  Features["avx512bitalg"] = false;
656  } else if (Name == "fma") {
657  if (Enabled)
658  setSSELevel(Features, AVX, Enabled);
659  else
660  setSSELevel(Features, AVX512F, Enabled);
661  } else if (Name == "fma4") {
662  setXOPLevel(Features, FMA4, Enabled);
663  } else if (Name == "xop") {
664  setXOPLevel(Features, XOP, Enabled);
665  } else if (Name == "sse4a") {
666  setXOPLevel(Features, SSE4A, Enabled);
667  } else if (Name == "f16c") {
668  if (Enabled)
669  setSSELevel(Features, AVX, Enabled);
670  else
671  setSSELevel(Features, AVX512F, Enabled);
672  } else if (Name == "sha") {
673  if (Enabled)
674  setSSELevel(Features, SSE2, Enabled);
675  } else if (Name == "sse4") {
676  // We can get here via the __target__ attribute since that's not controlled
677  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
678  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
679  // disabled.
680  if (Enabled)
681  setSSELevel(Features, SSE42, Enabled);
682  else
683  setSSELevel(Features, SSE41, Enabled);
684  } else if (Name == "xsave") {
685  if (!Enabled)
686  Features["xsaveopt"] = false;
687  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
688  if (Enabled)
689  Features["xsave"] = true;
690  }
691 }
692 
693 /// handleTargetFeatures - Perform initialization based on the user
694 /// configured set of features.
695 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
696  DiagnosticsEngine &Diags) {
697  for (const auto &Feature : Features) {
698  if (Feature[0] != '+')
699  continue;
700 
701  if (Feature == "+aes") {
702  HasAES = true;
703  } else if (Feature == "+vaes") {
704  HasVAES = true;
705  } else if (Feature == "+pclmul") {
706  HasPCLMUL = true;
707  } else if (Feature == "+vpclmulqdq") {
708  HasVPCLMULQDQ = true;
709  } else if (Feature == "+lzcnt") {
710  HasLZCNT = true;
711  } else if (Feature == "+rdrnd") {
712  HasRDRND = true;
713  } else if (Feature == "+fsgsbase") {
714  HasFSGSBASE = true;
715  } else if (Feature == "+bmi") {
716  HasBMI = true;
717  } else if (Feature == "+bmi2") {
718  HasBMI2 = true;
719  } else if (Feature == "+popcnt") {
720  HasPOPCNT = true;
721  } else if (Feature == "+rtm") {
722  HasRTM = true;
723  } else if (Feature == "+prfchw") {
724  HasPRFCHW = true;
725  } else if (Feature == "+rdseed") {
726  HasRDSEED = true;
727  } else if (Feature == "+adx") {
728  HasADX = true;
729  } else if (Feature == "+tbm") {
730  HasTBM = true;
731  } else if (Feature == "+lwp") {
732  HasLWP = true;
733  } else if (Feature == "+fma") {
734  HasFMA = true;
735  } else if (Feature == "+f16c") {
736  HasF16C = true;
737  } else if (Feature == "+gfni") {
738  HasGFNI = true;
739  } else if (Feature == "+avx512cd") {
740  HasAVX512CD = true;
741  } else if (Feature == "+avx512vpopcntdq") {
742  HasAVX512VPOPCNTDQ = true;
743  } else if (Feature == "+avx512vnni") {
744  HasAVX512VNNI = true;
745  } else if (Feature == "+avx512er") {
746  HasAVX512ER = true;
747  } else if (Feature == "+avx512pf") {
748  HasAVX512PF = true;
749  } else if (Feature == "+avx512dq") {
750  HasAVX512DQ = true;
751  } else if (Feature == "+avx512bitalg") {
752  HasAVX512BITALG = true;
753  } else if (Feature == "+avx512bw") {
754  HasAVX512BW = true;
755  } else if (Feature == "+avx512vl") {
756  HasAVX512VL = true;
757  } else if (Feature == "+avx512vbmi") {
758  HasAVX512VBMI = true;
759  } else if (Feature == "+avx512vbmi2") {
760  HasAVX512VBMI2 = true;
761  } else if (Feature == "+avx512ifma") {
762  HasAVX512IFMA = true;
763  } else if (Feature == "+sha") {
764  HasSHA = true;
765  } else if (Feature == "+mpx") {
766  HasMPX = true;
767  } else if (Feature == "+shstk") {
768  HasSHSTK = true;
769  } else if (Feature == "+movbe") {
770  HasMOVBE = true;
771  } else if (Feature == "+sgx") {
772  HasSGX = true;
773  } else if (Feature == "+cx16") {
774  HasCX16 = true;
775  } else if (Feature == "+fxsr") {
776  HasFXSR = true;
777  } else if (Feature == "+xsave") {
778  HasXSAVE = true;
779  } else if (Feature == "+xsaveopt") {
780  HasXSAVEOPT = true;
781  } else if (Feature == "+xsavec") {
782  HasXSAVEC = true;
783  } else if (Feature == "+xsaves") {
784  HasXSAVES = true;
785  } else if (Feature == "+mwaitx") {
786  HasMWAITX = true;
787  } else if (Feature == "+pku") {
788  HasPKU = true;
789  } else if (Feature == "+clflushopt") {
790  HasCLFLUSHOPT = true;
791  } else if (Feature == "+clwb") {
792  HasCLWB = true;
793  } else if (Feature == "+wbnoinvd") {
794  HasWBNOINVD = true;
795  } else if (Feature == "+prefetchwt1") {
796  HasPREFETCHWT1 = true;
797  } else if (Feature == "+clzero") {
798  HasCLZERO = true;
799  } else if (Feature == "+cldemote") {
800  HasCLDEMOTE = true;
801  } else if (Feature == "+rdpid") {
802  HasRDPID = true;
803  } else if (Feature == "+retpoline-external-thunk") {
804  HasRetpolineExternalThunk = true;
805  } else if (Feature == "+sahf") {
806  HasLAHFSAHF = true;
807  } else if (Feature == "+waitpkg") {
808  HasWAITPKG = true;
809  } else if (Feature == "+movdiri") {
810  HasMOVDIRI = true;
811  } else if (Feature == "+movdir64b") {
812  HasMOVDIR64B = true;
813  } else if (Feature == "+pconfig") {
814  HasPCONFIG = true;
815  } else if (Feature == "+ptwrite") {
816  HasPTWRITE = true;
817  } else if (Feature == "+invpcid") {
818  HasINVPCID = true;
819  }
820 
821  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
822  .Case("+avx512f", AVX512F)
823  .Case("+avx2", AVX2)
824  .Case("+avx", AVX)
825  .Case("+sse4.2", SSE42)
826  .Case("+sse4.1", SSE41)
827  .Case("+ssse3", SSSE3)
828  .Case("+sse3", SSE3)
829  .Case("+sse2", SSE2)
830  .Case("+sse", SSE1)
831  .Default(NoSSE);
832  SSELevel = std::max(SSELevel, Level);
833 
834  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
835  .Case("+3dnowa", AMD3DNowAthlon)
836  .Case("+3dnow", AMD3DNow)
837  .Case("+mmx", MMX)
838  .Default(NoMMX3DNow);
839  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
840 
841  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
842  .Case("+xop", XOP)
843  .Case("+fma4", FMA4)
844  .Case("+sse4a", SSE4A)
845  .Default(NoXOP);
846  XOPLevel = std::max(XOPLevel, XLevel);
847  }
848 
849  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
850  // matches the selected sse level.
851  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
852  (FPMath == FP_387 && SSELevel >= SSE1)) {
853  Diags.Report(diag::err_target_unsupported_fpmath)
854  << (FPMath == FP_SSE ? "sse" : "387");
855  return false;
856  }
857 
858  SimdDefaultAlign =
859  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
860  return true;
861 }
862 
863 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
864 /// definitions for this particular subtarget.
865 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
866  MacroBuilder &Builder) const {
867  std::string CodeModel = getTargetOpts().CodeModel;
868  if (CodeModel == "default")
869  CodeModel = "small";
870  Builder.defineMacro("__code_model_" + CodeModel + "_");
871 
872  // Target identification.
873  if (getTriple().getArch() == llvm::Triple::x86_64) {
874  Builder.defineMacro("__amd64__");
875  Builder.defineMacro("__amd64");
876  Builder.defineMacro("__x86_64");
877  Builder.defineMacro("__x86_64__");
878  if (getTriple().getArchName() == "x86_64h") {
879  Builder.defineMacro("__x86_64h");
880  Builder.defineMacro("__x86_64h__");
881  }
882  } else {
883  DefineStd(Builder, "i386", Opts);
884  }
885 
886  // Subtarget options.
887  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
888  // truly should be based on -mtune options.
889  switch (CPU) {
890  case CK_Generic:
891  break;
892  case CK_i386:
893  // The rest are coming from the i386 define above.
894  Builder.defineMacro("__tune_i386__");
895  break;
896  case CK_i486:
897  case CK_WinChipC6:
898  case CK_WinChip2:
899  case CK_C3:
900  defineCPUMacros(Builder, "i486");
901  break;
902  case CK_PentiumMMX:
903  Builder.defineMacro("__pentium_mmx__");
904  Builder.defineMacro("__tune_pentium_mmx__");
905  LLVM_FALLTHROUGH;
906  case CK_i586:
907  case CK_Pentium:
908  defineCPUMacros(Builder, "i586");
909  defineCPUMacros(Builder, "pentium");
910  break;
911  case CK_Pentium3:
912  case CK_PentiumM:
913  Builder.defineMacro("__tune_pentium3__");
914  LLVM_FALLTHROUGH;
915  case CK_Pentium2:
916  case CK_C3_2:
917  Builder.defineMacro("__tune_pentium2__");
918  LLVM_FALLTHROUGH;
919  case CK_PentiumPro:
920  defineCPUMacros(Builder, "i686");
921  defineCPUMacros(Builder, "pentiumpro");
922  break;
923  case CK_Pentium4:
924  defineCPUMacros(Builder, "pentium4");
925  break;
926  case CK_Yonah:
927  case CK_Prescott:
928  case CK_Nocona:
929  defineCPUMacros(Builder, "nocona");
930  break;
931  case CK_Core2:
932  case CK_Penryn:
933  defineCPUMacros(Builder, "core2");
934  break;
935  case CK_Bonnell:
936  defineCPUMacros(Builder, "atom");
937  break;
938  case CK_Silvermont:
939  defineCPUMacros(Builder, "slm");
940  break;
941  case CK_Goldmont:
942  defineCPUMacros(Builder, "goldmont");
943  break;
944  case CK_GoldmontPlus:
945  defineCPUMacros(Builder, "goldmont_plus");
946  break;
947  case CK_Tremont:
948  defineCPUMacros(Builder, "tremont");
949  break;
950  case CK_Nehalem:
951  case CK_Westmere:
952  case CK_SandyBridge:
953  case CK_IvyBridge:
954  case CK_Haswell:
955  case CK_Broadwell:
956  case CK_SkylakeClient:
957  case CK_SkylakeServer:
958  case CK_Cascadelake:
959  case CK_Cannonlake:
960  case CK_IcelakeClient:
961  case CK_IcelakeServer:
962  // FIXME: Historically, we defined this legacy name, it would be nice to
963  // remove it at some point. We've never exposed fine-grained names for
964  // recent primary x86 CPUs, and we should keep it that way.
965  defineCPUMacros(Builder, "corei7");
966  break;
967  case CK_KNL:
968  defineCPUMacros(Builder, "knl");
969  break;
970  case CK_KNM:
971  break;
972  case CK_Lakemont:
973  defineCPUMacros(Builder, "i586", /*Tuning*/false);
974  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
975  Builder.defineMacro("__tune_lakemont__");
976  break;
977  case CK_K6_2:
978  Builder.defineMacro("__k6_2__");
979  Builder.defineMacro("__tune_k6_2__");
980  LLVM_FALLTHROUGH;
981  case CK_K6_3:
982  if (CPU != CK_K6_2) { // In case of fallthrough
983  // FIXME: GCC may be enabling these in cases where some other k6
984  // architecture is specified but -m3dnow is explicitly provided. The
985  // exact semantics need to be determined and emulated here.
986  Builder.defineMacro("__k6_3__");
987  Builder.defineMacro("__tune_k6_3__");
988  }
989  LLVM_FALLTHROUGH;
990  case CK_K6:
991  defineCPUMacros(Builder, "k6");
992  break;
993  case CK_Athlon:
994  case CK_AthlonXP:
995  defineCPUMacros(Builder, "athlon");
996  if (SSELevel != NoSSE) {
997  Builder.defineMacro("__athlon_sse__");
998  Builder.defineMacro("__tune_athlon_sse__");
999  }
1000  break;
1001  case CK_K8:
1002  case CK_K8SSE3:
1003  case CK_x86_64:
1004  defineCPUMacros(Builder, "k8");
1005  break;
1006  case CK_AMDFAM10:
1007  defineCPUMacros(Builder, "amdfam10");
1008  break;
1009  case CK_BTVER1:
1010  defineCPUMacros(Builder, "btver1");
1011  break;
1012  case CK_BTVER2:
1013  defineCPUMacros(Builder, "btver2");
1014  break;
1015  case CK_BDVER1:
1016  defineCPUMacros(Builder, "bdver1");
1017  break;
1018  case CK_BDVER2:
1019  defineCPUMacros(Builder, "bdver2");
1020  break;
1021  case CK_BDVER3:
1022  defineCPUMacros(Builder, "bdver3");
1023  break;
1024  case CK_BDVER4:
1025  defineCPUMacros(Builder, "bdver4");
1026  break;
1027  case CK_ZNVER1:
1028  defineCPUMacros(Builder, "znver1");
1029  break;
1030  case CK_Geode:
1031  defineCPUMacros(Builder, "geode");
1032  break;
1033  }
1034 
1035  // Target properties.
1036  Builder.defineMacro("__REGISTER_PREFIX__", "");
1037 
1038  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1039  // functions in glibc header files that use FP Stack inline asm which the
1040  // backend can't deal with (PR879).
1041  Builder.defineMacro("__NO_MATH_INLINES");
1042 
1043  if (HasAES)
1044  Builder.defineMacro("__AES__");
1045 
1046  if (HasVAES)
1047  Builder.defineMacro("__VAES__");
1048 
1049  if (HasPCLMUL)
1050  Builder.defineMacro("__PCLMUL__");
1051 
1052  if (HasVPCLMULQDQ)
1053  Builder.defineMacro("__VPCLMULQDQ__");
1054 
1055  if (HasLZCNT)
1056  Builder.defineMacro("__LZCNT__");
1057 
1058  if (HasRDRND)
1059  Builder.defineMacro("__RDRND__");
1060 
1061  if (HasFSGSBASE)
1062  Builder.defineMacro("__FSGSBASE__");
1063 
1064  if (HasBMI)
1065  Builder.defineMacro("__BMI__");
1066 
1067  if (HasBMI2)
1068  Builder.defineMacro("__BMI2__");
1069 
1070  if (HasPOPCNT)
1071  Builder.defineMacro("__POPCNT__");
1072 
1073  if (HasRTM)
1074  Builder.defineMacro("__RTM__");
1075 
1076  if (HasPRFCHW)
1077  Builder.defineMacro("__PRFCHW__");
1078 
1079  if (HasRDSEED)
1080  Builder.defineMacro("__RDSEED__");
1081 
1082  if (HasADX)
1083  Builder.defineMacro("__ADX__");
1084 
1085  if (HasTBM)
1086  Builder.defineMacro("__TBM__");
1087 
1088  if (HasLWP)
1089  Builder.defineMacro("__LWP__");
1090 
1091  if (HasMWAITX)
1092  Builder.defineMacro("__MWAITX__");
1093 
1094  if (HasMOVBE)
1095  Builder.defineMacro("__MOVBE__");
1096 
1097  switch (XOPLevel) {
1098  case XOP:
1099  Builder.defineMacro("__XOP__");
1100  LLVM_FALLTHROUGH;
1101  case FMA4:
1102  Builder.defineMacro("__FMA4__");
1103  LLVM_FALLTHROUGH;
1104  case SSE4A:
1105  Builder.defineMacro("__SSE4A__");
1106  LLVM_FALLTHROUGH;
1107  case NoXOP:
1108  break;
1109  }
1110 
1111  if (HasFMA)
1112  Builder.defineMacro("__FMA__");
1113 
1114  if (HasF16C)
1115  Builder.defineMacro("__F16C__");
1116 
1117  if (HasGFNI)
1118  Builder.defineMacro("__GFNI__");
1119 
1120  if (HasAVX512CD)
1121  Builder.defineMacro("__AVX512CD__");
1122  if (HasAVX512VPOPCNTDQ)
1123  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1124  if (HasAVX512VNNI)
1125  Builder.defineMacro("__AVX512VNNI__");
1126  if (HasAVX512ER)
1127  Builder.defineMacro("__AVX512ER__");
1128  if (HasAVX512PF)
1129  Builder.defineMacro("__AVX512PF__");
1130  if (HasAVX512DQ)
1131  Builder.defineMacro("__AVX512DQ__");
1132  if (HasAVX512BITALG)
1133  Builder.defineMacro("__AVX512BITALG__");
1134  if (HasAVX512BW)
1135  Builder.defineMacro("__AVX512BW__");
1136  if (HasAVX512VL)
1137  Builder.defineMacro("__AVX512VL__");
1138  if (HasAVX512VBMI)
1139  Builder.defineMacro("__AVX512VBMI__");
1140  if (HasAVX512VBMI2)
1141  Builder.defineMacro("__AVX512VBMI2__");
1142  if (HasAVX512IFMA)
1143  Builder.defineMacro("__AVX512IFMA__");
1144 
1145  if (HasSHA)
1146  Builder.defineMacro("__SHA__");
1147 
1148  if (HasFXSR)
1149  Builder.defineMacro("__FXSR__");
1150  if (HasXSAVE)
1151  Builder.defineMacro("__XSAVE__");
1152  if (HasXSAVEOPT)
1153  Builder.defineMacro("__XSAVEOPT__");
1154  if (HasXSAVEC)
1155  Builder.defineMacro("__XSAVEC__");
1156  if (HasXSAVES)
1157  Builder.defineMacro("__XSAVES__");
1158  if (HasPKU)
1159  Builder.defineMacro("__PKU__");
1160  if (HasCLFLUSHOPT)
1161  Builder.defineMacro("__CLFLUSHOPT__");
1162  if (HasCLWB)
1163  Builder.defineMacro("__CLWB__");
1164  if (HasWBNOINVD)
1165  Builder.defineMacro("__WBNOINVD__");
1166  if (HasMPX)
1167  Builder.defineMacro("__MPX__");
1168  if (HasSHSTK)
1169  Builder.defineMacro("__SHSTK__");
1170  if (HasSGX)
1171  Builder.defineMacro("__SGX__");
1172  if (HasPREFETCHWT1)
1173  Builder.defineMacro("__PREFETCHWT1__");
1174  if (HasCLZERO)
1175  Builder.defineMacro("__CLZERO__");
1176  if (HasRDPID)
1177  Builder.defineMacro("__RDPID__");
1178  if (HasCLDEMOTE)
1179  Builder.defineMacro("__CLDEMOTE__");
1180  if (HasWAITPKG)
1181  Builder.defineMacro("__WAITPKG__");
1182  if (HasMOVDIRI)
1183  Builder.defineMacro("__MOVDIRI__");
1184  if (HasMOVDIR64B)
1185  Builder.defineMacro("__MOVDIR64B__");
1186  if (HasPCONFIG)
1187  Builder.defineMacro("__PCONFIG__");
1188  if (HasPTWRITE)
1189  Builder.defineMacro("__PTWRITE__");
1190  if (HasINVPCID)
1191  Builder.defineMacro("__INVPCID__");
1192 
1193  // Each case falls through to the previous one here.
1194  switch (SSELevel) {
1195  case AVX512F:
1196  Builder.defineMacro("__AVX512F__");
1197  LLVM_FALLTHROUGH;
1198  case AVX2:
1199  Builder.defineMacro("__AVX2__");
1200  LLVM_FALLTHROUGH;
1201  case AVX:
1202  Builder.defineMacro("__AVX__");
1203  LLVM_FALLTHROUGH;
1204  case SSE42:
1205  Builder.defineMacro("__SSE4_2__");
1206  LLVM_FALLTHROUGH;
1207  case SSE41:
1208  Builder.defineMacro("__SSE4_1__");
1209  LLVM_FALLTHROUGH;
1210  case SSSE3:
1211  Builder.defineMacro("__SSSE3__");
1212  LLVM_FALLTHROUGH;
1213  case SSE3:
1214  Builder.defineMacro("__SSE3__");
1215  LLVM_FALLTHROUGH;
1216  case SSE2:
1217  Builder.defineMacro("__SSE2__");
1218  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1219  LLVM_FALLTHROUGH;
1220  case SSE1:
1221  Builder.defineMacro("__SSE__");
1222  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1223  LLVM_FALLTHROUGH;
1224  case NoSSE:
1225  break;
1226  }
1227 
1228  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1229  switch (SSELevel) {
1230  case AVX512F:
1231  case AVX2:
1232  case AVX:
1233  case SSE42:
1234  case SSE41:
1235  case SSSE3:
1236  case SSE3:
1237  case SSE2:
1238  Builder.defineMacro("_M_IX86_FP", Twine(2));
1239  break;
1240  case SSE1:
1241  Builder.defineMacro("_M_IX86_FP", Twine(1));
1242  break;
1243  default:
1244  Builder.defineMacro("_M_IX86_FP", Twine(0));
1245  break;
1246  }
1247  }
1248 
1249  // Each case falls through to the previous one here.
1250  switch (MMX3DNowLevel) {
1251  case AMD3DNowAthlon:
1252  Builder.defineMacro("__3dNOW_A__");
1253  LLVM_FALLTHROUGH;
1254  case AMD3DNow:
1255  Builder.defineMacro("__3dNOW__");
1256  LLVM_FALLTHROUGH;
1257  case MMX:
1258  Builder.defineMacro("__MMX__");
1259  LLVM_FALLTHROUGH;
1260  case NoMMX3DNow:
1261  break;
1262  }
1263 
1264  if (CPU >= CK_i486) {
1265  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1266  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1267  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1268  }
1269  if (CPU >= CK_i586)
1270  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1271  if (HasCX16)
1272  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1273 
1274  if (HasFloat128)
1275  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1276 }
1277 
1278 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1279  return llvm::StringSwitch<bool>(Name)
1280  .Case("3dnow", true)
1281  .Case("3dnowa", true)
1282  .Case("adx", true)
1283  .Case("aes", true)
1284  .Case("avx", true)
1285  .Case("avx2", true)
1286  .Case("avx512f", true)
1287  .Case("avx512cd", true)
1288  .Case("avx512vpopcntdq", true)
1289  .Case("avx512vnni", true)
1290  .Case("avx512er", true)
1291  .Case("avx512pf", true)
1292  .Case("avx512dq", true)
1293  .Case("avx512bitalg", true)
1294  .Case("avx512bw", true)
1295  .Case("avx512vl", true)
1296  .Case("avx512vbmi", true)
1297  .Case("avx512vbmi2", true)
1298  .Case("avx512ifma", true)
1299  .Case("bmi", true)
1300  .Case("bmi2", true)
1301  .Case("cldemote", true)
1302  .Case("clflushopt", true)
1303  .Case("clwb", true)
1304  .Case("clzero", true)
1305  .Case("cx16", true)
1306  .Case("f16c", true)
1307  .Case("fma", true)
1308  .Case("fma4", true)
1309  .Case("fsgsbase", true)
1310  .Case("fxsr", true)
1311  .Case("gfni", true)
1312  .Case("invpcid", true)
1313  .Case("lwp", true)
1314  .Case("lzcnt", true)
1315  .Case("mmx", true)
1316  .Case("movbe", true)
1317  .Case("movdiri", true)
1318  .Case("movdir64b", true)
1319  .Case("mpx", true)
1320  .Case("mwaitx", true)
1321  .Case("pclmul", true)
1322  .Case("pconfig", true)
1323  .Case("pku", true)
1324  .Case("popcnt", true)
1325  .Case("prefetchwt1", true)
1326  .Case("prfchw", true)
1327  .Case("ptwrite", true)
1328  .Case("rdpid", true)
1329  .Case("rdrnd", true)
1330  .Case("rdseed", true)
1331  .Case("rtm", true)
1332  .Case("sahf", true)
1333  .Case("sgx", true)
1334  .Case("sha", true)
1335  .Case("shstk", true)
1336  .Case("sse", true)
1337  .Case("sse2", true)
1338  .Case("sse3", true)
1339  .Case("ssse3", true)
1340  .Case("sse4", true)
1341  .Case("sse4.1", true)
1342  .Case("sse4.2", true)
1343  .Case("sse4a", true)
1344  .Case("tbm", true)
1345  .Case("vaes", true)
1346  .Case("vpclmulqdq", true)
1347  .Case("wbnoinvd", true)
1348  .Case("waitpkg", true)
1349  .Case("x87", true)
1350  .Case("xop", true)
1351  .Case("xsave", true)
1352  .Case("xsavec", true)
1353  .Case("xsaves", true)
1354  .Case("xsaveopt", true)
1355  .Default(false);
1356 }
1357 
1358 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1359  return llvm::StringSwitch<bool>(Feature)
1360  .Case("adx", HasADX)
1361  .Case("aes", HasAES)
1362  .Case("avx", SSELevel >= AVX)
1363  .Case("avx2", SSELevel >= AVX2)
1364  .Case("avx512f", SSELevel >= AVX512F)
1365  .Case("avx512cd", HasAVX512CD)
1366  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1367  .Case("avx512vnni", HasAVX512VNNI)
1368  .Case("avx512er", HasAVX512ER)
1369  .Case("avx512pf", HasAVX512PF)
1370  .Case("avx512dq", HasAVX512DQ)
1371  .Case("avx512bitalg", HasAVX512BITALG)
1372  .Case("avx512bw", HasAVX512BW)
1373  .Case("avx512vl", HasAVX512VL)
1374  .Case("avx512vbmi", HasAVX512VBMI)
1375  .Case("avx512vbmi2", HasAVX512VBMI2)
1376  .Case("avx512ifma", HasAVX512IFMA)
1377  .Case("bmi", HasBMI)
1378  .Case("bmi2", HasBMI2)
1379  .Case("cldemote", HasCLDEMOTE)
1380  .Case("clflushopt", HasCLFLUSHOPT)
1381  .Case("clwb", HasCLWB)
1382  .Case("clzero", HasCLZERO)
1383  .Case("cx16", HasCX16)
1384  .Case("f16c", HasF16C)
1385  .Case("fma", HasFMA)
1386  .Case("fma4", XOPLevel >= FMA4)
1387  .Case("fsgsbase", HasFSGSBASE)
1388  .Case("fxsr", HasFXSR)
1389  .Case("gfni", HasGFNI)
1390  .Case("invpcid", HasINVPCID)
1391  .Case("lwp", HasLWP)
1392  .Case("lzcnt", HasLZCNT)
1393  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1394  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1395  .Case("mmx", MMX3DNowLevel >= MMX)
1396  .Case("movbe", HasMOVBE)
1397  .Case("movdiri", HasMOVDIRI)
1398  .Case("movdir64b", HasMOVDIR64B)
1399  .Case("mpx", HasMPX)
1400  .Case("mwaitx", HasMWAITX)
1401  .Case("pclmul", HasPCLMUL)
1402  .Case("pconfig", HasPCONFIG)
1403  .Case("pku", HasPKU)
1404  .Case("popcnt", HasPOPCNT)
1405  .Case("prefetchwt1", HasPREFETCHWT1)
1406  .Case("prfchw", HasPRFCHW)
1407  .Case("ptwrite", HasPTWRITE)
1408  .Case("rdpid", HasRDPID)
1409  .Case("rdrnd", HasRDRND)
1410  .Case("rdseed", HasRDSEED)
1411  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1412  .Case("rtm", HasRTM)
1413  .Case("sahf", HasLAHFSAHF)
1414  .Case("sgx", HasSGX)
1415  .Case("sha", HasSHA)
1416  .Case("shstk", HasSHSTK)
1417  .Case("sse", SSELevel >= SSE1)
1418  .Case("sse2", SSELevel >= SSE2)
1419  .Case("sse3", SSELevel >= SSE3)
1420  .Case("ssse3", SSELevel >= SSSE3)
1421  .Case("sse4.1", SSELevel >= SSE41)
1422  .Case("sse4.2", SSELevel >= SSE42)
1423  .Case("sse4a", XOPLevel >= SSE4A)
1424  .Case("tbm", HasTBM)
1425  .Case("vaes", HasVAES)
1426  .Case("vpclmulqdq", HasVPCLMULQDQ)
1427  .Case("wbnoinvd", HasWBNOINVD)
1428  .Case("waitpkg", HasWAITPKG)
1429  .Case("x86", true)
1430  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1431  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1432  .Case("xop", XOPLevel >= XOP)
1433  .Case("xsave", HasXSAVE)
1434  .Case("xsavec", HasXSAVEC)
1435  .Case("xsaves", HasXSAVES)
1436  .Case("xsaveopt", HasXSAVEOPT)
1437  .Default(false);
1438 }
1439 
1440 // We can't use a generic validation scheme for the features accepted here
1441 // versus subtarget features accepted in the target attribute because the
1442 // bitfield structure that's initialized in the runtime only supports the
1443 // below currently rather than the full range of subtarget features. (See
1444 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1445 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1446  return llvm::StringSwitch<bool>(FeatureStr)
1447 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1448 #include "llvm/Support/X86TargetParser.def"
1449  .Default(false);
1450 }
1451 
1452 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1453  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1454 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1455 #include "llvm/Support/X86TargetParser.def"
1456  ;
1457  // Note, this function should only be used after ensuring the value is
1458  // correct, so it asserts if the value is out of range.
1459 }
1460 
1461 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1462  enum class FeatPriority {
1463 #define FEATURE(FEAT) FEAT,
1464 #include "clang/Basic/X86Target.def"
1465  };
1466  switch (Feat) {
1467 #define FEATURE(FEAT) \
1468  case llvm::X86::FEAT: \
1469  return static_cast<unsigned>(FeatPriority::FEAT);
1470 #include "clang/Basic/X86Target.def"
1471  default:
1472  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1473  }
1474 }
1475 
1476 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1477  // Valid CPUs have a 'key feature' that compares just better than its key
1478  // feature.
1479  CPUKind Kind = getCPUKind(Name);
1480  if (Kind != CK_Generic) {
1481  switch (Kind) {
1482  default:
1483  llvm_unreachable(
1484  "CPU Type without a key feature used in 'target' attribute");
1485 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1486  case CK_##ENUM: \
1487  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1488 #include "clang/Basic/X86Target.def"
1489  }
1490  }
1491 
1492  // Now we know we have a feature, so get its priority and shift it a few so
1493  // that we have sufficient room for the CPUs (above).
1494  return getFeaturePriority(getFeature(Name)) << 1;
1495 }
1496 
1497 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1498  return llvm::StringSwitch<bool>(Name)
1499 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1500 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1501 #include "clang/Basic/X86Target.def"
1502  .Default(false);
1503 }
1504 
1505 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1506  return llvm::StringSwitch<StringRef>(Name)
1507 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1508 #include "clang/Basic/X86Target.def"
1509  .Default(Name);
1510 }
1511 
1512 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1513  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1514 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1515 #include "clang/Basic/X86Target.def"
1516  .Default(0);
1517 }
1518 
1519 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1520  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1521  StringRef WholeList =
1522  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1523 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1524 #include "clang/Basic/X86Target.def"
1525  .Default("");
1526  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1527 }
1528 
1529 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const {
1530  switch (Kind) {
1531  case CK_Generic:
1532  return "";
1533 #define PROC(ENUM, STRING, IS64BIT) \
1534  case CK_##ENUM: \
1535  return STRING;
1536 #include "clang/Basic/X86Target.def"
1537  }
1538  llvm_unreachable("Invalid CPUKind");
1539 }
1540 
1541 // We can't use a generic validation scheme for the cpus accepted here
1542 // versus subtarget cpus accepted in the target attribute because the
1543 // variables intitialized by the runtime only support the below currently
1544 // rather than the full range of cpus.
1545 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1546  return llvm::StringSwitch<bool>(FeatureStr)
1547 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1548 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1549  .Cases(STR, ALIAS, true)
1550 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1551 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1552 #include "llvm/Support/X86TargetParser.def"
1553  .Default(false);
1554 }
1555 
1556 bool X86TargetInfo::validateAsmConstraint(
1557  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1558  switch (*Name) {
1559  default:
1560  return false;
1561  // Constant constraints.
1562  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1563  // instructions.
1564  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1565  // x86_64 instructions.
1566  case 's':
1567  Info.setRequiresImmediate();
1568  return true;
1569  case 'I':
1570  Info.setRequiresImmediate(0, 31);
1571  return true;
1572  case 'J':
1573  Info.setRequiresImmediate(0, 63);
1574  return true;
1575  case 'K':
1576  Info.setRequiresImmediate(-128, 127);
1577  return true;
1578  case 'L':
1579  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1580  return true;
1581  case 'M':
1582  Info.setRequiresImmediate(0, 3);
1583  return true;
1584  case 'N':
1585  Info.setRequiresImmediate(0, 255);
1586  return true;
1587  case 'O':
1588  Info.setRequiresImmediate(0, 127);
1589  return true;
1590  // Register constraints.
1591  case 'Y': // 'Y' is the first character for several 2-character constraints.
1592  // Shift the pointer to the second character of the constraint.
1593  Name++;
1594  switch (*Name) {
1595  default:
1596  return false;
1597  case 'z':
1598  case '0': // First SSE register.
1599  case '2':
1600  case 't': // Any SSE register, when SSE2 is enabled.
1601  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1602  case 'm': // Any MMX register, when inter-unit moves enabled.
1603  case 'k': // AVX512 arch mask registers: k1-k7.
1604  Info.setAllowsRegister();
1605  return true;
1606  }
1607  case 'f': // Any x87 floating point stack register.
1608  // Constraint 'f' cannot be used for output operands.
1609  if (Info.ConstraintStr[0] == '=')
1610  return false;
1611  Info.setAllowsRegister();
1612  return true;
1613  case 'a': // eax.
1614  case 'b': // ebx.
1615  case 'c': // ecx.
1616  case 'd': // edx.
1617  case 'S': // esi.
1618  case 'D': // edi.
1619  case 'A': // edx:eax.
1620  case 't': // Top of floating point stack.
1621  case 'u': // Second from top of floating point stack.
1622  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1623  case 'y': // Any MMX register.
1624  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1625  case 'x': // Any SSE register.
1626  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1627  // for intermideate k reg operations).
1628  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1629  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1630  case 'l': // "Index" registers: any general register that can be used as an
1631  // index in a base+index memory access.
1632  Info.setAllowsRegister();
1633  return true;
1634  // Floating point constant constraints.
1635  case 'C': // SSE floating point constant.
1636  case 'G': // x87 floating point constant.
1637  return true;
1638  }
1639 }
1640 
1641 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1642  unsigned Size) const {
1643  // Strip off constraint modifiers.
1644  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1645  Constraint = Constraint.substr(1);
1646 
1647  return validateOperandSize(Constraint, Size);
1648 }
1649 
1650 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1651  unsigned Size) const {
1652  return validateOperandSize(Constraint, Size);
1653 }
1654 
1655 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1656  unsigned Size) const {
1657  switch (Constraint[0]) {
1658  default:
1659  break;
1660  case 'k':
1661  // Registers k0-k7 (AVX512) size limit is 64 bit.
1662  case 'y':
1663  return Size <= 64;
1664  case 'f':
1665  case 't':
1666  case 'u':
1667  return Size <= 128;
1668  case 'Y':
1669  // 'Y' is the first character for several 2-character constraints.
1670  switch (Constraint[1]) {
1671  default:
1672  return false;
1673  case 'm':
1674  // 'Ym' is synonymous with 'y'.
1675  case 'k':
1676  return Size <= 64;
1677  case 'z':
1678  case '0':
1679  // XMM0
1680  if (SSELevel >= SSE1)
1681  return Size <= 128U;
1682  return false;
1683  case 'i':
1684  case 't':
1685  case '2':
1686  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1687  if (SSELevel < SSE2)
1688  return false;
1689  break;
1690  }
1691  LLVM_FALLTHROUGH;
1692  case 'v':
1693  case 'x':
1694  if (SSELevel >= AVX512F)
1695  // 512-bit zmm registers can be used if target supports AVX512F.
1696  return Size <= 512U;
1697  else if (SSELevel >= AVX)
1698  // 256-bit ymm registers can be used if target supports AVX.
1699  return Size <= 256U;
1700  return Size <= 128U;
1701 
1702  }
1703 
1704  return true;
1705 }
1706 
1707 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1708  switch (*Constraint) {
1709  case 'a':
1710  return std::string("{ax}");
1711  case 'b':
1712  return std::string("{bx}");
1713  case 'c':
1714  return std::string("{cx}");
1715  case 'd':
1716  return std::string("{dx}");
1717  case 'S':
1718  return std::string("{si}");
1719  case 'D':
1720  return std::string("{di}");
1721  case 'p': // address
1722  return std::string("im");
1723  case 't': // top of floating point stack.
1724  return std::string("{st}");
1725  case 'u': // second from top of floating point stack.
1726  return std::string("{st(1)}"); // second from top of floating point stack.
1727  case 'Y':
1728  switch (Constraint[1]) {
1729  default:
1730  // Break from inner switch and fall through (copy single char),
1731  // continue parsing after copying the current constraint into
1732  // the return string.
1733  break;
1734  case 'k':
1735  case 'm':
1736  case 'i':
1737  case 't':
1738  case 'z':
1739  case '0':
1740  case '2':
1741  // "^" hints llvm that this is a 2 letter constraint.
1742  // "Constraint++" is used to promote the string iterator
1743  // to the next constraint.
1744  return std::string("^") + std::string(Constraint++, 2);
1745  }
1746  LLVM_FALLTHROUGH;
1747  default:
1748  return std::string(1, *Constraint);
1749  }
1750 }
1751 
1752 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1753  // Perform any per-CPU checks necessary to determine if this CPU is
1754  // acceptable.
1755  switch (Kind) {
1756  case CK_Generic:
1757  // No processor selected!
1758  return false;
1759 #define PROC(ENUM, STRING, IS64BIT) \
1760  case CK_##ENUM: \
1761  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1762 #include "clang/Basic/X86Target.def"
1763  }
1764  llvm_unreachable("Unhandled CPU kind");
1765 }
1766 
1767 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1768 #define PROC(ENUM, STRING, IS64BIT) \
1769  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1770  Values.emplace_back(STRING);
1771  // Go through CPUKind checking to ensure that the alias is de-aliased and
1772  // 64 bit-ness is checked.
1773 #define PROC_ALIAS(ENUM, ALIAS) \
1774  if (checkCPUKind(getCPUKind(ALIAS))) \
1775  Values.emplace_back(ALIAS);
1776 #include "clang/Basic/X86Target.def"
1777 }
1778 
1779 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1780  return llvm::StringSwitch<CPUKind>(CPU)
1781 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1782 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1783 #include "clang/Basic/X86Target.def"
1784  .Default(CK_Generic);
1785 }
1786 
1787 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1788  return llvm::makeArrayRef(GCCRegNames);
1789 }
1790 
1791 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1792  return llvm::makeArrayRef(AddlRegNames);
1793 }
1794 
1795 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1796  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1797  Builtin::FirstTSBuiltin + 1);
1798 }
1799 
1800 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1801  return llvm::makeArrayRef(BuiltinInfoX86,
1802  X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1803 }
clang::targets::DefineStd
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:54
hasFeature
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:92
clang::targets::BuiltinInfoX86
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
clang::targets::X86TargetInfo::setMMXLevel
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:519
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1294
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1641
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1791
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:852
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1655
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1767
clang::targets::X86TargetInfo::getCPUKindCanonicalName
std::string getCPUKindCanonicalName(CPUKind Kind) const
Definition: X86.cpp:1529
clang::targets::X86TargetInfo::setXOPLevel
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:552
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:67
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:49
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1445
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1519
X86_FEATURE_COMPAT
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:148
Diagnostic.h
Defines the Diagnostic-related interfaces.
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1452
CPU_SPECIFIC_ALIAS
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1556
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition: X86.cpp:43
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1497
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1278
X86_VENDOR
#define X86_VENDOR(ENUM, STRING)
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:384
CPUSpecificCPUDispatchNameDealias
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1505
clang::targets::X86TargetInfo::getCPUKind
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1779
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1358
clang::targets::X86TargetInfo::setSSELevel
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:440
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
clang::targets::X86TargetInfo::CPUKind
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:114
clang::targets::X86_64TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1800
Kind
Kind
Definition: ChrootChecker.cpp:28
getFeaturePriority
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1461
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1707
clang::targets::X86_32TargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1795
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1512
clang
Dataflow Directional Tag Classes.
Definition: CFGReachabilityAnalysis.h:21
clang::targets::X86TargetInfo::multiVersionSortPriority
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1476
CPU_SPECIFIC
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:695
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1650
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:865
PROC
#define PROC(ENUM, STRING, IS64BIT)
max
__DEVICE__ int max(int __a, int __b)
Definition: __clang_cuda_device_functions.h:1611
clang::targets::X86TargetInfo::checkCPUKind
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1752
clang::targets::defineCPUMacros
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:70
clang::MacroBuilder::defineMacro
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:29
clang::targets::X86TargetInfo::setFeatureEnabledImpl
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:587
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1545
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1787
Builtins.h
Defines enum values for all the target-independent builtin functions.
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:104
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