1083 if (BuiltinID == Builtin::BI__builtin_cpu_supports)
1085 if (BuiltinID == Builtin::BI__builtin_cpu_init)
1087 if (BuiltinID == Builtin::BI__builtin_cpu_is)
1094 unsigned ICEArguments = 0;
1102 if (BuiltinID == RISCVVector::BI__builtin_rvv_vget_v ||
1103 BuiltinID == RISCVVector::BI__builtin_rvv_vset_v)
1104 ICEArguments = 1 << 1;
1109 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_load)
1110 ICEArguments |= (1 << 1);
1111 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_store)
1112 ICEArguments |= (1 << 2);
1114 for (
unsigned i = 0, e = E->
getNumArgs(); i != e; i++) {
1119 Ops.push_back(AggValue);
1125 Intrinsic::ID ID = Intrinsic::not_intrinsic;
1126 int PolicyAttrs = 0;
1127 bool IsMasked =
false;
1129 unsigned SegInstSEW = 8;
1131 unsigned TWiden = 0;
1135 switch (BuiltinID) {
1136 default: llvm_unreachable(
"unexpected builtin ID");
1137 case RISCV::BI__builtin_riscv_orc_b_32:
1138 case RISCV::BI__builtin_riscv_orc_b_64:
1139 case RISCV::BI__builtin_riscv_clmul_32:
1140 case RISCV::BI__builtin_riscv_clmul_64:
1141 case RISCV::BI__builtin_riscv_clmulh_32:
1142 case RISCV::BI__builtin_riscv_clmulh_64:
1143 case RISCV::BI__builtin_riscv_clmulr_32:
1144 case RISCV::BI__builtin_riscv_clmulr_64:
1145 case RISCV::BI__builtin_riscv_xperm4_32:
1146 case RISCV::BI__builtin_riscv_xperm4_64:
1147 case RISCV::BI__builtin_riscv_xperm8_32:
1148 case RISCV::BI__builtin_riscv_xperm8_64:
1149 case RISCV::BI__builtin_riscv_brev8_32:
1150 case RISCV::BI__builtin_riscv_brev8_64:
1151 case RISCV::BI__builtin_riscv_zip_32:
1152 case RISCV::BI__builtin_riscv_unzip_32: {
1153 switch (BuiltinID) {
1154 default: llvm_unreachable(
"unexpected builtin ID");
1156 case RISCV::BI__builtin_riscv_orc_b_32:
1157 case RISCV::BI__builtin_riscv_orc_b_64:
1158 ID = Intrinsic::riscv_orc_b;
1162 case RISCV::BI__builtin_riscv_clmul_32:
1163 case RISCV::BI__builtin_riscv_clmul_64:
1164 ID = Intrinsic::clmul;
1166 case RISCV::BI__builtin_riscv_clmulh_32:
1167 case RISCV::BI__builtin_riscv_clmulh_64:
1168 ID = Intrinsic::riscv_clmulh;
1170 case RISCV::BI__builtin_riscv_clmulr_32:
1171 case RISCV::BI__builtin_riscv_clmulr_64:
1172 ID = Intrinsic::riscv_clmulr;
1176 case RISCV::BI__builtin_riscv_xperm8_32:
1177 case RISCV::BI__builtin_riscv_xperm8_64:
1178 ID = Intrinsic::riscv_xperm8;
1180 case RISCV::BI__builtin_riscv_xperm4_32:
1181 case RISCV::BI__builtin_riscv_xperm4_64:
1182 ID = Intrinsic::riscv_xperm4;
1186 case RISCV::BI__builtin_riscv_brev8_32:
1187 case RISCV::BI__builtin_riscv_brev8_64:
1188 ID = Intrinsic::riscv_brev8;
1190 case RISCV::BI__builtin_riscv_zip_32:
1191 ID = Intrinsic::riscv_zip;
1193 case RISCV::BI__builtin_riscv_unzip_32:
1194 ID = Intrinsic::riscv_unzip;
1198 IntrinsicTypes = {ResultType};
1203 case RISCV::BI__builtin_riscv_paadd_i8x4:
1204 case RISCV::BI__builtin_riscv_paadd_i16x2:
1205 case RISCV::BI__builtin_riscv_paadd_i8x8:
1206 case RISCV::BI__builtin_riscv_paadd_i16x4:
1207 case RISCV::BI__builtin_riscv_paadd_i32x2:
1208 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1209 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1210 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1211 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1212 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1213 case RISCV::BI__builtin_riscv_pasub_i8x4:
1214 case RISCV::BI__builtin_riscv_pasub_i16x2:
1215 case RISCV::BI__builtin_riscv_pasub_i8x8:
1216 case RISCV::BI__builtin_riscv_pasub_i16x4:
1217 case RISCV::BI__builtin_riscv_pasub_i32x2:
1218 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1219 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1220 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1221 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1222 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1224 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1225 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1226 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1227 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1228 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1229 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1230 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1231 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1232 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1233 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1234 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1235 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1236 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1237 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1238 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1239 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1240 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1241 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1243 case RISCV::BI__builtin_riscv_pabd_i8x4:
1244 case RISCV::BI__builtin_riscv_pabd_i16x2:
1245 case RISCV::BI__builtin_riscv_pabd_i8x8:
1246 case RISCV::BI__builtin_riscv_pabd_i16x4:
1247 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1248 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1249 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1250 case RISCV::BI__builtin_riscv_pabdu_u16x4: {
1251 switch (BuiltinID) {
1253 llvm_unreachable(
"unexpected builtin ID");
1254 case RISCV::BI__builtin_riscv_paadd_i8x4:
1255 case RISCV::BI__builtin_riscv_paadd_i16x2:
1256 case RISCV::BI__builtin_riscv_paadd_i8x8:
1257 case RISCV::BI__builtin_riscv_paadd_i16x4:
1258 case RISCV::BI__builtin_riscv_paadd_i32x2:
1259 ID = Intrinsic::riscv_paadd;
1261 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1262 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1263 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1264 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1265 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1266 ID = Intrinsic::riscv_paaddu;
1268 case RISCV::BI__builtin_riscv_pasub_i8x4:
1269 case RISCV::BI__builtin_riscv_pasub_i16x2:
1270 case RISCV::BI__builtin_riscv_pasub_i8x8:
1271 case RISCV::BI__builtin_riscv_pasub_i16x4:
1272 case RISCV::BI__builtin_riscv_pasub_i32x2:
1273 ID = Intrinsic::riscv_pasub;
1275 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1276 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1277 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1278 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1279 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1280 ID = Intrinsic::riscv_pasubu;
1282 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1283 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1284 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1285 ID = Intrinsic::riscv_pas;
1287 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1288 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1289 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1290 ID = Intrinsic::riscv_psa;
1292 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1293 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1294 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1295 ID = Intrinsic::riscv_psas;
1297 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1298 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1299 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1300 ID = Intrinsic::riscv_pssa;
1302 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1303 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1304 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1305 ID = Intrinsic::riscv_paas;
1307 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1308 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1309 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1310 ID = Intrinsic::riscv_pasa;
1312 case RISCV::BI__builtin_riscv_pabd_i8x4:
1313 case RISCV::BI__builtin_riscv_pabd_i16x2:
1314 case RISCV::BI__builtin_riscv_pabd_i8x8:
1315 case RISCV::BI__builtin_riscv_pabd_i16x4:
1316 ID = Intrinsic::riscv_pabd;
1318 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1319 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1320 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1321 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1322 ID = Intrinsic::riscv_pabdu;
1326 IntrinsicTypes = {ResultType};
1333 case RISCV::BI__builtin_riscv_sha256sig0:
1334 ID = Intrinsic::riscv_sha256sig0;
1336 case RISCV::BI__builtin_riscv_sha256sig1:
1337 ID = Intrinsic::riscv_sha256sig1;
1339 case RISCV::BI__builtin_riscv_sha256sum0:
1340 ID = Intrinsic::riscv_sha256sum0;
1342 case RISCV::BI__builtin_riscv_sha256sum1:
1343 ID = Intrinsic::riscv_sha256sum1;
1347 case RISCV::BI__builtin_riscv_sm4ks:
1348 ID = Intrinsic::riscv_sm4ks;
1350 case RISCV::BI__builtin_riscv_sm4ed:
1351 ID = Intrinsic::riscv_sm4ed;
1355 case RISCV::BI__builtin_riscv_sm3p0:
1356 ID = Intrinsic::riscv_sm3p0;
1358 case RISCV::BI__builtin_riscv_sm3p1:
1359 ID = Intrinsic::riscv_sm3p1;
1362 case RISCV::BI__builtin_riscv_clz_32:
1363 case RISCV::BI__builtin_riscv_clz_64: {
1366 if (
Result->getType() != ResultType)
1371 case RISCV::BI__builtin_riscv_ctz_32:
1372 case RISCV::BI__builtin_riscv_ctz_64: {
1375 if (
Result->getType() != ResultType)
1382 case RISCV::BI__builtin_riscv_ntl_load: {
1384 unsigned DomainVal = 5;
1385 if (Ops.size() == 2)
1388 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1390 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1391 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1395 if(ResTy->isScalableTy()) {
1397 llvm::Type *ScalarTy = ResTy->getScalarType();
1398 Width = ScalarTy->getPrimitiveSizeInBits() *
1399 SVTy->getElementCount().getKnownMinValue();
1401 Width = ResTy->getPrimitiveSizeInBits();
1402 LoadInst *Load =
Builder.CreateLoad(
1405 Load->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1406 Load->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1411 case RISCV::BI__builtin_riscv_ntl_store: {
1412 unsigned DomainVal = 5;
1413 if (Ops.size() == 3)
1416 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1418 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1419 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1422 StoreInst *Store =
Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
1423 Store->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1424 Store->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1430 case RISCV::BI__builtin_riscv_pause: {
1431 llvm::Function *Fn =
CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
1432 return Builder.CreateCall(Fn, {});
1436 case RISCV::BI__builtin_riscv_cv_alu_addN:
1437 ID = Intrinsic::riscv_cv_alu_addN;
1439 case RISCV::BI__builtin_riscv_cv_alu_addRN:
1440 ID = Intrinsic::riscv_cv_alu_addRN;
1442 case RISCV::BI__builtin_riscv_cv_alu_adduN:
1443 ID = Intrinsic::riscv_cv_alu_adduN;
1445 case RISCV::BI__builtin_riscv_cv_alu_adduRN:
1446 ID = Intrinsic::riscv_cv_alu_adduRN;
1448 case RISCV::BI__builtin_riscv_cv_alu_clip:
1449 ID = Intrinsic::riscv_cv_alu_clip;
1451 case RISCV::BI__builtin_riscv_cv_alu_clipu:
1452 ID = Intrinsic::riscv_cv_alu_clipu;
1454 case RISCV::BI__builtin_riscv_cv_alu_extbs:
1457 case RISCV::BI__builtin_riscv_cv_alu_extbz:
1460 case RISCV::BI__builtin_riscv_cv_alu_exths:
1463 case RISCV::BI__builtin_riscv_cv_alu_exthz:
1466 case RISCV::BI__builtin_riscv_cv_alu_sle:
1469 case RISCV::BI__builtin_riscv_cv_alu_sleu:
1472 case RISCV::BI__builtin_riscv_cv_alu_subN:
1473 ID = Intrinsic::riscv_cv_alu_subN;
1475 case RISCV::BI__builtin_riscv_cv_alu_subRN:
1476 ID = Intrinsic::riscv_cv_alu_subRN;
1478 case RISCV::BI__builtin_riscv_cv_alu_subuN:
1479 ID = Intrinsic::riscv_cv_alu_subuN;
1481 case RISCV::BI__builtin_riscv_cv_alu_subuRN:
1482 ID = Intrinsic::riscv_cv_alu_subuRN;
1486 case RISCV::BI__builtin_riscv_nds_ffb_32:
1487 case RISCV::BI__builtin_riscv_nds_ffb_64:
1488 IntrinsicTypes = {ResultType};
1489 ID = Intrinsic::riscv_nds_ffb;
1491 case RISCV::BI__builtin_riscv_nds_ffzmism_32:
1492 case RISCV::BI__builtin_riscv_nds_ffzmism_64:
1493 IntrinsicTypes = {ResultType};
1494 ID = Intrinsic::riscv_nds_ffzmism;
1496 case RISCV::BI__builtin_riscv_nds_ffmism_32:
1497 case RISCV::BI__builtin_riscv_nds_ffmism_64:
1498 IntrinsicTypes = {ResultType};
1499 ID = Intrinsic::riscv_nds_ffmism;
1501 case RISCV::BI__builtin_riscv_nds_flmism_32:
1502 case RISCV::BI__builtin_riscv_nds_flmism_64:
1503 IntrinsicTypes = {ResultType};
1504 ID = Intrinsic::riscv_nds_flmism;
1508 case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
1510 case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
1514#include "clang/Basic/riscv_vector_builtin_cg.inc"
1517#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
1520#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
1523 assert(ID != Intrinsic::not_intrinsic);
1525 llvm::Function *F =
CGM.getIntrinsic(ID, IntrinsicTypes);
1526 return Builder.CreateCall(F, Ops,
"");