1083 if (BuiltinID == Builtin::BI__builtin_cpu_supports)
1085 if (BuiltinID == Builtin::BI__builtin_cpu_init)
1087 if (BuiltinID == Builtin::BI__builtin_cpu_is)
1094 unsigned ICEArguments = 0;
1102 if (BuiltinID == RISCVVector::BI__builtin_rvv_vget_v ||
1103 BuiltinID == RISCVVector::BI__builtin_rvv_vset_v)
1104 ICEArguments = 1 << 1;
1109 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_load)
1110 ICEArguments |= (1 << 1);
1111 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_store)
1112 ICEArguments |= (1 << 2);
1114 for (
unsigned i = 0, e = E->
getNumArgs(); i != e; i++) {
1119 Ops.push_back(AggValue);
1125 Intrinsic::ID ID = Intrinsic::not_intrinsic;
1126 int PolicyAttrs = 0;
1127 bool IsMasked =
false;
1129 unsigned SegInstSEW = 8;
1131 unsigned TWiden = 0;
1135 switch (BuiltinID) {
1136 default: llvm_unreachable(
"unexpected builtin ID");
1137 case RISCV::BI__builtin_riscv_orc_b_32:
1138 case RISCV::BI__builtin_riscv_orc_b_64:
1139 case RISCV::BI__builtin_riscv_clmul_32:
1140 case RISCV::BI__builtin_riscv_clmul_64:
1141 case RISCV::BI__builtin_riscv_clmulh_32:
1142 case RISCV::BI__builtin_riscv_clmulh_64:
1143 case RISCV::BI__builtin_riscv_clmulr_32:
1144 case RISCV::BI__builtin_riscv_clmulr_64:
1145 case RISCV::BI__builtin_riscv_xperm4_32:
1146 case RISCV::BI__builtin_riscv_xperm4_64:
1147 case RISCV::BI__builtin_riscv_xperm8_32:
1148 case RISCV::BI__builtin_riscv_xperm8_64:
1149 case RISCV::BI__builtin_riscv_brev8_32:
1150 case RISCV::BI__builtin_riscv_brev8_64:
1151 case RISCV::BI__builtin_riscv_zip_32:
1152 case RISCV::BI__builtin_riscv_unzip_32: {
1153 switch (BuiltinID) {
1154 default: llvm_unreachable(
"unexpected builtin ID");
1156 case RISCV::BI__builtin_riscv_orc_b_32:
1157 case RISCV::BI__builtin_riscv_orc_b_64:
1158 ID = Intrinsic::riscv_orc_b;
1162 case RISCV::BI__builtin_riscv_clmul_32:
1163 case RISCV::BI__builtin_riscv_clmul_64:
1164 ID = Intrinsic::clmul;
1166 case RISCV::BI__builtin_riscv_clmulh_32:
1167 case RISCV::BI__builtin_riscv_clmulh_64:
1168 ID = Intrinsic::riscv_clmulh;
1170 case RISCV::BI__builtin_riscv_clmulr_32:
1171 case RISCV::BI__builtin_riscv_clmulr_64:
1172 ID = Intrinsic::riscv_clmulr;
1176 case RISCV::BI__builtin_riscv_xperm8_32:
1177 case RISCV::BI__builtin_riscv_xperm8_64:
1178 ID = Intrinsic::riscv_xperm8;
1180 case RISCV::BI__builtin_riscv_xperm4_32:
1181 case RISCV::BI__builtin_riscv_xperm4_64:
1182 ID = Intrinsic::riscv_xperm4;
1186 case RISCV::BI__builtin_riscv_brev8_32:
1187 case RISCV::BI__builtin_riscv_brev8_64:
1188 ID = Intrinsic::riscv_brev8;
1190 case RISCV::BI__builtin_riscv_zip_32:
1191 ID = Intrinsic::riscv_zip;
1193 case RISCV::BI__builtin_riscv_unzip_32:
1194 ID = Intrinsic::riscv_unzip;
1198 IntrinsicTypes = {ResultType};
1203 case RISCV::BI__builtin_riscv_rev16_64:
1204 ID = Intrinsic::riscv_rev16_64;
1208 case RISCV::BI__builtin_riscv_pwsll_s_u16x4:
1209 case RISCV::BI__builtin_riscv_pwsll_s_u32x2:
1210 ID = Intrinsic::riscv_pwsll;
1211 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1213 case RISCV::BI__builtin_riscv_pwsla_s_i16x4:
1214 case RISCV::BI__builtin_riscv_pwsla_s_i32x2:
1215 ID = Intrinsic::riscv_pwsla;
1216 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1220 case RISCV::BI__builtin_riscv_pnsrl_s_u8x4:
1221 case RISCV::BI__builtin_riscv_pnsrl_s_u16x2:
1222 ID = Intrinsic::riscv_pnsrl;
1223 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1225 case RISCV::BI__builtin_riscv_pnsra_s_i8x4:
1226 case RISCV::BI__builtin_riscv_pnsra_s_i16x2:
1227 ID = Intrinsic::riscv_pnsra;
1228 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1230 case RISCV::BI__builtin_riscv_pnsrar_s_i8x4:
1231 case RISCV::BI__builtin_riscv_pnsrar_s_i16x2:
1232 ID = Intrinsic::riscv_pnsrar;
1233 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1237 case RISCV::BI__builtin_riscv_pnclipu_s_u8x4:
1238 case RISCV::BI__builtin_riscv_pnclipu_s_u16x2:
1239 ID = Intrinsic::riscv_pnclipu;
1240 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1242 case RISCV::BI__builtin_riscv_pnclipru_s_u8x4:
1243 case RISCV::BI__builtin_riscv_pnclipru_s_u16x2:
1244 ID = Intrinsic::riscv_pnclipru;
1245 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1247 case RISCV::BI__builtin_riscv_pnclip_s_i8x4:
1248 case RISCV::BI__builtin_riscv_pnclip_s_i16x2:
1249 ID = Intrinsic::riscv_pnclip;
1250 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1252 case RISCV::BI__builtin_riscv_pnclipr_s_i8x4:
1253 case RISCV::BI__builtin_riscv_pnclipr_s_i16x2:
1254 ID = Intrinsic::riscv_pnclipr;
1255 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1259 case RISCV::BI__builtin_riscv_paadd_i8x4:
1260 case RISCV::BI__builtin_riscv_paadd_i16x2:
1261 case RISCV::BI__builtin_riscv_paadd_i8x8:
1262 case RISCV::BI__builtin_riscv_paadd_i16x4:
1263 case RISCV::BI__builtin_riscv_paadd_i32x2:
1264 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1265 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1266 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1267 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1268 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1269 case RISCV::BI__builtin_riscv_pasub_i8x4:
1270 case RISCV::BI__builtin_riscv_pasub_i16x2:
1271 case RISCV::BI__builtin_riscv_pasub_i8x8:
1272 case RISCV::BI__builtin_riscv_pasub_i16x4:
1273 case RISCV::BI__builtin_riscv_pasub_i32x2:
1274 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1275 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1276 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1277 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1278 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1280 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1281 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1282 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1283 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1284 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1285 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1286 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1287 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1288 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1289 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1290 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1291 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1292 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1293 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1294 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1295 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1296 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1297 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1299 case RISCV::BI__builtin_riscv_psll_s_u8x4:
1300 case RISCV::BI__builtin_riscv_psll_s_u16x2:
1301 case RISCV::BI__builtin_riscv_psll_s_u8x8:
1302 case RISCV::BI__builtin_riscv_psll_s_u16x4:
1303 case RISCV::BI__builtin_riscv_psll_s_u32x2:
1304 case RISCV::BI__builtin_riscv_psrl_s_u8x4:
1305 case RISCV::BI__builtin_riscv_psrl_s_u16x2:
1306 case RISCV::BI__builtin_riscv_psrl_s_u8x8:
1307 case RISCV::BI__builtin_riscv_psrl_s_u16x4:
1308 case RISCV::BI__builtin_riscv_psrl_s_u32x2:
1309 case RISCV::BI__builtin_riscv_psra_s_i8x4:
1310 case RISCV::BI__builtin_riscv_psra_s_i16x2:
1311 case RISCV::BI__builtin_riscv_psra_s_i8x8:
1312 case RISCV::BI__builtin_riscv_psra_s_i16x4:
1313 case RISCV::BI__builtin_riscv_psra_s_i32x2:
1315 case RISCV::BI__builtin_riscv_pabd_i8x4:
1316 case RISCV::BI__builtin_riscv_pabd_i16x2:
1317 case RISCV::BI__builtin_riscv_pabd_i8x8:
1318 case RISCV::BI__builtin_riscv_pabd_i16x4:
1319 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1320 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1321 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1322 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1324 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1325 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1326 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1327 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1328 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1330 case RISCV::BI__builtin_riscv_pmulh_i16x2:
1331 case RISCV::BI__builtin_riscv_pmulh_i16x4:
1332 case RISCV::BI__builtin_riscv_pmulh_i32x2:
1333 case RISCV::BI__builtin_riscv_pmulhr_i16x2:
1334 case RISCV::BI__builtin_riscv_pmulhr_i16x4:
1335 case RISCV::BI__builtin_riscv_pmulhr_i32x2:
1336 case RISCV::BI__builtin_riscv_pmulhu_u16x2:
1337 case RISCV::BI__builtin_riscv_pmulhu_u16x4:
1338 case RISCV::BI__builtin_riscv_pmulhu_u32x2:
1339 case RISCV::BI__builtin_riscv_pmulhru_u16x2:
1340 case RISCV::BI__builtin_riscv_pmulhru_u16x4:
1341 case RISCV::BI__builtin_riscv_pmulhru_u32x2:
1342 case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
1343 case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
1344 case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
1345 case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
1346 case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
1347 case RISCV::BI__builtin_riscv_pmulhrsu_i32x2:
1349 case RISCV::BI__builtin_riscv_pmhacc_i16x2:
1350 case RISCV::BI__builtin_riscv_pmhacc_i16x4:
1351 case RISCV::BI__builtin_riscv_pmhacc_i32x2:
1352 case RISCV::BI__builtin_riscv_pmhracc_i16x2:
1353 case RISCV::BI__builtin_riscv_pmhracc_i16x4:
1354 case RISCV::BI__builtin_riscv_pmhracc_i32x2:
1355 case RISCV::BI__builtin_riscv_pmhaccu_u16x2:
1356 case RISCV::BI__builtin_riscv_pmhaccu_u16x4:
1357 case RISCV::BI__builtin_riscv_pmhaccu_u32x2:
1358 case RISCV::BI__builtin_riscv_pmhraccu_u16x2:
1359 case RISCV::BI__builtin_riscv_pmhraccu_u16x4:
1360 case RISCV::BI__builtin_riscv_pmhraccu_u32x2:
1361 case RISCV::BI__builtin_riscv_pmhaccsu_i16x2:
1362 case RISCV::BI__builtin_riscv_pmhaccsu_i16x4:
1363 case RISCV::BI__builtin_riscv_pmhaccsu_i32x2:
1364 case RISCV::BI__builtin_riscv_pmhraccsu_i16x2:
1365 case RISCV::BI__builtin_riscv_pmhraccsu_i16x4:
1366 case RISCV::BI__builtin_riscv_pmhraccsu_i32x2:
1368 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x2:
1369 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2:
1370 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x2:
1371 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2:
1372 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x4:
1373 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4:
1374 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x4:
1375 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4:
1376 case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2:
1377 case RISCV::BI__builtin_riscv_pmhacc_h1_i32x2:
1378 case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2:
1379 case RISCV::BI__builtin_riscv_pmhaccsu_h1_i32x2:
1381 case RISCV::BI__builtin_riscv_psabs_i8x4:
1382 case RISCV::BI__builtin_riscv_psabs_i16x2:
1383 case RISCV::BI__builtin_riscv_psabs_i8x8:
1384 case RISCV::BI__builtin_riscv_psabs_i16x4:
1386 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1387 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1388 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1389 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1390 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1391 case RISCV::BI__builtin_riscv_pmulqr_i32x2:
1392 case RISCV::BI__builtin_riscv_psext_b_i16x2:
1393 case RISCV::BI__builtin_riscv_pzext_b_u16x2:
1394 case RISCV::BI__builtin_riscv_psext_b_i16x4:
1395 case RISCV::BI__builtin_riscv_psext_b_i32x2:
1396 case RISCV::BI__builtin_riscv_psext_h_i32x2:
1397 case RISCV::BI__builtin_riscv_pzext_b_u16x4:
1398 case RISCV::BI__builtin_riscv_pzext_h_u32x2:
1400 case RISCV::BI__builtin_riscv_pssha_s_i16x2:
1401 case RISCV::BI__builtin_riscv_psshar_s_i16x2:
1402 case RISCV::BI__builtin_riscv_psshl_s_u16x2:
1403 case RISCV::BI__builtin_riscv_psshlr_s_u16x2:
1404 case RISCV::BI__builtin_riscv_pssha_s_i16x4:
1405 case RISCV::BI__builtin_riscv_pssha_s_i32x2:
1406 case RISCV::BI__builtin_riscv_psshar_s_i16x4:
1407 case RISCV::BI__builtin_riscv_psshar_s_i32x2:
1408 case RISCV::BI__builtin_riscv_psshl_s_u16x4:
1409 case RISCV::BI__builtin_riscv_psshl_s_u32x2:
1410 case RISCV::BI__builtin_riscv_psshlr_s_u16x4:
1411 case RISCV::BI__builtin_riscv_psshlr_s_u32x2:
1413 case RISCV::BI__builtin_riscv_pusati_u16x2:
1414 case RISCV::BI__builtin_riscv_psati_i16x2:
1415 case RISCV::BI__builtin_riscv_pusati_u16x4:
1416 case RISCV::BI__builtin_riscv_pusati_u32x2:
1417 case RISCV::BI__builtin_riscv_psati_i16x4:
1418 case RISCV::BI__builtin_riscv_psati_i32x2:
1420 case RISCV::BI__builtin_riscv_sati_i32:
1421 case RISCV::BI__builtin_riscv_usati_u32:
1422 case RISCV::BI__builtin_riscv_sati_i64:
1423 case RISCV::BI__builtin_riscv_usati_u64:
1425 case RISCV::BI__builtin_riscv_mulh_i32:
1426 case RISCV::BI__builtin_riscv_mulhu_u32: {
1427 switch (BuiltinID) {
1429 llvm_unreachable(
"unexpected builtin ID");
1430 case RISCV::BI__builtin_riscv_paadd_i8x4:
1431 case RISCV::BI__builtin_riscv_paadd_i16x2:
1432 case RISCV::BI__builtin_riscv_paadd_i8x8:
1433 case RISCV::BI__builtin_riscv_paadd_i16x4:
1434 case RISCV::BI__builtin_riscv_paadd_i32x2:
1435 ID = Intrinsic::riscv_paadd;
1437 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1438 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1439 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1440 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1441 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1442 ID = Intrinsic::riscv_paaddu;
1444 case RISCV::BI__builtin_riscv_pasub_i8x4:
1445 case RISCV::BI__builtin_riscv_pasub_i16x2:
1446 case RISCV::BI__builtin_riscv_pasub_i8x8:
1447 case RISCV::BI__builtin_riscv_pasub_i16x4:
1448 case RISCV::BI__builtin_riscv_pasub_i32x2:
1449 ID = Intrinsic::riscv_pasub;
1451 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1452 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1453 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1454 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1455 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1456 ID = Intrinsic::riscv_pasubu;
1458 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1459 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1460 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1461 ID = Intrinsic::riscv_pas;
1463 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1464 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1465 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1466 ID = Intrinsic::riscv_psa;
1468 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1469 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1470 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1471 ID = Intrinsic::riscv_psas;
1473 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1474 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1475 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1476 ID = Intrinsic::riscv_pssa;
1478 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1479 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1480 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1481 ID = Intrinsic::riscv_paas;
1483 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1484 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1485 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1486 ID = Intrinsic::riscv_pasa;
1488 case RISCV::BI__builtin_riscv_psll_s_u8x4:
1489 case RISCV::BI__builtin_riscv_psll_s_u16x2:
1490 case RISCV::BI__builtin_riscv_psll_s_u8x8:
1491 case RISCV::BI__builtin_riscv_psll_s_u16x4:
1492 case RISCV::BI__builtin_riscv_psll_s_u32x2:
1493 ID = Intrinsic::riscv_psll;
1495 case RISCV::BI__builtin_riscv_psrl_s_u8x4:
1496 case RISCV::BI__builtin_riscv_psrl_s_u16x2:
1497 case RISCV::BI__builtin_riscv_psrl_s_u8x8:
1498 case RISCV::BI__builtin_riscv_psrl_s_u16x4:
1499 case RISCV::BI__builtin_riscv_psrl_s_u32x2:
1500 ID = Intrinsic::riscv_psrl;
1502 case RISCV::BI__builtin_riscv_psra_s_i8x4:
1503 case RISCV::BI__builtin_riscv_psra_s_i16x2:
1504 case RISCV::BI__builtin_riscv_psra_s_i8x8:
1505 case RISCV::BI__builtin_riscv_psra_s_i16x4:
1506 case RISCV::BI__builtin_riscv_psra_s_i32x2:
1507 ID = Intrinsic::riscv_psra;
1509 case RISCV::BI__builtin_riscv_pabd_i8x4:
1510 case RISCV::BI__builtin_riscv_pabd_i16x2:
1511 case RISCV::BI__builtin_riscv_pabd_i8x8:
1512 case RISCV::BI__builtin_riscv_pabd_i16x4:
1513 ID = Intrinsic::riscv_pabd;
1515 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1516 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1517 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1518 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1519 ID = Intrinsic::riscv_pabdu;
1521 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1522 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1523 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1524 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1525 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1526 ID = Intrinsic::riscv_pmerge;
1528 case RISCV::BI__builtin_riscv_pmulh_i16x2:
1529 case RISCV::BI__builtin_riscv_pmulh_i16x4:
1530 case RISCV::BI__builtin_riscv_pmulh_i32x2:
1531 ID = Intrinsic::smulh;
1533 case RISCV::BI__builtin_riscv_pmulhr_i16x2:
1534 case RISCV::BI__builtin_riscv_pmulhr_i16x4:
1535 case RISCV::BI__builtin_riscv_pmulhr_i32x2:
1536 ID = Intrinsic::riscv_pmulhr;
1538 case RISCV::BI__builtin_riscv_pmulhu_u16x2:
1539 case RISCV::BI__builtin_riscv_pmulhu_u16x4:
1540 case RISCV::BI__builtin_riscv_pmulhu_u32x2:
1541 ID = Intrinsic::umulh;
1543 case RISCV::BI__builtin_riscv_pmulhru_u16x2:
1544 case RISCV::BI__builtin_riscv_pmulhru_u16x4:
1545 case RISCV::BI__builtin_riscv_pmulhru_u32x2:
1546 ID = Intrinsic::riscv_pmulhru;
1548 case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
1549 case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
1550 case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
1551 ID = Intrinsic::riscv_pmulhsu;
1553 case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
1554 case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
1555 case RISCV::BI__builtin_riscv_pmulhrsu_i32x2:
1556 ID = Intrinsic::riscv_pmulhrsu;
1558 case RISCV::BI__builtin_riscv_pmhacc_i16x2:
1559 case RISCV::BI__builtin_riscv_pmhacc_i16x4:
1560 case RISCV::BI__builtin_riscv_pmhacc_i32x2:
1561 ID = Intrinsic::riscv_pmhacc;
1563 case RISCV::BI__builtin_riscv_pmhracc_i16x2:
1564 case RISCV::BI__builtin_riscv_pmhracc_i16x4:
1565 case RISCV::BI__builtin_riscv_pmhracc_i32x2:
1566 ID = Intrinsic::riscv_pmhracc;
1568 case RISCV::BI__builtin_riscv_pmhaccu_u16x2:
1569 case RISCV::BI__builtin_riscv_pmhaccu_u16x4:
1570 case RISCV::BI__builtin_riscv_pmhaccu_u32x2:
1571 ID = Intrinsic::riscv_pmhaccu;
1573 case RISCV::BI__builtin_riscv_pmhraccu_u16x2:
1574 case RISCV::BI__builtin_riscv_pmhraccu_u16x4:
1575 case RISCV::BI__builtin_riscv_pmhraccu_u32x2:
1576 ID = Intrinsic::riscv_pmhraccu;
1578 case RISCV::BI__builtin_riscv_pmhaccsu_i16x2:
1579 case RISCV::BI__builtin_riscv_pmhaccsu_i16x4:
1580 case RISCV::BI__builtin_riscv_pmhaccsu_i32x2:
1581 ID = Intrinsic::riscv_pmhaccsu;
1583 case RISCV::BI__builtin_riscv_pmhraccsu_i16x2:
1584 case RISCV::BI__builtin_riscv_pmhraccsu_i16x4:
1585 case RISCV::BI__builtin_riscv_pmhraccsu_i32x2:
1586 ID = Intrinsic::riscv_pmhraccsu;
1588 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x2:
1589 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x4:
1590 ID = Intrinsic::riscv_pmhacc_b0;
1592 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2:
1593 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4:
1594 ID = Intrinsic::riscv_pmhacc_b1;
1596 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x2:
1597 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x4:
1598 ID = Intrinsic::riscv_pmhaccsu_b0;
1600 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2:
1601 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4:
1602 ID = Intrinsic::riscv_pmhaccsu_b1;
1604 case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2:
1605 ID = Intrinsic::riscv_pmhacc_h0;
1607 case RISCV::BI__builtin_riscv_pmhacc_h1_i32x2:
1608 ID = Intrinsic::riscv_pmhacc_h1;
1610 case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2:
1611 ID = Intrinsic::riscv_pmhaccsu_h0;
1613 case RISCV::BI__builtin_riscv_pmhaccsu_h1_i32x2:
1614 ID = Intrinsic::riscv_pmhaccsu_h1;
1616 case RISCV::BI__builtin_riscv_psabs_i8x4:
1617 case RISCV::BI__builtin_riscv_psabs_i16x2:
1618 case RISCV::BI__builtin_riscv_psabs_i8x8:
1619 case RISCV::BI__builtin_riscv_psabs_i16x4:
1620 ID = Intrinsic::riscv_psabs;
1622 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1623 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1624 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1625 ID = Intrinsic::riscv_pmulq;
1627 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1628 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1629 case RISCV::BI__builtin_riscv_pmulqr_i32x2:
1630 ID = Intrinsic::riscv_pmulqr;
1632 case RISCV::BI__builtin_riscv_psext_b_i16x2:
1633 case RISCV::BI__builtin_riscv_psext_b_i16x4:
1634 case RISCV::BI__builtin_riscv_psext_b_i32x2:
1635 ID = Intrinsic::riscv_psext_b;
1637 case RISCV::BI__builtin_riscv_psext_h_i32x2:
1638 ID = Intrinsic::riscv_psext_h;
1640 case RISCV::BI__builtin_riscv_pzext_b_u16x2:
1641 case RISCV::BI__builtin_riscv_pzext_b_u16x4:
1642 ID = Intrinsic::riscv_pzext_b;
1644 case RISCV::BI__builtin_riscv_pzext_h_u32x2:
1645 ID = Intrinsic::riscv_pzext_h;
1647 case RISCV::BI__builtin_riscv_pssha_s_i16x2:
1648 case RISCV::BI__builtin_riscv_pssha_s_i16x4:
1649 case RISCV::BI__builtin_riscv_pssha_s_i32x2:
1650 ID = Intrinsic::riscv_pssha;
1652 case RISCV::BI__builtin_riscv_psshar_s_i16x2:
1653 case RISCV::BI__builtin_riscv_psshar_s_i16x4:
1654 case RISCV::BI__builtin_riscv_psshar_s_i32x2:
1655 ID = Intrinsic::riscv_psshar;
1657 case RISCV::BI__builtin_riscv_psshl_s_u16x2:
1658 case RISCV::BI__builtin_riscv_psshl_s_u16x4:
1659 case RISCV::BI__builtin_riscv_psshl_s_u32x2:
1660 ID = Intrinsic::riscv_psshl;
1662 case RISCV::BI__builtin_riscv_psshlr_s_u16x2:
1663 case RISCV::BI__builtin_riscv_psshlr_s_u16x4:
1664 case RISCV::BI__builtin_riscv_psshlr_s_u32x2:
1665 ID = Intrinsic::riscv_psshlr;
1667 case RISCV::BI__builtin_riscv_psati_i16x2:
1668 case RISCV::BI__builtin_riscv_psati_i16x4:
1669 case RISCV::BI__builtin_riscv_psati_i32x2:
1670 ID = Intrinsic::riscv_psati;
1672 case RISCV::BI__builtin_riscv_pusati_u16x2:
1673 case RISCV::BI__builtin_riscv_pusati_u16x4:
1674 case RISCV::BI__builtin_riscv_pusati_u32x2:
1675 ID = Intrinsic::riscv_pusati;
1677 case RISCV::BI__builtin_riscv_sati_i32:
1678 case RISCV::BI__builtin_riscv_sati_i64:
1679 ID = Intrinsic::riscv_sati;
1681 case RISCV::BI__builtin_riscv_usati_u32:
1682 case RISCV::BI__builtin_riscv_usati_u64:
1683 ID = Intrinsic::riscv_usati;
1685 case RISCV::BI__builtin_riscv_mulh_i32:
1686 ID = Intrinsic::smulh;
1688 case RISCV::BI__builtin_riscv_mulhu_u32:
1689 ID = Intrinsic::umulh;
1693 IntrinsicTypes = {ResultType};
1698 case RISCV::BI__builtin_riscv_aadd_i32:
1699 ID = Intrinsic::riscv_aadd_i32;
1701 case RISCV::BI__builtin_riscv_aaddu_u32:
1702 ID = Intrinsic::riscv_aaddu_u32;
1704 case RISCV::BI__builtin_riscv_asub_i32:
1705 ID = Intrinsic::riscv_asub_i32;
1707 case RISCV::BI__builtin_riscv_asubu_u32:
1708 ID = Intrinsic::riscv_asubu_u32;
1712 case RISCV::BI__builtin_riscv_mulhr_i32:
1713 case RISCV::BI__builtin_riscv_mulhru_u32:
1714 case RISCV::BI__builtin_riscv_mulhsu_i32:
1715 case RISCV::BI__builtin_riscv_mulhrsu_i32: {
1716 switch (BuiltinID) {
1718 llvm_unreachable(
"unexpected builtin ID");
1719 case RISCV::BI__builtin_riscv_mulhr_i32:
1720 ID = Intrinsic::riscv_mulhr_i32;
1722 case RISCV::BI__builtin_riscv_mulhru_u32:
1723 ID = Intrinsic::riscv_mulhru_u32;
1725 case RISCV::BI__builtin_riscv_mulhsu_i32:
1726 ID = Intrinsic::riscv_mulhsu_i32;
1728 case RISCV::BI__builtin_riscv_mulhrsu_i32:
1729 ID = Intrinsic::riscv_mulhrsu_i32;
1736 case RISCV::BI__builtin_riscv_mhacc_i32:
1737 ID = Intrinsic::riscv_mhacc_i32;
1739 case RISCV::BI__builtin_riscv_mhracc_i32:
1740 ID = Intrinsic::riscv_mhracc_i32;
1742 case RISCV::BI__builtin_riscv_mhaccu_u32:
1743 ID = Intrinsic::riscv_mhaccu_u32;
1745 case RISCV::BI__builtin_riscv_mhraccu_u32:
1746 ID = Intrinsic::riscv_mhraccu_u32;
1748 case RISCV::BI__builtin_riscv_mhaccsu_i32:
1749 ID = Intrinsic::riscv_mhaccsu_i32;
1751 case RISCV::BI__builtin_riscv_mhraccsu_i32:
1752 ID = Intrinsic::riscv_mhraccsu_i32;
1756 case RISCV::BI__builtin_riscv_mulq_i32:
1757 ID = Intrinsic::riscv_mulq_i32;
1759 case RISCV::BI__builtin_riscv_mulqr_i32:
1760 ID = Intrinsic::riscv_mulqr_i32;
1764 case RISCV::BI__builtin_riscv_mqwacc_i64:
1765 ID = Intrinsic::riscv_mqwacc_i64;
1767 case RISCV::BI__builtin_riscv_mqrwacc_i64:
1768 ID = Intrinsic::riscv_mqrwacc_i64;
1772 case RISCV::BI__builtin_riscv_pmqwacc_i32x2:
1773 case RISCV::BI__builtin_riscv_pmqrwacc_i32x2: {
1774 ID = BuiltinID == RISCV::BI__builtin_riscv_pmqwacc_i32x2
1775 ? Intrinsic::riscv_pmqwacc_i32x2
1776 : Intrinsic::riscv_pmqrwacc_i32x2;
1781 case RISCV::BI__builtin_riscv_pm4add_i8x4:
1782 case RISCV::BI__builtin_riscv_pm4add_i8x8:
1783 case RISCV::BI__builtin_riscv_pm4add_i16x4:
1784 case RISCV::BI__builtin_riscv_pm2add_i16x2:
1785 case RISCV::BI__builtin_riscv_pm2add_i16x4:
1786 case RISCV::BI__builtin_riscv_pm2add_i32x2:
1787 case RISCV::BI__builtin_riscv_pm2add_x_i16x2:
1788 case RISCV::BI__builtin_riscv_pm2add_x_i16x4:
1789 case RISCV::BI__builtin_riscv_pm2add_x_i32x2:
1790 case RISCV::BI__builtin_riscv_pm4addu_u8x4:
1791 case RISCV::BI__builtin_riscv_pm4addu_u8x8:
1792 case RISCV::BI__builtin_riscv_pm4addu_u16x4:
1793 case RISCV::BI__builtin_riscv_pm2addu_u16x2:
1794 case RISCV::BI__builtin_riscv_pm2addu_u16x4:
1795 case RISCV::BI__builtin_riscv_pm2addu_u32x2:
1796 case RISCV::BI__builtin_riscv_pmq2add_i16x2:
1797 case RISCV::BI__builtin_riscv_pmq2add_i16x4:
1798 case RISCV::BI__builtin_riscv_pmq2add_i32x2:
1799 case RISCV::BI__builtin_riscv_pmqr2add_i16x2:
1800 case RISCV::BI__builtin_riscv_pmqr2add_i16x4:
1801 case RISCV::BI__builtin_riscv_pmqr2add_i32x2:
1802 case RISCV::BI__builtin_riscv_pm2sadd_i16x2:
1803 case RISCV::BI__builtin_riscv_pm2sadd_i16x4:
1804 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2:
1805 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4:
1806 case RISCV::BI__builtin_riscv_pm2sub_i16x2:
1807 case RISCV::BI__builtin_riscv_pm2sub_i16x4:
1808 case RISCV::BI__builtin_riscv_pm2sub_i32x2:
1809 case RISCV::BI__builtin_riscv_pm2sub_x_i16x2:
1810 case RISCV::BI__builtin_riscv_pm2sub_x_i16x4:
1811 case RISCV::BI__builtin_riscv_pm2sub_x_i32x2:
1812 case RISCV::BI__builtin_riscv_pm4addsu_i8x4:
1813 case RISCV::BI__builtin_riscv_pm4addsu_i8x8:
1814 case RISCV::BI__builtin_riscv_pm4addsu_i16x4:
1815 case RISCV::BI__builtin_riscv_pm2addsu_i16x2:
1816 case RISCV::BI__builtin_riscv_pm2addsu_i16x4:
1817 case RISCV::BI__builtin_riscv_pm2addsu_i32x2:
1819 case RISCV::BI__builtin_riscv_pm2wadd_i64:
1820 case RISCV::BI__builtin_riscv_pm2wadd_x_i64:
1821 case RISCV::BI__builtin_riscv_pm2waddu_u64:
1822 case RISCV::BI__builtin_riscv_pm2wsub_i64:
1823 case RISCV::BI__builtin_riscv_pm2wsub_x_i64:
1824 case RISCV::BI__builtin_riscv_pm2waddsu_i64: {
1825 switch (BuiltinID) {
1827 llvm_unreachable(
"unexpected builtin ID");
1828 case RISCV::BI__builtin_riscv_pm4add_i8x4:
1829 case RISCV::BI__builtin_riscv_pm4add_i8x8:
1830 case RISCV::BI__builtin_riscv_pm4add_i16x4:
1831 ID = Intrinsic::riscv_pm4add;
1833 case RISCV::BI__builtin_riscv_pm2add_i16x2:
1834 case RISCV::BI__builtin_riscv_pm2add_i16x4:
1835 case RISCV::BI__builtin_riscv_pm2add_i32x2:
1836 ID = Intrinsic::riscv_pm2add;
1838 case RISCV::BI__builtin_riscv_pm2add_x_i16x2:
1839 case RISCV::BI__builtin_riscv_pm2add_x_i16x4:
1840 case RISCV::BI__builtin_riscv_pm2add_x_i32x2:
1841 ID = Intrinsic::riscv_pm2add_x;
1843 case RISCV::BI__builtin_riscv_pm4addu_u8x4:
1844 case RISCV::BI__builtin_riscv_pm4addu_u8x8:
1845 case RISCV::BI__builtin_riscv_pm4addu_u16x4:
1846 ID = Intrinsic::riscv_pm4addu;
1848 case RISCV::BI__builtin_riscv_pm2addu_u16x2:
1849 case RISCV::BI__builtin_riscv_pm2addu_u16x4:
1850 case RISCV::BI__builtin_riscv_pm2addu_u32x2:
1851 ID = Intrinsic::riscv_pm2addu;
1853 case RISCV::BI__builtin_riscv_pmq2add_i16x2:
1854 case RISCV::BI__builtin_riscv_pmq2add_i16x4:
1855 case RISCV::BI__builtin_riscv_pmq2add_i32x2:
1856 ID = Intrinsic::riscv_pmq2add;
1858 case RISCV::BI__builtin_riscv_pmqr2add_i16x2:
1859 case RISCV::BI__builtin_riscv_pmqr2add_i16x4:
1860 case RISCV::BI__builtin_riscv_pmqr2add_i32x2:
1861 ID = Intrinsic::riscv_pmqr2add;
1863 case RISCV::BI__builtin_riscv_pm2sadd_i16x2:
1864 case RISCV::BI__builtin_riscv_pm2sadd_i16x4:
1865 ID = Intrinsic::riscv_pm2sadd;
1867 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2:
1868 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4:
1869 ID = Intrinsic::riscv_pm2sadd_x;
1871 case RISCV::BI__builtin_riscv_pm2sub_i16x2:
1872 case RISCV::BI__builtin_riscv_pm2sub_i16x4:
1873 case RISCV::BI__builtin_riscv_pm2sub_i32x2:
1874 ID = Intrinsic::riscv_pm2sub;
1876 case RISCV::BI__builtin_riscv_pm2sub_x_i16x2:
1877 case RISCV::BI__builtin_riscv_pm2sub_x_i16x4:
1878 case RISCV::BI__builtin_riscv_pm2sub_x_i32x2:
1879 ID = Intrinsic::riscv_pm2sub_x;
1881 case RISCV::BI__builtin_riscv_pm4addsu_i8x4:
1882 case RISCV::BI__builtin_riscv_pm4addsu_i8x8:
1883 case RISCV::BI__builtin_riscv_pm4addsu_i16x4:
1884 ID = Intrinsic::riscv_pm4addsu;
1886 case RISCV::BI__builtin_riscv_pm2addsu_i16x2:
1887 case RISCV::BI__builtin_riscv_pm2addsu_i16x4:
1888 case RISCV::BI__builtin_riscv_pm2addsu_i32x2:
1889 ID = Intrinsic::riscv_pm2addsu;
1891 case RISCV::BI__builtin_riscv_pm2wadd_i64:
1892 ID = Intrinsic::riscv_pm2wadd;
1894 case RISCV::BI__builtin_riscv_pm2wadd_x_i64:
1895 ID = Intrinsic::riscv_pm2wadd_x;
1897 case RISCV::BI__builtin_riscv_pm2waddu_u64:
1898 ID = Intrinsic::riscv_pm2waddu;
1900 case RISCV::BI__builtin_riscv_pm2wsub_i64:
1901 ID = Intrinsic::riscv_pm2wsub;
1903 case RISCV::BI__builtin_riscv_pm2wsub_x_i64:
1904 ID = Intrinsic::riscv_pm2wsub_x;
1906 case RISCV::BI__builtin_riscv_pm2waddsu_i64:
1907 ID = Intrinsic::riscv_pm2waddsu;
1911 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1916 case RISCV::BI__builtin_riscv_pwmacc_i32x2:
1917 case RISCV::BI__builtin_riscv_pwmaccu_u32x2:
1918 case RISCV::BI__builtin_riscv_pwmaccsu_i32x2: {
1919 switch (BuiltinID) {
1921 llvm_unreachable(
"unexpected builtin ID");
1922 case RISCV::BI__builtin_riscv_pwmacc_i32x2:
1923 ID = Intrinsic::riscv_pwmacc_i32x2;
1925 case RISCV::BI__builtin_riscv_pwmaccu_u32x2:
1926 ID = Intrinsic::riscv_pwmaccu_u32x2;
1928 case RISCV::BI__builtin_riscv_pwmaccsu_i32x2:
1929 ID = Intrinsic::riscv_pwmaccsu_i32x2;
1933 IntrinsicTypes = {ResultType, Ops[1]->getType()};
1938 case RISCV::BI__builtin_riscv_pm2wadda_i64:
1939 case RISCV::BI__builtin_riscv_pm2wadda_x_i64:
1940 case RISCV::BI__builtin_riscv_pm2waddau_u64:
1941 case RISCV::BI__builtin_riscv_pm2wsuba_i64:
1942 case RISCV::BI__builtin_riscv_pm2wsuba_x_i64:
1943 case RISCV::BI__builtin_riscv_pm2waddasu_i64: {
1944 switch (BuiltinID) {
1946 llvm_unreachable(
"unexpected builtin ID");
1947 case RISCV::BI__builtin_riscv_pm2wadda_i64:
1948 ID = Intrinsic::riscv_pm2wadda;
1950 case RISCV::BI__builtin_riscv_pm2wadda_x_i64:
1951 ID = Intrinsic::riscv_pm2wadda_x;
1953 case RISCV::BI__builtin_riscv_pm2waddau_u64:
1954 ID = Intrinsic::riscv_pm2waddau;
1956 case RISCV::BI__builtin_riscv_pm2wsuba_i64:
1957 ID = Intrinsic::riscv_pm2wsuba;
1959 case RISCV::BI__builtin_riscv_pm2wsuba_x_i64:
1960 ID = Intrinsic::riscv_pm2wsuba_x;
1962 case RISCV::BI__builtin_riscv_pm2waddasu_i64:
1963 ID = Intrinsic::riscv_pm2waddasu;
1967 IntrinsicTypes = {ResultType, Ops[1]->getType()};
1972 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1973 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1974 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1975 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1976 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1977 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1978 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1979 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1980 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1981 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1982 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1983 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1984 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1985 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
1987 case RISCV::BI__builtin_riscv_pnclipp_i8x4:
1988 case RISCV::BI__builtin_riscv_pnclipp_i8x8:
1989 case RISCV::BI__builtin_riscv_pnclipp_i16x2:
1990 case RISCV::BI__builtin_riscv_pnclipp_i16x4:
1991 case RISCV::BI__builtin_riscv_pnclipp_i32x2:
1992 case RISCV::BI__builtin_riscv_pnclipup_u8x4:
1993 case RISCV::BI__builtin_riscv_pnclipup_u8x8:
1994 case RISCV::BI__builtin_riscv_pnclipup_u16x2:
1995 case RISCV::BI__builtin_riscv_pnclipup_u16x4:
1996 case RISCV::BI__builtin_riscv_pnclipup_u32x2: {
1997 switch (BuiltinID) {
1999 llvm_unreachable(
"unexpected builtin ID");
2000 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
2001 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
2002 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
2003 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
2004 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
2005 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
2006 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
2007 ID = Intrinsic::riscv_predsum;
2009 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
2010 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
2011 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
2012 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
2013 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
2014 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
2015 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
2016 ID = Intrinsic::riscv_predsumu;
2018 case RISCV::BI__builtin_riscv_pnclipp_i8x4:
2019 case RISCV::BI__builtin_riscv_pnclipp_i8x8:
2020 case RISCV::BI__builtin_riscv_pnclipp_i16x2:
2021 case RISCV::BI__builtin_riscv_pnclipp_i16x4:
2022 case RISCV::BI__builtin_riscv_pnclipp_i32x2:
2023 ID = Intrinsic::riscv_pnclipp;
2025 case RISCV::BI__builtin_riscv_pnclipup_u8x4:
2026 case RISCV::BI__builtin_riscv_pnclipup_u8x8:
2027 case RISCV::BI__builtin_riscv_pnclipup_u16x2:
2028 case RISCV::BI__builtin_riscv_pnclipup_u16x4:
2029 case RISCV::BI__builtin_riscv_pnclipup_u32x2:
2030 ID = Intrinsic::riscv_pnclipup;
2034 IntrinsicTypes = {ResultType, Ops[0]->getType()};
2039 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
2040 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
2041 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
2042 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
2043 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
2044 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64: {
2045 switch (BuiltinID) {
2047 llvm_unreachable(
"unexpected builtin ID");
2048 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
2049 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
2050 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
2051 ID = Intrinsic::riscv_pabdsumu;
2053 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
2054 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
2055 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64:
2056 ID = Intrinsic::riscv_pabdsumau;
2062 IntrinsicTypes = {ResultType, Ops.back()->getType()};
2066 case RISCV::BI__builtin_riscv_pmul_b00_i16x2:
2067 case RISCV::BI__builtin_riscv_pmul_b01_i16x2:
2068 case RISCV::BI__builtin_riscv_pmul_b11_i16x2:
2069 case RISCV::BI__builtin_riscv_pmulu_b00_u16x2:
2070 case RISCV::BI__builtin_riscv_pmulu_b01_u16x2:
2071 case RISCV::BI__builtin_riscv_pmulu_b11_u16x2:
2072 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2:
2073 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2:
2074 case RISCV::BI__builtin_riscv_pmul_b00_i16x4:
2075 case RISCV::BI__builtin_riscv_pmul_b01_i16x4:
2076 case RISCV::BI__builtin_riscv_pmul_b11_i16x4:
2077 case RISCV::BI__builtin_riscv_pmulu_b00_u16x4:
2078 case RISCV::BI__builtin_riscv_pmulu_b01_u16x4:
2079 case RISCV::BI__builtin_riscv_pmulu_b11_u16x4:
2080 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4:
2081 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4:
2082 case RISCV::BI__builtin_riscv_pmul_h00_i32x2:
2083 case RISCV::BI__builtin_riscv_pmul_h01_i32x2:
2084 case RISCV::BI__builtin_riscv_pmul_h11_i32x2:
2085 case RISCV::BI__builtin_riscv_pmulu_h00_u32x2:
2086 case RISCV::BI__builtin_riscv_pmulu_h01_u32x2:
2087 case RISCV::BI__builtin_riscv_pmulu_h11_u32x2:
2088 case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2:
2089 case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
2090 case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
2091 case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
2092 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
2093 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
2094 case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
2095 case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
2096 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
2097 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
2098 case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
2099 case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
2100 case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
2101 case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: {
2102 switch (BuiltinID) {
2104 llvm_unreachable(
"unexpected builtin ID");
2105 case RISCV::BI__builtin_riscv_pmul_b00_i16x2:
2106 case RISCV::BI__builtin_riscv_pmul_b00_i16x4:
2107 case RISCV::BI__builtin_riscv_pmul_h00_i32x2:
2108 ID = Intrinsic::riscv_pmul_00;
2110 case RISCV::BI__builtin_riscv_pmul_b01_i16x2:
2111 case RISCV::BI__builtin_riscv_pmul_b01_i16x4:
2112 case RISCV::BI__builtin_riscv_pmul_h01_i32x2:
2113 ID = Intrinsic::riscv_pmul_01;
2115 case RISCV::BI__builtin_riscv_pmul_b11_i16x2:
2116 case RISCV::BI__builtin_riscv_pmul_b11_i16x4:
2117 case RISCV::BI__builtin_riscv_pmul_h11_i32x2:
2118 ID = Intrinsic::riscv_pmul_11;
2120 case RISCV::BI__builtin_riscv_pmulu_b00_u16x2:
2121 case RISCV::BI__builtin_riscv_pmulu_b00_u16x4:
2122 case RISCV::BI__builtin_riscv_pmulu_h00_u32x2:
2123 ID = Intrinsic::riscv_pmulu_00;
2125 case RISCV::BI__builtin_riscv_pmulu_b01_u16x2:
2126 case RISCV::BI__builtin_riscv_pmulu_b01_u16x4:
2127 case RISCV::BI__builtin_riscv_pmulu_h01_u32x2:
2128 ID = Intrinsic::riscv_pmulu_01;
2130 case RISCV::BI__builtin_riscv_pmulu_b11_u16x2:
2131 case RISCV::BI__builtin_riscv_pmulu_b11_u16x4:
2132 case RISCV::BI__builtin_riscv_pmulu_h11_u32x2:
2133 ID = Intrinsic::riscv_pmulu_11;
2135 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2:
2136 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4:
2137 case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2:
2138 ID = Intrinsic::riscv_pmulsu_00;
2140 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2:
2141 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4:
2142 case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
2143 ID = Intrinsic::riscv_pmulsu_11;
2145 case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
2146 case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
2147 ID = Intrinsic::riscv_pmulh_b0;
2149 case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
2150 case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
2151 ID = Intrinsic::riscv_pmulh_b1;
2153 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
2154 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
2155 ID = Intrinsic::riscv_pmulhsu_b0;
2157 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
2158 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
2159 ID = Intrinsic::riscv_pmulhsu_b1;
2161 case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
2162 ID = Intrinsic::riscv_pmulh_h0;
2164 case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
2165 ID = Intrinsic::riscv_pmulh_h1;
2167 case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
2168 ID = Intrinsic::riscv_pmulhsu_h0;
2170 case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2:
2171 ID = Intrinsic::riscv_pmulhsu_h1;
2175 IntrinsicTypes = {ResultType};
2180 case RISCV::BI__builtin_riscv_mul_h00_i32:
2181 case RISCV::BI__builtin_riscv_mul_w00_i64:
2182 case RISCV::BI__builtin_riscv_mul_h01_i32:
2183 case RISCV::BI__builtin_riscv_mul_w01_i64:
2184 case RISCV::BI__builtin_riscv_mul_h11_i32:
2185 case RISCV::BI__builtin_riscv_mul_w11_i64:
2186 case RISCV::BI__builtin_riscv_mulu_h00_u32:
2187 case RISCV::BI__builtin_riscv_mulu_w00_u64:
2188 case RISCV::BI__builtin_riscv_mulu_h01_u32:
2189 case RISCV::BI__builtin_riscv_mulu_w01_u64:
2190 case RISCV::BI__builtin_riscv_mulu_h11_u32:
2191 case RISCV::BI__builtin_riscv_mulu_w11_u64:
2192 case RISCV::BI__builtin_riscv_mulsu_h00_i32:
2193 case RISCV::BI__builtin_riscv_mulsu_w00_i64:
2194 case RISCV::BI__builtin_riscv_mulsu_h11_i32:
2195 case RISCV::BI__builtin_riscv_mulsu_w11_i64: {
2196 switch (BuiltinID) {
2198 llvm_unreachable(
"unexpected builtin ID");
2199 case RISCV::BI__builtin_riscv_mul_h00_i32:
2200 case RISCV::BI__builtin_riscv_mul_w00_i64:
2201 ID = Intrinsic::riscv_mul_00;
2203 case RISCV::BI__builtin_riscv_mul_h01_i32:
2204 case RISCV::BI__builtin_riscv_mul_w01_i64:
2205 ID = Intrinsic::riscv_mul_01;
2207 case RISCV::BI__builtin_riscv_mul_h11_i32:
2208 case RISCV::BI__builtin_riscv_mul_w11_i64:
2209 ID = Intrinsic::riscv_mul_11;
2211 case RISCV::BI__builtin_riscv_mulu_h00_u32:
2212 case RISCV::BI__builtin_riscv_mulu_w00_u64:
2213 ID = Intrinsic::riscv_mulu_00;
2215 case RISCV::BI__builtin_riscv_mulu_h01_u32:
2216 case RISCV::BI__builtin_riscv_mulu_w01_u64:
2217 ID = Intrinsic::riscv_mulu_01;
2219 case RISCV::BI__builtin_riscv_mulu_h11_u32:
2220 case RISCV::BI__builtin_riscv_mulu_w11_u64:
2221 ID = Intrinsic::riscv_mulu_11;
2223 case RISCV::BI__builtin_riscv_mulsu_h00_i32:
2224 case RISCV::BI__builtin_riscv_mulsu_w00_i64:
2225 ID = Intrinsic::riscv_mulsu_00;
2227 case RISCV::BI__builtin_riscv_mulsu_h11_i32:
2228 case RISCV::BI__builtin_riscv_mulsu_w11_i64:
2229 ID = Intrinsic::riscv_mulsu_11;
2233 IntrinsicTypes = {ResultType, Ops[0]->getType()};
2238 case RISCV::BI__builtin_riscv_mulh_h0_i32:
2239 case RISCV::BI__builtin_riscv_mulh_h1_i32:
2240 case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
2241 case RISCV::BI__builtin_riscv_mulhsu_h1_i32: {
2242 switch (BuiltinID) {
2244 llvm_unreachable(
"unexpected builtin ID");
2245 case RISCV::BI__builtin_riscv_mulh_h0_i32:
2246 ID = Intrinsic::riscv_mulh_h0;
2248 case RISCV::BI__builtin_riscv_mulh_h1_i32:
2249 ID = Intrinsic::riscv_mulh_h1;
2251 case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
2252 ID = Intrinsic::riscv_mulhsu_h0;
2254 case RISCV::BI__builtin_riscv_mulhsu_h1_i32:
2255 ID = Intrinsic::riscv_mulhsu_h1;
2259 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2264 case RISCV::BI__builtin_riscv_mqacc_h00_i32:
2265 case RISCV::BI__builtin_riscv_mqacc_h01_i32:
2266 case RISCV::BI__builtin_riscv_mqacc_h11_i32:
2267 case RISCV::BI__builtin_riscv_mqracc_h00_i32:
2268 case RISCV::BI__builtin_riscv_mqracc_h01_i32:
2269 case RISCV::BI__builtin_riscv_mqracc_h11_i32:
2270 case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2:
2271 case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2:
2272 case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2:
2273 case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2:
2274 case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2:
2275 case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2:
2276 case RISCV::BI__builtin_riscv_mqacc_w00_i64:
2277 case RISCV::BI__builtin_riscv_mqacc_w01_i64:
2278 case RISCV::BI__builtin_riscv_mqacc_w11_i64:
2279 case RISCV::BI__builtin_riscv_mqracc_w00_i64:
2280 case RISCV::BI__builtin_riscv_mqracc_w01_i64:
2281 case RISCV::BI__builtin_riscv_mqracc_w11_i64: {
2282 switch (BuiltinID) {
2284 llvm_unreachable(
"unexpected builtin ID");
2285 case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2:
2286 ID = Intrinsic::riscv_pmqacc_h00;
2288 case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2:
2289 ID = Intrinsic::riscv_pmqacc_h01;
2291 case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2:
2292 ID = Intrinsic::riscv_pmqacc_h11;
2294 case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2:
2295 ID = Intrinsic::riscv_pmqracc_h00;
2297 case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2:
2298 ID = Intrinsic::riscv_pmqracc_h01;
2300 case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2:
2301 ID = Intrinsic::riscv_pmqracc_h11;
2304 case RISCV::BI__builtin_riscv_mqacc_h00_i32:
2305 case RISCV::BI__builtin_riscv_mqacc_w00_i64:
2306 ID = Intrinsic::riscv_mqacc_00;
2308 case RISCV::BI__builtin_riscv_mqacc_h01_i32:
2309 case RISCV::BI__builtin_riscv_mqacc_w01_i64:
2310 ID = Intrinsic::riscv_mqacc_01;
2312 case RISCV::BI__builtin_riscv_mqacc_h11_i32:
2313 case RISCV::BI__builtin_riscv_mqacc_w11_i64:
2314 ID = Intrinsic::riscv_mqacc_11;
2316 case RISCV::BI__builtin_riscv_mqracc_h00_i32:
2317 case RISCV::BI__builtin_riscv_mqracc_w00_i64:
2318 ID = Intrinsic::riscv_mqracc_00;
2320 case RISCV::BI__builtin_riscv_mqracc_h01_i32:
2321 case RISCV::BI__builtin_riscv_mqracc_w01_i64:
2322 ID = Intrinsic::riscv_mqracc_01;
2324 case RISCV::BI__builtin_riscv_mqracc_h11_i32:
2325 case RISCV::BI__builtin_riscv_mqracc_w11_i64:
2326 ID = Intrinsic::riscv_mqracc_11;
2330 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2335 case RISCV::BI__builtin_riscv_macc_h00_i32:
2336 case RISCV::BI__builtin_riscv_pmacc_h00_i32x2:
2337 case RISCV::BI__builtin_riscv_macc_w00_i64:
2338 case RISCV::BI__builtin_riscv_macc_h01_i32:
2339 case RISCV::BI__builtin_riscv_pmacc_h01_i32x2:
2340 case RISCV::BI__builtin_riscv_macc_w01_i64:
2341 case RISCV::BI__builtin_riscv_macc_h11_i32:
2342 case RISCV::BI__builtin_riscv_pmacc_h11_i32x2:
2343 case RISCV::BI__builtin_riscv_macc_w11_i64:
2344 case RISCV::BI__builtin_riscv_maccu_h00_u32:
2345 case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2:
2346 case RISCV::BI__builtin_riscv_maccu_w00_u64:
2347 case RISCV::BI__builtin_riscv_maccu_h01_u32:
2348 case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2:
2349 case RISCV::BI__builtin_riscv_maccu_w01_u64:
2350 case RISCV::BI__builtin_riscv_maccu_h11_u32:
2351 case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2:
2352 case RISCV::BI__builtin_riscv_maccu_w11_u64:
2353 case RISCV::BI__builtin_riscv_maccsu_h00_i32:
2354 case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2:
2355 case RISCV::BI__builtin_riscv_maccsu_w00_i64:
2356 case RISCV::BI__builtin_riscv_maccsu_h11_i32:
2357 case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2:
2358 case RISCV::BI__builtin_riscv_maccsu_w11_i64: {
2359 switch (BuiltinID) {
2361 llvm_unreachable(
"unexpected builtin ID");
2362 case RISCV::BI__builtin_riscv_macc_h00_i32:
2363 case RISCV::BI__builtin_riscv_pmacc_h00_i32x2:
2364 case RISCV::BI__builtin_riscv_macc_w00_i64:
2365 ID = Intrinsic::riscv_macc_00;
2367 case RISCV::BI__builtin_riscv_macc_h01_i32:
2368 case RISCV::BI__builtin_riscv_pmacc_h01_i32x2:
2369 case RISCV::BI__builtin_riscv_macc_w01_i64:
2370 ID = Intrinsic::riscv_macc_01;
2372 case RISCV::BI__builtin_riscv_macc_h11_i32:
2373 case RISCV::BI__builtin_riscv_pmacc_h11_i32x2:
2374 case RISCV::BI__builtin_riscv_macc_w11_i64:
2375 ID = Intrinsic::riscv_macc_11;
2377 case RISCV::BI__builtin_riscv_maccu_h00_u32:
2378 case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2:
2379 case RISCV::BI__builtin_riscv_maccu_w00_u64:
2380 ID = Intrinsic::riscv_maccu_00;
2382 case RISCV::BI__builtin_riscv_maccu_h01_u32:
2383 case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2:
2384 case RISCV::BI__builtin_riscv_maccu_w01_u64:
2385 ID = Intrinsic::riscv_maccu_01;
2387 case RISCV::BI__builtin_riscv_maccu_h11_u32:
2388 case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2:
2389 case RISCV::BI__builtin_riscv_maccu_w11_u64:
2390 ID = Intrinsic::riscv_maccu_11;
2392 case RISCV::BI__builtin_riscv_maccsu_h00_i32:
2393 case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2:
2394 case RISCV::BI__builtin_riscv_maccsu_w00_i64:
2395 ID = Intrinsic::riscv_maccsu_00;
2397 case RISCV::BI__builtin_riscv_maccsu_h11_i32:
2398 case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2:
2399 case RISCV::BI__builtin_riscv_maccsu_w11_i64:
2400 ID = Intrinsic::riscv_maccsu_11;
2404 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2411 case RISCV::BI__builtin_riscv_sha256sig0:
2412 ID = Intrinsic::riscv_sha256sig0;
2414 case RISCV::BI__builtin_riscv_sha256sig1:
2415 ID = Intrinsic::riscv_sha256sig1;
2417 case RISCV::BI__builtin_riscv_sha256sum0:
2418 ID = Intrinsic::riscv_sha256sum0;
2420 case RISCV::BI__builtin_riscv_sha256sum1:
2421 ID = Intrinsic::riscv_sha256sum1;
2425 case RISCV::BI__builtin_riscv_sm4ks:
2426 ID = Intrinsic::riscv_sm4ks;
2428 case RISCV::BI__builtin_riscv_sm4ed:
2429 ID = Intrinsic::riscv_sm4ed;
2433 case RISCV::BI__builtin_riscv_sm3p0:
2434 ID = Intrinsic::riscv_sm3p0;
2436 case RISCV::BI__builtin_riscv_sm3p1:
2437 ID = Intrinsic::riscv_sm3p1;
2440 case RISCV::BI__builtin_riscv_clz_32:
2441 case RISCV::BI__builtin_riscv_clz_64: {
2444 if (
Result->getType() != ResultType)
2449 case RISCV::BI__builtin_riscv_ctz_32:
2450 case RISCV::BI__builtin_riscv_ctz_64: {
2453 if (
Result->getType() != ResultType)
2460 case RISCV::BI__builtin_riscv_ntl_load: {
2462 unsigned DomainVal = 5;
2463 if (Ops.size() == 2)
2466 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
2468 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
2469 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
2473 if(ResTy->isScalableTy()) {
2475 llvm::Type *ScalarTy = ResTy->getScalarType();
2476 Width = ScalarTy->getPrimitiveSizeInBits() *
2477 SVTy->getElementCount().getKnownMinValue();
2479 Width = ResTy->getPrimitiveSizeInBits();
2480 LoadInst *Load =
Builder.CreateLoad(
2483 Load->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
2484 Load->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
2489 case RISCV::BI__builtin_riscv_ntl_store: {
2490 unsigned DomainVal = 5;
2491 if (Ops.size() == 3)
2494 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
2496 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
2497 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
2500 StoreInst *Store =
Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
2501 Store->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
2502 Store->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
2508 case RISCV::BI__builtin_riscv_pause: {
2509 llvm::Function *Fn =
CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
2510 return Builder.CreateCall(Fn, {});
2514 case RISCV::BI__builtin_riscv_cv_alu_addN:
2515 ID = Intrinsic::riscv_cv_alu_addN;
2517 case RISCV::BI__builtin_riscv_cv_alu_addRN:
2518 ID = Intrinsic::riscv_cv_alu_addRN;
2520 case RISCV::BI__builtin_riscv_cv_alu_adduN:
2521 ID = Intrinsic::riscv_cv_alu_adduN;
2523 case RISCV::BI__builtin_riscv_cv_alu_adduRN:
2524 ID = Intrinsic::riscv_cv_alu_adduRN;
2526 case RISCV::BI__builtin_riscv_cv_alu_clip:
2527 ID = Intrinsic::riscv_cv_alu_clip;
2529 case RISCV::BI__builtin_riscv_cv_alu_clipu:
2530 ID = Intrinsic::riscv_cv_alu_clipu;
2532 case RISCV::BI__builtin_riscv_cv_alu_extbs:
2535 case RISCV::BI__builtin_riscv_cv_alu_extbz:
2538 case RISCV::BI__builtin_riscv_cv_alu_exths:
2541 case RISCV::BI__builtin_riscv_cv_alu_exthz:
2544 case RISCV::BI__builtin_riscv_cv_alu_sle:
2547 case RISCV::BI__builtin_riscv_cv_alu_sleu:
2550 case RISCV::BI__builtin_riscv_cv_alu_subN:
2551 ID = Intrinsic::riscv_cv_alu_subN;
2553 case RISCV::BI__builtin_riscv_cv_alu_subRN:
2554 ID = Intrinsic::riscv_cv_alu_subRN;
2556 case RISCV::BI__builtin_riscv_cv_alu_subuN:
2557 ID = Intrinsic::riscv_cv_alu_subuN;
2559 case RISCV::BI__builtin_riscv_cv_alu_subuRN:
2560 ID = Intrinsic::riscv_cv_alu_subuRN;
2564 case RISCV::BI__builtin_riscv_nds_ffb_32:
2565 case RISCV::BI__builtin_riscv_nds_ffb_64:
2566 IntrinsicTypes = {ResultType};
2567 ID = Intrinsic::riscv_nds_ffb;
2569 case RISCV::BI__builtin_riscv_nds_ffzmism_32:
2570 case RISCV::BI__builtin_riscv_nds_ffzmism_64:
2571 IntrinsicTypes = {ResultType};
2572 ID = Intrinsic::riscv_nds_ffzmism;
2574 case RISCV::BI__builtin_riscv_nds_ffmism_32:
2575 case RISCV::BI__builtin_riscv_nds_ffmism_64:
2576 IntrinsicTypes = {ResultType};
2577 ID = Intrinsic::riscv_nds_ffmism;
2579 case RISCV::BI__builtin_riscv_nds_flmism_32:
2580 case RISCV::BI__builtin_riscv_nds_flmism_64:
2581 IntrinsicTypes = {ResultType};
2582 ID = Intrinsic::riscv_nds_flmism;
2586 case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
2588 case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
2592#include "clang/Basic/riscv_vector_builtin_cg.inc"
2595#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
2598#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
2601 assert(ID != Intrinsic::not_intrinsic);
2603 llvm::Function *F =
CGM.getIntrinsic(ID, IntrinsicTypes);
2604 return Builder.CreateCall(F, Ops,
"");
1.14.0