1083 if (BuiltinID == Builtin::BI__builtin_cpu_supports)
1085 if (BuiltinID == Builtin::BI__builtin_cpu_init)
1087 if (BuiltinID == Builtin::BI__builtin_cpu_is)
1094 unsigned ICEArguments = 0;
1102 if (BuiltinID == RISCVVector::BI__builtin_rvv_vget_v ||
1103 BuiltinID == RISCVVector::BI__builtin_rvv_vset_v)
1104 ICEArguments = 1 << 1;
1109 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_load)
1110 ICEArguments |= (1 << 1);
1111 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_store)
1112 ICEArguments |= (1 << 2);
1114 for (
unsigned i = 0, e = E->
getNumArgs(); i != e; i++) {
1119 Ops.push_back(AggValue);
1125 Intrinsic::ID ID = Intrinsic::not_intrinsic;
1126 int PolicyAttrs = 0;
1127 bool IsMasked =
false;
1129 unsigned SegInstSEW = 8;
1131 unsigned TWiden = 0;
1135 switch (BuiltinID) {
1136 default: llvm_unreachable(
"unexpected builtin ID");
1137 case RISCV::BI__builtin_riscv_orc_b_32:
1138 case RISCV::BI__builtin_riscv_orc_b_64:
1139 case RISCV::BI__builtin_riscv_clmul_32:
1140 case RISCV::BI__builtin_riscv_clmul_64:
1141 case RISCV::BI__builtin_riscv_clmulh_32:
1142 case RISCV::BI__builtin_riscv_clmulh_64:
1143 case RISCV::BI__builtin_riscv_clmulr_32:
1144 case RISCV::BI__builtin_riscv_clmulr_64:
1145 case RISCV::BI__builtin_riscv_xperm4_32:
1146 case RISCV::BI__builtin_riscv_xperm4_64:
1147 case RISCV::BI__builtin_riscv_xperm8_32:
1148 case RISCV::BI__builtin_riscv_xperm8_64:
1149 case RISCV::BI__builtin_riscv_brev8_32:
1150 case RISCV::BI__builtin_riscv_brev8_64:
1151 case RISCV::BI__builtin_riscv_zip_32:
1152 case RISCV::BI__builtin_riscv_unzip_32: {
1153 switch (BuiltinID) {
1154 default: llvm_unreachable(
"unexpected builtin ID");
1156 case RISCV::BI__builtin_riscv_orc_b_32:
1157 case RISCV::BI__builtin_riscv_orc_b_64:
1158 ID = Intrinsic::riscv_orc_b;
1162 case RISCV::BI__builtin_riscv_clmul_32:
1163 case RISCV::BI__builtin_riscv_clmul_64:
1164 ID = Intrinsic::clmul;
1166 case RISCV::BI__builtin_riscv_clmulh_32:
1167 case RISCV::BI__builtin_riscv_clmulh_64:
1168 ID = Intrinsic::riscv_clmulh;
1170 case RISCV::BI__builtin_riscv_clmulr_32:
1171 case RISCV::BI__builtin_riscv_clmulr_64:
1172 ID = Intrinsic::riscv_clmulr;
1176 case RISCV::BI__builtin_riscv_xperm8_32:
1177 case RISCV::BI__builtin_riscv_xperm8_64:
1178 ID = Intrinsic::riscv_xperm8;
1180 case RISCV::BI__builtin_riscv_xperm4_32:
1181 case RISCV::BI__builtin_riscv_xperm4_64:
1182 ID = Intrinsic::riscv_xperm4;
1186 case RISCV::BI__builtin_riscv_brev8_32:
1187 case RISCV::BI__builtin_riscv_brev8_64:
1188 ID = Intrinsic::riscv_brev8;
1190 case RISCV::BI__builtin_riscv_zip_32:
1191 ID = Intrinsic::riscv_zip;
1193 case RISCV::BI__builtin_riscv_unzip_32:
1194 ID = Intrinsic::riscv_unzip;
1198 IntrinsicTypes = {ResultType};
1203 case RISCV::BI__builtin_riscv_paadd_i8x4:
1204 case RISCV::BI__builtin_riscv_paadd_i16x2:
1205 case RISCV::BI__builtin_riscv_paadd_i8x8:
1206 case RISCV::BI__builtin_riscv_paadd_i16x4:
1207 case RISCV::BI__builtin_riscv_paadd_i32x2:
1208 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1209 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1210 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1211 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1212 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1213 case RISCV::BI__builtin_riscv_pasub_i8x4:
1214 case RISCV::BI__builtin_riscv_pasub_i16x2:
1215 case RISCV::BI__builtin_riscv_pasub_i8x8:
1216 case RISCV::BI__builtin_riscv_pasub_i16x4:
1217 case RISCV::BI__builtin_riscv_pasub_i32x2:
1218 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1219 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1220 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1221 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1222 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1224 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1225 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1226 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1227 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1228 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1229 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1230 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1231 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1232 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1233 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1234 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1235 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1236 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1237 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1238 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1239 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1240 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1241 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1243 case RISCV::BI__builtin_riscv_pabd_i8x4:
1244 case RISCV::BI__builtin_riscv_pabd_i16x2:
1245 case RISCV::BI__builtin_riscv_pabd_i8x8:
1246 case RISCV::BI__builtin_riscv_pabd_i16x4:
1247 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1248 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1249 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1250 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1252 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1253 case RISCV::BI__builtin_riscv_pmerge_i8x4:
1254 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1255 case RISCV::BI__builtin_riscv_pmerge_i16x2:
1256 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1257 case RISCV::BI__builtin_riscv_pmerge_i8x8:
1258 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1259 case RISCV::BI__builtin_riscv_pmerge_i16x4:
1260 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1261 case RISCV::BI__builtin_riscv_pmerge_i32x2:
1263 case RISCV::BI__builtin_riscv_psabs_i8x4:
1264 case RISCV::BI__builtin_riscv_psabs_i16x2:
1265 case RISCV::BI__builtin_riscv_psabs_i8x8:
1266 case RISCV::BI__builtin_riscv_psabs_i16x4: {
1267 switch (BuiltinID) {
1269 llvm_unreachable(
"unexpected builtin ID");
1270 case RISCV::BI__builtin_riscv_paadd_i8x4:
1271 case RISCV::BI__builtin_riscv_paadd_i16x2:
1272 case RISCV::BI__builtin_riscv_paadd_i8x8:
1273 case RISCV::BI__builtin_riscv_paadd_i16x4:
1274 case RISCV::BI__builtin_riscv_paadd_i32x2:
1275 ID = Intrinsic::riscv_paadd;
1277 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1278 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1279 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1280 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1281 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1282 ID = Intrinsic::riscv_paaddu;
1284 case RISCV::BI__builtin_riscv_pasub_i8x4:
1285 case RISCV::BI__builtin_riscv_pasub_i16x2:
1286 case RISCV::BI__builtin_riscv_pasub_i8x8:
1287 case RISCV::BI__builtin_riscv_pasub_i16x4:
1288 case RISCV::BI__builtin_riscv_pasub_i32x2:
1289 ID = Intrinsic::riscv_pasub;
1291 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1292 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1293 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1294 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1295 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1296 ID = Intrinsic::riscv_pasubu;
1298 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1299 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1300 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1301 ID = Intrinsic::riscv_pas;
1303 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1304 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1305 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1306 ID = Intrinsic::riscv_psa;
1308 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1309 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1310 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1311 ID = Intrinsic::riscv_psas;
1313 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1314 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1315 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1316 ID = Intrinsic::riscv_pssa;
1318 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1319 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1320 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1321 ID = Intrinsic::riscv_paas;
1323 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1324 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1325 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1326 ID = Intrinsic::riscv_pasa;
1328 case RISCV::BI__builtin_riscv_pabd_i8x4:
1329 case RISCV::BI__builtin_riscv_pabd_i16x2:
1330 case RISCV::BI__builtin_riscv_pabd_i8x8:
1331 case RISCV::BI__builtin_riscv_pabd_i16x4:
1332 ID = Intrinsic::riscv_pabd;
1334 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1335 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1336 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1337 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1338 ID = Intrinsic::riscv_pabdu;
1340 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1341 case RISCV::BI__builtin_riscv_pmerge_i8x4:
1342 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1343 case RISCV::BI__builtin_riscv_pmerge_i16x2:
1344 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1345 case RISCV::BI__builtin_riscv_pmerge_i8x8:
1346 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1347 case RISCV::BI__builtin_riscv_pmerge_i16x4:
1348 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1349 case RISCV::BI__builtin_riscv_pmerge_i32x2:
1350 ID = Intrinsic::riscv_pmerge;
1352 case RISCV::BI__builtin_riscv_psabs_i8x4:
1353 case RISCV::BI__builtin_riscv_psabs_i16x2:
1354 case RISCV::BI__builtin_riscv_psabs_i8x8:
1355 case RISCV::BI__builtin_riscv_psabs_i16x4:
1356 ID = Intrinsic::riscv_psabs;
1360 IntrinsicTypes = {ResultType};
1365 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1366 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1367 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1368 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1369 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1370 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1371 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1372 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1373 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1374 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1375 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1376 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1377 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1378 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: {
1379 switch (BuiltinID) {
1381 llvm_unreachable(
"unexpected builtin ID");
1382 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1383 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1384 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1385 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1386 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1387 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1388 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1389 ID = Intrinsic::riscv_predsum;
1391 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1392 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1393 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1394 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1395 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1396 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1397 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
1398 ID = Intrinsic::riscv_predsumu;
1402 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1407 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1408 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1409 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1410 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1411 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1412 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64: {
1413 switch (BuiltinID) {
1415 llvm_unreachable(
"unexpected builtin ID");
1416 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1417 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1418 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1419 ID = Intrinsic::riscv_pabdsumu;
1421 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1422 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1423 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64:
1424 ID = Intrinsic::riscv_pabdsumau;
1430 IntrinsicTypes = {ResultType, Ops.back()->getType()};
1437 case RISCV::BI__builtin_riscv_sha256sig0:
1438 ID = Intrinsic::riscv_sha256sig0;
1440 case RISCV::BI__builtin_riscv_sha256sig1:
1441 ID = Intrinsic::riscv_sha256sig1;
1443 case RISCV::BI__builtin_riscv_sha256sum0:
1444 ID = Intrinsic::riscv_sha256sum0;
1446 case RISCV::BI__builtin_riscv_sha256sum1:
1447 ID = Intrinsic::riscv_sha256sum1;
1451 case RISCV::BI__builtin_riscv_sm4ks:
1452 ID = Intrinsic::riscv_sm4ks;
1454 case RISCV::BI__builtin_riscv_sm4ed:
1455 ID = Intrinsic::riscv_sm4ed;
1459 case RISCV::BI__builtin_riscv_sm3p0:
1460 ID = Intrinsic::riscv_sm3p0;
1462 case RISCV::BI__builtin_riscv_sm3p1:
1463 ID = Intrinsic::riscv_sm3p1;
1466 case RISCV::BI__builtin_riscv_clz_32:
1467 case RISCV::BI__builtin_riscv_clz_64: {
1470 if (
Result->getType() != ResultType)
1475 case RISCV::BI__builtin_riscv_ctz_32:
1476 case RISCV::BI__builtin_riscv_ctz_64: {
1479 if (
Result->getType() != ResultType)
1486 case RISCV::BI__builtin_riscv_ntl_load: {
1488 unsigned DomainVal = 5;
1489 if (Ops.size() == 2)
1492 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1494 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1495 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1499 if(ResTy->isScalableTy()) {
1501 llvm::Type *ScalarTy = ResTy->getScalarType();
1502 Width = ScalarTy->getPrimitiveSizeInBits() *
1503 SVTy->getElementCount().getKnownMinValue();
1505 Width = ResTy->getPrimitiveSizeInBits();
1506 LoadInst *Load =
Builder.CreateLoad(
1509 Load->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1510 Load->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1515 case RISCV::BI__builtin_riscv_ntl_store: {
1516 unsigned DomainVal = 5;
1517 if (Ops.size() == 3)
1520 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1522 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1523 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1526 StoreInst *Store =
Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
1527 Store->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1528 Store->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1534 case RISCV::BI__builtin_riscv_pause: {
1535 llvm::Function *Fn =
CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
1536 return Builder.CreateCall(Fn, {});
1540 case RISCV::BI__builtin_riscv_cv_alu_addN:
1541 ID = Intrinsic::riscv_cv_alu_addN;
1543 case RISCV::BI__builtin_riscv_cv_alu_addRN:
1544 ID = Intrinsic::riscv_cv_alu_addRN;
1546 case RISCV::BI__builtin_riscv_cv_alu_adduN:
1547 ID = Intrinsic::riscv_cv_alu_adduN;
1549 case RISCV::BI__builtin_riscv_cv_alu_adduRN:
1550 ID = Intrinsic::riscv_cv_alu_adduRN;
1552 case RISCV::BI__builtin_riscv_cv_alu_clip:
1553 ID = Intrinsic::riscv_cv_alu_clip;
1555 case RISCV::BI__builtin_riscv_cv_alu_clipu:
1556 ID = Intrinsic::riscv_cv_alu_clipu;
1558 case RISCV::BI__builtin_riscv_cv_alu_extbs:
1561 case RISCV::BI__builtin_riscv_cv_alu_extbz:
1564 case RISCV::BI__builtin_riscv_cv_alu_exths:
1567 case RISCV::BI__builtin_riscv_cv_alu_exthz:
1570 case RISCV::BI__builtin_riscv_cv_alu_sle:
1573 case RISCV::BI__builtin_riscv_cv_alu_sleu:
1576 case RISCV::BI__builtin_riscv_cv_alu_subN:
1577 ID = Intrinsic::riscv_cv_alu_subN;
1579 case RISCV::BI__builtin_riscv_cv_alu_subRN:
1580 ID = Intrinsic::riscv_cv_alu_subRN;
1582 case RISCV::BI__builtin_riscv_cv_alu_subuN:
1583 ID = Intrinsic::riscv_cv_alu_subuN;
1585 case RISCV::BI__builtin_riscv_cv_alu_subuRN:
1586 ID = Intrinsic::riscv_cv_alu_subuRN;
1590 case RISCV::BI__builtin_riscv_nds_ffb_32:
1591 case RISCV::BI__builtin_riscv_nds_ffb_64:
1592 IntrinsicTypes = {ResultType};
1593 ID = Intrinsic::riscv_nds_ffb;
1595 case RISCV::BI__builtin_riscv_nds_ffzmism_32:
1596 case RISCV::BI__builtin_riscv_nds_ffzmism_64:
1597 IntrinsicTypes = {ResultType};
1598 ID = Intrinsic::riscv_nds_ffzmism;
1600 case RISCV::BI__builtin_riscv_nds_ffmism_32:
1601 case RISCV::BI__builtin_riscv_nds_ffmism_64:
1602 IntrinsicTypes = {ResultType};
1603 ID = Intrinsic::riscv_nds_ffmism;
1605 case RISCV::BI__builtin_riscv_nds_flmism_32:
1606 case RISCV::BI__builtin_riscv_nds_flmism_64:
1607 IntrinsicTypes = {ResultType};
1608 ID = Intrinsic::riscv_nds_flmism;
1612 case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
1614 case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
1618#include "clang/Basic/riscv_vector_builtin_cg.inc"
1621#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
1624#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
1627 assert(ID != Intrinsic::not_intrinsic);
1629 llvm::Function *F =
CGM.getIntrinsic(ID, IntrinsicTypes);
1630 return Builder.CreateCall(F, Ops,
"");