clang 24.0.0git
RISCV.cpp
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1//===-------- RISCV.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CodeGenFunction.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsRISCV.h"
16#include "llvm/TargetParser/RISCVISAInfo.h"
17#include "llvm/TargetParser/RISCVTargetParser.h"
18
19using namespace clang;
20using namespace CodeGen;
21using namespace llvm;
22
23// The 0th bit simulates the `vta` of RVV
24// The 1st bit simulates the `vma` of RVV
25static constexpr unsigned RVV_VTA = 0x1;
26static constexpr unsigned RVV_VMA = 0x2;
27
28// RISC-V Vector builtin helper functions are marked NOINLINE to prevent
29// excessive inlining in CodeGenFunction::EmitRISCVBuiltinExpr's large switch
30// statement, which would significantly increase compilation time.
31static LLVM_ATTRIBUTE_NOINLINE Value *
32emitRVVVLEFFBuiltin(CodeGenFunction *CGF, const CallExpr *E,
33 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
34 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
35 int PolicyAttrs, bool IsMasked) {
36 auto &Builder = CGF->Builder;
37 auto &CGM = CGF->CGM;
38 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
39 if (IsMasked) {
40 // Move mask to right before vl.
41 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
42 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
43 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
44 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
45 IntrinsicTypes = {ResultType, Ops[4]->getType(), Ops[2]->getType()};
46 } else {
47 if (PolicyAttrs & RVV_VTA)
48 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
49 IntrinsicTypes = {ResultType, Ops[3]->getType(), Ops[1]->getType()};
50 }
51 Value *NewVL = Ops[2];
52 Ops.erase(Ops.begin() + 2);
53 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
54 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
55 llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
56 // Store new_vl.
57 clang::CharUnits Align;
58 if (IsMasked)
59 Align = CGM.getNaturalPointeeTypeAlignment(
60 E->getArg(E->getNumArgs() - 2)->getType());
61 else
62 Align = CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
63 llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
64 Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
65 return V;
66}
67
68static LLVM_ATTRIBUTE_NOINLINE Value *
69emitRVVVSSEBuiltin(CodeGenFunction *CGF, const CallExpr *E,
70 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
71 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
72 int PolicyAttrs, bool IsMasked) {
73 auto &Builder = CGF->Builder;
74 auto &CGM = CGF->CGM;
75 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
76 if (IsMasked) {
77 // Builtin: (mask, ptr, stride, value, vl). Intrinsic: (value, ptr, stride,
78 // mask, vl)
79 std::swap(Ops[0], Ops[3]);
80 } else {
81 // Builtin: (ptr, stride, value, vl). Intrinsic: (value, ptr, stride, vl)
82 std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
83 }
84 if (IsMasked)
85 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[4]->getType()};
86 else
87 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[3]->getType()};
88 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
89 return Builder.CreateCall(F, Ops, "");
90}
91
92static LLVM_ATTRIBUTE_NOINLINE Value *
93emitRVVIndexedStoreBuiltin(CodeGenFunction *CGF, const CallExpr *E,
94 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
95 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
96 int PolicyAttrs, bool IsMasked) {
97 auto &Builder = CGF->Builder;
98 auto &CGM = CGF->CGM;
99 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
100 if (IsMasked) {
101 // Builtin: (mask, ptr, index, value, vl).
102 // Intrinsic: (value, ptr, index, mask, vl)
103 std::swap(Ops[0], Ops[3]);
104 } else {
105 // Builtin: (ptr, index, value, vl).
106 // Intrinsic: (value, ptr, index, vl)
107 std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
108 }
109 if (IsMasked)
110 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
111 Ops[4]->getType()};
112 else
113 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
114 Ops[3]->getType()};
115 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
116 return Builder.CreateCall(F, Ops, "");
117}
118
119static LLVM_ATTRIBUTE_NOINLINE Value *
120emitRVVPseudoUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E,
121 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
122 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
123 int PolicyAttrs, bool IsMasked) {
124 auto &Builder = CGF->Builder;
125 auto &CGM = CGF->CGM;
126 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
127 if (IsMasked) {
128 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
129 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
130 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
131 } else {
132 if (PolicyAttrs & RVV_VTA)
133 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
134 }
135 auto ElemTy = cast<llvm::VectorType>(ResultType)->getElementType();
136 Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(ElemTy));
137 if (IsMasked) {
138 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
139 // maskedoff, op1, op2, mask, vl, policy
140 IntrinsicTypes = {ResultType, ElemTy, Ops[4]->getType()};
141 } else {
142 // passthru, op1, op2, vl
143 IntrinsicTypes = {ResultType, ElemTy, Ops[3]->getType()};
144 }
145 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
146 return Builder.CreateCall(F, Ops, "");
147}
148
149static LLVM_ATTRIBUTE_NOINLINE Value *
150emitRVVPseudoVNotBuiltin(CodeGenFunction *CGF, const CallExpr *E,
151 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
152 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
153 int PolicyAttrs, bool IsMasked) {
154 auto &Builder = CGF->Builder;
155 auto &CGM = CGF->CGM;
156 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
157 if (IsMasked) {
158 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
159 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
160 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
161 } else {
162 if (PolicyAttrs & RVV_VTA)
163 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
164 }
165 auto ElemTy = cast<llvm::VectorType>(ResultType)->getElementType();
166 Ops.insert(Ops.begin() + 2, llvm::Constant::getAllOnesValue(ElemTy));
167 if (IsMasked) {
168 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
169 // maskedoff, op1, po2, mask, vl, policy
170 IntrinsicTypes = {ResultType, ElemTy, Ops[4]->getType()};
171 } else {
172 // passthru, op1, op2, vl
173 IntrinsicTypes = {ResultType, ElemTy, Ops[3]->getType()};
174 }
175 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
176 return Builder.CreateCall(F, Ops, "");
177}
178
179static LLVM_ATTRIBUTE_NOINLINE Value *
180emitRVVPseudoMaskBuiltin(CodeGenFunction *CGF, const CallExpr *E,
181 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
182 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
183 int PolicyAttrs, bool IsMasked) {
184 auto &Builder = CGF->Builder;
185 auto &CGM = CGF->CGM;
186 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
187 // op1, vl
188 IntrinsicTypes = {ResultType, Ops[1]->getType()};
189 Ops.insert(Ops.begin() + 1, Ops[0]);
190 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
191 return Builder.CreateCall(F, Ops, "");
192}
193
194static LLVM_ATTRIBUTE_NOINLINE Value *
195emitRVVPseudoVFUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E,
196 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
197 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
198 int PolicyAttrs, bool IsMasked) {
199 auto &Builder = CGF->Builder;
200 auto &CGM = CGF->CGM;
201 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
202 if (IsMasked) {
203 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
204 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
205 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
206 Ops.insert(Ops.begin() + 2, Ops[1]);
207 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
208 // maskedoff, op1, op2, mask, vl
209 IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops.back()->getType()};
210 } else {
211 if (PolicyAttrs & RVV_VTA)
212 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
213 // op1, po2, vl
214 IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
215 Ops.insert(Ops.begin() + 2, Ops[1]);
216 }
217 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
218 return Builder.CreateCall(F, Ops, "");
219}
220
221static LLVM_ATTRIBUTE_NOINLINE Value *
222emitRVVPseudoVWCVTBuiltin(CodeGenFunction *CGF, const CallExpr *E,
223 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
224 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
225 int PolicyAttrs, bool IsMasked) {
226 auto &Builder = CGF->Builder;
227 auto &CGM = CGF->CGM;
228 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
229 if (IsMasked) {
230 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
231 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
232 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
233 } else {
234 if (PolicyAttrs & RVV_VTA)
235 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
236 }
237 auto ElemTy = cast<llvm::VectorType>(Ops[1]->getType())->getElementType();
238 Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(ElemTy));
239 if (IsMasked) {
240 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
241 // maskedoff, op1, op2, mask, vl, policy
242 IntrinsicTypes = {ResultType, Ops[1]->getType(), ElemTy, Ops[4]->getType()};
243 } else {
244 // passtru, op1, op2, vl
245 IntrinsicTypes = {ResultType, Ops[1]->getType(), ElemTy, Ops[3]->getType()};
246 }
247 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
248 return Builder.CreateCall(F, Ops, "");
249}
250
251static LLVM_ATTRIBUTE_NOINLINE Value *
252emitRVVPseudoVNCVTBuiltin(CodeGenFunction *CGF, const CallExpr *E,
253 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
254 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
255 int PolicyAttrs, bool IsMasked) {
256 auto &Builder = CGF->Builder;
257 auto &CGM = CGF->CGM;
258 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
259 if (IsMasked) {
260 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
261 if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
262 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
263 } else {
264 if (PolicyAttrs & RVV_VTA)
265 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
266 }
267 Ops.insert(Ops.begin() + 2,
268 llvm::Constant::getNullValue(Ops.back()->getType()));
269 if (IsMasked) {
270 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
271 // maskedoff, op1, xlen, mask, vl
272 IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[4]->getType(),
273 Ops[4]->getType()};
274 } else {
275 // passthru, op1, xlen, vl
276 IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType(),
277 Ops[3]->getType()};
278 }
279 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
280 return Builder.CreateCall(F, Ops, "");
281}
282
283static LLVM_ATTRIBUTE_NOINLINE Value *
284emitRVVVlenbBuiltin(CodeGenFunction *CGF, const CallExpr *E,
285 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
286 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
287 int PolicyAttrs, bool IsMasked) {
288 auto &Builder = CGF->Builder;
289 auto &CGM = CGF->CGM;
290 LLVMContext &Context = CGM.getLLVMContext();
291 llvm::MDBuilder MDHelper(Context);
292 llvm::Metadata *OpsMD[] = {llvm::MDString::get(Context, "vlenb")};
293 llvm::MDNode *RegName = llvm::MDNode::get(Context, OpsMD);
294 llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
295 llvm::Function *F =
296 CGM.getIntrinsic(llvm::Intrinsic::read_register, {CGF->SizeTy});
297 return Builder.CreateCall(F, Metadata);
298}
299
300static LLVM_ATTRIBUTE_NOINLINE Value *
301emitRVVVsetvliBuiltin(CodeGenFunction *CGF, const CallExpr *E,
302 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
303 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
304 int PolicyAttrs, bool IsMasked) {
305 auto &Builder = CGF->Builder;
306 auto &CGM = CGF->CGM;
307 llvm::Function *F = CGM.getIntrinsic(ID, {ResultType});
308 return Builder.CreateCall(F, Ops, "");
309}
310
311static LLVM_ATTRIBUTE_NOINLINE Value *
312emitRVVVSEMaskBuiltin(CodeGenFunction *CGF, const CallExpr *E,
313 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
314 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
315 int PolicyAttrs, bool IsMasked) {
316 auto &Builder = CGF->Builder;
317 auto &CGM = CGF->CGM;
318 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
319 if (IsMasked) {
320 // Builtin: (mask, ptr, value, vl).
321 // Intrinsic: (value, ptr, mask, vl)
322 std::swap(Ops[0], Ops[2]);
323 } else {
324 // Builtin: (ptr, value, vl).
325 // Intrinsic: (value, ptr, vl)
326 std::swap(Ops[0], Ops[1]);
327 }
328 if (IsMasked)
329 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[3]->getType()};
330 else
331 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType()};
332 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
333 return Builder.CreateCall(F, Ops, "");
334}
335
336static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVUnitStridedSegLoadTupleBuiltin(
337 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
338 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
339 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
340 auto &Builder = CGF->Builder;
341 auto &CGM = CGF->CGM;
342 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
343 bool NoPassthru =
344 (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) |
345 (!IsMasked && (PolicyAttrs & RVV_VTA));
346 unsigned Offset = IsMasked ? NoPassthru ? 1 : 2 : NoPassthru ? 0 : 1;
347 if (IsMasked)
348 IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops[0]->getType(),
349 Ops.back()->getType()};
350 else
351 IntrinsicTypes = {ResultType, Ops[Offset]->getType(),
352 Ops.back()->getType()};
353 if (IsMasked)
354 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
355 if (NoPassthru)
356 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
357 if (IsMasked)
358 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
359 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
360 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
361 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
362 if (ReturnValue.isNull())
363 return LoadValue;
364 return Builder.CreateStore(LoadValue, ReturnValue.getValue());
365}
366
367static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVUnitStridedSegStoreTupleBuiltin(
368 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
369 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
370 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
371 auto &Builder = CGF->Builder;
372 auto &CGM = CGF->CGM;
373 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
374 // Masked
375 // Builtin: (mask, ptr, v_tuple, vl)
376 // Intrinsic: (tuple, ptr, mask, vl, SegInstSEW)
377 // Unmasked
378 // Builtin: (ptr, v_tuple, vl)
379 // Intrinsic: (tuple, ptr, vl, SegInstSEW)
380 if (IsMasked)
381 std::swap(Ops[0], Ops[2]);
382 else
383 std::swap(Ops[0], Ops[1]);
384 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
385 if (IsMasked)
386 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
387 Ops[3]->getType()};
388 else
389 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType()};
390 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
391 return Builder.CreateCall(F, Ops, "");
392}
393
394static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVUnitStridedSegLoadFFTupleBuiltin(
395 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
396 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
397 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
398 auto &Builder = CGF->Builder;
399 auto &CGM = CGF->CGM;
400 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
401 bool NoPassthru =
402 (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) |
403 (!IsMasked && (PolicyAttrs & RVV_VTA));
404 unsigned Offset = IsMasked ? NoPassthru ? 1 : 2 : NoPassthru ? 0 : 1;
405 if (IsMasked)
406 IntrinsicTypes = {ResultType, Ops.back()->getType(), Ops[Offset]->getType(),
407 Ops[0]->getType()};
408 else
409 IntrinsicTypes = {ResultType, Ops.back()->getType(),
410 Ops[Offset]->getType()};
411 if (IsMasked)
412 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
413 if (NoPassthru)
414 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
415 if (IsMasked)
416 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
417 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
418 Value *NewVL = Ops[2];
419 Ops.erase(Ops.begin() + 2);
420 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
421 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
422 // Get alignment from the new vl operand
423 clang::CharUnits Align =
424 CGM.getNaturalPointeeTypeAlignment(E->getArg(Offset + 1)->getType());
425 llvm::Value *ReturnTuple = Builder.CreateExtractValue(LoadValue, 0);
426 // Store new_vl
427 llvm::Value *V = Builder.CreateExtractValue(LoadValue, 1);
428 Builder.CreateStore(V, Address(NewVL, V->getType(), Align));
429 if (ReturnValue.isNull())
430 return ReturnTuple;
431 return Builder.CreateStore(ReturnTuple, ReturnValue.getValue());
432}
433
434static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVStridedSegLoadTupleBuiltin(
435 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
436 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
437 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
438 auto &Builder = CGF->Builder;
439 auto &CGM = CGF->CGM;
440 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
441 bool NoPassthru =
442 (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) |
443 (!IsMasked && (PolicyAttrs & RVV_VTA));
444 unsigned Offset = IsMasked ? NoPassthru ? 1 : 2 : NoPassthru ? 0 : 1;
445 if (IsMasked)
446 IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops.back()->getType(),
447 Ops[0]->getType()};
448 else
449 IntrinsicTypes = {ResultType, Ops[Offset]->getType(),
450 Ops.back()->getType()};
451 if (IsMasked)
452 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
453 if (NoPassthru)
454 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
455 if (IsMasked)
456 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
457 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
458 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
459 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
460 if (ReturnValue.isNull())
461 return LoadValue;
462 return Builder.CreateStore(LoadValue, ReturnValue.getValue());
463}
464
465static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVStridedSegStoreTupleBuiltin(
466 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
467 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
468 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
469 auto &Builder = CGF->Builder;
470 auto &CGM = CGF->CGM;
471 llvm::SmallVector<llvm::Type *, 4> IntrinsicTypes;
472 // Masked
473 // Builtin: (mask, ptr, stride, v_tuple, vl)
474 // Intrinsic: (tuple, ptr, stride, mask, vl, SegInstSEW)
475 // Unmasked
476 // Builtin: (ptr, stride, v_tuple, vl)
477 // Intrinsic: (tuple, ptr, stride, vl, SegInstSEW)
478 if (IsMasked)
479 std::swap(Ops[0], Ops[3]);
480 else
481 std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
482 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
483 if (IsMasked)
484 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[4]->getType(),
485 Ops[3]->getType()};
486 else
487 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[3]->getType()};
488 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
489 return Builder.CreateCall(F, Ops, "");
490}
491
492static LLVM_ATTRIBUTE_NOINLINE Value *
493emitRVVAveragingBuiltin(CodeGenFunction *CGF, const CallExpr *E,
494 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
495 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
496 int PolicyAttrs, bool IsMasked) {
497 auto &Builder = CGF->Builder;
498 auto &CGM = CGF->CGM;
499 // LLVM intrinsic
500 // Unmasked: (passthru, op0, op1, round_mode, vl)
501 // Masked: (passthru, vector_in, vector_in/scalar_in, mask, vxrm, vl,
502 // policy)
503
504 bool HasMaskedOff =
505 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
506 (!IsMasked && PolicyAttrs & RVV_VTA));
507
508 if (IsMasked)
509 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
510
511 if (!HasMaskedOff)
512 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
513
514 if (IsMasked)
515 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
516
517 llvm::Function *F = CGM.getIntrinsic(
518 ID, {ResultType, Ops[2]->getType(), Ops.back()->getType()});
519 return Builder.CreateCall(F, Ops, "");
520}
521
522static LLVM_ATTRIBUTE_NOINLINE Value *
523emitRVVNarrowingClipBuiltin(CodeGenFunction *CGF, const CallExpr *E,
524 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
525 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
526 int PolicyAttrs, bool IsMasked) {
527 auto &Builder = CGF->Builder;
528 auto &CGM = CGF->CGM;
529 // LLVM intrinsic
530 // Unmasked: (passthru, op0, op1, round_mode, vl)
531 // Masked: (passthru, vector_in, vector_in/scalar_in, mask, vxrm, vl,
532 // policy)
533
534 bool HasMaskedOff =
535 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
536 (!IsMasked && PolicyAttrs & RVV_VTA));
537
538 if (IsMasked)
539 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
540
541 if (!HasMaskedOff)
542 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
543
544 if (IsMasked)
545 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
546
547 llvm::Function *F =
548 CGM.getIntrinsic(ID, {ResultType, Ops[1]->getType(), Ops[2]->getType(),
549 Ops.back()->getType()});
550 return Builder.CreateCall(F, Ops, "");
551}
552
553static LLVM_ATTRIBUTE_NOINLINE Value *
554emitRVVFloatingPointBuiltin(CodeGenFunction *CGF, const CallExpr *E,
555 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
556 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
557 int PolicyAttrs, bool IsMasked) {
558 auto &Builder = CGF->Builder;
559 auto &CGM = CGF->CGM;
560 // LLVM intrinsic
561 // Unmasked: (passthru, op0, op1, round_mode, vl)
562 // Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
563
564 bool HasMaskedOff =
565 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
566 (!IsMasked && PolicyAttrs & RVV_VTA));
567 bool HasRoundModeOp =
568 IsMasked ? (HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5)
569 : (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
570
571 if (!HasRoundModeOp)
572 Ops.insert(Ops.end() - 1,
573 ConstantInt::get(Ops.back()->getType(), 7)); // frm
574
575 if (IsMasked)
576 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
577
578 if (!HasMaskedOff)
579 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
580
581 if (IsMasked)
582 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
583
584 llvm::Function *F = CGM.getIntrinsic(
585 ID, {ResultType, Ops[2]->getType(), Ops.back()->getType()});
586 return Builder.CreateCall(F, Ops, "");
587}
588
589static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVWideningFloatingPointBuiltin(
590 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
591 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
592 int PolicyAttrs, bool IsMasked) {
593 auto &Builder = CGF->Builder;
594 auto &CGM = CGF->CGM;
595 // LLVM intrinsic
596 // Unmasked: (passthru, op0, op1, round_mode, vl)
597 // Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
598
599 bool HasMaskedOff =
600 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
601 (!IsMasked && PolicyAttrs & RVV_VTA));
602 bool HasRoundModeOp =
603 IsMasked ? (HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5)
604 : (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
605
606 if (!HasRoundModeOp)
607 Ops.insert(Ops.end() - 1,
608 ConstantInt::get(Ops.back()->getType(), 7)); // frm
609
610 if (IsMasked)
611 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
612
613 if (!HasMaskedOff)
614 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
615
616 if (IsMasked)
617 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
618
619 llvm::Function *F =
620 CGM.getIntrinsic(ID, {ResultType, Ops[1]->getType(), Ops[2]->getType(),
621 Ops.back()->getType()});
622 return Builder.CreateCall(F, Ops, "");
623}
624
625static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVIndexedSegLoadTupleBuiltin(
626 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
627 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
628 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
629 auto &Builder = CGF->Builder;
630 auto &CGM = CGF->CGM;
631 llvm::SmallVector<llvm::Type *, 5> IntrinsicTypes;
632
633 bool NoPassthru =
634 (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) |
635 (!IsMasked && (PolicyAttrs & RVV_VTA));
636
637 if (IsMasked)
638 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
639 if (NoPassthru)
640 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
641
642 if (IsMasked)
643 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
644 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
645
646 if (IsMasked)
647 IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType(),
648 Ops[3]->getType(), Ops[4]->getType()};
649 else
650 IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType(),
651 Ops[3]->getType()};
652 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
653 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
654
655 if (ReturnValue.isNull())
656 return LoadValue;
657 return Builder.CreateStore(LoadValue, ReturnValue.getValue());
658}
659
660static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVIndexedSegStoreTupleBuiltin(
661 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
662 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
663 int PolicyAttrs, bool IsMasked, unsigned SegInstSEW) {
664 auto &Builder = CGF->Builder;
665 auto &CGM = CGF->CGM;
666 llvm::SmallVector<llvm::Type *, 5> IntrinsicTypes;
667 // Masked
668 // Builtin: (mask, ptr, index, v_tuple, vl)
669 // Intrinsic: (tuple, ptr, index, mask, vl, SegInstSEW)
670 // Unmasked
671 // Builtin: (ptr, index, v_tuple, vl)
672 // Intrinsic: (tuple, ptr, index, vl, SegInstSEW)
673
674 if (IsMasked)
675 std::swap(Ops[0], Ops[3]);
676 else
677 std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
678
679 Ops.push_back(ConstantInt::get(Ops.back()->getType(), SegInstSEW));
680
681 if (IsMasked)
682 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
683 Ops[3]->getType(), Ops[4]->getType()};
684 else
685 IntrinsicTypes = {Ops[0]->getType(), Ops[1]->getType(), Ops[2]->getType(),
686 Ops[3]->getType()};
687 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
688 return Builder.CreateCall(F, Ops, "");
689}
690
691static LLVM_ATTRIBUTE_NOINLINE Value *
692emitRVVFMABuiltin(CodeGenFunction *CGF, const CallExpr *E,
693 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
694 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
695 int PolicyAttrs, bool IsMasked) {
696 auto &Builder = CGF->Builder;
697 auto &CGM = CGF->CGM;
698 // LLVM intrinsic
699 // Unmasked: (vector_in, vector_in/scalar_in, vector_in, round_mode,
700 // vl, policy)
701 // Masked: (vector_in, vector_in/scalar_in, vector_in, mask, frm,
702 // vl, policy)
703
704 bool HasRoundModeOp = IsMasked ? Ops.size() == 6 : Ops.size() == 5;
705
706 if (!HasRoundModeOp)
707 Ops.insert(Ops.end() - 1,
708 ConstantInt::get(Ops.back()->getType(), 7)); // frm
709
710 if (IsMasked)
711 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
712
713 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
714
715 llvm::Function *F = CGM.getIntrinsic(
716 ID, {ResultType, Ops[1]->getType(), Ops.back()->getType()});
717 return Builder.CreateCall(F, Ops, "");
718}
719
720static LLVM_ATTRIBUTE_NOINLINE Value *
721emitRVVWideningFMABuiltin(CodeGenFunction *CGF, const CallExpr *E,
722 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
723 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
724 int PolicyAttrs, bool IsMasked) {
725 auto &Builder = CGF->Builder;
726 auto &CGM = CGF->CGM;
727 // LLVM intrinsic
728 // Unmasked: (vector_in, vector_in/scalar_in, vector_in, round_mode, vl,
729 // policy) Masked: (vector_in, vector_in/scalar_in, vector_in, mask, frm,
730 // vl, policy)
731
732 bool HasRoundModeOp = IsMasked ? Ops.size() == 6 : Ops.size() == 5;
733
734 if (!HasRoundModeOp)
735 Ops.insert(Ops.end() - 1,
736 ConstantInt::get(Ops.back()->getType(), 7)); // frm
737
738 if (IsMasked)
739 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 4);
740
741 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
742
743 llvm::Function *F =
744 CGM.getIntrinsic(ID, {ResultType, Ops[1]->getType(), Ops[2]->getType(),
745 Ops.back()->getType()});
746 return Builder.CreateCall(F, Ops, "");
747}
748
749static LLVM_ATTRIBUTE_NOINLINE Value *
750emitRVVFloatingUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E,
751 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
752 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
753 int PolicyAttrs, bool IsMasked) {
754 auto &Builder = CGF->Builder;
755 auto &CGM = CGF->CGM;
756 llvm::SmallVector<llvm::Type *, 3> IntrinsicTypes;
757 // LLVM intrinsic
758 // Unmasked: (passthru, op0, round_mode, vl)
759 // Masked: (passthru, op0, mask, frm, vl, policy)
760
761 bool HasMaskedOff =
762 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
763 (!IsMasked && PolicyAttrs & RVV_VTA));
764 bool HasRoundModeOp =
765 IsMasked ? (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4)
766 : (HasMaskedOff ? Ops.size() == 4 : Ops.size() == 3);
767
768 if (!HasRoundModeOp)
769 Ops.insert(Ops.end() - 1,
770 ConstantInt::get(Ops.back()->getType(), 7)); // frm
771
772 if (IsMasked)
773 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
774
775 if (!HasMaskedOff)
776 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
777
778 if (IsMasked)
779 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
780
781 IntrinsicTypes = {ResultType, Ops.back()->getType()};
782 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
783 return Builder.CreateCall(F, Ops, "");
784}
785
786static LLVM_ATTRIBUTE_NOINLINE Value *
787emitRVVFloatingConvBuiltin(CodeGenFunction *CGF, const CallExpr *E,
788 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
789 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
790 int PolicyAttrs, bool IsMasked) {
791 auto &Builder = CGF->Builder;
792 auto &CGM = CGF->CGM;
793 // LLVM intrinsic
794 // Unmasked: (passthru, op0, frm, vl)
795 // Masked: (passthru, op0, mask, frm, vl, policy)
796 bool HasMaskedOff =
797 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
798 (!IsMasked && PolicyAttrs & RVV_VTA));
799 bool HasRoundModeOp =
800 IsMasked ? (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4)
801 : (HasMaskedOff ? Ops.size() == 4 : Ops.size() == 3);
802
803 if (!HasRoundModeOp)
804 Ops.insert(Ops.end() - 1,
805 ConstantInt::get(Ops.back()->getType(), 7)); // frm
806
807 if (IsMasked)
808 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
809
810 if (!HasMaskedOff)
811 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
812
813 if (IsMasked)
814 Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
815
816 llvm::Function *F = CGM.getIntrinsic(
817 ID, {ResultType, Ops[1]->getType(), Ops.back()->getType()});
818 return Builder.CreateCall(F, Ops, "");
819}
820
821static LLVM_ATTRIBUTE_NOINLINE Value *emitRVVFloatingReductionBuiltin(
822 CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue,
823 llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
824 int PolicyAttrs, bool IsMasked) {
825 auto &Builder = CGF->Builder;
826 auto &CGM = CGF->CGM;
827 // LLVM intrinsic
828 // Unmasked: (passthru, op0, op1, round_mode, vl)
829 // Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
830
831 bool HasMaskedOff =
832 !((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
833 (!IsMasked && PolicyAttrs & RVV_VTA));
834 bool HasRoundModeOp =
835 IsMasked ? (HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5)
836 : (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
837
838 if (!HasRoundModeOp)
839 Ops.insert(Ops.end() - 1,
840 ConstantInt::get(Ops.back()->getType(), 7)); // frm
841
842 if (IsMasked)
843 std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
844
845 if (!HasMaskedOff)
846 Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
847
848 llvm::Function *F = CGM.getIntrinsic(
849 ID, {ResultType, Ops[1]->getType(), Ops.back()->getType()});
850 return Builder.CreateCall(F, Ops, "");
851}
852
853static LLVM_ATTRIBUTE_NOINLINE Value *
854emitRVVReinterpretBuiltin(CodeGenFunction *CGF, const CallExpr *E,
855 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
856 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
857 int PolicyAttrs, bool IsMasked) {
858 auto &Builder = CGF->Builder;
859 auto &CGM = CGF->CGM;
860
861 if (ResultType->isIntOrIntVectorTy(1) ||
862 Ops[0]->getType()->isIntOrIntVectorTy(1)) {
863 assert(isa<ScalableVectorType>(ResultType) &&
864 isa<ScalableVectorType>(Ops[0]->getType()));
865
866 LLVMContext &Context = CGM.getLLVMContext();
867 ScalableVectorType *Boolean64Ty =
868 ScalableVectorType::get(llvm::Type::getInt1Ty(Context), 64);
869
870 if (ResultType->isIntOrIntVectorTy(1)) {
871 // Casting from m1 vector integer -> vector boolean
872 // Ex: <vscale x 8 x i8>
873 // --(bitcast)--------> <vscale x 64 x i1>
874 // --(vector_extract)-> <vscale x 8 x i1>
875 llvm::Value *BitCast = Builder.CreateBitCast(Ops[0], Boolean64Ty);
876 return Builder.CreateExtractVector(ResultType, BitCast,
877 ConstantInt::get(CGF->Int64Ty, 0));
878 } else {
879 // Casting from vector boolean -> m1 vector integer
880 // Ex: <vscale x 1 x i1>
881 // --(vector_insert)-> <vscale x 64 x i1>
882 // --(bitcast)-------> <vscale x 8 x i8>
883 llvm::Value *Boolean64Val = Builder.CreateInsertVector(
884 Boolean64Ty, llvm::PoisonValue::get(Boolean64Ty), Ops[0],
885 ConstantInt::get(CGF->Int64Ty, 0));
886 return Builder.CreateBitCast(Boolean64Val, ResultType);
887 }
888 }
889 return Builder.CreateBitCast(Ops[0], ResultType);
890}
891
892static LLVM_ATTRIBUTE_NOINLINE Value *
893emitRVVGetBuiltin(CodeGenFunction *CGF, const CallExpr *E,
894 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
895 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
896 int PolicyAttrs, bool IsMasked) {
897 auto &Builder = CGF->Builder;
898 auto *VecTy = cast<ScalableVectorType>(ResultType);
899 if (auto *OpVecTy = dyn_cast<ScalableVectorType>(Ops[0]->getType())) {
900 unsigned MaxIndex =
901 OpVecTy->getMinNumElements() / VecTy->getMinNumElements();
902 assert(isPowerOf2_32(MaxIndex));
903 // Mask to only valid indices.
904 Ops[1] = Builder.CreateZExt(Ops[1], Builder.getInt64Ty());
905 Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1);
906 Ops[1] =
907 Builder.CreateMul(Ops[1], ConstantInt::get(Ops[1]->getType(),
908 VecTy->getMinNumElements()));
909 return Builder.CreateExtractVector(ResultType, Ops[0], Ops[1]);
910 }
911
912 return Builder.CreateIntrinsic(
913 Intrinsic::riscv_tuple_extract, {ResultType, Ops[0]->getType()},
914 {Ops[0], Builder.CreateTrunc(Ops[1], Builder.getInt32Ty())});
915}
916
917static LLVM_ATTRIBUTE_NOINLINE Value *
918emitRVVSetBuiltin(CodeGenFunction *CGF, const CallExpr *E,
919 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
920 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
921 int PolicyAttrs, bool IsMasked) {
922 auto &Builder = CGF->Builder;
923 if (auto *ResVecTy = dyn_cast<ScalableVectorType>(ResultType)) {
924 auto *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
925 unsigned MaxIndex =
926 ResVecTy->getMinNumElements() / VecTy->getMinNumElements();
927 assert(isPowerOf2_32(MaxIndex));
928 // Mask to only valid indices.
929 Ops[1] = Builder.CreateZExt(Ops[1], Builder.getInt64Ty());
930 Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1);
931 Ops[1] =
932 Builder.CreateMul(Ops[1], ConstantInt::get(Ops[1]->getType(),
933 VecTy->getMinNumElements()));
934 return Builder.CreateInsertVector(ResultType, Ops[0], Ops[2], Ops[1]);
935 }
936
937 return Builder.CreateIntrinsic(
938 Intrinsic::riscv_tuple_insert, {ResultType, Ops[2]->getType()},
939 {Ops[0], Ops[2], Builder.CreateTrunc(Ops[1], Builder.getInt32Ty())});
940}
941
942static LLVM_ATTRIBUTE_NOINLINE Value *
943emitRVVCreateBuiltin(CodeGenFunction *CGF, const CallExpr *E,
944 ReturnValueSlot ReturnValue, llvm::Type *ResultType,
945 Intrinsic::ID ID, SmallVectorImpl<Value *> &Ops,
946 int PolicyAttrs, bool IsMasked) {
947 auto &Builder = CGF->Builder;
948 llvm::Value *ReturnVector = llvm::PoisonValue::get(ResultType);
949 auto *VecTy = cast<ScalableVectorType>(Ops[0]->getType());
950 for (unsigned I = 0, N = Ops.size(); I < N; ++I) {
951 if (isa<ScalableVectorType>(ResultType)) {
952 llvm::Value *Idx = ConstantInt::get(Builder.getInt64Ty(),
953 VecTy->getMinNumElements() * I);
954 ReturnVector =
955 Builder.CreateInsertVector(ResultType, ReturnVector, Ops[I], Idx);
956 } else {
957 llvm::Value *Idx = ConstantInt::get(Builder.getInt32Ty(), I);
958 ReturnVector = Builder.CreateIntrinsic(Intrinsic::riscv_tuple_insert,
959 {ResultType, Ops[I]->getType()},
960 {ReturnVector, Ops[I], Idx});
961 }
962 }
963 return ReturnVector;
964}
965
966Value *CodeGenFunction::EmitRISCVCpuInit() {
967 llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, {VoidPtrTy}, false);
968 llvm::FunctionCallee Func =
969 CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
970 auto *CalleeGV = cast<llvm::GlobalValue>(Func.getCallee());
971 CalleeGV->setDSOLocal(true);
972 CalleeGV->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
973 return Builder.CreateCall(Func, {llvm::ConstantPointerNull::get(VoidPtrTy)});
974}
975
976Value *CodeGenFunction::EmitRISCVCpuSupports(const CallExpr *E) {
977
978 const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
979 StringRef FeatureStr = cast<StringLiteral>(FeatureExpr)->getString();
980 if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
981 return Builder.getFalse();
982
983 return EmitRISCVCpuSupports(ArrayRef<StringRef>(FeatureStr));
984}
985
986static Value *loadRISCVFeatureBits(unsigned Index, CGBuilderTy &Builder,
987 CodeGenModule &CGM) {
988 llvm::Type *Int32Ty = Builder.getInt32Ty();
989 llvm::Type *Int64Ty = Builder.getInt64Ty();
990 llvm::ArrayType *ArrayOfInt64Ty =
991 llvm::ArrayType::get(Int64Ty, llvm::RISCVISAInfo::FeatureBitSize);
992 llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
993 llvm::Constant *RISCVFeaturesBits =
994 CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
995 cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
996 Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
997 llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
998 IndexVal};
999 Value *Ptr =
1000 Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
1001 Value *FeaturesBit =
1002 Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
1003 return FeaturesBit;
1004}
1005
1006Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs) {
1007 const unsigned RISCVFeatureLength = llvm::RISCVISAInfo::FeatureBitSize;
1008 uint64_t RequireBitMasks[RISCVFeatureLength] = {0};
1009
1010 for (auto Feat : FeaturesStrs) {
1011 auto [GroupID, BitPos] = RISCVISAInfo::getRISCVFeaturesBitsInfo(Feat);
1012
1013 // If there isn't BitPos for this feature, skip this version.
1014 // It also report the warning to user during compilation.
1015 if (BitPos == -1)
1016 return Builder.getFalse();
1017
1018 RequireBitMasks[GroupID] |= (1ULL << BitPos);
1019 }
1020
1021 Value *Result = nullptr;
1022 for (unsigned Idx = 0; Idx < RISCVFeatureLength; Idx++) {
1023 if (RequireBitMasks[Idx] == 0)
1024 continue;
1025
1026 Value *Mask = Builder.getInt64(RequireBitMasks[Idx]);
1027 Value *Bitset =
1028 Builder.CreateAnd(loadRISCVFeatureBits(Idx, Builder, CGM), Mask);
1029 Value *CmpV = Builder.CreateICmpEQ(Bitset, Mask);
1030 Result = (!Result) ? CmpV : Builder.CreateAnd(Result, CmpV);
1031 }
1032
1033 assert(Result && "Should have value here.");
1034
1035 return Result;
1036}
1037
1038Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) {
1039 const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
1040 StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
1041 return EmitRISCVCpuIs(CPUStr);
1042}
1043
1044Value *CodeGenFunction::EmitRISCVCpuIs(StringRef CPUStr) {
1045 llvm::Type *Int32Ty = Builder.getInt32Ty();
1046 llvm::Type *Int64Ty = Builder.getInt64Ty();
1047 llvm::StructType *StructTy = llvm::StructType::get(Int32Ty, Int64Ty, Int64Ty);
1048 llvm::Constant *RISCVCPUModel =
1049 CGM.CreateRuntimeVariable(StructTy, "__riscv_cpu_model");
1050 cast<llvm::GlobalValue>(RISCVCPUModel)->setDSOLocal(true);
1051
1052 auto loadRISCVCPUID = [&](unsigned Index) {
1053 Value *Ptr = Builder.CreateStructGEP(StructTy, RISCVCPUModel, Index);
1054 Value *CPUID = Builder.CreateAlignedLoad(StructTy->getTypeAtIndex(Index),
1055 Ptr, llvm::MaybeAlign());
1056 return CPUID;
1057 };
1058
1059 const llvm::RISCV::CPUModel Model = llvm::RISCV::getCPUModel(CPUStr);
1060
1061 // Compare mvendorid.
1062 Value *VendorID = loadRISCVCPUID(0);
1063 Value *Result =
1064 Builder.CreateICmpEQ(VendorID, Builder.getInt32(Model.MVendorID));
1065
1066 // Compare marchid.
1067 Value *ArchID = loadRISCVCPUID(1);
1068 Result = Builder.CreateAnd(
1069 Result, Builder.CreateICmpEQ(ArchID, Builder.getInt64(Model.MArchID)));
1070
1071 // Compare mimpid.
1072 Value *ImpID = loadRISCVCPUID(2);
1073 Result = Builder.CreateAnd(
1074 Result, Builder.CreateICmpEQ(ImpID, Builder.getInt64(Model.MImpID)));
1075
1076 return Result;
1077}
1078
1079Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
1080 const CallExpr *E,
1081 ReturnValueSlot ReturnValue) {
1082
1083 if (BuiltinID == Builtin::BI__builtin_cpu_supports)
1084 return EmitRISCVCpuSupports(E);
1085 if (BuiltinID == Builtin::BI__builtin_cpu_init)
1086 return EmitRISCVCpuInit();
1087 if (BuiltinID == Builtin::BI__builtin_cpu_is)
1088 return EmitRISCVCpuIs(E);
1089
1090 SmallVector<Value *, 4> Ops;
1091 llvm::Type *ResultType = ConvertType(E->getType());
1092
1093 // Find out if any arguments are required to be integer constant expressions.
1094 unsigned ICEArguments = 0;
1095 ASTContext::GetBuiltinTypeError Error;
1096 getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
1097 if (Error == ASTContext::GE_Missing_type) {
1098 // Vector intrinsics don't have a type string.
1099 assert(BuiltinID >= clang::RISCV::FirstRVVBuiltin &&
1100 BuiltinID <= clang::RISCV::LastRVVBuiltin);
1101 ICEArguments = 0;
1102 if (BuiltinID == RISCVVector::BI__builtin_rvv_vget_v ||
1103 BuiltinID == RISCVVector::BI__builtin_rvv_vset_v)
1104 ICEArguments = 1 << 1;
1105 } else {
1106 assert(Error == ASTContext::GE_None && "Unexpected error");
1107 }
1108
1109 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_load)
1110 ICEArguments |= (1 << 1);
1111 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_store)
1112 ICEArguments |= (1 << 2);
1113
1114 for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
1115 // Handle aggregate argument, namely RVV tuple types in segment load/store
1116 if (hasAggregateEvaluationKind(E->getArg(i)->getType())) {
1117 LValue L = EmitAggExprToLValue(E->getArg(i));
1118 llvm::Value *AggValue = Builder.CreateLoad(L.getAddress());
1119 Ops.push_back(AggValue);
1120 continue;
1121 }
1122 Ops.push_back(EmitScalarOrConstFoldImmArg(ICEArguments, i, E));
1123 }
1124
1125 Intrinsic::ID ID = Intrinsic::not_intrinsic;
1126 int PolicyAttrs = 0;
1127 bool IsMasked = false;
1128 // This is used by segment load/store to determine it's llvm type.
1129 unsigned SegInstSEW = 8;
1130 // This is used by XSfmm.
1131 unsigned TWiden = 0;
1132
1133 // Required for overloaded intrinsics.
1134 llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
1135 switch (BuiltinID) {
1136 default: llvm_unreachable("unexpected builtin ID");
1137 case RISCV::BI__builtin_riscv_orc_b_32:
1138 case RISCV::BI__builtin_riscv_orc_b_64:
1139 case RISCV::BI__builtin_riscv_clmul_32:
1140 case RISCV::BI__builtin_riscv_clmul_64:
1141 case RISCV::BI__builtin_riscv_clmulh_32:
1142 case RISCV::BI__builtin_riscv_clmulh_64:
1143 case RISCV::BI__builtin_riscv_clmulr_32:
1144 case RISCV::BI__builtin_riscv_clmulr_64:
1145 case RISCV::BI__builtin_riscv_xperm4_32:
1146 case RISCV::BI__builtin_riscv_xperm4_64:
1147 case RISCV::BI__builtin_riscv_xperm8_32:
1148 case RISCV::BI__builtin_riscv_xperm8_64:
1149 case RISCV::BI__builtin_riscv_brev8_32:
1150 case RISCV::BI__builtin_riscv_brev8_64:
1151 case RISCV::BI__builtin_riscv_zip_32:
1152 case RISCV::BI__builtin_riscv_unzip_32: {
1153 switch (BuiltinID) {
1154 default: llvm_unreachable("unexpected builtin ID");
1155 // Zbb
1156 case RISCV::BI__builtin_riscv_orc_b_32:
1157 case RISCV::BI__builtin_riscv_orc_b_64:
1158 ID = Intrinsic::riscv_orc_b;
1159 break;
1160
1161 // Zbc
1162 case RISCV::BI__builtin_riscv_clmul_32:
1163 case RISCV::BI__builtin_riscv_clmul_64:
1164 ID = Intrinsic::clmul;
1165 break;
1166 case RISCV::BI__builtin_riscv_clmulh_32:
1167 case RISCV::BI__builtin_riscv_clmulh_64:
1168 ID = Intrinsic::riscv_clmulh;
1169 break;
1170 case RISCV::BI__builtin_riscv_clmulr_32:
1171 case RISCV::BI__builtin_riscv_clmulr_64:
1172 ID = Intrinsic::riscv_clmulr;
1173 break;
1174
1175 // Zbkx
1176 case RISCV::BI__builtin_riscv_xperm8_32:
1177 case RISCV::BI__builtin_riscv_xperm8_64:
1178 ID = Intrinsic::riscv_xperm8;
1179 break;
1180 case RISCV::BI__builtin_riscv_xperm4_32:
1181 case RISCV::BI__builtin_riscv_xperm4_64:
1182 ID = Intrinsic::riscv_xperm4;
1183 break;
1184
1185 // Zbkb
1186 case RISCV::BI__builtin_riscv_brev8_32:
1187 case RISCV::BI__builtin_riscv_brev8_64:
1188 ID = Intrinsic::riscv_brev8;
1189 break;
1190 case RISCV::BI__builtin_riscv_zip_32:
1191 ID = Intrinsic::riscv_zip;
1192 break;
1193 case RISCV::BI__builtin_riscv_unzip_32:
1194 ID = Intrinsic::riscv_unzip;
1195 break;
1196 }
1197
1198 IntrinsicTypes = {ResultType};
1199 break;
1200 }
1201
1202 // Packed Widening Shifts
1203 case RISCV::BI__builtin_riscv_pwsll_s_u16x4:
1204 case RISCV::BI__builtin_riscv_pwsll_s_u32x2:
1205 ID = Intrinsic::riscv_pwsll;
1206 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1207 break;
1208 case RISCV::BI__builtin_riscv_pwsla_s_i16x4:
1209 case RISCV::BI__builtin_riscv_pwsla_s_i32x2:
1210 ID = Intrinsic::riscv_pwsla;
1211 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1212 break;
1213
1214 // Packed Narrowing Shifts
1215 case RISCV::BI__builtin_riscv_pnsrl_s_u8x4:
1216 case RISCV::BI__builtin_riscv_pnsrl_s_u16x2:
1217 ID = Intrinsic::riscv_pnsrl;
1218 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1219 break;
1220 case RISCV::BI__builtin_riscv_pnsra_s_i8x4:
1221 case RISCV::BI__builtin_riscv_pnsra_s_i16x2:
1222 ID = Intrinsic::riscv_pnsra;
1223 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1224 break;
1225 case RISCV::BI__builtin_riscv_pnsrar_s_i8x4:
1226 case RISCV::BI__builtin_riscv_pnsrar_s_i16x2:
1227 ID = Intrinsic::riscv_pnsrar;
1228 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1229 break;
1230
1231 // Packed Averaging Addition and Subtraction
1232 case RISCV::BI__builtin_riscv_paadd_i8x4:
1233 case RISCV::BI__builtin_riscv_paadd_i16x2:
1234 case RISCV::BI__builtin_riscv_paadd_i8x8:
1235 case RISCV::BI__builtin_riscv_paadd_i16x4:
1236 case RISCV::BI__builtin_riscv_paadd_i32x2:
1237 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1238 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1239 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1240 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1241 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1242 case RISCV::BI__builtin_riscv_pasub_i8x4:
1243 case RISCV::BI__builtin_riscv_pasub_i16x2:
1244 case RISCV::BI__builtin_riscv_pasub_i8x8:
1245 case RISCV::BI__builtin_riscv_pasub_i16x4:
1246 case RISCV::BI__builtin_riscv_pasub_i32x2:
1247 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1248 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1249 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1250 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1251 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1252 // Packed Exchanged Addition and Subtraction
1253 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1254 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1255 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1256 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1257 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1258 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1259 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1260 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1261 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1262 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1263 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1264 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1265 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1266 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1267 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1268 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1269 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1270 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1271 // Packed Shift
1272 case RISCV::BI__builtin_riscv_psll_s_u8x4:
1273 case RISCV::BI__builtin_riscv_psll_s_u16x2:
1274 case RISCV::BI__builtin_riscv_psll_s_u8x8:
1275 case RISCV::BI__builtin_riscv_psll_s_u16x4:
1276 case RISCV::BI__builtin_riscv_psll_s_u32x2:
1277 case RISCV::BI__builtin_riscv_psrl_s_u8x4:
1278 case RISCV::BI__builtin_riscv_psrl_s_u16x2:
1279 case RISCV::BI__builtin_riscv_psrl_s_u8x8:
1280 case RISCV::BI__builtin_riscv_psrl_s_u16x4:
1281 case RISCV::BI__builtin_riscv_psrl_s_u32x2:
1282 case RISCV::BI__builtin_riscv_psra_s_i8x4:
1283 case RISCV::BI__builtin_riscv_psra_s_i16x2:
1284 case RISCV::BI__builtin_riscv_psra_s_i8x8:
1285 case RISCV::BI__builtin_riscv_psra_s_i16x4:
1286 case RISCV::BI__builtin_riscv_psra_s_i32x2:
1287 // Packed Absolute Value and Absolute Difference
1288 case RISCV::BI__builtin_riscv_pabd_i8x4:
1289 case RISCV::BI__builtin_riscv_pabd_i16x2:
1290 case RISCV::BI__builtin_riscv_pabd_i8x8:
1291 case RISCV::BI__builtin_riscv_pabd_i16x4:
1292 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1293 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1294 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1295 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1296 // Packed Merge
1297 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1298 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1299 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1300 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1301 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1302 // Packed Multiply High
1303 case RISCV::BI__builtin_riscv_pmulh_i16x2:
1304 case RISCV::BI__builtin_riscv_pmulh_i16x4:
1305 case RISCV::BI__builtin_riscv_pmulh_i32x2:
1306 case RISCV::BI__builtin_riscv_pmulhr_i16x2:
1307 case RISCV::BI__builtin_riscv_pmulhr_i16x4:
1308 case RISCV::BI__builtin_riscv_pmulhr_i32x2:
1309 case RISCV::BI__builtin_riscv_pmulhu_u16x2:
1310 case RISCV::BI__builtin_riscv_pmulhu_u16x4:
1311 case RISCV::BI__builtin_riscv_pmulhu_u32x2:
1312 case RISCV::BI__builtin_riscv_pmulhru_u16x2:
1313 case RISCV::BI__builtin_riscv_pmulhru_u16x4:
1314 case RISCV::BI__builtin_riscv_pmulhru_u32x2:
1315 case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
1316 case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
1317 case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
1318 case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
1319 case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
1320 case RISCV::BI__builtin_riscv_pmulhrsu_i32x2:
1321 // Packed Multiply High Accumulate
1322 case RISCV::BI__builtin_riscv_pmhacc_i16x2:
1323 case RISCV::BI__builtin_riscv_pmhacc_i16x4:
1324 case RISCV::BI__builtin_riscv_pmhacc_i32x2:
1325 case RISCV::BI__builtin_riscv_pmhracc_i16x2:
1326 case RISCV::BI__builtin_riscv_pmhracc_i16x4:
1327 case RISCV::BI__builtin_riscv_pmhracc_i32x2:
1328 case RISCV::BI__builtin_riscv_pmhaccu_u16x2:
1329 case RISCV::BI__builtin_riscv_pmhaccu_u16x4:
1330 case RISCV::BI__builtin_riscv_pmhaccu_u32x2:
1331 case RISCV::BI__builtin_riscv_pmhraccu_u16x2:
1332 case RISCV::BI__builtin_riscv_pmhraccu_u16x4:
1333 case RISCV::BI__builtin_riscv_pmhraccu_u32x2:
1334 case RISCV::BI__builtin_riscv_pmhaccsu_i16x2:
1335 case RISCV::BI__builtin_riscv_pmhaccsu_i16x4:
1336 case RISCV::BI__builtin_riscv_pmhaccsu_i32x2:
1337 case RISCV::BI__builtin_riscv_pmhraccsu_i16x2:
1338 case RISCV::BI__builtin_riscv_pmhraccsu_i16x4:
1339 case RISCV::BI__builtin_riscv_pmhraccsu_i32x2:
1340 // Packed Multiply High Accumulate.
1341 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x2:
1342 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2:
1343 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x2:
1344 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2:
1345 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x4:
1346 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4:
1347 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x4:
1348 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4:
1349 case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2:
1350 case RISCV::BI__builtin_riscv_pmhacc_h1_i32x2:
1351 case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2:
1352 case RISCV::BI__builtin_riscv_pmhaccsu_h1_i32x2:
1353 // Packed Saturating Absolute Value
1354 case RISCV::BI__builtin_riscv_psabs_i8x4:
1355 case RISCV::BI__builtin_riscv_psabs_i16x2:
1356 case RISCV::BI__builtin_riscv_psabs_i8x8:
1357 case RISCV::BI__builtin_riscv_psabs_i16x4:
1358 // Packed "Q-format" Multiplication
1359 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1360 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1361 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1362 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1363 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1364 case RISCV::BI__builtin_riscv_pmulqr_i32x2:
1365 case RISCV::BI__builtin_riscv_psext_b_i16x2:
1366 case RISCV::BI__builtin_riscv_pzext_b_u16x2:
1367 case RISCV::BI__builtin_riscv_psext_b_i16x4:
1368 case RISCV::BI__builtin_riscv_psext_b_i32x2:
1369 case RISCV::BI__builtin_riscv_psext_h_i32x2:
1370 case RISCV::BI__builtin_riscv_pzext_b_u16x4:
1371 case RISCV::BI__builtin_riscv_pzext_h_u32x2:
1372 // Packed Saturating and Rounding Shifts
1373 case RISCV::BI__builtin_riscv_pssha_s_i16x2:
1374 case RISCV::BI__builtin_riscv_psshar_s_i16x2:
1375 case RISCV::BI__builtin_riscv_psshl_s_u16x2:
1376 case RISCV::BI__builtin_riscv_psshlr_s_u16x2:
1377 case RISCV::BI__builtin_riscv_pssha_s_i16x4:
1378 case RISCV::BI__builtin_riscv_pssha_s_i32x2:
1379 case RISCV::BI__builtin_riscv_psshar_s_i16x4:
1380 case RISCV::BI__builtin_riscv_psshar_s_i32x2:
1381 case RISCV::BI__builtin_riscv_psshl_s_u16x4:
1382 case RISCV::BI__builtin_riscv_psshl_s_u32x2:
1383 case RISCV::BI__builtin_riscv_psshlr_s_u16x4:
1384 case RISCV::BI__builtin_riscv_psshlr_s_u32x2:
1385 // Packed Saturation
1386 case RISCV::BI__builtin_riscv_pusati_u16x2:
1387 case RISCV::BI__builtin_riscv_psati_i16x2:
1388 case RISCV::BI__builtin_riscv_pusati_u16x4:
1389 case RISCV::BI__builtin_riscv_pusati_u32x2:
1390 case RISCV::BI__builtin_riscv_psati_i16x4:
1391 case RISCV::BI__builtin_riscv_psati_i32x2:
1392 // Scalar Multiply High
1393 case RISCV::BI__builtin_riscv_mulh_i32:
1394 case RISCV::BI__builtin_riscv_mulhu_u32: {
1395 switch (BuiltinID) {
1396 default:
1397 llvm_unreachable("unexpected builtin ID");
1398 case RISCV::BI__builtin_riscv_paadd_i8x4:
1399 case RISCV::BI__builtin_riscv_paadd_i16x2:
1400 case RISCV::BI__builtin_riscv_paadd_i8x8:
1401 case RISCV::BI__builtin_riscv_paadd_i16x4:
1402 case RISCV::BI__builtin_riscv_paadd_i32x2:
1403 ID = Intrinsic::riscv_paadd;
1404 break;
1405 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1406 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1407 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1408 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1409 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1410 ID = Intrinsic::riscv_paaddu;
1411 break;
1412 case RISCV::BI__builtin_riscv_pasub_i8x4:
1413 case RISCV::BI__builtin_riscv_pasub_i16x2:
1414 case RISCV::BI__builtin_riscv_pasub_i8x8:
1415 case RISCV::BI__builtin_riscv_pasub_i16x4:
1416 case RISCV::BI__builtin_riscv_pasub_i32x2:
1417 ID = Intrinsic::riscv_pasub;
1418 break;
1419 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1420 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1421 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1422 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1423 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1424 ID = Intrinsic::riscv_pasubu;
1425 break;
1426 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1427 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1428 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1429 ID = Intrinsic::riscv_pas;
1430 break;
1431 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1432 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1433 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1434 ID = Intrinsic::riscv_psa;
1435 break;
1436 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1437 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1438 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1439 ID = Intrinsic::riscv_psas;
1440 break;
1441 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1442 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1443 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1444 ID = Intrinsic::riscv_pssa;
1445 break;
1446 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1447 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1448 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1449 ID = Intrinsic::riscv_paas;
1450 break;
1451 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1452 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1453 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1454 ID = Intrinsic::riscv_pasa;
1455 break;
1456 case RISCV::BI__builtin_riscv_psll_s_u8x4:
1457 case RISCV::BI__builtin_riscv_psll_s_u16x2:
1458 case RISCV::BI__builtin_riscv_psll_s_u8x8:
1459 case RISCV::BI__builtin_riscv_psll_s_u16x4:
1460 case RISCV::BI__builtin_riscv_psll_s_u32x2:
1461 ID = Intrinsic::riscv_psll;
1462 break;
1463 case RISCV::BI__builtin_riscv_psrl_s_u8x4:
1464 case RISCV::BI__builtin_riscv_psrl_s_u16x2:
1465 case RISCV::BI__builtin_riscv_psrl_s_u8x8:
1466 case RISCV::BI__builtin_riscv_psrl_s_u16x4:
1467 case RISCV::BI__builtin_riscv_psrl_s_u32x2:
1468 ID = Intrinsic::riscv_psrl;
1469 break;
1470 case RISCV::BI__builtin_riscv_psra_s_i8x4:
1471 case RISCV::BI__builtin_riscv_psra_s_i16x2:
1472 case RISCV::BI__builtin_riscv_psra_s_i8x8:
1473 case RISCV::BI__builtin_riscv_psra_s_i16x4:
1474 case RISCV::BI__builtin_riscv_psra_s_i32x2:
1475 ID = Intrinsic::riscv_psra;
1476 break;
1477 case RISCV::BI__builtin_riscv_pabd_i8x4:
1478 case RISCV::BI__builtin_riscv_pabd_i16x2:
1479 case RISCV::BI__builtin_riscv_pabd_i8x8:
1480 case RISCV::BI__builtin_riscv_pabd_i16x4:
1481 ID = Intrinsic::riscv_pabd;
1482 break;
1483 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1484 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1485 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1486 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1487 ID = Intrinsic::riscv_pabdu;
1488 break;
1489 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1490 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1491 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1492 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1493 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1494 ID = Intrinsic::riscv_pmerge;
1495 break;
1496 case RISCV::BI__builtin_riscv_pmulh_i16x2:
1497 case RISCV::BI__builtin_riscv_pmulh_i16x4:
1498 case RISCV::BI__builtin_riscv_pmulh_i32x2:
1499 ID = Intrinsic::smulh;
1500 break;
1501 case RISCV::BI__builtin_riscv_pmulhr_i16x2:
1502 case RISCV::BI__builtin_riscv_pmulhr_i16x4:
1503 case RISCV::BI__builtin_riscv_pmulhr_i32x2:
1504 ID = Intrinsic::riscv_pmulhr;
1505 break;
1506 case RISCV::BI__builtin_riscv_pmulhu_u16x2:
1507 case RISCV::BI__builtin_riscv_pmulhu_u16x4:
1508 case RISCV::BI__builtin_riscv_pmulhu_u32x2:
1509 ID = Intrinsic::umulh;
1510 break;
1511 case RISCV::BI__builtin_riscv_pmulhru_u16x2:
1512 case RISCV::BI__builtin_riscv_pmulhru_u16x4:
1513 case RISCV::BI__builtin_riscv_pmulhru_u32x2:
1514 ID = Intrinsic::riscv_pmulhru;
1515 break;
1516 case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
1517 case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
1518 case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
1519 ID = Intrinsic::riscv_pmulhsu;
1520 break;
1521 case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
1522 case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
1523 case RISCV::BI__builtin_riscv_pmulhrsu_i32x2:
1524 ID = Intrinsic::riscv_pmulhrsu;
1525 break;
1526 case RISCV::BI__builtin_riscv_pmhacc_i16x2:
1527 case RISCV::BI__builtin_riscv_pmhacc_i16x4:
1528 case RISCV::BI__builtin_riscv_pmhacc_i32x2:
1529 ID = Intrinsic::riscv_pmhacc;
1530 break;
1531 case RISCV::BI__builtin_riscv_pmhracc_i16x2:
1532 case RISCV::BI__builtin_riscv_pmhracc_i16x4:
1533 case RISCV::BI__builtin_riscv_pmhracc_i32x2:
1534 ID = Intrinsic::riscv_pmhracc;
1535 break;
1536 case RISCV::BI__builtin_riscv_pmhaccu_u16x2:
1537 case RISCV::BI__builtin_riscv_pmhaccu_u16x4:
1538 case RISCV::BI__builtin_riscv_pmhaccu_u32x2:
1539 ID = Intrinsic::riscv_pmhaccu;
1540 break;
1541 case RISCV::BI__builtin_riscv_pmhraccu_u16x2:
1542 case RISCV::BI__builtin_riscv_pmhraccu_u16x4:
1543 case RISCV::BI__builtin_riscv_pmhraccu_u32x2:
1544 ID = Intrinsic::riscv_pmhraccu;
1545 break;
1546 case RISCV::BI__builtin_riscv_pmhaccsu_i16x2:
1547 case RISCV::BI__builtin_riscv_pmhaccsu_i16x4:
1548 case RISCV::BI__builtin_riscv_pmhaccsu_i32x2:
1549 ID = Intrinsic::riscv_pmhaccsu;
1550 break;
1551 case RISCV::BI__builtin_riscv_pmhraccsu_i16x2:
1552 case RISCV::BI__builtin_riscv_pmhraccsu_i16x4:
1553 case RISCV::BI__builtin_riscv_pmhraccsu_i32x2:
1554 ID = Intrinsic::riscv_pmhraccsu;
1555 break;
1556 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x2:
1557 case RISCV::BI__builtin_riscv_pmhacc_b0_i16x4:
1558 ID = Intrinsic::riscv_pmhacc_b0;
1559 break;
1560 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2:
1561 case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4:
1562 ID = Intrinsic::riscv_pmhacc_b1;
1563 break;
1564 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x2:
1565 case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x4:
1566 ID = Intrinsic::riscv_pmhaccsu_b0;
1567 break;
1568 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2:
1569 case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4:
1570 ID = Intrinsic::riscv_pmhaccsu_b1;
1571 break;
1572 case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2:
1573 ID = Intrinsic::riscv_pmhacc_h0;
1574 break;
1575 case RISCV::BI__builtin_riscv_pmhacc_h1_i32x2:
1576 ID = Intrinsic::riscv_pmhacc_h1;
1577 break;
1578 case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2:
1579 ID = Intrinsic::riscv_pmhaccsu_h0;
1580 break;
1581 case RISCV::BI__builtin_riscv_pmhaccsu_h1_i32x2:
1582 ID = Intrinsic::riscv_pmhaccsu_h1;
1583 break;
1584 case RISCV::BI__builtin_riscv_psabs_i8x4:
1585 case RISCV::BI__builtin_riscv_psabs_i16x2:
1586 case RISCV::BI__builtin_riscv_psabs_i8x8:
1587 case RISCV::BI__builtin_riscv_psabs_i16x4:
1588 ID = Intrinsic::riscv_psabs;
1589 break;
1590 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1591 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1592 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1593 ID = Intrinsic::riscv_pmulq;
1594 break;
1595 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1596 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1597 case RISCV::BI__builtin_riscv_pmulqr_i32x2:
1598 ID = Intrinsic::riscv_pmulqr;
1599 break;
1600 case RISCV::BI__builtin_riscv_psext_b_i16x2:
1601 case RISCV::BI__builtin_riscv_psext_b_i16x4:
1602 case RISCV::BI__builtin_riscv_psext_b_i32x2:
1603 ID = Intrinsic::riscv_psext_b;
1604 break;
1605 case RISCV::BI__builtin_riscv_psext_h_i32x2:
1606 ID = Intrinsic::riscv_psext_h;
1607 break;
1608 case RISCV::BI__builtin_riscv_pzext_b_u16x2:
1609 case RISCV::BI__builtin_riscv_pzext_b_u16x4:
1610 ID = Intrinsic::riscv_pzext_b;
1611 break;
1612 case RISCV::BI__builtin_riscv_pzext_h_u32x2:
1613 ID = Intrinsic::riscv_pzext_h;
1614 break;
1615 case RISCV::BI__builtin_riscv_pssha_s_i16x2:
1616 case RISCV::BI__builtin_riscv_pssha_s_i16x4:
1617 case RISCV::BI__builtin_riscv_pssha_s_i32x2:
1618 ID = Intrinsic::riscv_pssha;
1619 break;
1620 case RISCV::BI__builtin_riscv_psshar_s_i16x2:
1621 case RISCV::BI__builtin_riscv_psshar_s_i16x4:
1622 case RISCV::BI__builtin_riscv_psshar_s_i32x2:
1623 ID = Intrinsic::riscv_psshar;
1624 break;
1625 case RISCV::BI__builtin_riscv_psshl_s_u16x2:
1626 case RISCV::BI__builtin_riscv_psshl_s_u16x4:
1627 case RISCV::BI__builtin_riscv_psshl_s_u32x2:
1628 ID = Intrinsic::riscv_psshl;
1629 break;
1630 case RISCV::BI__builtin_riscv_psshlr_s_u16x2:
1631 case RISCV::BI__builtin_riscv_psshlr_s_u16x4:
1632 case RISCV::BI__builtin_riscv_psshlr_s_u32x2:
1633 ID = Intrinsic::riscv_psshlr;
1634 break;
1635 case RISCV::BI__builtin_riscv_psati_i16x2:
1636 case RISCV::BI__builtin_riscv_psati_i16x4:
1637 case RISCV::BI__builtin_riscv_psati_i32x2:
1638 ID = Intrinsic::riscv_psati;
1639 break;
1640 case RISCV::BI__builtin_riscv_pusati_u16x2:
1641 case RISCV::BI__builtin_riscv_pusati_u16x4:
1642 case RISCV::BI__builtin_riscv_pusati_u32x2:
1643 ID = Intrinsic::riscv_pusati;
1644 break;
1645 case RISCV::BI__builtin_riscv_mulh_i32:
1646 ID = Intrinsic::smulh;
1647 break;
1648 case RISCV::BI__builtin_riscv_mulhu_u32:
1649 ID = Intrinsic::umulh;
1650 break;
1651 }
1652
1653 IntrinsicTypes = {ResultType};
1654 break;
1655 }
1656
1657 // Scalar Multiply High
1658 case RISCV::BI__builtin_riscv_mulhr_i32:
1659 case RISCV::BI__builtin_riscv_mulhru_u32:
1660 case RISCV::BI__builtin_riscv_mulhsu_i32:
1661 case RISCV::BI__builtin_riscv_mulhrsu_i32: {
1662 switch (BuiltinID) {
1663 default:
1664 llvm_unreachable("unexpected builtin ID");
1665 case RISCV::BI__builtin_riscv_mulhr_i32:
1666 ID = Intrinsic::riscv_mulhr_i32;
1667 break;
1668 case RISCV::BI__builtin_riscv_mulhru_u32:
1669 ID = Intrinsic::riscv_mulhru_u32;
1670 break;
1671 case RISCV::BI__builtin_riscv_mulhsu_i32:
1672 ID = Intrinsic::riscv_mulhsu_i32;
1673 break;
1674 case RISCV::BI__builtin_riscv_mulhrsu_i32:
1675 ID = Intrinsic::riscv_mulhrsu_i32;
1676 break;
1677 }
1678 break;
1679 }
1680
1681 // Packed "Q-format" Multiply with Widening Accumulate
1682 case RISCV::BI__builtin_riscv_pmqwacc_i32x2:
1683 case RISCV::BI__builtin_riscv_pmqrwacc_i32x2: {
1684 ID = BuiltinID == RISCV::BI__builtin_riscv_pmqwacc_i32x2
1685 ? Intrinsic::riscv_pmqwacc_i32x2
1686 : Intrinsic::riscv_pmqrwacc_i32x2;
1687 break;
1688 }
1689
1690 // Packed Multiplication with Horizontal Addition
1691 case RISCV::BI__builtin_riscv_pm4add_i8x4:
1692 case RISCV::BI__builtin_riscv_pm4add_i8x8:
1693 case RISCV::BI__builtin_riscv_pm4add_i16x4:
1694 case RISCV::BI__builtin_riscv_pm2add_i16x2:
1695 case RISCV::BI__builtin_riscv_pm2add_i16x4:
1696 case RISCV::BI__builtin_riscv_pm2add_i32x2:
1697 case RISCV::BI__builtin_riscv_pm2add_x_i16x2:
1698 case RISCV::BI__builtin_riscv_pm2add_x_i16x4:
1699 case RISCV::BI__builtin_riscv_pm2add_x_i32x2:
1700 case RISCV::BI__builtin_riscv_pm4addu_u8x4:
1701 case RISCV::BI__builtin_riscv_pm4addu_u8x8:
1702 case RISCV::BI__builtin_riscv_pm4addu_u16x4:
1703 case RISCV::BI__builtin_riscv_pm2addu_u16x2:
1704 case RISCV::BI__builtin_riscv_pm2addu_u16x4:
1705 case RISCV::BI__builtin_riscv_pm2addu_u32x2:
1706 case RISCV::BI__builtin_riscv_pmq2add_i16x2:
1707 case RISCV::BI__builtin_riscv_pmq2add_i16x4:
1708 case RISCV::BI__builtin_riscv_pmq2add_i32x2:
1709 case RISCV::BI__builtin_riscv_pmqr2add_i16x2:
1710 case RISCV::BI__builtin_riscv_pmqr2add_i16x4:
1711 case RISCV::BI__builtin_riscv_pmqr2add_i32x2:
1712 case RISCV::BI__builtin_riscv_pm2sadd_i16x2:
1713 case RISCV::BI__builtin_riscv_pm2sadd_i16x4:
1714 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2:
1715 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4:
1716 case RISCV::BI__builtin_riscv_pm2sub_i16x2:
1717 case RISCV::BI__builtin_riscv_pm2sub_i16x4:
1718 case RISCV::BI__builtin_riscv_pm2sub_i32x2:
1719 case RISCV::BI__builtin_riscv_pm2sub_x_i16x2:
1720 case RISCV::BI__builtin_riscv_pm2sub_x_i16x4:
1721 case RISCV::BI__builtin_riscv_pm2sub_x_i32x2:
1722 case RISCV::BI__builtin_riscv_pm4addsu_i8x4:
1723 case RISCV::BI__builtin_riscv_pm4addsu_i8x8:
1724 case RISCV::BI__builtin_riscv_pm4addsu_i16x4:
1725 case RISCV::BI__builtin_riscv_pm2addsu_i16x2:
1726 case RISCV::BI__builtin_riscv_pm2addsu_i16x4:
1727 case RISCV::BI__builtin_riscv_pm2addsu_i32x2: {
1728 switch (BuiltinID) {
1729 default:
1730 llvm_unreachable("unexpected builtin ID");
1731 case RISCV::BI__builtin_riscv_pm4add_i8x4:
1732 case RISCV::BI__builtin_riscv_pm4add_i8x8:
1733 case RISCV::BI__builtin_riscv_pm4add_i16x4:
1734 ID = Intrinsic::riscv_pm4add;
1735 break;
1736 case RISCV::BI__builtin_riscv_pm2add_i16x2:
1737 case RISCV::BI__builtin_riscv_pm2add_i16x4:
1738 case RISCV::BI__builtin_riscv_pm2add_i32x2:
1739 ID = Intrinsic::riscv_pm2add;
1740 break;
1741 case RISCV::BI__builtin_riscv_pm2add_x_i16x2:
1742 case RISCV::BI__builtin_riscv_pm2add_x_i16x4:
1743 case RISCV::BI__builtin_riscv_pm2add_x_i32x2:
1744 ID = Intrinsic::riscv_pm2add_x;
1745 break;
1746 case RISCV::BI__builtin_riscv_pm4addu_u8x4:
1747 case RISCV::BI__builtin_riscv_pm4addu_u8x8:
1748 case RISCV::BI__builtin_riscv_pm4addu_u16x4:
1749 ID = Intrinsic::riscv_pm4addu;
1750 break;
1751 case RISCV::BI__builtin_riscv_pm2addu_u16x2:
1752 case RISCV::BI__builtin_riscv_pm2addu_u16x4:
1753 case RISCV::BI__builtin_riscv_pm2addu_u32x2:
1754 ID = Intrinsic::riscv_pm2addu;
1755 break;
1756 case RISCV::BI__builtin_riscv_pmq2add_i16x2:
1757 case RISCV::BI__builtin_riscv_pmq2add_i16x4:
1758 case RISCV::BI__builtin_riscv_pmq2add_i32x2:
1759 ID = Intrinsic::riscv_pmq2add;
1760 break;
1761 case RISCV::BI__builtin_riscv_pmqr2add_i16x2:
1762 case RISCV::BI__builtin_riscv_pmqr2add_i16x4:
1763 case RISCV::BI__builtin_riscv_pmqr2add_i32x2:
1764 ID = Intrinsic::riscv_pmqr2add;
1765 break;
1766 case RISCV::BI__builtin_riscv_pm2sadd_i16x2:
1767 case RISCV::BI__builtin_riscv_pm2sadd_i16x4:
1768 ID = Intrinsic::riscv_pm2sadd;
1769 break;
1770 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2:
1771 case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4:
1772 ID = Intrinsic::riscv_pm2sadd_x;
1773 break;
1774 case RISCV::BI__builtin_riscv_pm2sub_i16x2:
1775 case RISCV::BI__builtin_riscv_pm2sub_i16x4:
1776 case RISCV::BI__builtin_riscv_pm2sub_i32x2:
1777 ID = Intrinsic::riscv_pm2sub;
1778 break;
1779 case RISCV::BI__builtin_riscv_pm2sub_x_i16x2:
1780 case RISCV::BI__builtin_riscv_pm2sub_x_i16x4:
1781 case RISCV::BI__builtin_riscv_pm2sub_x_i32x2:
1782 ID = Intrinsic::riscv_pm2sub_x;
1783 break;
1784 case RISCV::BI__builtin_riscv_pm4addsu_i8x4:
1785 case RISCV::BI__builtin_riscv_pm4addsu_i8x8:
1786 case RISCV::BI__builtin_riscv_pm4addsu_i16x4:
1787 ID = Intrinsic::riscv_pm4addsu;
1788 break;
1789 case RISCV::BI__builtin_riscv_pm2addsu_i16x2:
1790 case RISCV::BI__builtin_riscv_pm2addsu_i16x4:
1791 case RISCV::BI__builtin_riscv_pm2addsu_i32x2:
1792 ID = Intrinsic::riscv_pm2addsu;
1793 break;
1794 }
1795
1796 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1797 break;
1798 }
1799
1800 // Packed Reduction Sum
1801 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1802 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1803 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1804 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1805 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1806 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1807 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1808 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1809 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1810 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1811 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1812 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1813 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1814 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
1815 // Packed Narrowing Clip Pair
1816 case RISCV::BI__builtin_riscv_pnclipp_i8x4:
1817 case RISCV::BI__builtin_riscv_pnclipp_i8x8:
1818 case RISCV::BI__builtin_riscv_pnclipp_i16x2:
1819 case RISCV::BI__builtin_riscv_pnclipp_i16x4:
1820 case RISCV::BI__builtin_riscv_pnclipp_i32x2:
1821 case RISCV::BI__builtin_riscv_pnclipup_u8x4:
1822 case RISCV::BI__builtin_riscv_pnclipup_u8x8:
1823 case RISCV::BI__builtin_riscv_pnclipup_u16x2:
1824 case RISCV::BI__builtin_riscv_pnclipup_u16x4:
1825 case RISCV::BI__builtin_riscv_pnclipup_u32x2: {
1826 switch (BuiltinID) {
1827 default:
1828 llvm_unreachable("unexpected builtin ID");
1829 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1830 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1831 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1832 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1833 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1834 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1835 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1836 ID = Intrinsic::riscv_predsum;
1837 break;
1838 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1839 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1840 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1841 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1842 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1843 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1844 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
1845 ID = Intrinsic::riscv_predsumu;
1846 break;
1847 case RISCV::BI__builtin_riscv_pnclipp_i8x4:
1848 case RISCV::BI__builtin_riscv_pnclipp_i8x8:
1849 case RISCV::BI__builtin_riscv_pnclipp_i16x2:
1850 case RISCV::BI__builtin_riscv_pnclipp_i16x4:
1851 case RISCV::BI__builtin_riscv_pnclipp_i32x2:
1852 ID = Intrinsic::riscv_pnclipp;
1853 break;
1854 case RISCV::BI__builtin_riscv_pnclipup_u8x4:
1855 case RISCV::BI__builtin_riscv_pnclipup_u8x8:
1856 case RISCV::BI__builtin_riscv_pnclipup_u16x2:
1857 case RISCV::BI__builtin_riscv_pnclipup_u16x4:
1858 case RISCV::BI__builtin_riscv_pnclipup_u32x2:
1859 ID = Intrinsic::riscv_pnclipup;
1860 break;
1861 }
1862
1863 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1864 break;
1865 }
1866
1867 // Packed Absolute Difference Sum
1868 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1869 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1870 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1871 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1872 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1873 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64: {
1874 switch (BuiltinID) {
1875 default:
1876 llvm_unreachable("unexpected builtin ID");
1877 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1878 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1879 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1880 ID = Intrinsic::riscv_pabdsumu;
1881 break;
1882 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1883 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1884 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64:
1885 ID = Intrinsic::riscv_pabdsumau;
1886 break;
1887 }
1888
1889 // The two vector sources are the last two arguments; the accumulate form
1890 // has an extra accumulator argument first.
1891 IntrinsicTypes = {ResultType, Ops.back()->getType()};
1892 break;
1893 }
1894 // Packed Multiply Parts.
1895 case RISCV::BI__builtin_riscv_pmul_b00_i16x2:
1896 case RISCV::BI__builtin_riscv_pmul_b01_i16x2:
1897 case RISCV::BI__builtin_riscv_pmul_b11_i16x2:
1898 case RISCV::BI__builtin_riscv_pmulu_b00_u16x2:
1899 case RISCV::BI__builtin_riscv_pmulu_b01_u16x2:
1900 case RISCV::BI__builtin_riscv_pmulu_b11_u16x2:
1901 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2:
1902 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2:
1903 case RISCV::BI__builtin_riscv_pmul_b00_i16x4:
1904 case RISCV::BI__builtin_riscv_pmul_b01_i16x4:
1905 case RISCV::BI__builtin_riscv_pmul_b11_i16x4:
1906 case RISCV::BI__builtin_riscv_pmulu_b00_u16x4:
1907 case RISCV::BI__builtin_riscv_pmulu_b01_u16x4:
1908 case RISCV::BI__builtin_riscv_pmulu_b11_u16x4:
1909 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4:
1910 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4:
1911 case RISCV::BI__builtin_riscv_pmul_h00_i32x2:
1912 case RISCV::BI__builtin_riscv_pmul_h01_i32x2:
1913 case RISCV::BI__builtin_riscv_pmul_h11_i32x2:
1914 case RISCV::BI__builtin_riscv_pmulu_h00_u32x2:
1915 case RISCV::BI__builtin_riscv_pmulu_h01_u32x2:
1916 case RISCV::BI__builtin_riscv_pmulu_h11_u32x2:
1917 case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2:
1918 case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
1919 case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
1920 case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
1921 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
1922 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
1923 case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
1924 case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
1925 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
1926 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
1927 case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
1928 case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
1929 case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
1930 case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: {
1931 switch (BuiltinID) {
1932 default:
1933 llvm_unreachable("unexpected builtin ID");
1934 case RISCV::BI__builtin_riscv_pmul_b00_i16x2:
1935 case RISCV::BI__builtin_riscv_pmul_b00_i16x4:
1936 case RISCV::BI__builtin_riscv_pmul_h00_i32x2:
1937 ID = Intrinsic::riscv_pmul_00;
1938 break;
1939 case RISCV::BI__builtin_riscv_pmul_b01_i16x2:
1940 case RISCV::BI__builtin_riscv_pmul_b01_i16x4:
1941 case RISCV::BI__builtin_riscv_pmul_h01_i32x2:
1942 ID = Intrinsic::riscv_pmul_01;
1943 break;
1944 case RISCV::BI__builtin_riscv_pmul_b11_i16x2:
1945 case RISCV::BI__builtin_riscv_pmul_b11_i16x4:
1946 case RISCV::BI__builtin_riscv_pmul_h11_i32x2:
1947 ID = Intrinsic::riscv_pmul_11;
1948 break;
1949 case RISCV::BI__builtin_riscv_pmulu_b00_u16x2:
1950 case RISCV::BI__builtin_riscv_pmulu_b00_u16x4:
1951 case RISCV::BI__builtin_riscv_pmulu_h00_u32x2:
1952 ID = Intrinsic::riscv_pmulu_00;
1953 break;
1954 case RISCV::BI__builtin_riscv_pmulu_b01_u16x2:
1955 case RISCV::BI__builtin_riscv_pmulu_b01_u16x4:
1956 case RISCV::BI__builtin_riscv_pmulu_h01_u32x2:
1957 ID = Intrinsic::riscv_pmulu_01;
1958 break;
1959 case RISCV::BI__builtin_riscv_pmulu_b11_u16x2:
1960 case RISCV::BI__builtin_riscv_pmulu_b11_u16x4:
1961 case RISCV::BI__builtin_riscv_pmulu_h11_u32x2:
1962 ID = Intrinsic::riscv_pmulu_11;
1963 break;
1964 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x2:
1965 case RISCV::BI__builtin_riscv_pmulsu_b00_i16x4:
1966 case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2:
1967 ID = Intrinsic::riscv_pmulsu_00;
1968 break;
1969 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x2:
1970 case RISCV::BI__builtin_riscv_pmulsu_b11_i16x4:
1971 case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
1972 ID = Intrinsic::riscv_pmulsu_11;
1973 break;
1974 case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
1975 case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
1976 ID = Intrinsic::riscv_pmulh_b0;
1977 break;
1978 case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
1979 case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
1980 ID = Intrinsic::riscv_pmulh_b1;
1981 break;
1982 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
1983 case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
1984 ID = Intrinsic::riscv_pmulhsu_b0;
1985 break;
1986 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
1987 case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
1988 ID = Intrinsic::riscv_pmulhsu_b1;
1989 break;
1990 case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
1991 ID = Intrinsic::riscv_pmulh_h0;
1992 break;
1993 case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
1994 ID = Intrinsic::riscv_pmulh_h1;
1995 break;
1996 case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
1997 ID = Intrinsic::riscv_pmulhsu_h0;
1998 break;
1999 case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2:
2000 ID = Intrinsic::riscv_pmulhsu_h1;
2001 break;
2002 }
2003
2004 IntrinsicTypes = {ResultType};
2005 break;
2006 }
2007
2008 // Scalar Multiply Parts.
2009 case RISCV::BI__builtin_riscv_mul_h00_i32:
2010 case RISCV::BI__builtin_riscv_mul_w00_i64:
2011 case RISCV::BI__builtin_riscv_mul_h01_i32:
2012 case RISCV::BI__builtin_riscv_mul_w01_i64:
2013 case RISCV::BI__builtin_riscv_mul_h11_i32:
2014 case RISCV::BI__builtin_riscv_mul_w11_i64:
2015 case RISCV::BI__builtin_riscv_mulu_h00_u32:
2016 case RISCV::BI__builtin_riscv_mulu_w00_u64:
2017 case RISCV::BI__builtin_riscv_mulu_h01_u32:
2018 case RISCV::BI__builtin_riscv_mulu_w01_u64:
2019 case RISCV::BI__builtin_riscv_mulu_h11_u32:
2020 case RISCV::BI__builtin_riscv_mulu_w11_u64:
2021 case RISCV::BI__builtin_riscv_mulsu_h00_i32:
2022 case RISCV::BI__builtin_riscv_mulsu_w00_i64:
2023 case RISCV::BI__builtin_riscv_mulsu_h11_i32:
2024 case RISCV::BI__builtin_riscv_mulsu_w11_i64: {
2025 switch (BuiltinID) {
2026 default:
2027 llvm_unreachable("unexpected builtin ID");
2028 case RISCV::BI__builtin_riscv_mul_h00_i32:
2029 case RISCV::BI__builtin_riscv_mul_w00_i64:
2030 ID = Intrinsic::riscv_mul_00;
2031 break;
2032 case RISCV::BI__builtin_riscv_mul_h01_i32:
2033 case RISCV::BI__builtin_riscv_mul_w01_i64:
2034 ID = Intrinsic::riscv_mul_01;
2035 break;
2036 case RISCV::BI__builtin_riscv_mul_h11_i32:
2037 case RISCV::BI__builtin_riscv_mul_w11_i64:
2038 ID = Intrinsic::riscv_mul_11;
2039 break;
2040 case RISCV::BI__builtin_riscv_mulu_h00_u32:
2041 case RISCV::BI__builtin_riscv_mulu_w00_u64:
2042 ID = Intrinsic::riscv_mulu_00;
2043 break;
2044 case RISCV::BI__builtin_riscv_mulu_h01_u32:
2045 case RISCV::BI__builtin_riscv_mulu_w01_u64:
2046 ID = Intrinsic::riscv_mulu_01;
2047 break;
2048 case RISCV::BI__builtin_riscv_mulu_h11_u32:
2049 case RISCV::BI__builtin_riscv_mulu_w11_u64:
2050 ID = Intrinsic::riscv_mulu_11;
2051 break;
2052 case RISCV::BI__builtin_riscv_mulsu_h00_i32:
2053 case RISCV::BI__builtin_riscv_mulsu_w00_i64:
2054 ID = Intrinsic::riscv_mulsu_00;
2055 break;
2056 case RISCV::BI__builtin_riscv_mulsu_h11_i32:
2057 case RISCV::BI__builtin_riscv_mulsu_w11_i64:
2058 ID = Intrinsic::riscv_mulsu_11;
2059 break;
2060 }
2061
2062 IntrinsicTypes = {ResultType, Ops[0]->getType()};
2063 break;
2064 }
2065
2066 // Scalar Multiply High Parts
2067 case RISCV::BI__builtin_riscv_mulh_h0_i32:
2068 case RISCV::BI__builtin_riscv_mulh_h1_i32:
2069 case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
2070 case RISCV::BI__builtin_riscv_mulhsu_h1_i32: {
2071 switch (BuiltinID) {
2072 default:
2073 llvm_unreachable("unexpected builtin ID");
2074 case RISCV::BI__builtin_riscv_mulh_h0_i32:
2075 ID = Intrinsic::riscv_mulh_h0;
2076 break;
2077 case RISCV::BI__builtin_riscv_mulh_h1_i32:
2078 ID = Intrinsic::riscv_mulh_h1;
2079 break;
2080 case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
2081 ID = Intrinsic::riscv_mulhsu_h0;
2082 break;
2083 case RISCV::BI__builtin_riscv_mulhsu_h1_i32:
2084 ID = Intrinsic::riscv_mulhsu_h1;
2085 break;
2086 }
2087
2088 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2089 break;
2090 }
2091
2092 // Packed "Q-format" Multiply Parts Accumulate
2093 case RISCV::BI__builtin_riscv_mqacc_h00_i32:
2094 case RISCV::BI__builtin_riscv_mqacc_h01_i32:
2095 case RISCV::BI__builtin_riscv_mqacc_h11_i32:
2096 case RISCV::BI__builtin_riscv_mqracc_h00_i32:
2097 case RISCV::BI__builtin_riscv_mqracc_h01_i32:
2098 case RISCV::BI__builtin_riscv_mqracc_h11_i32:
2099 case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2:
2100 case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2:
2101 case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2:
2102 case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2:
2103 case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2:
2104 case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2:
2105 case RISCV::BI__builtin_riscv_mqacc_w00_i64:
2106 case RISCV::BI__builtin_riscv_mqacc_w01_i64:
2107 case RISCV::BI__builtin_riscv_mqacc_w11_i64:
2108 case RISCV::BI__builtin_riscv_mqracc_w00_i64:
2109 case RISCV::BI__builtin_riscv_mqracc_w01_i64:
2110 case RISCV::BI__builtin_riscv_mqracc_w11_i64: {
2111 switch (BuiltinID) {
2112 default:
2113 llvm_unreachable("unexpected builtin ID");
2114 case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2:
2115 ID = Intrinsic::riscv_pmqacc_h00;
2116 break;
2117 case RISCV::BI__builtin_riscv_pmqacc_h01_i32x2:
2118 ID = Intrinsic::riscv_pmqacc_h01;
2119 break;
2120 case RISCV::BI__builtin_riscv_pmqacc_h11_i32x2:
2121 ID = Intrinsic::riscv_pmqacc_h11;
2122 break;
2123 case RISCV::BI__builtin_riscv_pmqracc_h00_i32x2:
2124 ID = Intrinsic::riscv_pmqracc_h00;
2125 break;
2126 case RISCV::BI__builtin_riscv_pmqracc_h01_i32x2:
2127 ID = Intrinsic::riscv_pmqracc_h01;
2128 break;
2129 case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2:
2130 ID = Intrinsic::riscv_pmqracc_h11;
2131 break;
2132 // Scalar "Q-format" Multiply Parts Accumulate
2133 case RISCV::BI__builtin_riscv_mqacc_h00_i32:
2134 case RISCV::BI__builtin_riscv_mqacc_w00_i64:
2135 ID = Intrinsic::riscv_mqacc_00;
2136 break;
2137 case RISCV::BI__builtin_riscv_mqacc_h01_i32:
2138 case RISCV::BI__builtin_riscv_mqacc_w01_i64:
2139 ID = Intrinsic::riscv_mqacc_01;
2140 break;
2141 case RISCV::BI__builtin_riscv_mqacc_h11_i32:
2142 case RISCV::BI__builtin_riscv_mqacc_w11_i64:
2143 ID = Intrinsic::riscv_mqacc_11;
2144 break;
2145 case RISCV::BI__builtin_riscv_mqracc_h00_i32:
2146 case RISCV::BI__builtin_riscv_mqracc_w00_i64:
2147 ID = Intrinsic::riscv_mqracc_00;
2148 break;
2149 case RISCV::BI__builtin_riscv_mqracc_h01_i32:
2150 case RISCV::BI__builtin_riscv_mqracc_w01_i64:
2151 ID = Intrinsic::riscv_mqracc_01;
2152 break;
2153 case RISCV::BI__builtin_riscv_mqracc_h11_i32:
2154 case RISCV::BI__builtin_riscv_mqracc_w11_i64:
2155 ID = Intrinsic::riscv_mqracc_11;
2156 break;
2157 }
2158
2159 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2160 break;
2161 }
2162
2163 // Packed Multiply Parts Accumulate.
2164 case RISCV::BI__builtin_riscv_macc_h00_i32:
2165 case RISCV::BI__builtin_riscv_pmacc_h00_i32x2:
2166 case RISCV::BI__builtin_riscv_macc_w00_i64:
2167 case RISCV::BI__builtin_riscv_macc_h01_i32:
2168 case RISCV::BI__builtin_riscv_pmacc_h01_i32x2:
2169 case RISCV::BI__builtin_riscv_macc_w01_i64:
2170 case RISCV::BI__builtin_riscv_macc_h11_i32:
2171 case RISCV::BI__builtin_riscv_pmacc_h11_i32x2:
2172 case RISCV::BI__builtin_riscv_macc_w11_i64:
2173 case RISCV::BI__builtin_riscv_maccu_h00_u32:
2174 case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2:
2175 case RISCV::BI__builtin_riscv_maccu_w00_u64:
2176 case RISCV::BI__builtin_riscv_maccu_h01_u32:
2177 case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2:
2178 case RISCV::BI__builtin_riscv_maccu_w01_u64:
2179 case RISCV::BI__builtin_riscv_maccu_h11_u32:
2180 case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2:
2181 case RISCV::BI__builtin_riscv_maccu_w11_u64:
2182 case RISCV::BI__builtin_riscv_maccsu_h00_i32:
2183 case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2:
2184 case RISCV::BI__builtin_riscv_maccsu_w00_i64:
2185 case RISCV::BI__builtin_riscv_maccsu_h11_i32:
2186 case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2:
2187 case RISCV::BI__builtin_riscv_maccsu_w11_i64: {
2188 switch (BuiltinID) {
2189 default:
2190 llvm_unreachable("unexpected builtin ID");
2191 case RISCV::BI__builtin_riscv_macc_h00_i32:
2192 case RISCV::BI__builtin_riscv_pmacc_h00_i32x2:
2193 case RISCV::BI__builtin_riscv_macc_w00_i64:
2194 ID = Intrinsic::riscv_macc_00;
2195 break;
2196 case RISCV::BI__builtin_riscv_macc_h01_i32:
2197 case RISCV::BI__builtin_riscv_pmacc_h01_i32x2:
2198 case RISCV::BI__builtin_riscv_macc_w01_i64:
2199 ID = Intrinsic::riscv_macc_01;
2200 break;
2201 case RISCV::BI__builtin_riscv_macc_h11_i32:
2202 case RISCV::BI__builtin_riscv_pmacc_h11_i32x2:
2203 case RISCV::BI__builtin_riscv_macc_w11_i64:
2204 ID = Intrinsic::riscv_macc_11;
2205 break;
2206 case RISCV::BI__builtin_riscv_maccu_h00_u32:
2207 case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2:
2208 case RISCV::BI__builtin_riscv_maccu_w00_u64:
2209 ID = Intrinsic::riscv_maccu_00;
2210 break;
2211 case RISCV::BI__builtin_riscv_maccu_h01_u32:
2212 case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2:
2213 case RISCV::BI__builtin_riscv_maccu_w01_u64:
2214 ID = Intrinsic::riscv_maccu_01;
2215 break;
2216 case RISCV::BI__builtin_riscv_maccu_h11_u32:
2217 case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2:
2218 case RISCV::BI__builtin_riscv_maccu_w11_u64:
2219 ID = Intrinsic::riscv_maccu_11;
2220 break;
2221 case RISCV::BI__builtin_riscv_maccsu_h00_i32:
2222 case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2:
2223 case RISCV::BI__builtin_riscv_maccsu_w00_i64:
2224 ID = Intrinsic::riscv_maccsu_00;
2225 break;
2226 case RISCV::BI__builtin_riscv_maccsu_h11_i32:
2227 case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2:
2228 case RISCV::BI__builtin_riscv_maccsu_w11_i64:
2229 ID = Intrinsic::riscv_maccsu_11;
2230 break;
2231 }
2232
2233 IntrinsicTypes = {ResultType, Ops[1]->getType()};
2234 break;
2235 }
2236
2237 // Zk builtins
2238
2239 // Zknh
2240 case RISCV::BI__builtin_riscv_sha256sig0:
2241 ID = Intrinsic::riscv_sha256sig0;
2242 break;
2243 case RISCV::BI__builtin_riscv_sha256sig1:
2244 ID = Intrinsic::riscv_sha256sig1;
2245 break;
2246 case RISCV::BI__builtin_riscv_sha256sum0:
2247 ID = Intrinsic::riscv_sha256sum0;
2248 break;
2249 case RISCV::BI__builtin_riscv_sha256sum1:
2250 ID = Intrinsic::riscv_sha256sum1;
2251 break;
2252
2253 // Zksed
2254 case RISCV::BI__builtin_riscv_sm4ks:
2255 ID = Intrinsic::riscv_sm4ks;
2256 break;
2257 case RISCV::BI__builtin_riscv_sm4ed:
2258 ID = Intrinsic::riscv_sm4ed;
2259 break;
2260
2261 // Zksh
2262 case RISCV::BI__builtin_riscv_sm3p0:
2263 ID = Intrinsic::riscv_sm3p0;
2264 break;
2265 case RISCV::BI__builtin_riscv_sm3p1:
2266 ID = Intrinsic::riscv_sm3p1;
2267 break;
2268
2269 case RISCV::BI__builtin_riscv_clz_32:
2270 case RISCV::BI__builtin_riscv_clz_64: {
2271 Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
2272 Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
2273 if (Result->getType() != ResultType)
2274 Result =
2275 Builder.CreateIntCast(Result, ResultType, /*isSigned*/ false, "cast");
2276 return Result;
2277 }
2278 case RISCV::BI__builtin_riscv_ctz_32:
2279 case RISCV::BI__builtin_riscv_ctz_64: {
2280 Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
2281 Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
2282 if (Result->getType() != ResultType)
2283 Result =
2284 Builder.CreateIntCast(Result, ResultType, /*isSigned*/ false, "cast");
2285 return Result;
2286 }
2287
2288 // Zihintntl
2289 case RISCV::BI__builtin_riscv_ntl_load: {
2290 llvm::Type *ResTy = ConvertType(E->getType());
2291 unsigned DomainVal = 5; // Default __RISCV_NTLH_ALL
2292 if (Ops.size() == 2)
2293 DomainVal = cast<ConstantInt>(Ops[1])->getZExtValue();
2294
2295 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
2296 getLLVMContext(),
2297 llvm::ConstantAsMetadata::get(Builder.getInt32(DomainVal)));
2298 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
2299 getLLVMContext(), llvm::ConstantAsMetadata::get(Builder.getInt32(1)));
2300
2301 int Width;
2302 if(ResTy->isScalableTy()) {
2303 const ScalableVectorType *SVTy = cast<ScalableVectorType>(ResTy);
2304 llvm::Type *ScalarTy = ResTy->getScalarType();
2305 Width = ScalarTy->getPrimitiveSizeInBits() *
2306 SVTy->getElementCount().getKnownMinValue();
2307 } else
2308 Width = ResTy->getPrimitiveSizeInBits();
2309 LoadInst *Load = Builder.CreateLoad(
2310 Address(Ops[0], ResTy, CharUnits::fromQuantity(Width / 8)));
2311
2312 Load->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
2313 Load->setMetadata(CGM.getModule().getMDKindID("riscv-nontemporal-domain"),
2314 RISCVDomainNode);
2315
2316 return Load;
2317 }
2318 case RISCV::BI__builtin_riscv_ntl_store: {
2319 unsigned DomainVal = 5; // Default __RISCV_NTLH_ALL
2320 if (Ops.size() == 3)
2321 DomainVal = cast<ConstantInt>(Ops[2])->getZExtValue();
2322
2323 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
2324 getLLVMContext(),
2325 llvm::ConstantAsMetadata::get(Builder.getInt32(DomainVal)));
2326 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
2327 getLLVMContext(), llvm::ConstantAsMetadata::get(Builder.getInt32(1)));
2328
2329 StoreInst *Store = Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
2330 Store->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
2331 Store->setMetadata(CGM.getModule().getMDKindID("riscv-nontemporal-domain"),
2332 RISCVDomainNode);
2333
2334 return Store;
2335 }
2336 // Zihintpause
2337 case RISCV::BI__builtin_riscv_pause: {
2338 llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
2339 return Builder.CreateCall(Fn, {});
2340 }
2341
2342 // XCValu
2343 case RISCV::BI__builtin_riscv_cv_alu_addN:
2344 ID = Intrinsic::riscv_cv_alu_addN;
2345 break;
2346 case RISCV::BI__builtin_riscv_cv_alu_addRN:
2347 ID = Intrinsic::riscv_cv_alu_addRN;
2348 break;
2349 case RISCV::BI__builtin_riscv_cv_alu_adduN:
2350 ID = Intrinsic::riscv_cv_alu_adduN;
2351 break;
2352 case RISCV::BI__builtin_riscv_cv_alu_adduRN:
2353 ID = Intrinsic::riscv_cv_alu_adduRN;
2354 break;
2355 case RISCV::BI__builtin_riscv_cv_alu_clip:
2356 ID = Intrinsic::riscv_cv_alu_clip;
2357 break;
2358 case RISCV::BI__builtin_riscv_cv_alu_clipu:
2359 ID = Intrinsic::riscv_cv_alu_clipu;
2360 break;
2361 case RISCV::BI__builtin_riscv_cv_alu_extbs:
2362 return Builder.CreateSExt(Builder.CreateTrunc(Ops[0], Int8Ty), Int32Ty,
2363 "extbs");
2364 case RISCV::BI__builtin_riscv_cv_alu_extbz:
2365 return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int8Ty), Int32Ty,
2366 "extbz");
2367 case RISCV::BI__builtin_riscv_cv_alu_exths:
2368 return Builder.CreateSExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
2369 "exths");
2370 case RISCV::BI__builtin_riscv_cv_alu_exthz:
2371 return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
2372 "exthz");
2373 case RISCV::BI__builtin_riscv_cv_alu_sle:
2374 return Builder.CreateZExt(Builder.CreateICmpSLE(Ops[0], Ops[1]), Int32Ty,
2375 "sle");
2376 case RISCV::BI__builtin_riscv_cv_alu_sleu:
2377 return Builder.CreateZExt(Builder.CreateICmpULE(Ops[0], Ops[1]), Int32Ty,
2378 "sleu");
2379 case RISCV::BI__builtin_riscv_cv_alu_subN:
2380 ID = Intrinsic::riscv_cv_alu_subN;
2381 break;
2382 case RISCV::BI__builtin_riscv_cv_alu_subRN:
2383 ID = Intrinsic::riscv_cv_alu_subRN;
2384 break;
2385 case RISCV::BI__builtin_riscv_cv_alu_subuN:
2386 ID = Intrinsic::riscv_cv_alu_subuN;
2387 break;
2388 case RISCV::BI__builtin_riscv_cv_alu_subuRN:
2389 ID = Intrinsic::riscv_cv_alu_subuRN;
2390 break;
2391
2392 // XAndesPerf
2393 case RISCV::BI__builtin_riscv_nds_ffb_32:
2394 case RISCV::BI__builtin_riscv_nds_ffb_64:
2395 IntrinsicTypes = {ResultType};
2396 ID = Intrinsic::riscv_nds_ffb;
2397 break;
2398 case RISCV::BI__builtin_riscv_nds_ffzmism_32:
2399 case RISCV::BI__builtin_riscv_nds_ffzmism_64:
2400 IntrinsicTypes = {ResultType};
2401 ID = Intrinsic::riscv_nds_ffzmism;
2402 break;
2403 case RISCV::BI__builtin_riscv_nds_ffmism_32:
2404 case RISCV::BI__builtin_riscv_nds_ffmism_64:
2405 IntrinsicTypes = {ResultType};
2406 ID = Intrinsic::riscv_nds_ffmism;
2407 break;
2408 case RISCV::BI__builtin_riscv_nds_flmism_32:
2409 case RISCV::BI__builtin_riscv_nds_flmism_64:
2410 IntrinsicTypes = {ResultType};
2411 ID = Intrinsic::riscv_nds_flmism;
2412 break;
2413
2414 // XAndesBFHCvt
2415 case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
2416 return Builder.CreateFPExt(Ops[0], FloatTy);
2417 case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
2418 return Builder.CreateFPTrunc(Ops[0], BFloatTy);
2419
2420 // Vector builtins are handled from here.
2421#include "clang/Basic/riscv_vector_builtin_cg.inc"
2422
2423 // SiFive Vector builtins are handled from here.
2424#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
2425
2426 // Andes Vector builtins are handled from here.
2427#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
2428 }
2429
2430 assert(ID != Intrinsic::not_intrinsic);
2431
2432 llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
2433 return Builder.CreateCall(F, Ops, "");
2434}
V
#define V(N, I)
Definition ASTContext.h:3855
emitRVVStridedSegLoadTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVStridedSegLoadTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:434
emitRVVPseudoUnaryBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:120
emitRVVCreateBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVCreateBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:943
emitRVVGetBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVGetBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:893
emitRVVFloatingPointBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVFloatingPointBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:554
emitRVVFloatingReductionBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVFloatingReductionBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:821
emitRVVPseudoMaskBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoMaskBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:180
RVV_VMA
static constexpr unsigned RVV_VMA
Definition RISCV.cpp:26
loadRISCVFeatureBits
static Value * loadRISCVFeatureBits(unsigned Index, CGBuilderTy &Builder, CodeGenModule &CGM)
Definition RISCV.cpp:986
emitRVVFloatingUnaryBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVFloatingUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:750
emitRVVFMABuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVFMABuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:692
emitRVVVLEFFBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVVLEFFBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:32
emitRVVPseudoVNotBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoVNotBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:150
emitRVVStridedSegStoreTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVStridedSegStoreTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:465
emitRVVVSEMaskBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVVSEMaskBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:312
emitRVVNarrowingClipBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVNarrowingClipBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:523
emitRVVVsetvliBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVVsetvliBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:301
emitRVVVSSEBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVVSSEBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:69
emitRVVIndexedSegLoadTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVIndexedSegLoadTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:625
emitRVVFloatingConvBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVFloatingConvBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:787
emitRVVUnitStridedSegLoadFFTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVUnitStridedSegLoadFFTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:394
emitRVVAveragingBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVAveragingBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:493
emitRVVUnitStridedSegStoreTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVUnitStridedSegStoreTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:367
emitRVVWideningFMABuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVWideningFMABuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:721
emitRVVIndexedStoreBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVIndexedStoreBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:93
emitRVVSetBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVSetBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:918
emitRVVIndexedSegStoreTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVIndexedSegStoreTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:660
emitRVVReinterpretBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVReinterpretBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:854
emitRVVPseudoVWCVTBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoVWCVTBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:222
emitRVVPseudoVNCVTBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoVNCVTBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:252
RVV_VTA
static constexpr unsigned RVV_VTA
Definition RISCV.cpp:25
emitRVVWideningFloatingPointBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVWideningFloatingPointBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:589
emitRVVVlenbBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVVlenbBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:284
emitRVVUnitStridedSegLoadTupleBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVUnitStridedSegLoadTupleBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked, unsigned SegInstSEW)
Definition RISCV.cpp:336
emitRVVPseudoVFUnaryBuiltin
static LLVM_ATTRIBUTE_NOINLINE Value * emitRVVPseudoVFUnaryBuiltin(CodeGenFunction *CGF, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Type *ResultType, Intrinsic::ID ID, SmallVectorImpl< Value * > &Ops, int PolicyAttrs, bool IsMasked)
Definition RISCV.cpp:195
getType
TokenType getType() const
Returns the token's type, e.g.
Definition FormatToken.h:999
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
clang::ASTContext::GetBuiltinType
QualType GetBuiltinType(unsigned ID, GetBuiltinTypeError &Error, unsigned *IntegerConstantArgs=nullptr) const
Return the type for the specified builtin.
Definition ASTContext.cpp:13078
clang::ASTContext::GE_None
@ GE_None
No error.
Definition ASTContext.h:2746
clang::ASTContext::GE_Missing_type
@ GE_Missing_type
Missing a type.
Definition ASTContext.h:2749
clang::CallExpr
CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).
Definition Expr.h:2991
clang::CallExpr::getArg
Expr * getArg(unsigned Arg)
getArg - Return the specified argument.
Definition Expr.h:3195
clang::CallExpr::getNumArgs
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this call.
Definition Expr.h:3182
clang::CharUnits
This is an opaque type for sizes expressed in character units.
Definition CharUnits.h:38
clang::CharUnits::fromQuantity
static CharUnits fromQuantity(QuantityType Quantity)
Construct a CharUnits quantity from a raw integer type.
Definition CharUnits.h:58
clang::CodeGen::Address
Like RawAddress, an abstract representation of an aligned address, but the pointer contained in this ...
Definition Address.h:128
clang::CodeGen::CodeGenFunction
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
Definition CodeGenFunction.h:259
clang::CodeGen::CodeGenFunction::EmitScalarOrConstFoldImmArg
llvm::Value * EmitScalarOrConstFoldImmArg(unsigned ICEArguments, unsigned Idx, const CallExpr *E)
Definition CodeGenFunction.cpp:2215
clang::CodeGen::CodeGenFunction::EmitRISCVCpuSupports
llvm::Value * EmitRISCVCpuSupports(const CallExpr *E)
Definition RISCV.cpp:976
clang::CodeGen::CodeGenFunction::EmitRISCVCpuInit
llvm::Value * EmitRISCVCpuInit()
Definition RISCV.cpp:966
clang::CodeGen::CodeGenFunction::ConvertType
llvm::Type * ConvertType(QualType T)
Definition CodeGenFunction.cpp:229
clang::CodeGen::CodeGenFunction::EmitRISCVBuiltinExpr
llvm::Value * EmitRISCVBuiltinExpr(unsigned BuiltinID, const CallExpr *E, ReturnValueSlot ReturnValue)
Definition RISCV.cpp:1079
clang::CodeGen::CodeGenFunction::EmitRISCVCpuIs
llvm::Value * EmitRISCVCpuIs(const CallExpr *E)
Definition RISCV.cpp:1038
clang::CodeGen::CodeGenFunction::EmitAggExprToLValue
LValue EmitAggExprToLValue(const Expr *E)
EmitAggExprToLValue - Emit the computation of the specified expression of aggregate type into a tempo...
Definition CGExprAgg.cpp:2182
clang::CodeGen::CodeGenFunction::hasAggregateEvaluationKind
static bool hasAggregateEvaluationKind(QualType T)
Definition CodeGenFunction.h:2724
clang::CodeGen::CodeGenFunction::ReturnValue
Address ReturnValue
ReturnValue - The temporary alloca to hold the return value.
Definition CodeGenFunction.h:427
clang::CodeGen::CodeGenFunction::getLLVMContext
llvm::LLVMContext & getLLVMContext()
Definition CodeGenFunction.h:2285
clang::CodeGen::CodeGenModule
This class organizes the cross-function state that is used while generating LLVM code.
Definition CodeGenModule.h:333
clang::CodeGen::CodeGenModule::CreateRuntimeVariable
llvm::Constant * CreateRuntimeVariable(llvm::Type *Ty, StringRef Name)
Create a new runtime global variable with the specified type and name.
Definition CodeGenModule.cpp:6345
clang::CodeGen::CodeGenModule::getLLVMContext
llvm::LLVMContext & getLLVMContext()
Definition CodeGenModule.h:938
clang::CodeGen::CodeGenModule::getIntrinsic
llvm::Function * getIntrinsic(unsigned IID, ArrayRef< llvm::Type * > Tys={})
Definition CodeGenModule.cpp:7303
clang::CodeGen::LValue
LValue - This represents an lvalue references.
Definition CGValue.h:183
clang::CodeGen::LValue::getAddress
Address getAddress() const
Definition CGValue.h:373
clang::CodeGen::ReturnValueSlot
ReturnValueSlot - Contains the address where the return value of a function can be stored,...
Definition CGCall.h:384
clang::Expr
This represents one expression.
Definition Expr.h:113
clang::Expr::IgnoreParenCasts
Expr * IgnoreParenCasts() LLVM_READONLY
Skip past any parentheses and casts which might surround this expression until reaching a fixed point...
Definition Expr.cpp:3131
clang::Expr::getType
QualType getType() const
Definition Expr.h:145
clang::Value::getType
QualType getType() const
Definition Value.cpp:238
clang
Top level wrappers for InstallAPI frontend operations.
Definition CalledOnceCheck.h:17
clang::isa
bool isa(CodeGen::Address addr)
Definition Address.h:330
clang::ObjCSubstitutionContext::Result
@ Result
The result type of a method or function.
Definition TypeBase.h:906
clang::cast
U cast(CodeGen::Address addr)
Definition Address.h:327
llvm
Diagnostic wrappers for TextAPI types for error reporting.
Definition Dominators.h:30
clang::CodeGen::CodeGenTypeCache::Int8Ty
llvm::IntegerType * Int8Ty
i8, i16, i32, and i64
Definition CodeGenTypeCache.h:37
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