1083 if (BuiltinID == Builtin::BI__builtin_cpu_supports)
1085 if (BuiltinID == Builtin::BI__builtin_cpu_init)
1087 if (BuiltinID == Builtin::BI__builtin_cpu_is)
1094 unsigned ICEArguments = 0;
1102 if (BuiltinID == RISCVVector::BI__builtin_rvv_vget_v ||
1103 BuiltinID == RISCVVector::BI__builtin_rvv_vset_v)
1104 ICEArguments = 1 << 1;
1109 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_load)
1110 ICEArguments |= (1 << 1);
1111 if (BuiltinID == RISCV::BI__builtin_riscv_ntl_store)
1112 ICEArguments |= (1 << 2);
1114 for (
unsigned i = 0, e = E->
getNumArgs(); i != e; i++) {
1119 Ops.push_back(AggValue);
1125 Intrinsic::ID ID = Intrinsic::not_intrinsic;
1126 int PolicyAttrs = 0;
1127 bool IsMasked =
false;
1129 unsigned SegInstSEW = 8;
1131 unsigned TWiden = 0;
1135 switch (BuiltinID) {
1136 default: llvm_unreachable(
"unexpected builtin ID");
1137 case RISCV::BI__builtin_riscv_orc_b_32:
1138 case RISCV::BI__builtin_riscv_orc_b_64:
1139 case RISCV::BI__builtin_riscv_clmul_32:
1140 case RISCV::BI__builtin_riscv_clmul_64:
1141 case RISCV::BI__builtin_riscv_clmulh_32:
1142 case RISCV::BI__builtin_riscv_clmulh_64:
1143 case RISCV::BI__builtin_riscv_clmulr_32:
1144 case RISCV::BI__builtin_riscv_clmulr_64:
1145 case RISCV::BI__builtin_riscv_xperm4_32:
1146 case RISCV::BI__builtin_riscv_xperm4_64:
1147 case RISCV::BI__builtin_riscv_xperm8_32:
1148 case RISCV::BI__builtin_riscv_xperm8_64:
1149 case RISCV::BI__builtin_riscv_brev8_32:
1150 case RISCV::BI__builtin_riscv_brev8_64:
1151 case RISCV::BI__builtin_riscv_zip_32:
1152 case RISCV::BI__builtin_riscv_unzip_32: {
1153 switch (BuiltinID) {
1154 default: llvm_unreachable(
"unexpected builtin ID");
1156 case RISCV::BI__builtin_riscv_orc_b_32:
1157 case RISCV::BI__builtin_riscv_orc_b_64:
1158 ID = Intrinsic::riscv_orc_b;
1162 case RISCV::BI__builtin_riscv_clmul_32:
1163 case RISCV::BI__builtin_riscv_clmul_64:
1164 ID = Intrinsic::clmul;
1166 case RISCV::BI__builtin_riscv_clmulh_32:
1167 case RISCV::BI__builtin_riscv_clmulh_64:
1168 ID = Intrinsic::riscv_clmulh;
1170 case RISCV::BI__builtin_riscv_clmulr_32:
1171 case RISCV::BI__builtin_riscv_clmulr_64:
1172 ID = Intrinsic::riscv_clmulr;
1176 case RISCV::BI__builtin_riscv_xperm8_32:
1177 case RISCV::BI__builtin_riscv_xperm8_64:
1178 ID = Intrinsic::riscv_xperm8;
1180 case RISCV::BI__builtin_riscv_xperm4_32:
1181 case RISCV::BI__builtin_riscv_xperm4_64:
1182 ID = Intrinsic::riscv_xperm4;
1186 case RISCV::BI__builtin_riscv_brev8_32:
1187 case RISCV::BI__builtin_riscv_brev8_64:
1188 ID = Intrinsic::riscv_brev8;
1190 case RISCV::BI__builtin_riscv_zip_32:
1191 ID = Intrinsic::riscv_zip;
1193 case RISCV::BI__builtin_riscv_unzip_32:
1194 ID = Intrinsic::riscv_unzip;
1198 IntrinsicTypes = {ResultType};
1203 case RISCV::BI__builtin_riscv_paadd_i8x4:
1204 case RISCV::BI__builtin_riscv_paadd_i16x2:
1205 case RISCV::BI__builtin_riscv_paadd_i8x8:
1206 case RISCV::BI__builtin_riscv_paadd_i16x4:
1207 case RISCV::BI__builtin_riscv_paadd_i32x2:
1208 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1209 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1210 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1211 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1212 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1213 case RISCV::BI__builtin_riscv_pasub_i8x4:
1214 case RISCV::BI__builtin_riscv_pasub_i16x2:
1215 case RISCV::BI__builtin_riscv_pasub_i8x8:
1216 case RISCV::BI__builtin_riscv_pasub_i16x4:
1217 case RISCV::BI__builtin_riscv_pasub_i32x2:
1218 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1219 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1220 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1221 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1222 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1224 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1225 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1226 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1227 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1228 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1229 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1230 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1231 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1232 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1233 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1234 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1235 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1236 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1237 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1238 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1239 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1240 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1241 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1243 case RISCV::BI__builtin_riscv_pabd_i8x4:
1244 case RISCV::BI__builtin_riscv_pabd_i16x2:
1245 case RISCV::BI__builtin_riscv_pabd_i8x8:
1246 case RISCV::BI__builtin_riscv_pabd_i16x4:
1247 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1248 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1249 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1250 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1252 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1253 case RISCV::BI__builtin_riscv_pmerge_i8x4:
1254 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1255 case RISCV::BI__builtin_riscv_pmerge_i16x2:
1256 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1257 case RISCV::BI__builtin_riscv_pmerge_i8x8:
1258 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1259 case RISCV::BI__builtin_riscv_pmerge_i16x4:
1260 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1261 case RISCV::BI__builtin_riscv_pmerge_i32x2:
1263 case RISCV::BI__builtin_riscv_psabs_i8x4:
1264 case RISCV::BI__builtin_riscv_psabs_i16x2:
1265 case RISCV::BI__builtin_riscv_psabs_i8x8:
1266 case RISCV::BI__builtin_riscv_psabs_i16x4:
1268 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1269 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1270 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1271 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1272 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1273 case RISCV::BI__builtin_riscv_pmulqr_i32x2: {
1274 switch (BuiltinID) {
1276 llvm_unreachable(
"unexpected builtin ID");
1277 case RISCV::BI__builtin_riscv_paadd_i8x4:
1278 case RISCV::BI__builtin_riscv_paadd_i16x2:
1279 case RISCV::BI__builtin_riscv_paadd_i8x8:
1280 case RISCV::BI__builtin_riscv_paadd_i16x4:
1281 case RISCV::BI__builtin_riscv_paadd_i32x2:
1282 ID = Intrinsic::riscv_paadd;
1284 case RISCV::BI__builtin_riscv_paaddu_u8x4:
1285 case RISCV::BI__builtin_riscv_paaddu_u16x2:
1286 case RISCV::BI__builtin_riscv_paaddu_u8x8:
1287 case RISCV::BI__builtin_riscv_paaddu_u16x4:
1288 case RISCV::BI__builtin_riscv_paaddu_u32x2:
1289 ID = Intrinsic::riscv_paaddu;
1291 case RISCV::BI__builtin_riscv_pasub_i8x4:
1292 case RISCV::BI__builtin_riscv_pasub_i16x2:
1293 case RISCV::BI__builtin_riscv_pasub_i8x8:
1294 case RISCV::BI__builtin_riscv_pasub_i16x4:
1295 case RISCV::BI__builtin_riscv_pasub_i32x2:
1296 ID = Intrinsic::riscv_pasub;
1298 case RISCV::BI__builtin_riscv_pasubu_u8x4:
1299 case RISCV::BI__builtin_riscv_pasubu_u16x2:
1300 case RISCV::BI__builtin_riscv_pasubu_u8x8:
1301 case RISCV::BI__builtin_riscv_pasubu_u16x4:
1302 case RISCV::BI__builtin_riscv_pasubu_u32x2:
1303 ID = Intrinsic::riscv_pasubu;
1305 case RISCV::BI__builtin_riscv_pas_x_i16x2:
1306 case RISCV::BI__builtin_riscv_pas_x_i16x4:
1307 case RISCV::BI__builtin_riscv_pas_x_i32x2:
1308 ID = Intrinsic::riscv_pas;
1310 case RISCV::BI__builtin_riscv_psa_x_i16x2:
1311 case RISCV::BI__builtin_riscv_psa_x_i16x4:
1312 case RISCV::BI__builtin_riscv_psa_x_i32x2:
1313 ID = Intrinsic::riscv_psa;
1315 case RISCV::BI__builtin_riscv_psas_x_i16x2:
1316 case RISCV::BI__builtin_riscv_psas_x_i16x4:
1317 case RISCV::BI__builtin_riscv_psas_x_i32x2:
1318 ID = Intrinsic::riscv_psas;
1320 case RISCV::BI__builtin_riscv_pssa_x_i16x2:
1321 case RISCV::BI__builtin_riscv_pssa_x_i16x4:
1322 case RISCV::BI__builtin_riscv_pssa_x_i32x2:
1323 ID = Intrinsic::riscv_pssa;
1325 case RISCV::BI__builtin_riscv_paas_x_i16x2:
1326 case RISCV::BI__builtin_riscv_paas_x_i16x4:
1327 case RISCV::BI__builtin_riscv_paas_x_i32x2:
1328 ID = Intrinsic::riscv_paas;
1330 case RISCV::BI__builtin_riscv_pasa_x_i16x2:
1331 case RISCV::BI__builtin_riscv_pasa_x_i16x4:
1332 case RISCV::BI__builtin_riscv_pasa_x_i32x2:
1333 ID = Intrinsic::riscv_pasa;
1335 case RISCV::BI__builtin_riscv_pabd_i8x4:
1336 case RISCV::BI__builtin_riscv_pabd_i16x2:
1337 case RISCV::BI__builtin_riscv_pabd_i8x8:
1338 case RISCV::BI__builtin_riscv_pabd_i16x4:
1339 ID = Intrinsic::riscv_pabd;
1341 case RISCV::BI__builtin_riscv_pabdu_u8x4:
1342 case RISCV::BI__builtin_riscv_pabdu_u16x2:
1343 case RISCV::BI__builtin_riscv_pabdu_u8x8:
1344 case RISCV::BI__builtin_riscv_pabdu_u16x4:
1345 ID = Intrinsic::riscv_pabdu;
1347 case RISCV::BI__builtin_riscv_pmerge_u8x4:
1348 case RISCV::BI__builtin_riscv_pmerge_i8x4:
1349 case RISCV::BI__builtin_riscv_pmerge_u16x2:
1350 case RISCV::BI__builtin_riscv_pmerge_i16x2:
1351 case RISCV::BI__builtin_riscv_pmerge_u8x8:
1352 case RISCV::BI__builtin_riscv_pmerge_i8x8:
1353 case RISCV::BI__builtin_riscv_pmerge_u16x4:
1354 case RISCV::BI__builtin_riscv_pmerge_i16x4:
1355 case RISCV::BI__builtin_riscv_pmerge_u32x2:
1356 case RISCV::BI__builtin_riscv_pmerge_i32x2:
1357 ID = Intrinsic::riscv_pmerge;
1359 case RISCV::BI__builtin_riscv_psabs_i8x4:
1360 case RISCV::BI__builtin_riscv_psabs_i16x2:
1361 case RISCV::BI__builtin_riscv_psabs_i8x8:
1362 case RISCV::BI__builtin_riscv_psabs_i16x4:
1363 ID = Intrinsic::riscv_psabs;
1365 case RISCV::BI__builtin_riscv_pmulq_i16x2:
1366 case RISCV::BI__builtin_riscv_pmulq_i16x4:
1367 case RISCV::BI__builtin_riscv_pmulq_i32x2:
1368 ID = Intrinsic::riscv_pmulq;
1370 case RISCV::BI__builtin_riscv_pmulqr_i16x2:
1371 case RISCV::BI__builtin_riscv_pmulqr_i16x4:
1372 case RISCV::BI__builtin_riscv_pmulqr_i32x2:
1373 ID = Intrinsic::riscv_pmulqr;
1377 IntrinsicTypes = {ResultType};
1382 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1383 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1384 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1385 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1386 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1387 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1388 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1389 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1390 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1391 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1392 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1393 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1394 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1395 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: {
1396 switch (BuiltinID) {
1398 llvm_unreachable(
"unexpected builtin ID");
1399 case RISCV::BI__builtin_riscv_predsum_i8x4_i32:
1400 case RISCV::BI__builtin_riscv_predsum_i16x2_i32:
1401 case RISCV::BI__builtin_riscv_predsum_i8x8_i32:
1402 case RISCV::BI__builtin_riscv_predsum_i16x4_i32:
1403 case RISCV::BI__builtin_riscv_predsum_i8x8_i64:
1404 case RISCV::BI__builtin_riscv_predsum_i16x4_i64:
1405 case RISCV::BI__builtin_riscv_predsum_i32x2_i64:
1406 ID = Intrinsic::riscv_predsum;
1408 case RISCV::BI__builtin_riscv_predsumu_u8x4_u32:
1409 case RISCV::BI__builtin_riscv_predsumu_u16x2_u32:
1410 case RISCV::BI__builtin_riscv_predsumu_u8x8_u32:
1411 case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
1412 case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
1413 case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
1414 case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
1415 ID = Intrinsic::riscv_predsumu;
1419 IntrinsicTypes = {ResultType, Ops[0]->getType()};
1424 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1425 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1426 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1427 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1428 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1429 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64: {
1430 switch (BuiltinID) {
1432 llvm_unreachable(
"unexpected builtin ID");
1433 case RISCV::BI__builtin_riscv_pabdsumu_u8x4_u32:
1434 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u32:
1435 case RISCV::BI__builtin_riscv_pabdsumu_u8x8_u64:
1436 ID = Intrinsic::riscv_pabdsumu;
1438 case RISCV::BI__builtin_riscv_pabdsumau_u8x4_u32:
1439 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u32:
1440 case RISCV::BI__builtin_riscv_pabdsumau_u8x8_u64:
1441 ID = Intrinsic::riscv_pabdsumau;
1447 IntrinsicTypes = {ResultType, Ops.back()->getType()};
1454 case RISCV::BI__builtin_riscv_sha256sig0:
1455 ID = Intrinsic::riscv_sha256sig0;
1457 case RISCV::BI__builtin_riscv_sha256sig1:
1458 ID = Intrinsic::riscv_sha256sig1;
1460 case RISCV::BI__builtin_riscv_sha256sum0:
1461 ID = Intrinsic::riscv_sha256sum0;
1463 case RISCV::BI__builtin_riscv_sha256sum1:
1464 ID = Intrinsic::riscv_sha256sum1;
1468 case RISCV::BI__builtin_riscv_sm4ks:
1469 ID = Intrinsic::riscv_sm4ks;
1471 case RISCV::BI__builtin_riscv_sm4ed:
1472 ID = Intrinsic::riscv_sm4ed;
1476 case RISCV::BI__builtin_riscv_sm3p0:
1477 ID = Intrinsic::riscv_sm3p0;
1479 case RISCV::BI__builtin_riscv_sm3p1:
1480 ID = Intrinsic::riscv_sm3p1;
1483 case RISCV::BI__builtin_riscv_clz_32:
1484 case RISCV::BI__builtin_riscv_clz_64: {
1487 if (
Result->getType() != ResultType)
1492 case RISCV::BI__builtin_riscv_ctz_32:
1493 case RISCV::BI__builtin_riscv_ctz_64: {
1496 if (
Result->getType() != ResultType)
1503 case RISCV::BI__builtin_riscv_ntl_load: {
1505 unsigned DomainVal = 5;
1506 if (Ops.size() == 2)
1509 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1511 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1512 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1516 if(ResTy->isScalableTy()) {
1518 llvm::Type *ScalarTy = ResTy->getScalarType();
1519 Width = ScalarTy->getPrimitiveSizeInBits() *
1520 SVTy->getElementCount().getKnownMinValue();
1522 Width = ResTy->getPrimitiveSizeInBits();
1523 LoadInst *Load =
Builder.CreateLoad(
1526 Load->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1527 Load->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1532 case RISCV::BI__builtin_riscv_ntl_store: {
1533 unsigned DomainVal = 5;
1534 if (Ops.size() == 3)
1537 llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
1539 llvm::ConstantAsMetadata::get(
Builder.getInt32(DomainVal)));
1540 llvm::MDNode *NontemporalNode = llvm::MDNode::get(
1543 StoreInst *Store =
Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
1544 Store->setMetadata(llvm::LLVMContext::MD_nontemporal, NontemporalNode);
1545 Store->setMetadata(
CGM.getModule().getMDKindID(
"riscv-nontemporal-domain"),
1551 case RISCV::BI__builtin_riscv_pause: {
1552 llvm::Function *Fn =
CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
1553 return Builder.CreateCall(Fn, {});
1557 case RISCV::BI__builtin_riscv_cv_alu_addN:
1558 ID = Intrinsic::riscv_cv_alu_addN;
1560 case RISCV::BI__builtin_riscv_cv_alu_addRN:
1561 ID = Intrinsic::riscv_cv_alu_addRN;
1563 case RISCV::BI__builtin_riscv_cv_alu_adduN:
1564 ID = Intrinsic::riscv_cv_alu_adduN;
1566 case RISCV::BI__builtin_riscv_cv_alu_adduRN:
1567 ID = Intrinsic::riscv_cv_alu_adduRN;
1569 case RISCV::BI__builtin_riscv_cv_alu_clip:
1570 ID = Intrinsic::riscv_cv_alu_clip;
1572 case RISCV::BI__builtin_riscv_cv_alu_clipu:
1573 ID = Intrinsic::riscv_cv_alu_clipu;
1575 case RISCV::BI__builtin_riscv_cv_alu_extbs:
1578 case RISCV::BI__builtin_riscv_cv_alu_extbz:
1581 case RISCV::BI__builtin_riscv_cv_alu_exths:
1584 case RISCV::BI__builtin_riscv_cv_alu_exthz:
1587 case RISCV::BI__builtin_riscv_cv_alu_sle:
1590 case RISCV::BI__builtin_riscv_cv_alu_sleu:
1593 case RISCV::BI__builtin_riscv_cv_alu_subN:
1594 ID = Intrinsic::riscv_cv_alu_subN;
1596 case RISCV::BI__builtin_riscv_cv_alu_subRN:
1597 ID = Intrinsic::riscv_cv_alu_subRN;
1599 case RISCV::BI__builtin_riscv_cv_alu_subuN:
1600 ID = Intrinsic::riscv_cv_alu_subuN;
1602 case RISCV::BI__builtin_riscv_cv_alu_subuRN:
1603 ID = Intrinsic::riscv_cv_alu_subuRN;
1607 case RISCV::BI__builtin_riscv_nds_ffb_32:
1608 case RISCV::BI__builtin_riscv_nds_ffb_64:
1609 IntrinsicTypes = {ResultType};
1610 ID = Intrinsic::riscv_nds_ffb;
1612 case RISCV::BI__builtin_riscv_nds_ffzmism_32:
1613 case RISCV::BI__builtin_riscv_nds_ffzmism_64:
1614 IntrinsicTypes = {ResultType};
1615 ID = Intrinsic::riscv_nds_ffzmism;
1617 case RISCV::BI__builtin_riscv_nds_ffmism_32:
1618 case RISCV::BI__builtin_riscv_nds_ffmism_64:
1619 IntrinsicTypes = {ResultType};
1620 ID = Intrinsic::riscv_nds_ffmism;
1622 case RISCV::BI__builtin_riscv_nds_flmism_32:
1623 case RISCV::BI__builtin_riscv_nds_flmism_64:
1624 IntrinsicTypes = {ResultType};
1625 ID = Intrinsic::riscv_nds_flmism;
1629 case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
1631 case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
1635#include "clang/Basic/riscv_vector_builtin_cg.inc"
1638#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
1641#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
1644 assert(ID != Intrinsic::not_intrinsic);
1646 llvm::Function *F =
CGM.getIntrinsic(ID, IntrinsicTypes);
1647 return Builder.CreateCall(F, Ops,
"");