clang 20.0.0git
PPC.cpp
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1//===--- PPC.cpp - Implement PPC target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPC.h"
17#include "llvm/TargetParser/PPCTargetParser.h"
18
19using namespace clang;
20using namespace clang::targets;
21
22static constexpr Builtin::Info BuiltinInfo[] = {
23#define BUILTIN(ID, TYPE, ATTRS) \
24 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
25#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
26 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
27#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::HEADER, ALL_LANGUAGES},
29#include "clang/Basic/BuiltinsPPC.def"
30};
31
32/// handleTargetFeatures - Perform initialization based on the user
33/// configured set of features.
34bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
35 DiagnosticsEngine &Diags) {
36 FloatABI = HardFloat;
37 for (const auto &Feature : Features) {
38 if (Feature == "+altivec") {
39 HasAltivec = true;
40 } else if (Feature == "+vsx") {
41 HasVSX = true;
42 } else if (Feature == "+crbits") {
43 UseCRBits = true;
44 } else if (Feature == "+bpermd") {
45 HasBPERMD = true;
46 } else if (Feature == "+extdiv") {
47 HasExtDiv = true;
48 } else if (Feature == "+power8-vector") {
49 HasP8Vector = true;
50 } else if (Feature == "+crypto") {
51 HasP8Crypto = true;
52 } else if (Feature == "+direct-move") {
53 HasDirectMove = true;
54 } else if (Feature == "+htm") {
55 HasHTM = true;
56 } else if (Feature == "+float128") {
57 HasFloat128 = !getTriple().isOSAIX();
58 } else if (Feature == "+power9-vector") {
59 HasP9Vector = true;
60 } else if (Feature == "+power10-vector") {
61 HasP10Vector = true;
62 } else if (Feature == "+pcrelative-memops") {
63 HasPCRelativeMemops = true;
64 } else if (Feature == "+prefix-instrs") {
65 HasPrefixInstrs = true;
66 } else if (Feature == "+spe" || Feature == "+efpu2") {
67 HasStrictFP = false;
68 HasSPE = true;
70 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
71 } else if (Feature == "-hard-float") {
72 FloatABI = SoftFloat;
73 } else if (Feature == "+paired-vector-memops") {
74 PairedVectorMemops = true;
75 } else if (Feature == "+mma") {
76 HasMMA = true;
77 } else if (Feature == "+rop-protect") {
78 HasROPProtect = true;
79 } else if (Feature == "+privileged") {
80 HasPrivileged = true;
81 } else if (Feature == "+aix-small-local-exec-tls") {
82 HasAIXSmallLocalExecTLS = true;
83 } else if (Feature == "+aix-small-local-dynamic-tls") {
84 HasAIXSmallLocalDynamicTLS = true;
85 } else if (Feature == "+isa-v206-instructions") {
86 IsISA2_06 = true;
87 } else if (Feature == "+isa-v207-instructions") {
88 IsISA2_07 = true;
89 } else if (Feature == "+isa-v30-instructions") {
90 IsISA3_0 = true;
91 } else if (Feature == "+isa-v31-instructions") {
92 IsISA3_1 = true;
93 } else if (Feature == "+quadword-atomics") {
94 HasQuadwordAtomics = true;
95 } else if (Feature == "+aix-shared-lib-tls-model-opt") {
96 HasAIXShLibTLSModelOpt = true;
97 } else if (Feature == "+longcall") {
98 UseLongCalls = true;
99 }
100 // TODO: Finish this list and add an assert that we've handled them
101 // all.
102 }
103
104 return true;
105}
106
107static void defineXLCompatMacros(MacroBuilder &Builder) {
108 Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
109 Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
110 Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
111 Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
112 Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
113 Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
114 Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
115 Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
116 Builder.defineMacro("__isync", "__builtin_ppc_isync");
117 Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
118 Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
119 Builder.defineMacro("__sync", "__builtin_ppc_sync");
120 Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
121 Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
122 Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
123 Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
124 Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
125 Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
126 Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
127 Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
128 Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
129 Builder.defineMacro("__compare_and_swaplp",
130 "__builtin_ppc_compare_and_swaplp");
131 Builder.defineMacro("__fetch_and_add", "__builtin_ppc_fetch_and_add");
132 Builder.defineMacro("__fetch_and_addlp", "__builtin_ppc_fetch_and_addlp");
133 Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and");
134 Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp");
135 Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or");
136 Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
137 Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
138 Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
139 Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
140 Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
141 Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
142 Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
143 Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw");
144 Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
145 Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
146 Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
147 Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
148 Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
149 Builder.defineMacro("__tw", "__builtin_ppc_tw");
150 Builder.defineMacro("__trap", "__builtin_ppc_trap");
151 Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
152 Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
153 Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
154 Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
155 Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
156 Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
157 Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
158 Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
159 Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
160 Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
161 Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
162 Builder.defineMacro("__setb", "__builtin_ppc_setb");
163 Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
164 Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
165 Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
166 Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
167 Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
168 Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
169 Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
170 Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
171 Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
172 Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
173 Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
174 Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
175 Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
176 Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
177 Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
178 Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
179 Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
180 Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp");
181 Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig");
182 Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0");
183 Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1");
184 Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf");
185 Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi");
186 Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp");
187 Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub");
188 Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs");
189 Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd");
190 Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds");
191 Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub");
192 Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
193 Builder.defineMacro("__fre", "__builtin_ppc_fre");
194 Builder.defineMacro("__fres", "__builtin_ppc_fres");
195 Builder.defineMacro("__swdiv_nochk", "__builtin_ppc_swdiv_nochk");
196 Builder.defineMacro("__swdivs_nochk", "__builtin_ppc_swdivs_nochk");
197 Builder.defineMacro("__alloca", "__builtin_alloca");
198 Builder.defineMacro("__vcipher", "__builtin_altivec_crypto_vcipher");
199 Builder.defineMacro("__vcipherlast", "__builtin_altivec_crypto_vcipherlast");
200 Builder.defineMacro("__vncipher", "__builtin_altivec_crypto_vncipher");
201 Builder.defineMacro("__vncipherlast",
202 "__builtin_altivec_crypto_vncipherlast");
203 Builder.defineMacro("__vpermxor", "__builtin_altivec_crypto_vpermxor");
204 Builder.defineMacro("__vpmsumb", "__builtin_altivec_crypto_vpmsumb");
205 Builder.defineMacro("__vpmsumd", "__builtin_altivec_crypto_vpmsumd");
206 Builder.defineMacro("__vpmsumh", "__builtin_altivec_crypto_vpmsumh");
207 Builder.defineMacro("__vpmsumw", "__builtin_altivec_crypto_vpmsumw");
208 Builder.defineMacro("__divde", "__builtin_divde");
209 Builder.defineMacro("__divwe", "__builtin_divwe");
210 Builder.defineMacro("__divdeu", "__builtin_divdeu");
211 Builder.defineMacro("__divweu", "__builtin_divweu");
212 Builder.defineMacro("__alignx", "__builtin_ppc_alignx");
213 Builder.defineMacro("__bcopy", "bcopy");
214 Builder.defineMacro("__bpermd", "__builtin_bpermd");
215 Builder.defineMacro("__cntlz4", "__builtin_clz");
216 Builder.defineMacro("__cntlz8", "__builtin_clzll");
217 Builder.defineMacro("__cmplx", "__builtin_complex");
218 Builder.defineMacro("__cmplxf", "__builtin_complex");
219 Builder.defineMacro("__cnttz4", "__builtin_ctz");
220 Builder.defineMacro("__cnttz8", "__builtin_ctzll");
221 Builder.defineMacro("__darn", "__builtin_darn");
222 Builder.defineMacro("__darn_32", "__builtin_darn_32");
223 Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
224 Builder.defineMacro("__dcbf", "__builtin_dcbf");
225 Builder.defineMacro("__fence", "__builtin_ppc_fence");
226 Builder.defineMacro("__fmadd", "__builtin_fma");
227 Builder.defineMacro("__fmadds", "__builtin_fmaf");
228 Builder.defineMacro("__abs", "__builtin_abs");
229 Builder.defineMacro("__labs", "__builtin_labs");
230 Builder.defineMacro("__llabs", "__builtin_llabs");
231 Builder.defineMacro("__popcnt4", "__builtin_popcount");
232 Builder.defineMacro("__popcnt8", "__builtin_popcountll");
233 Builder.defineMacro("__readflm", "__builtin_readflm");
234 Builder.defineMacro("__rotatel4", "__builtin_rotateleft32");
235 Builder.defineMacro("__rotatel8", "__builtin_rotateleft64");
236 Builder.defineMacro("__rdlam", "__builtin_ppc_rdlam");
237 Builder.defineMacro("__setflm", "__builtin_setflm");
238 Builder.defineMacro("__setrnd", "__builtin_setrnd");
239 Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
240 Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
241 Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
242 Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
243 Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr");
244 Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
245 Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr");
246 Builder.defineMacro("__fric", "__builtin_ppc_fric");
247 Builder.defineMacro("__frim", "__builtin_ppc_frim");
248 Builder.defineMacro("__frims", "__builtin_ppc_frims");
249 Builder.defineMacro("__frin", "__builtin_ppc_frin");
250 Builder.defineMacro("__frins", "__builtin_ppc_frins");
251 Builder.defineMacro("__frip", "__builtin_ppc_frip");
252 Builder.defineMacro("__frips", "__builtin_ppc_frips");
253 Builder.defineMacro("__friz", "__builtin_ppc_friz");
254 Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
255 Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
256 Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
257 Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
258 Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
259 Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
260 Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
261 Builder.defineMacro("__addex", "__builtin_ppc_addex");
262 Builder.defineMacro("__cmplxl", "__builtin_complex");
263 Builder.defineMacro("__compare_exp_uo", "__builtin_ppc_compare_exp_uo");
264 Builder.defineMacro("__compare_exp_lt", "__builtin_ppc_compare_exp_lt");
265 Builder.defineMacro("__compare_exp_gt", "__builtin_ppc_compare_exp_gt");
266 Builder.defineMacro("__compare_exp_eq", "__builtin_ppc_compare_exp_eq");
267 Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
268 Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
269 Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
270 Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs");
271 Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss");
272 Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe");
273 Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl");
274 Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs");
275 Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe");
276 Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl");
277 Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs");
278 Builder.defineMacro("__builtin_mffs", "__builtin_ppc_mffs");
279 Builder.defineMacro("__builtin_mffsl", "__builtin_ppc_mffsl");
280 Builder.defineMacro("__builtin_mtfsf", "__builtin_ppc_mtfsf");
281 Builder.defineMacro("__builtin_set_fpscr_rn", "__builtin_ppc_set_fpscr_rn");
282}
283
284/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
285/// #defines that are not tied to a specific subtarget.
287 MacroBuilder &Builder) const {
288
289 // We define the XLC compatibility macros only on AIX and Linux since XLC
290 // was never available on any other platforms.
291 if (getTriple().isOSAIX() || getTriple().isOSLinux())
292 defineXLCompatMacros(Builder);
293
294 // Target identification.
295 Builder.defineMacro("__ppc__");
296 Builder.defineMacro("__PPC__");
297 Builder.defineMacro("_ARCH_PPC");
298 Builder.defineMacro("__powerpc__");
299 Builder.defineMacro("__POWERPC__");
300 if (PointerWidth == 64) {
301 Builder.defineMacro("_ARCH_PPC64");
302 Builder.defineMacro("__powerpc64__");
303 Builder.defineMacro("__PPC64__");
304 } else if (getTriple().isOSAIX()) {
305 // The XL compilers on AIX define _ARCH_PPC64 for both 32 and 64-bit modes.
306 Builder.defineMacro("_ARCH_PPC64");
307 }
308 if (getTriple().isOSAIX()) {
309 Builder.defineMacro("__THW_PPC__");
310 // Define __PPC and __powerpc for AIX XL C/C++ compatibility
311 Builder.defineMacro("__PPC");
312 Builder.defineMacro("__powerpc");
313 }
314
315 // Target properties.
316 if (getTriple().getArch() == llvm::Triple::ppc64le ||
317 getTriple().getArch() == llvm::Triple::ppcle) {
318 Builder.defineMacro("_LITTLE_ENDIAN");
319 } else {
320 if (!getTriple().isOSNetBSD() &&
321 !getTriple().isOSOpenBSD())
322 Builder.defineMacro("_BIG_ENDIAN");
323 }
324
325 // ABI options.
326 if (ABI == "elfv1")
327 Builder.defineMacro("_CALL_ELF", "1");
328 if (ABI == "elfv2")
329 Builder.defineMacro("_CALL_ELF", "2");
330
331 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
332 // our support post-dates this and it should work on all 64-bit ppc linux
333 // platforms. It is guaranteed to work on all elfv2 platforms.
334 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
335 Builder.defineMacro("_CALL_LINUX", "1");
336
337 // Subtarget options.
338 if (!getTriple().isOSAIX()){
339 Builder.defineMacro("__NATURAL_ALIGNMENT__");
340 }
341 Builder.defineMacro("__REGISTER_PREFIX__", "");
342
343 // FIXME: Should be controlled by command line option.
344 if (LongDoubleWidth == 128) {
345 Builder.defineMacro("__LONG_DOUBLE_128__");
346 Builder.defineMacro("__LONGDOUBLE128");
347 if (Opts.PPCIEEELongDouble)
348 Builder.defineMacro("__LONG_DOUBLE_IEEE128__");
349 else
350 Builder.defineMacro("__LONG_DOUBLE_IBM128__");
351 }
352
353 if (getTriple().isOSAIX() && Opts.LongDoubleSize == 64) {
354 assert(LongDoubleWidth == 64);
355 Builder.defineMacro("__LONGDOUBLE64");
356 }
357
358 // Define this for elfv2 (64-bit only).
359 if (ABI == "elfv2")
360 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
361
362 if (ArchDefs & ArchDefineName)
363 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
364 if (ArchDefs & ArchDefinePpcgr)
365 Builder.defineMacro("_ARCH_PPCGR");
366 if (ArchDefs & ArchDefinePpcsq)
367 Builder.defineMacro("_ARCH_PPCSQ");
368 if (ArchDefs & ArchDefine440)
369 Builder.defineMacro("_ARCH_440");
370 if (ArchDefs & ArchDefine603)
371 Builder.defineMacro("_ARCH_603");
372 if (ArchDefs & ArchDefine604)
373 Builder.defineMacro("_ARCH_604");
374 if (ArchDefs & ArchDefinePwr4)
375 Builder.defineMacro("_ARCH_PWR4");
376 if (ArchDefs & ArchDefinePwr5)
377 Builder.defineMacro("_ARCH_PWR5");
378 if (ArchDefs & ArchDefinePwr5x)
379 Builder.defineMacro("_ARCH_PWR5X");
380 if (ArchDefs & ArchDefinePwr6)
381 Builder.defineMacro("_ARCH_PWR6");
382 if (ArchDefs & ArchDefinePwr6x)
383 Builder.defineMacro("_ARCH_PWR6X");
384 if (ArchDefs & ArchDefinePwr7)
385 Builder.defineMacro("_ARCH_PWR7");
386 if (ArchDefs & ArchDefinePwr8)
387 Builder.defineMacro("_ARCH_PWR8");
388 if (ArchDefs & ArchDefinePwr9)
389 Builder.defineMacro("_ARCH_PWR9");
390 if (ArchDefs & ArchDefinePwr10)
391 Builder.defineMacro("_ARCH_PWR10");
392 if (ArchDefs & ArchDefinePwr11)
393 Builder.defineMacro("_ARCH_PWR11");
394 if (ArchDefs & ArchDefineA2)
395 Builder.defineMacro("_ARCH_A2");
396 if (ArchDefs & ArchDefineE500)
397 Builder.defineMacro("__NO_LWSYNC__");
398 if (ArchDefs & ArchDefineFuture)
399 Builder.defineMacro("_ARCH_PWR_FUTURE");
400
401 if (HasAltivec) {
402 Builder.defineMacro("__VEC__", "10206");
403 Builder.defineMacro("__ALTIVEC__");
404 }
405 if (HasSPE) {
406 Builder.defineMacro("__SPE__");
407 Builder.defineMacro("__NO_FPRS__");
408 }
409 if (HasVSX)
410 Builder.defineMacro("__VSX__");
411 if (HasP8Vector)
412 Builder.defineMacro("__POWER8_VECTOR__");
413 if (HasP8Crypto)
414 Builder.defineMacro("__CRYPTO__");
415 if (HasHTM)
416 Builder.defineMacro("__HTM__");
417 if (HasFloat128)
418 Builder.defineMacro("__FLOAT128__");
419 if (HasP9Vector)
420 Builder.defineMacro("__POWER9_VECTOR__");
421 if (HasMMA)
422 Builder.defineMacro("__MMA__");
423 if (HasROPProtect)
424 Builder.defineMacro("__ROP_PROTECT__");
425 if (HasP10Vector)
426 Builder.defineMacro("__POWER10_VECTOR__");
427 if (HasPCRelativeMemops)
428 Builder.defineMacro("__PCREL__");
429
430 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
431 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
432 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
433 if (PointerWidth == 64)
434 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
435
436 // We have support for the bswap intrinsics so we can define this.
437 Builder.defineMacro("__HAVE_BSWAP__", "1");
438
439 // FIXME: The following are not yet generated here by Clang, but are
440 // generated by GCC:
441 //
442 // _SOFT_FLOAT_
443 // __RECIP_PRECISION__
444 // __APPLE_ALTIVEC__
445 // __RECIP__
446 // __RECIPF__
447 // __RSQRTE__
448 // __RSQRTEF__
449 // _SOFT_DOUBLE_
450 // __NO_LWSYNC__
451 // __CMODEL_MEDIUM__
452 // __CMODEL_LARGE__
453 // _CALL_SYSV
454 // _CALL_DARWIN
455}
456
457// Handle explicit options being passed to the compiler here:
458// - if we've explicitly turned off vsx and turned on any of:
459// - power8-vector
460// - direct-move
461// - float128
462// - power9-vector
463// - paired-vector-memops
464// - mma
465// - power10-vector
466// - if we've explicitly turned on vsx and turned off altivec.
467// - if we've explicitly turned off hard-float and turned on altivec.
468// then go ahead and error since the customer has expressed an incompatible
469// set of options.
471 const std::vector<std::string> &FeaturesVec) {
472 auto FindVSXSubfeature = [&](StringRef Feature, StringRef SubOption,
473 StringRef Option) {
474 if (llvm::is_contained(FeaturesVec, Feature)) {
475 Diags.Report(diag::err_opt_not_valid_with_opt) << SubOption << Option;
476 return true;
477 }
478 return false;
479 };
480
481 // Cannot allow soft-float with VSX, Altivec, or any
482 // VSX subfeatures.
483 bool Found = false;
484 if (llvm::is_contained(FeaturesVec, "-hard-float")) {
485 Found |= FindVSXSubfeature("+vsx", "-mvsx", "-msoft-float");
486 Found |= FindVSXSubfeature("+altivec", "-maltivec", "-msoft-float");
487 Found |=
488 FindVSXSubfeature("+power8-vector", "-mpower8-vector", "-msoft-float");
489 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move", "-msoft-float");
490 Found |= FindVSXSubfeature("+float128", "-mfloat128", "-msoft-float");
491 Found |=
492 FindVSXSubfeature("+power9-vector", "-mpower9-vector", "-msoft-float");
493 Found |= FindVSXSubfeature("+paired-vector-memops",
494 "-mpaired-vector-memops", "-msoft-float");
495 Found |= FindVSXSubfeature("+mma", "-mmma", "-msoft-float");
496 Found |= FindVSXSubfeature("+crypto", "-mcrypto", "-msoft-float");
497 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector",
498 "-msoft-float");
499 }
500 if (Found)
501 return false;
502
503 // Cannot allow VSX with no Altivec.
504 if (llvm::is_contained(FeaturesVec, "+vsx") &&
505 llvm::is_contained(FeaturesVec, "-altivec")) {
506 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mvsx"
507 << "-mno-altivec";
508 return false;
509 }
510
511 // vsx was not explicitly turned off.
512 if (!llvm::is_contained(FeaturesVec, "-vsx"))
513 return true;
514
515 Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector", "-mno-vsx");
516 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move", "-mno-vsx");
517 Found |= FindVSXSubfeature("+float128", "-mfloat128", "-mno-vsx");
518 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector", "-mno-vsx");
519 Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops",
520 "-mno-vsx");
521 Found |= FindVSXSubfeature("+mma", "-mmma", "-mno-vsx");
522 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector", "-mno-vsx");
523
524 // Return false if any vsx subfeatures was found.
525 return !Found;
526}
527
529 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
530 const std::vector<std::string> &FeaturesVec) const {
531 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
532 .Case("7400", true)
533 .Case("g4", true)
534 .Case("7450", true)
535 .Case("g4+", true)
536 .Case("970", true)
537 .Case("g5", true)
538 .Case("pwr6", true)
539 .Case("pwr7", true)
540 .Case("pwr8", true)
541 .Case("pwr9", true)
542 .Case("ppc64", true)
543 .Case("ppc64le", true)
544 .Default(false);
545
546 Features["power9-vector"] = (CPU == "pwr9");
547 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
548 .Case("ppc64le", true)
549 .Case("pwr9", true)
550 .Case("pwr8", true)
551 .Default(false);
552 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
553 .Case("ppc64le", true)
554 .Case("pwr9", true)
555 .Case("pwr8", true)
556 .Default(false);
557 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
558 .Case("ppc64le", true)
559 .Case("pwr9", true)
560 .Case("pwr8", true)
561 .Case("pwr7", true)
562 .Default(false);
563 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
564 .Case("ppc64le", true)
565 .Case("pwr9", true)
566 .Case("pwr8", true)
567 .Case("pwr7", true)
568 .Default(false);
569 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
570 .Case("ppc64le", true)
571 .Case("pwr9", true)
572 .Case("pwr8", true)
573 .Default(false);
574 Features["crbits"] = llvm::StringSwitch<bool>(CPU)
575 .Case("ppc64le", true)
576 .Case("pwr9", true)
577 .Case("pwr8", true)
578 .Default(false);
579 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
580 .Case("ppc64le", true)
581 .Case("pwr9", true)
582 .Case("pwr8", true)
583 .Case("pwr7", true)
584 .Default(false);
585 Features["htm"] = llvm::StringSwitch<bool>(CPU)
586 .Case("ppc64le", true)
587 .Case("pwr9", true)
588 .Case("pwr8", true)
589 .Default(false);
590
591 // ROP Protect is off by default.
592 Features["rop-protect"] = false;
593 // Privileged instructions are off by default.
594 Features["privileged"] = false;
595
596 // The code generated by the -maix-small-local-[exec|dynamic]-tls option is
597 // turned off by default.
598 Features["aix-small-local-exec-tls"] = false;
599 Features["aix-small-local-dynamic-tls"] = false;
600
601 // Turn off TLS model opt by default.
602 Features["aix-shared-lib-tls-model-opt"] = false;
603
604 Features["spe"] = llvm::StringSwitch<bool>(CPU)
605 .Case("8548", true)
606 .Case("e500", true)
607 .Default(false);
608
609 Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
610 .Case("ppc64le", true)
611 .Case("pwr9", true)
612 .Case("pwr8", true)
613 .Case("pwr7", true)
614 .Case("a2", true)
615 .Default(false);
616
617 Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
618 .Case("ppc64le", true)
619 .Case("pwr9", true)
620 .Case("pwr8", true)
621 .Default(false);
622
623 Features["isa-v30-instructions"] =
624 llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);
625
626 Features["quadword-atomics"] =
627 getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU)
628 .Case("pwr9", true)
629 .Case("pwr8", true)
630 .Default(false);
631
632 // Power10 includes all the same features as Power9 plus any features specific
633 // to the Power10 core.
634 if (CPU == "pwr10" || CPU == "power10") {
635 initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
636 addP10SpecificFeatures(Features);
637 }
638
639 // Power11 includes all the same features as Power10 plus any features
640 // specific to the Power11 core.
641 if (CPU == "pwr11" || CPU == "power11") {
642 initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
643 addP11SpecificFeatures(Features);
644 }
645
646 // Future CPU should include all of the features of Power 11 as well as any
647 // additional features (yet to be determined) specific to it.
648 if (CPU == "future") {
649 initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
651 }
652
653 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
654 return false;
655
656 if (!(ArchDefs & ArchDefinePwr7) && (ArchDefs & ArchDefinePpcgr) &&
657 llvm::is_contained(FeaturesVec, "+float128")) {
658 // We have __float128 on PPC but not pre-VSX targets.
659 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
660 return false;
661 }
662
663 if (!(ArchDefs & ArchDefinePwr10)) {
664 if (llvm::is_contained(FeaturesVec, "+mma")) {
665 // MMA operations are not available pre-Power10.
666 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
667 return false;
668 }
669 if (llvm::is_contained(FeaturesVec, "+pcrel")) {
670 // PC-Relative instructions are not available pre-Power10,
671 // and these instructions also require prefixed instructions support.
672 Diags.Report(diag::err_opt_not_valid_without_opt)
673 << "-mpcrel"
674 << "-mcpu=pwr10 -mprefixed";
675 return false;
676 }
677 if (llvm::is_contained(FeaturesVec, "+prefixed")) {
678 // Prefixed instructions are not available pre-Power10.
679 Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed"
680 << "-mcpu=pwr10";
681 return false;
682 }
683 if (llvm::is_contained(FeaturesVec, "+paired-vector-memops")) {
684 // Paired vector memops are not available pre-Power10.
685 Diags.Report(diag::err_opt_not_valid_without_opt)
686 << "-mpaired-vector-memops"
687 << "-mcpu=pwr10";
688 return false;
689 }
690 }
691
692 if (!(ArchDefs & ArchDefinePwr8) &&
693 llvm::is_contained(FeaturesVec, "+rop-protect")) {
694 // We can turn on ROP Protect on Power 8 and above.
695 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mrop-protect" << CPU;
696 return false;
697 }
698
699 if (!(ArchDefs & ArchDefinePwr8) &&
700 llvm::is_contained(FeaturesVec, "+privileged")) {
701 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mprivileged" << CPU;
702 return false;
703 }
704 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
705}
706
707// Add any Power10 specific features.
709 llvm::StringMap<bool> &Features) const {
710 Features["htm"] = false; // HTM was removed for P10.
711 Features["paired-vector-memops"] = true;
712 Features["mma"] = true;
713 Features["power10-vector"] = true;
714 Features["pcrelative-memops"] = true;
715 Features["prefix-instrs"] = true;
716 Features["isa-v31-instructions"] = true;
717}
718
719// Add any Power11 specific features.
721 llvm::StringMap<bool> &Features) const {}
722
723// Add features specific to the "Future" CPU.
725 llvm::StringMap<bool> &Features) const {}
726
727bool PPCTargetInfo::hasFeature(StringRef Feature) const {
728 return llvm::StringSwitch<bool>(Feature)
729 .Case("powerpc", true)
730 .Case("altivec", HasAltivec)
731 .Case("vsx", HasVSX)
732 .Case("crbits", UseCRBits)
733 .Case("power8-vector", HasP8Vector)
734 .Case("crypto", HasP8Crypto)
735 .Case("direct-move", HasDirectMove)
736 .Case("htm", HasHTM)
737 .Case("bpermd", HasBPERMD)
738 .Case("extdiv", HasExtDiv)
739 .Case("float128", HasFloat128)
740 .Case("power9-vector", HasP9Vector)
741 .Case("paired-vector-memops", PairedVectorMemops)
742 .Case("power10-vector", HasP10Vector)
743 .Case("pcrelative-memops", HasPCRelativeMemops)
744 .Case("prefix-instrs", HasPrefixInstrs)
745 .Case("spe", HasSPE)
746 .Case("mma", HasMMA)
747 .Case("rop-protect", HasROPProtect)
748 .Case("privileged", HasPrivileged)
749 .Case("aix-small-local-exec-tls", HasAIXSmallLocalExecTLS)
750 .Case("aix-small-local-dynamic-tls", HasAIXSmallLocalDynamicTLS)
751 .Case("isa-v206-instructions", IsISA2_06)
752 .Case("isa-v207-instructions", IsISA2_07)
753 .Case("isa-v30-instructions", IsISA3_0)
754 .Case("isa-v31-instructions", IsISA3_1)
755 .Case("quadword-atomics", HasQuadwordAtomics)
756 .Case("aix-shared-lib-tls-model-opt", HasAIXShLibTLSModelOpt)
757 .Case("longcall", UseLongCalls)
758 .Default(false);
759}
760
761void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
762 StringRef Name, bool Enabled) const {
763 if (Enabled) {
764 if (Name == "efpu2")
765 Features["spe"] = true;
766 // If we're enabling any of the vsx based features then enable vsx and
767 // altivec. We'll diagnose any problems later.
768 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
769 .Case("vsx", true)
770 .Case("direct-move", true)
771 .Case("power8-vector", true)
772 .Case("power9-vector", true)
773 .Case("paired-vector-memops", true)
774 .Case("power10-vector", true)
775 .Case("float128", true)
776 .Case("mma", true)
777 .Default(false);
778 if (FeatureHasVSX)
779 Features["vsx"] = Features["altivec"] = true;
780 if (Name == "power9-vector")
781 Features["power8-vector"] = true;
782 else if (Name == "power10-vector")
783 Features["power8-vector"] = Features["power9-vector"] = true;
784 if (Name == "pcrel")
785 Features["pcrelative-memops"] = true;
786 else if (Name == "prefixed")
787 Features["prefix-instrs"] = true;
788 else
789 Features[Name] = true;
790 } else {
791 if (Name == "spe")
792 Features["efpu2"] = false;
793 // If we're disabling altivec, hard-float, or vsx go ahead and disable all
794 // of the vsx features.
795 if ((Name == "altivec") || (Name == "vsx") || (Name == "hard-float")) {
796 if (Name != "vsx")
797 Features["altivec"] = Features["crypto"] = false;
798 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
799 Features["float128"] = Features["power9-vector"] =
800 Features["paired-vector-memops"] = Features["mma"] =
801 Features["power10-vector"] = false;
802 }
803 if (Name == "power8-vector")
804 Features["power9-vector"] = Features["paired-vector-memops"] =
805 Features["mma"] = Features["power10-vector"] = false;
806 else if (Name == "power9-vector")
807 Features["paired-vector-memops"] = Features["mma"] =
808 Features["power10-vector"] = false;
809 if (Name == "pcrel")
810 Features["pcrelative-memops"] = false;
811 else if (Name == "prefixed")
812 Features["prefix-instrs"] = false;
813 else
814 Features[Name] = false;
815 }
816}
817
818// Make sure that registers are added in the correct array index which should be
819// the DWARF number for PPC registers.
820const char *const PPCTargetInfo::GCCRegNames[] = {
821 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
822 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
823 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
824 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3",
825 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12",
826 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
827 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
828 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3",
829 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3",
830 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12",
831 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
832 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30",
833 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp"
834};
835
837 return llvm::ArrayRef(GCCRegNames);
838}
839
840const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
841 // While some of these aliases do map to different registers
842 // they still share the same register name.
843 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
844 {{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"},
845 {{"6"}, "r6"}, {{"7"}, "r7"}, {{"8"}, "r8"},
846 {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"},
847 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"},
848 {{"15"}, "r15"}, {{"16"}, "r16"}, {{"17"}, "r17"},
849 {{"18"}, "r18"}, {{"19"}, "r19"}, {{"20"}, "r20"},
850 {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"},
851 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"},
852 {{"27"}, "r27"}, {{"28"}, "r28"}, {{"29"}, "r29"},
853 {{"30"}, "r30"}, {{"31"}, "r31"}, {{"fr0"}, "f0"},
854 {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"},
855 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"},
856 {{"fr7"}, "f7"}, {{"fr8"}, "f8"}, {{"fr9"}, "f9"},
857 {{"fr10"}, "f10"}, {{"fr11"}, "f11"}, {{"fr12"}, "f12"},
858 {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"},
859 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"},
860 {{"fr19"}, "f19"}, {{"fr20"}, "f20"}, {{"fr21"}, "f21"},
861 {{"fr22"}, "f22"}, {{"fr23"}, "f23"}, {{"fr24"}, "f24"},
862 {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
863 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"},
864 {{"fr31"}, "f31"}, {{"cc"}, "cr0"},
865};
866
868 return llvm::ArrayRef(GCCRegAliases);
869}
870
871// PPC ELFABIv2 DWARF Definition "Table 2.26. Mappings of Common Registers".
872// vs0 ~ vs31 is mapping to 32 - 63,
873// vs32 ~ vs63 is mapping to 77 - 108.
874// And this mapping applies to all OSes which run on powerpc.
876 // Table of additional register names to use in user input.
877 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
878 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39},
879 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43},
880 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47},
881 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51},
882 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55},
883 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59},
884 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63},
885 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80},
886 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84},
887 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88},
888 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92},
889 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96},
890 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100},
891 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
892 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
893};
894
897}
898
899bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
900 return llvm::PPC::isValidCPU(Name);
901}
902
904 llvm::PPC::fillValidCPUList(Values);
905}
906
908 if (HasAltivec)
909 Opts.AltiVec = 1;
910 TargetInfo::adjust(Diags, Opts);
911 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
912 LongDoubleFormat = Opts.PPCIEEELongDouble
913 ? &llvm::APFloat::IEEEquad()
914 : &llvm::APFloat::PPCDoubleDouble();
915 Opts.IEEE128 = 1;
916 if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI &&
917 HasQuadwordAtomics)
919}
920
924}
925
926bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
927 llvm::Triple Triple = getTriple();
928 if (Triple.isOSAIX()) {
929#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP, \
930 VALUE) \
931 .Case(NAME, true)
932 return llvm::StringSwitch<bool>(FeatureStr)
933#include "llvm/TargetParser/PPCTargetParser.def"
934 .Default(false);
935 }
936
937 assert(Triple.isOSLinux() &&
938 "__builtin_cpu_supports() is only supported for AIX and Linux.");
939
940#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
941 return llvm::StringSwitch<bool>(FeatureStr)
942#include "llvm/TargetParser/PPCTargetParser.def"
943 .Default(false);
944}
945
946bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
947 llvm::Triple Triple = getTriple();
948 assert((Triple.isOSAIX() || Triple.isOSLinux()) &&
949 "__builtin_cpu_is() is only supported for AIX and Linux.");
950
951#define PPC_CPU(NAME, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, \
952 AIXID) \
953 .Case(NAME, {Linux_SUPPORT_METHOD, AIX_SUPPORT_METHOD})
954
955 std::pair<unsigned, unsigned> SuppportMethod =
956 llvm::StringSwitch<std::pair<unsigned, unsigned>>(CPUName)
957#include "llvm/TargetParser/PPCTargetParser.def"
958 .Default({BUILTIN_PPC_UNSUPPORTED, BUILTIN_PPC_UNSUPPORTED});
959 return Triple.isOSLinux()
960 ? (SuppportMethod.first != BUILTIN_PPC_UNSUPPORTED)
961 : (SuppportMethod.second != BUILTIN_PPC_UNSUPPORTED);
962}
Defines the Diagnostic-related interfaces.
const TargetInfo::AddlRegName GCCAddlRegNames[]
Definition: PPC.cpp:875
static constexpr Builtin::Info BuiltinInfo[]
Definition: PPC.cpp:22
static void defineXLCompatMacros(MacroBuilder &Builder)
Definition: PPC.cpp:107
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, const std::vector< std::string > &FeaturesVec)
Definition: PPC.cpp:470
static constexpr Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:32
Defines the clang::MacroBuilder utility class.
Enumerates target-specific builtins in their own namespaces within namespace clang.
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1547
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:461
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1256
virtual void adjust(DiagnosticsEngine &Diags, LangOptions &Opts)
Set forced language options.
Definition: TargetInfo.cpp:392
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:532
unsigned char MaxAtomicInlineWidth
Definition: TargetInfo.h:242
void addFutureSpecificFeatures(llvm::StringMap< bool > &Features) const
Definition: PPC.cpp:724
ArrayRef< const char * > getGCCRegNames() const override
Definition: PPC.cpp:836
void addP11SpecificFeatures(llvm::StringMap< bool > &Features) const
Definition: PPC.cpp:720
bool validateCpuIs(StringRef Name) const override
Definition: PPC.cpp:946
bool isValidCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name.
Definition: PPC.cpp:899
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition: PPC.cpp:34
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: PPC.cpp:727
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: PPC.cpp:867
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: PPC.cpp:921
void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override
Set forced language options.
Definition: PPC.cpp:907
void addP10SpecificFeatures(llvm::StringMap< bool > &Features) const
Definition: PPC.cpp:708
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const override
Enable or disable a specific target feature; the feature name must be valid.
Definition: PPC.cpp:761
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific #defines that are not tied to ...
Definition: PPC.cpp:286
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: PPC.cpp:895
bool validateCpuSupports(StringRef Feature) const override
Definition: PPC.cpp:926
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: PPC.cpp:528
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: PPC.cpp:903
The JSON file list parser is used to communicate input to InstallAPI.
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:139