clang  9.0.0svn
PPC.h
Go to the documentation of this file.
1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28 
29  /// Flags for architecture specific defines.
30  typedef enum {
31  ArchDefineNone = 0,
32  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33  ArchDefinePpcgr = 1 << 1,
34  ArchDefinePpcsq = 1 << 2,
35  ArchDefine440 = 1 << 3,
36  ArchDefine603 = 1 << 4,
37  ArchDefine604 = 1 << 5,
38  ArchDefinePwr4 = 1 << 6,
39  ArchDefinePwr5 = 1 << 7,
40  ArchDefinePwr5x = 1 << 8,
41  ArchDefinePwr6 = 1 << 9,
42  ArchDefinePwr6x = 1 << 10,
43  ArchDefinePwr7 = 1 << 11,
44  ArchDefinePwr8 = 1 << 12,
45  ArchDefinePwr9 = 1 << 13,
46  ArchDefineA2 = 1 << 14,
47  ArchDefineA2q = 1 << 15
48  } ArchDefineTypes;
49 
50 
51  ArchDefineTypes ArchDefs = ArchDefineNone;
52  static const Builtin::Info BuiltinInfo[];
53  static const char *const GCCRegNames[];
54  static const TargetInfo::GCCRegAlias GCCRegAliases[];
55  std::string CPU;
56  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
57 
58  // Target cpu features.
59  bool HasAltivec = false;
60  bool HasVSX = false;
61  bool HasP8Vector = false;
62  bool HasP8Crypto = false;
63  bool HasDirectMove = false;
64  bool HasQPX = false;
65  bool HasHTM = false;
66  bool HasBPERMD = false;
67  bool HasExtDiv = false;
68  bool HasP9Vector = false;
69 
70 protected:
71  std::string ABI;
72 
73 public:
74  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
75  : TargetInfo(Triple) {
76  SuitableAlign = 128;
77  SimdDefaultAlign = 128;
78  LongDoubleWidth = LongDoubleAlign = 128;
79  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
80  }
81 
82  // Set the language option for altivec based on our value.
83  void adjust(LangOptions &Opts) override;
84 
85  // Note: GCC recognizes the following additional cpus:
86  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
87  // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
88  // titan, rs64.
89  bool isValidCPUName(StringRef Name) const override;
90  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
91 
92  bool setCPU(const std::string &Name) override {
93  bool CPUKnown = isValidCPUName(Name);
94  if (CPUKnown) {
95  CPU = Name;
96 
97  // CPU identification.
98  ArchDefs =
99  (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
100  .Case("440", ArchDefineName)
101  .Case("450", ArchDefineName | ArchDefine440)
102  .Case("601", ArchDefineName)
103  .Case("602", ArchDefineName | ArchDefinePpcgr)
104  .Case("603", ArchDefineName | ArchDefinePpcgr)
105  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
106  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
107  .Case("604", ArchDefineName | ArchDefinePpcgr)
108  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
109  .Case("620", ArchDefineName | ArchDefinePpcgr)
110  .Case("630", ArchDefineName | ArchDefinePpcgr)
111  .Case("7400", ArchDefineName | ArchDefinePpcgr)
112  .Case("7450", ArchDefineName | ArchDefinePpcgr)
113  .Case("750", ArchDefineName | ArchDefinePpcgr)
114  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
115  ArchDefinePpcsq)
116  .Case("a2", ArchDefineA2)
117  .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
118  .Cases("power3", "pwr3", ArchDefinePpcgr)
119  .Cases("power4", "pwr4",
120  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
121  .Cases("power5", "pwr5",
122  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
123  ArchDefinePpcsq)
124  .Cases("power5x", "pwr5x",
125  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
126  ArchDefinePpcgr | ArchDefinePpcsq)
127  .Cases("power6", "pwr6",
128  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
129  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
130  .Cases("power6x", "pwr6x",
131  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
132  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
133  ArchDefinePpcsq)
134  .Cases("power7", "pwr7",
135  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
136  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
137  ArchDefinePpcsq)
138  // powerpc64le automatically defaults to at least power8.
139  .Cases("power8", "pwr8", "ppc64le",
140  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
141  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
142  ArchDefinePpcgr | ArchDefinePpcsq)
143  .Cases("power9", "pwr9",
144  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
145  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
146  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
147  .Default(ArchDefineNone);
148  }
149  return CPUKnown;
150  }
151 
152  StringRef getABI() const override { return ABI; }
153 
154  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
155 
156  bool isCLZForZeroUndef() const override { return false; }
157 
158  void getTargetDefines(const LangOptions &Opts,
159  MacroBuilder &Builder) const override;
160 
161  bool
162  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
163  StringRef CPU,
164  const std::vector<std::string> &FeaturesVec) const override;
165 
166  bool handleTargetFeatures(std::vector<std::string> &Features,
167  DiagnosticsEngine &Diags) override;
168 
169  bool hasFeature(StringRef Feature) const override;
170 
171  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
172  bool Enabled) const override;
173 
174  ArrayRef<const char *> getGCCRegNames() const override;
175 
176  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
177 
178  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
179 
180  bool validateAsmConstraint(const char *&Name,
181  TargetInfo::ConstraintInfo &Info) const override {
182  switch (*Name) {
183  default:
184  return false;
185  case 'O': // Zero
186  break;
187  case 'f': // Floating point register
188  // Don't use floating point registers on soft float ABI.
189  if (FloatABI == SoftFloat)
190  return false;
191  LLVM_FALLTHROUGH;
192  case 'b': // Base register
193  Info.setAllowsRegister();
194  break;
195  // FIXME: The following are added to allow parsing.
196  // I just took a guess at what the actions should be.
197  // Also, is more specific checking needed? I.e. specific registers?
198  case 'd': // Floating point register (containing 64-bit value)
199  case 'v': // Altivec vector register
200  // Don't use floating point and altivec vector registers
201  // on soft float ABI
202  if (FloatABI == SoftFloat)
203  return false;
204  Info.setAllowsRegister();
205  break;
206  case 'w':
207  switch (Name[1]) {
208  case 'd': // VSX vector register to hold vector double data
209  case 'f': // VSX vector register to hold vector float data
210  case 's': // VSX vector register to hold scalar float data
211  case 'a': // Any VSX register
212  case 'c': // An individual CR bit
213  case 'i': // FP or VSX register to hold 64-bit integers data
214  break;
215  default:
216  return false;
217  }
218  Info.setAllowsRegister();
219  Name++; // Skip over 'w'.
220  break;
221  case 'h': // `MQ', `CTR', or `LINK' register
222  case 'q': // `MQ' register
223  case 'c': // `CTR' register
224  case 'l': // `LINK' register
225  case 'x': // `CR' register (condition register) number 0
226  case 'y': // `CR' register (condition register)
227  case 'z': // `XER[CA]' carry bit (part of the XER register)
228  Info.setAllowsRegister();
229  break;
230  case 'I': // Signed 16-bit constant
231  case 'J': // Unsigned 16-bit constant shifted left 16 bits
232  // (use `L' instead for SImode constants)
233  case 'K': // Unsigned 16-bit constant
234  case 'L': // Signed 16-bit constant shifted left 16 bits
235  case 'M': // Constant larger than 31
236  case 'N': // Exact power of 2
237  case 'P': // Constant whose negation is a signed 16-bit constant
238  case 'G': // Floating point constant that can be loaded into a
239  // register with one instruction per word
240  case 'H': // Integer/Floating point constant that can be loaded
241  // into a register using three instructions
242  break;
243  case 'm': // Memory operand. Note that on PowerPC targets, m can
244  // include addresses that update the base register. It
245  // is therefore only safe to use `m' in an asm statement
246  // if that asm statement accesses the operand exactly once.
247  // The asm statement must also use `%U<opno>' as a
248  // placeholder for the "update" flag in the corresponding
249  // load or store instruction. For example:
250  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
251  // is correct but:
252  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
253  // is not. Use es rather than m if you don't want the base
254  // register to be updated.
255  case 'e':
256  if (Name[1] != 's')
257  return false;
258  // es: A "stable" memory operand; that is, one which does not
259  // include any automodification of the base register. Unlike
260  // `m', this constraint can be used in asm statements that
261  // might access the operand several times, or that might not
262  // access it at all.
263  Info.setAllowsMemory();
264  Name++; // Skip over 'e'.
265  break;
266  case 'Q': // Memory operand that is an offset from a register (it is
267  // usually better to use `m' or `es' in asm statements)
268  case 'Z': // Memory operand that is an indexed or indirect from a
269  // register (it is usually better to use `m' or `es' in
270  // asm statements)
271  Info.setAllowsMemory();
272  Info.setAllowsRegister();
273  break;
274  case 'R': // AIX TOC entry
275  case 'a': // Address operand that is an indexed or indirect from a
276  // register (`p' is preferable for asm statements)
277  case 'S': // Constant suitable as a 64-bit mask operand
278  case 'T': // Constant suitable as a 32-bit mask operand
279  case 'U': // System V Release 4 small data area reference
280  case 't': // AND masks that can be performed by two rldic{l, r}
281  // instructions
282  case 'W': // Vector constant that does not require memory
283  case 'j': // Vector constant that is all zeros.
284  break;
285  // End FIXME.
286  }
287  return true;
288  }
289 
290  std::string convertConstraint(const char *&Constraint) const override {
291  std::string R;
292  switch (*Constraint) {
293  case 'e':
294  case 'w':
295  // Two-character constraint; add "^" hint for later parsing.
296  R = std::string("^") + std::string(Constraint, 2);
297  Constraint++;
298  break;
299  default:
300  return TargetInfo::convertConstraint(Constraint);
301  }
302  return R;
303  }
304 
305  const char *getClobbers() const override { return ""; }
306  int getEHDataRegisterNumber(unsigned RegNo) const override {
307  if (RegNo == 0)
308  return 3;
309  if (RegNo == 1)
310  return 4;
311  return -1;
312  }
313 
314  bool hasSjLjLowering() const override { return true; }
315 
316  bool useFloat128ManglingForLongDouble() const override {
317  return LongDoubleWidth == 128 &&
318  LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
319  getTriple().isOSBinFormatELF();
320  }
321 };
322 
323 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
324 public:
325  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
326  : PPCTargetInfo(Triple, Opts) {
327  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
328 
329  switch (getTriple().getOS()) {
330  case llvm::Triple::Linux:
331  case llvm::Triple::FreeBSD:
332  case llvm::Triple::NetBSD:
333  SizeType = UnsignedInt;
334  PtrDiffType = SignedInt;
335  IntPtrType = SignedInt;
336  break;
337  case llvm::Triple::AIX:
338  SizeType = UnsignedLong;
339  PtrDiffType = SignedLong;
340  IntPtrType = SignedLong;
341  SuitableAlign = 64;
342  break;
343  default:
344  break;
345  }
346 
347  switch (getTriple().getOS()) {
348  case llvm::Triple::FreeBSD:
349  case llvm::Triple::NetBSD:
350  case llvm::Triple::OpenBSD:
351  // FIXME: -mlong-double-128 is not yet supported on AIX.
352  case llvm::Triple::AIX:
353  LongDoubleWidth = LongDoubleAlign = 64;
354  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
355  break;
356  default:
357  break;
358  }
359 
360  // PPC32 supports atomics up to 4 bytes.
361  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
362  }
363 
365  // This is the ELF definition, and is overridden by the Darwin sub-target
367  }
368 };
369 
370 // Note: ABI differences may eventually require us to have a separate
371 // TargetInfo for little endian.
372 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
373 public:
374  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
375  : PPCTargetInfo(Triple, Opts) {
376  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
377  IntMaxType = SignedLong;
378  Int64Type = SignedLong;
379 
380  if ((Triple.getArch() == llvm::Triple::ppc64le)) {
381  resetDataLayout("e-m:e-i64:64-n32:64");
382  ABI = "elfv2";
383  } else {
384  resetDataLayout("E-m:e-i64:64-n32:64");
385  ABI = "elfv1";
386  }
387 
388  switch (getTriple().getOS()) {
389  case llvm::Triple::FreeBSD:
390  LongDoubleWidth = LongDoubleAlign = 64;
391  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
392  break;
393  case llvm::Triple::AIX:
394  // FIXME: -mlong-double-128 is not yet supported on AIX.
395  LongDoubleWidth = LongDoubleAlign = 64;
396  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
397  SuitableAlign = 64;
398  break;
399  default:
400  break;
401  }
402 
403  // PPC64 supports atomics up to 8 bytes.
404  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
405  }
406 
409  }
410 
411  // PPC64 Linux-specific ABI options.
412  bool setABI(const std::string &Name) override {
413  if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
414  ABI = Name;
415  return true;
416  }
417  return false;
418  }
419 
421  switch (CC) {
422  case CC_Swift:
423  return CCCR_OK;
424  default:
425  return CCCR_Warning;
426  }
427  }
428 };
429 
430 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
431  : public DarwinTargetInfo<PPC32TargetInfo> {
432 public:
433  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
434  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
435  HasAlignMac68kSupport = true;
436  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
437  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
438  LongLongAlign = 32;
439  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
440  }
441 
444  }
445 };
446 
447 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
448  : public DarwinTargetInfo<PPC64TargetInfo> {
449 public:
450  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
451  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
452  HasAlignMac68kSupport = true;
453  resetDataLayout("E-m:o-i64:64-n32:64");
454  }
455 };
456 
457 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
458  public AIXTargetInfo<PPC32TargetInfo> {
459 public:
463  }
464 };
465 
466 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
467  public AIXTargetInfo<PPC64TargetInfo> {
468 public:
470 };
471 
472 } // namespace targets
473 } // namespace clang
474 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:325
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:420
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:450
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:20
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:364
Options for controlling the target.
Definition: TargetOptions.h:26
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:374
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:49
bool useFloat128ManglingForLongDouble() const override
Return true if the &#39;long double&#39; type should be mangled like __float128.
Definition: PPC.h:316
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:148
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:152
static const char *const GCCRegNames[]
Definition: X86.cpp:43
AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: OSTargets.h:648
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:433
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:407
Exposes information about the current target.
Definition: TargetInfo.h:161
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:412
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:92
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:235
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument...
Definition: PPC.h:306
Defines the clang::TargetOptions class.
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:241
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:156
Dataflow Directional Tag Classes.
typedef char* __builtin_va_list;
Definition: TargetInfo.h:225
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:461
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:223
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm...
Definition: PPC.h:314
Defines the clang::TargetInfo interface.
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:442
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:74
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:290
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:180
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:305
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:949