clang  13.0.0git
PPC.h
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1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28 
29  /// Flags for architecture specific defines.
30  typedef enum {
31  ArchDefineNone = 0,
32  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33  ArchDefinePpcgr = 1 << 1,
34  ArchDefinePpcsq = 1 << 2,
35  ArchDefine440 = 1 << 3,
36  ArchDefine603 = 1 << 4,
37  ArchDefine604 = 1 << 5,
38  ArchDefinePwr4 = 1 << 6,
39  ArchDefinePwr5 = 1 << 7,
40  ArchDefinePwr5x = 1 << 8,
41  ArchDefinePwr6 = 1 << 9,
42  ArchDefinePwr6x = 1 << 10,
43  ArchDefinePwr7 = 1 << 11,
44  ArchDefinePwr8 = 1 << 12,
45  ArchDefinePwr9 = 1 << 13,
46  ArchDefinePwr10 = 1 << 14,
47  ArchDefineFuture = 1 << 15,
48  ArchDefineA2 = 1 << 16,
49  ArchDefineE500 = 1 << 18
50  } ArchDefineTypes;
51 
52  ArchDefineTypes ArchDefs = ArchDefineNone;
53  static const Builtin::Info BuiltinInfo[];
54  static const char *const GCCRegNames[];
55  static const TargetInfo::GCCRegAlias GCCRegAliases[];
56  std::string CPU;
57  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58 
59  // Target cpu features.
60  bool HasAltivec = false;
61  bool HasMMA = false;
62  bool HasROPProtection = false;
63  bool HasVSX = false;
64  bool HasP8Vector = false;
65  bool HasP8Crypto = false;
66  bool HasDirectMove = false;
67  bool HasHTM = false;
68  bool HasBPERMD = false;
69  bool HasExtDiv = false;
70  bool HasP9Vector = false;
71  bool HasSPE = false;
72  bool PairedVectorMemops = false;
73  bool HasP10Vector = false;
74  bool HasPCRelativeMemops = false;
75 
76 protected:
77  std::string ABI;
78 
79 public:
80  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
81  : TargetInfo(Triple) {
82  SuitableAlign = 128;
83  SimdDefaultAlign = 128;
84  LongDoubleWidth = LongDoubleAlign = 128;
85  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
86  HasStrictFP = true;
87  }
88 
89  // Set the language option for altivec based on our value.
90  void adjust(LangOptions &Opts) override;
91 
92  // Note: GCC recognizes the following additional cpus:
93  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
94  // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
95  bool isValidCPUName(StringRef Name) const override;
96  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
97 
98  bool setCPU(const std::string &Name) override {
99  bool CPUKnown = isValidCPUName(Name);
100  if (CPUKnown) {
101  CPU = Name;
102 
103  // CPU identification.
104  ArchDefs =
105  (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
106  .Case("440", ArchDefineName)
107  .Case("450", ArchDefineName | ArchDefine440)
108  .Case("601", ArchDefineName)
109  .Case("602", ArchDefineName | ArchDefinePpcgr)
110  .Case("603", ArchDefineName | ArchDefinePpcgr)
111  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
112  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
113  .Case("604", ArchDefineName | ArchDefinePpcgr)
114  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
115  .Case("620", ArchDefineName | ArchDefinePpcgr)
116  .Case("630", ArchDefineName | ArchDefinePpcgr)
117  .Case("7400", ArchDefineName | ArchDefinePpcgr)
118  .Case("7450", ArchDefineName | ArchDefinePpcgr)
119  .Case("750", ArchDefineName | ArchDefinePpcgr)
120  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
121  ArchDefinePpcsq)
122  .Case("a2", ArchDefineA2)
123  .Cases("power3", "pwr3", ArchDefinePpcgr)
124  .Cases("power4", "pwr4",
125  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
126  .Cases("power5", "pwr5",
127  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
128  ArchDefinePpcsq)
129  .Cases("power5x", "pwr5x",
130  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
131  ArchDefinePpcgr | ArchDefinePpcsq)
132  .Cases("power6", "pwr6",
133  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
134  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
135  .Cases("power6x", "pwr6x",
136  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
137  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
138  ArchDefinePpcsq)
139  .Cases("power7", "pwr7",
140  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
141  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
142  ArchDefinePpcsq)
143  // powerpc64le automatically defaults to at least power8.
144  .Cases("power8", "pwr8", "ppc64le",
145  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
146  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
147  ArchDefinePpcgr | ArchDefinePpcsq)
148  .Cases("power9", "pwr9",
149  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
150  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
151  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
152  .Cases("power10", "pwr10",
153  ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
154  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
155  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
156  ArchDefinePpcsq)
157  .Case("future",
158  ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
159  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
160  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
161  ArchDefinePpcgr | ArchDefinePpcsq)
162  .Cases("8548", "e500", ArchDefineE500)
163  .Default(ArchDefineNone);
164  }
165  return CPUKnown;
166  }
167 
168  StringRef getABI() const override { return ABI; }
169 
170  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
171 
172  bool isCLZForZeroUndef() const override { return false; }
173 
174  void getTargetDefines(const LangOptions &Opts,
175  MacroBuilder &Builder) const override;
176 
177  bool
178  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
179  StringRef CPU,
180  const std::vector<std::string> &FeaturesVec) const override;
181 
182  void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
183  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
184 
185  bool handleTargetFeatures(std::vector<std::string> &Features,
186  DiagnosticsEngine &Diags) override;
187 
188  bool hasFeature(StringRef Feature) const override;
189 
190  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
191  bool Enabled) const override;
192 
193  ArrayRef<const char *> getGCCRegNames() const override;
194 
195  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
196 
197  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
198 
199  bool validateAsmConstraint(const char *&Name,
200  TargetInfo::ConstraintInfo &Info) const override {
201  switch (*Name) {
202  default:
203  return false;
204  case 'O': // Zero
205  break;
206  case 'f': // Floating point register
207  // Don't use floating point registers on soft float ABI.
208  if (FloatABI == SoftFloat)
209  return false;
210  LLVM_FALLTHROUGH;
211  case 'b': // Base register
212  Info.setAllowsRegister();
213  break;
214  // FIXME: The following are added to allow parsing.
215  // I just took a guess at what the actions should be.
216  // Also, is more specific checking needed? I.e. specific registers?
217  case 'd': // Floating point register (containing 64-bit value)
218  case 'v': // Altivec vector register
219  // Don't use floating point and altivec vector registers
220  // on soft float ABI
221  if (FloatABI == SoftFloat)
222  return false;
223  Info.setAllowsRegister();
224  break;
225  case 'w':
226  switch (Name[1]) {
227  case 'd': // VSX vector register to hold vector double data
228  case 'f': // VSX vector register to hold vector float data
229  case 's': // VSX vector register to hold scalar double data
230  case 'w': // VSX vector register to hold scalar double data
231  case 'a': // Any VSX register
232  case 'c': // An individual CR bit
233  case 'i': // FP or VSX register to hold 64-bit integers data
234  break;
235  default:
236  return false;
237  }
238  Info.setAllowsRegister();
239  Name++; // Skip over 'w'.
240  break;
241  case 'h': // `MQ', `CTR', or `LINK' register
242  case 'q': // `MQ' register
243  case 'c': // `CTR' register
244  case 'l': // `LINK' register
245  case 'x': // `CR' register (condition register) number 0
246  case 'y': // `CR' register (condition register)
247  case 'z': // `XER[CA]' carry bit (part of the XER register)
248  Info.setAllowsRegister();
249  break;
250  case 'I': // Signed 16-bit constant
251  case 'J': // Unsigned 16-bit constant shifted left 16 bits
252  // (use `L' instead for SImode constants)
253  case 'K': // Unsigned 16-bit constant
254  case 'L': // Signed 16-bit constant shifted left 16 bits
255  case 'M': // Constant larger than 31
256  case 'N': // Exact power of 2
257  case 'P': // Constant whose negation is a signed 16-bit constant
258  case 'G': // Floating point constant that can be loaded into a
259  // register with one instruction per word
260  case 'H': // Integer/Floating point constant that can be loaded
261  // into a register using three instructions
262  break;
263  case 'm': // Memory operand. Note that on PowerPC targets, m can
264  // include addresses that update the base register. It
265  // is therefore only safe to use `m' in an asm statement
266  // if that asm statement accesses the operand exactly once.
267  // The asm statement must also use `%U<opno>' as a
268  // placeholder for the "update" flag in the corresponding
269  // load or store instruction. For example:
270  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
271  // is correct but:
272  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
273  // is not. Use es rather than m if you don't want the base
274  // register to be updated.
275  case 'e':
276  if (Name[1] != 's')
277  return false;
278  // es: A "stable" memory operand; that is, one which does not
279  // include any automodification of the base register. Unlike
280  // `m', this constraint can be used in asm statements that
281  // might access the operand several times, or that might not
282  // access it at all.
283  Info.setAllowsMemory();
284  Name++; // Skip over 'e'.
285  break;
286  case 'Q': // Memory operand that is an offset from a register (it is
287  // usually better to use `m' or `es' in asm statements)
288  Info.setAllowsRegister();
289  LLVM_FALLTHROUGH;
290  case 'Z': // Memory operand that is an indexed or indirect from a
291  // register (it is usually better to use `m' or `es' in
292  // asm statements)
293  Info.setAllowsMemory();
294  break;
295  case 'R': // AIX TOC entry
296  case 'a': // Address operand that is an indexed or indirect from a
297  // register (`p' is preferable for asm statements)
298  case 'S': // Constant suitable as a 64-bit mask operand
299  case 'T': // Constant suitable as a 32-bit mask operand
300  case 'U': // System V Release 4 small data area reference
301  case 't': // AND masks that can be performed by two rldic{l, r}
302  // instructions
303  case 'W': // Vector constant that does not require memory
304  case 'j': // Vector constant that is all zeros.
305  break;
306  // End FIXME.
307  }
308  return true;
309  }
310 
311  std::string convertConstraint(const char *&Constraint) const override {
312  std::string R;
313  switch (*Constraint) {
314  case 'e':
315  case 'w':
316  // Two-character constraint; add "^" hint for later parsing.
317  R = std::string("^") + std::string(Constraint, 2);
318  Constraint++;
319  break;
320  default:
321  return TargetInfo::convertConstraint(Constraint);
322  }
323  return R;
324  }
325 
326  const char *getClobbers() const override { return ""; }
327  int getEHDataRegisterNumber(unsigned RegNo) const override {
328  if (RegNo == 0)
329  return 3;
330  if (RegNo == 1)
331  return 4;
332  return -1;
333  }
334 
335  bool hasSjLjLowering() const override { return true; }
336 
337  const char *getLongDoubleMangling() const override {
338  if (LongDoubleWidth == 64)
339  return "e";
340  return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
341  ? "g"
342  : "u9__ieee128";
343  }
344  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
345 
346  bool hasExtIntType() const override { return true; }
347 
348  bool isSPRegName(StringRef RegName) const override {
349  return RegName.equals("r1") || RegName.equals("x1");
350  }
351 };
352 
353 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
354 public:
355  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
356  : PPCTargetInfo(Triple, Opts) {
357  if (Triple.isOSAIX())
358  resetDataLayout("E-m:a-p:32:32-i64:64-n32");
359  else if (Triple.getArch() == llvm::Triple::ppcle)
360  resetDataLayout("e-m:e-p:32:32-i64:64-n32");
361  else
362  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
363 
364  switch (getTriple().getOS()) {
365  case llvm::Triple::Linux:
366  case llvm::Triple::FreeBSD:
367  case llvm::Triple::NetBSD:
368  SizeType = UnsignedInt;
369  PtrDiffType = SignedInt;
370  IntPtrType = SignedInt;
371  break;
372  case llvm::Triple::AIX:
373  SizeType = UnsignedLong;
374  PtrDiffType = SignedLong;
375  IntPtrType = SignedLong;
376  LongDoubleWidth = 64;
377  LongDoubleAlign = DoubleAlign = 32;
378  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
379  break;
380  default:
381  break;
382  }
383 
384  if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
385  Triple.isMusl()) {
386  LongDoubleWidth = LongDoubleAlign = 64;
387  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
388  }
389 
390  // PPC32 supports atomics up to 4 bytes.
391  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
392  }
393 
395  // This is the ELF definition, and is overridden by the Darwin sub-target
397  }
398 };
399 
400 // Note: ABI differences may eventually require us to have a separate
401 // TargetInfo for little endian.
402 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
403 public:
404  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
405  : PPCTargetInfo(Triple, Opts) {
406  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
407  IntMaxType = SignedLong;
408  Int64Type = SignedLong;
409  std::string DataLayout = "";
410 
411  if (Triple.isOSAIX()) {
412  // TODO: Set appropriate ABI for AIX platform.
413  DataLayout = "E-m:a-i64:64-n32:64";
414  LongDoubleWidth = 64;
415  LongDoubleAlign = DoubleAlign = 32;
416  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
417  } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
418  DataLayout = "e-m:e-i64:64-n32:64";
419  ABI = "elfv2";
420  } else {
421  DataLayout = "E-m:e-i64:64-n32:64";
422  ABI = "elfv1";
423  }
424 
425  if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
426  LongDoubleWidth = LongDoubleAlign = 64;
427  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
428  }
429 
430  if (Triple.isOSAIX() || Triple.isOSLinux())
431  DataLayout += "-v256:256:256-v512:512:512";
432  resetDataLayout(DataLayout);
433 
434  // PPC64 supports atomics up to 8 bytes.
435  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
436  }
437 
440  }
441 
442  // PPC64 Linux-specific ABI options.
443  bool setABI(const std::string &Name) override {
444  if (Name == "elfv1" || Name == "elfv2") {
445  ABI = Name;
446  return true;
447  }
448  return false;
449  }
450 
452  switch (CC) {
453  case CC_Swift:
454  return CCCR_OK;
455  default:
456  return CCCR_Warning;
457  }
458  }
459 };
460 
461 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
462  : public DarwinTargetInfo<PPC32TargetInfo> {
463 public:
464  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
465  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
466  HasAlignMac68kSupport = true;
467  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
468  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
469  LongLongAlign = 32;
470  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
471  }
472 
475  }
476 };
477 
478 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
479  : public DarwinTargetInfo<PPC64TargetInfo> {
480 public:
481  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
482  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
483  HasAlignMac68kSupport = true;
484  resetDataLayout("E-m:o-i64:64-n32:64");
485  }
486 };
487 
488 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
489  public AIXTargetInfo<PPC32TargetInfo> {
490 public:
494  }
495 };
496 
497 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
498  public AIXTargetInfo<PPC64TargetInfo> {
499 public:
501 };
502 
503 } // namespace targets
504 } // namespace clang
505 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:481
clang::targets::PPC64TargetInfo::checkCallingConvention
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:451
clang::targets::DarwinPPC64TargetInfo
Definition: PPC.h:478
clang::targets::AIXPPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:492
TargetInfo.h
clang::targets::PPCTargetInfo::getEHDataRegisterNumber
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: PPC.h:327
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:191
clang::TargetInfo
Exposes information about the current target.
Definition: TargetInfo.h:180
clang::targets::PPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:394
clang::targets::PPCTargetInfo::ABI
std::string ABI
Definition: PPC.h:77
clang::TargetInfo::BuiltinVaListKind
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:255
clang::TargetInfo::ConstraintInfo::setAllowsRegister
void setAllowsRegister()
Definition: TargetInfo.h:975
clang::TargetInfo::ConstraintInfo::setAllowsMemory
void setAllowsMemory()
Definition: TargetInfo.h:974
BuiltinInfo
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:20
clang::targets::AIXTargetInfo::AIXTargetInfo
AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: OSTargets.h:722
clang::targets::PPC64TargetInfo::PPC64TargetInfo
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:404
clang::driver::tools::ppc::FloatABI
FloatABI
Definition: PPC.h:25
clang::CC_Swift
@ CC_Swift
Definition: Specifiers.h:268
clang::targets::PPCTargetInfo::getLongDoubleMangling
const char * getLongDoubleMangling() const override
Return the mangled code of long double.
Definition: PPC.h:337
clang::targets::DarwinTargetInfo
Definition: OSTargets.h:79
clang::targets::PPC64TargetInfo
Definition: PPC.h:402
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition: X86.cpp:43
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:464
clang::targets::PPCTargetInfo::setCPU
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:98
clang::CallingConv
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:253
clang::targets::PPCTargetInfo::hasExtIntType
bool hasExtIntType() const override
Determine whether the _ExtInt type is supported on this target.
Definition: PPC.h:346
clang::targets::PPC64TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:438
clang::targets::PPCTargetInfo::getFloat128Mangling
const char * getFloat128Mangling() const override
Return the mangled code of __float128.
Definition: PPC.h:344
clang::targets::PPCTargetInfo::isSPRegName
bool isSPRegName(StringRef RegName) const override
Definition: PPC.h:348
clang::TargetInfo::GCCRegAlias
Definition: TargetInfo.h:1086
clang::targets::AIXPPC32TargetInfo
Definition: PPC.h:488
clang::targets::PPC64TargetInfo::setABI
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:443
TargetOptions.h
llvm::ArrayRef
Definition: LLVM.h:31
clang::TargetInfo::CharPtrBuiltinVaList
@ CharPtrBuiltinVaList
typedef char* __builtin_va_list;
Definition: TargetInfo.h:257
clang::targets::PPCTargetInfo::PPCTargetInfo
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:80
clang::targets::PPCTargetInfo::isCLZForZeroUndef
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:172
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:910
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:58
clang::targets::AIXTargetInfo
Definition: OSTargets.h:673
clang::targets::PPCTargetInfo
Definition: PPC.h:27
clang
Dataflow Directional Tag Classes.
Definition: CalledOnceCheck.h:17
clang::targets::PPC32TargetInfo
Definition: PPC.h:353
clang::Builtin::Info
Definition: Builtins.h:53
OSTargets.h
clang::targets::DarwinPPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:473
clang::targets::PPCTargetInfo::getClobbers
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:326
clang::TargetInfo::convertConstraint
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:1057
clang::targets::PPCTargetInfo::hasSjLjLowering
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm....
Definition: PPC.h:335
clang::targets::PPCTargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:199
clang::TargetOptions
Options for controlling the target.
Definition: TargetOptions.h:26
llvm::SmallVectorImpl
Definition: LLVM.h:36
AIX
clang::driver::toolchains::AIX AIX
Definition: AIX.cpp:18
clang::targets::PPC32TargetInfo::PPC32TargetInfo
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:355
clang::targets::PPCTargetInfo::getABI
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:168
clang::TargetInfo::PowerABIBuiltinVaList
@ PowerABIBuiltinVaList
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:273
clang::TargetInfo::CallingConvCheckResult
CallingConvCheckResult
Definition: TargetInfo.h:1397
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::DarwinPPC32TargetInfo
Definition: PPC.h:461
clang::targets::PPCTargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:311
hasFeature
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature.
Definition: Module.cpp:101
clang::targets::AIXPPC64TargetInfo
Definition: PPC.h:497