clang 19.0.0git
PPC.h
Go to the documentation of this file.
1//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16#include "OSTargets.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace clang {
24namespace targets {
25
26// PPC abstract base class
27class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29 /// Flags for architecture specific defines.
30 typedef enum {
31 ArchDefineNone = 0,
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefineFuture = 1 << 15,
48 ArchDefineA2 = 1 << 16,
49 ArchDefineE500 = 1 << 18
50 } ArchDefineTypes;
51
52 ArchDefineTypes ArchDefs = ArchDefineNone;
53 static const char *const GCCRegNames[];
54 static const TargetInfo::GCCRegAlias GCCRegAliases[];
55 std::string CPU;
56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
57
58 // Target cpu features.
59 bool HasAltivec = false;
60 bool HasMMA = false;
61 bool HasROPProtect = false;
62 bool HasPrivileged = false;
63 bool HasAIXSmallLocalExecTLS = false;
64 bool HasVSX = false;
65 bool UseCRBits = false;
66 bool HasP8Vector = false;
67 bool HasP8Crypto = false;
68 bool HasDirectMove = false;
69 bool HasHTM = false;
70 bool HasBPERMD = false;
71 bool HasExtDiv = false;
72 bool HasP9Vector = false;
73 bool HasSPE = false;
74 bool PairedVectorMemops = false;
75 bool HasP10Vector = false;
76 bool HasPCRelativeMemops = false;
77 bool HasPrefixInstrs = false;
78 bool IsISA2_06 = false;
79 bool IsISA2_07 = false;
80 bool IsISA3_0 = false;
81 bool IsISA3_1 = false;
82 bool HasQuadwordAtomics = false;
83
84protected:
85 std::string ABI;
86
87public:
88 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
89 : TargetInfo(Triple) {
90 SuitableAlign = 128;
91 LongDoubleWidth = LongDoubleAlign = 128;
92 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
93 HasStrictFP = true;
94 HasIbm128 = true;
95 HasUnalignedAccess = true;
96 }
97
98 // Set the language option for altivec based on our value.
99 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
100
101 // Note: GCC recognizes the following additional cpus:
102 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
103 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
104 bool isValidCPUName(StringRef Name) const override;
105 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
106
107 bool setCPU(const std::string &Name) override {
108 bool CPUKnown = isValidCPUName(Name);
109 if (CPUKnown) {
110 CPU = Name;
111
112 // CPU identification.
113 ArchDefs =
114 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
115 .Case("440", ArchDefineName)
116 .Case("450", ArchDefineName | ArchDefine440)
117 .Case("601", ArchDefineName)
118 .Case("602", ArchDefineName | ArchDefinePpcgr)
119 .Case("603", ArchDefineName | ArchDefinePpcgr)
120 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
121 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
122 .Case("604", ArchDefineName | ArchDefinePpcgr)
123 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
124 .Case("620", ArchDefineName | ArchDefinePpcgr)
125 .Case("630", ArchDefineName | ArchDefinePpcgr)
126 .Case("7400", ArchDefineName | ArchDefinePpcgr)
127 .Case("7450", ArchDefineName | ArchDefinePpcgr)
128 .Case("750", ArchDefineName | ArchDefinePpcgr)
129 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
130 ArchDefinePpcsq)
131 .Case("a2", ArchDefineA2)
132 .Cases("power3", "pwr3", ArchDefinePpcgr)
133 .Cases("power4", "pwr4",
134 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
135 .Cases("power5", "pwr5",
136 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
137 ArchDefinePpcsq)
138 .Cases("power5x", "pwr5x",
139 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
140 ArchDefinePpcgr | ArchDefinePpcsq)
141 .Cases("power6", "pwr6",
142 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
143 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
144 .Cases("power6x", "pwr6x",
145 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
146 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
147 ArchDefinePpcsq)
148 .Cases("power7", "pwr7",
149 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
150 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
151 ArchDefinePpcsq)
152 // powerpc64le automatically defaults to at least power8.
153 .Cases("power8", "pwr8", "ppc64le",
154 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
155 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
156 ArchDefinePpcgr | ArchDefinePpcsq)
157 .Cases("power9", "pwr9",
158 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
159 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
160 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
161 .Cases("power10", "pwr10",
162 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
163 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
164 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
165 ArchDefinePpcsq)
166 .Case("future",
167 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
168 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
169 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
170 ArchDefinePpcgr | ArchDefinePpcsq)
171 .Cases("8548", "e500", ArchDefineE500)
172 .Default(ArchDefineNone);
173 }
174 return CPUKnown;
175 }
176
177 StringRef getABI() const override { return ABI; }
178
179 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
180
181 bool isCLZForZeroUndef() const override { return false; }
182
183 void getTargetDefines(const LangOptions &Opts,
184 MacroBuilder &Builder) const override;
185
186 bool
187 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
188 StringRef CPU,
189 const std::vector<std::string> &FeaturesVec) const override;
190
191 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
192 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
193
194 bool handleTargetFeatures(std::vector<std::string> &Features,
195 DiagnosticsEngine &Diags) override;
196
197 bool hasFeature(StringRef Feature) const override;
198
199 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
200 bool Enabled) const override;
201
202 bool supportsTargetAttributeTune() const override { return true; }
203
204 ArrayRef<const char *> getGCCRegNames() const override;
205
206 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
207
208 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
209
210 bool validateAsmConstraint(const char *&Name,
211 TargetInfo::ConstraintInfo &Info) const override {
212 switch (*Name) {
213 default:
214 return false;
215 case 'O': // Zero
216 break;
217 case 'f': // Floating point register
218 // Don't use floating point registers on soft float ABI.
219 if (FloatABI == SoftFloat)
220 return false;
221 [[fallthrough]];
222 case 'b': // Base register
223 Info.setAllowsRegister();
224 break;
225 // FIXME: The following are added to allow parsing.
226 // I just took a guess at what the actions should be.
227 // Also, is more specific checking needed? I.e. specific registers?
228 case 'd': // Floating point register (containing 64-bit value)
229 case 'v': // Altivec vector register
230 // Don't use floating point and altivec vector registers
231 // on soft float ABI
232 if (FloatABI == SoftFloat)
233 return false;
234 Info.setAllowsRegister();
235 break;
236 case 'w':
237 switch (Name[1]) {
238 case 'd': // VSX vector register to hold vector double data
239 case 'f': // VSX vector register to hold vector float data
240 case 's': // VSX vector register to hold scalar double data
241 case 'w': // VSX vector register to hold scalar double data
242 case 'a': // Any VSX register
243 case 'c': // An individual CR bit
244 case 'i': // FP or VSX register to hold 64-bit integers data
245 break;
246 default:
247 return false;
248 }
249 Info.setAllowsRegister();
250 Name++; // Skip over 'w'.
251 break;
252 case 'h': // `MQ', `CTR', or `LINK' register
253 case 'q': // `MQ' register
254 case 'c': // `CTR' register
255 case 'l': // `LINK' register
256 case 'x': // `CR' register (condition register) number 0
257 case 'y': // `CR' register (condition register)
258 case 'z': // `XER[CA]' carry bit (part of the XER register)
259 Info.setAllowsRegister();
260 break;
261 case 'I': // Signed 16-bit constant
262 case 'J': // Unsigned 16-bit constant shifted left 16 bits
263 // (use `L' instead for SImode constants)
264 case 'K': // Unsigned 16-bit constant
265 case 'L': // Signed 16-bit constant shifted left 16 bits
266 case 'M': // Constant larger than 31
267 case 'N': // Exact power of 2
268 case 'P': // Constant whose negation is a signed 16-bit constant
269 case 'G': // Floating point constant that can be loaded into a
270 // register with one instruction per word
271 case 'H': // Integer/Floating point constant that can be loaded
272 // into a register using three instructions
273 break;
274 case 'm': // Memory operand. Note that on PowerPC targets, m can
275 // include addresses that update the base register. It
276 // is therefore only safe to use `m' in an asm statement
277 // if that asm statement accesses the operand exactly once.
278 // The asm statement must also use `%U<opno>' as a
279 // placeholder for the "update" flag in the corresponding
280 // load or store instruction. For example:
281 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
282 // is correct but:
283 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
284 // is not. Use es rather than m if you don't want the base
285 // register to be updated.
286 case 'e':
287 if (Name[1] != 's')
288 return false;
289 // es: A "stable" memory operand; that is, one which does not
290 // include any automodification of the base register. Unlike
291 // `m', this constraint can be used in asm statements that
292 // might access the operand several times, or that might not
293 // access it at all.
294 Info.setAllowsMemory();
295 Name++; // Skip over 'e'.
296 break;
297 case 'Q': // Memory operand that is an offset from a register (it is
298 // usually better to use `m' or `es' in asm statements)
299 Info.setAllowsRegister();
300 [[fallthrough]];
301 case 'Z': // Memory operand that is an indexed or indirect from a
302 // register (it is usually better to use `m' or `es' in
303 // asm statements)
304 Info.setAllowsMemory();
305 break;
306 case 'R': // AIX TOC entry
307 case 'a': // Address operand that is an indexed or indirect from a
308 // register (`p' is preferable for asm statements)
309 case 'S': // Constant suitable as a 64-bit mask operand
310 case 'T': // Constant suitable as a 32-bit mask operand
311 case 'U': // System V Release 4 small data area reference
312 case 't': // AND masks that can be performed by two rldic{l, r}
313 // instructions
314 case 'W': // Vector constant that does not require memory
315 case 'j': // Vector constant that is all zeros.
316 break;
317 // End FIXME.
318 }
319 return true;
320 }
321
322 std::string convertConstraint(const char *&Constraint) const override {
323 std::string R;
324 switch (*Constraint) {
325 case 'e':
326 case 'w':
327 // Two-character constraint; add "^" hint for later parsing.
328 R = std::string("^") + std::string(Constraint, 2);
329 Constraint++;
330 break;
331 default:
332 return TargetInfo::convertConstraint(Constraint);
333 }
334 return R;
335 }
336
337 std::string_view getClobbers() const override { return ""; }
338 int getEHDataRegisterNumber(unsigned RegNo) const override {
339 if (RegNo == 0)
340 return 3;
341 if (RegNo == 1)
342 return 4;
343 return -1;
344 }
345
346 bool hasSjLjLowering() const override { return true; }
347
348 const char *getLongDoubleMangling() const override {
349 if (LongDoubleWidth == 64)
350 return "e";
351 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
352 ? "g"
353 : "u9__ieee128";
354 }
355 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
356 const char *getIbm128Mangling() const override { return "g"; }
357
358 bool hasBitIntType() const override { return true; }
359
360 bool isSPRegName(StringRef RegName) const override {
361 return RegName.equals("r1") || RegName.equals("x1");
362 }
363
364 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
365 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
366 static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
367 static constexpr int MINIMUM_AIX_OS_MINOR = 2;
368 bool supportsCpuSupports() const override { return getTriple().isOSGlibc(); }
369 bool supportsCpuIs() const override {
370 llvm::Triple Triple = getTriple();
371 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
372 return Triple.isOSGlibc() ||
373 (Triple.isOSAIX() &&
374 !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
375 }
376 bool validateCpuSupports(StringRef Feature) const override;
377 bool validateCpuIs(StringRef Name) const override;
378};
379
380class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
381public:
382 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
383 : PPCTargetInfo(Triple, Opts) {
384 if (Triple.isOSAIX())
385 resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
386 else if (Triple.getArch() == llvm::Triple::ppcle)
387 resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
388 else
389 resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32");
390
391 switch (getTriple().getOS()) {
392 case llvm::Triple::Linux:
393 case llvm::Triple::FreeBSD:
394 case llvm::Triple::NetBSD:
395 SizeType = UnsignedInt;
396 PtrDiffType = SignedInt;
397 IntPtrType = SignedInt;
398 break;
399 case llvm::Triple::AIX:
400 SizeType = UnsignedLong;
401 PtrDiffType = SignedLong;
402 IntPtrType = SignedLong;
403 LongDoubleWidth = 64;
404 LongDoubleAlign = DoubleAlign = 32;
405 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
406 break;
407 default:
408 break;
409 }
410
411 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
412 Triple.isMusl()) {
413 LongDoubleWidth = LongDoubleAlign = 64;
414 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
415 }
416
417 // PPC32 supports atomics up to 4 bytes.
418 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
419 }
420
422 // This is the ELF definition
423 return TargetInfo::PowerABIBuiltinVaList;
424 }
425};
426
427// Note: ABI differences may eventually require us to have a separate
428// TargetInfo for little endian.
429class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
430public:
431 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
432 : PPCTargetInfo(Triple, Opts) {
433 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
434 IntMaxType = SignedLong;
435 Int64Type = SignedLong;
436 std::string DataLayout;
437
438 if (Triple.isOSAIX()) {
439 // TODO: Set appropriate ABI for AIX platform.
440 DataLayout = "E-m:a-Fi64-i64:64-n32:64";
441 LongDoubleWidth = 64;
442 LongDoubleAlign = DoubleAlign = 32;
443 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
444 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
445 DataLayout = "e-m:e-Fn32-i64:64-n32:64";
446 ABI = "elfv2";
447 } else {
448 DataLayout = "E-m:e";
449 if (Triple.isPPC64ELFv2ABI()) {
450 ABI = "elfv2";
451 DataLayout += "-Fn32";
452 } else {
453 ABI = "elfv1";
454 DataLayout += "-Fi64";
455 }
456 DataLayout += "-i64:64-n32:64";
457 }
458
459 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
460 LongDoubleWidth = LongDoubleAlign = 64;
461 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
462 }
463
464 if (Triple.isOSAIX() || Triple.isOSLinux())
465 DataLayout += "-S128-v256:256:256-v512:512:512";
466 resetDataLayout(DataLayout);
467
468 // Newer PPC64 instruction sets support atomics up to 16 bytes.
469 MaxAtomicPromoteWidth = 128;
470 // Baseline PPC64 supports inlining atomics up to 8 bytes.
471 MaxAtomicInlineWidth = 64;
472 }
473
474 void setMaxAtomicWidth() override {
475 // For power8 and up, backend is able to inline 16-byte atomic lock free
476 // code.
477 // TODO: We should allow AIX to inline quadword atomics in the future.
478 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
479 MaxAtomicInlineWidth = 128;
480 }
481
483 return TargetInfo::CharPtrBuiltinVaList;
484 }
485
486 // PPC64 Linux-specific ABI options.
487 bool setABI(const std::string &Name) override {
488 if (Name == "elfv1" || Name == "elfv2") {
489 ABI = Name;
490 return true;
491 }
492 return false;
493 }
494
496 switch (CC) {
497 case CC_Swift:
498 return CCCR_OK;
499 case CC_SwiftAsync:
500 return CCCR_Error;
501 default:
502 return CCCR_Warning;
503 }
504 }
505};
506
507class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
508 public AIXTargetInfo<PPC32TargetInfo> {
509public:
510 using AIXTargetInfo::AIXTargetInfo;
511 BuiltinVaListKind getBuiltinVaListKind() const override {
512 return TargetInfo::CharPtrBuiltinVaList;
513 }
514};
515
516class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
517 public AIXTargetInfo<PPC64TargetInfo> {
518public:
519 using AIXTargetInfo::AIXTargetInfo;
520};
521
522} // namespace targets
523} // namespace clang
524#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature.
Definition: Module.cpp:100
Defines the clang::TargetOptions class.
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:449
Exposes information about the current target.
Definition: TargetInfo.h:213
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:314
Options for controlling the target.
Definition: TargetOptions.h:26
BuiltinVaListKind getBuiltinVaListKind() const override
Definition: PPC.h:511
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:421
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:382
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:487
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: PPC.h:474
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:495
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:431
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:482
bool isSPRegName(StringRef RegName) const override
Definition: PPC.h:360
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:88
bool supportsTargetAttributeTune() const override
Determine whether this TargetInfo supports tune in target attribute.
Definition: PPC.h:202
bool supportsCpuIs() const override
Definition: PPC.h:369
const char * getLongDoubleMangling() const override
Return the mangled code of long double.
Definition: PPC.h:348
bool supportsCpuSupports() const override
Definition: PPC.h:368
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:210
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: PPC.h:338
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition: PPC.h:358
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:322
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:337
const char * getIbm128Mangling() const override
Return the mangled code of __ibm128.
Definition: PPC.h:356
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm....
Definition: PPC.h:346
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:181
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:177
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:107
const char * getFloat128Mangling() const override
Return the mangled code of __float128.
Definition: PPC.h:355
Defines the clang::TargetInfo interface.
The JSON file list parser is used to communicate input to InstallAPI.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:275
@ CC_Swift
Definition: Specifiers.h:290
@ CC_SwiftAsync
Definition: Specifiers.h:291