clang 19.0.0git
PPC.h
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1//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16#include "OSTargets.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace clang {
24namespace targets {
25
26// PPC abstract base class
27class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29 /// Flags for architecture specific defines.
30 typedef enum {
31 ArchDefineNone = 0,
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefineFuture = 1 << 15,
48 ArchDefineA2 = 1 << 16,
49 ArchDefineE500 = 1 << 18
50 } ArchDefineTypes;
51
52 ArchDefineTypes ArchDefs = ArchDefineNone;
53 static const char *const GCCRegNames[];
54 static const TargetInfo::GCCRegAlias GCCRegAliases[];
55 std::string CPU;
56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
57
58 // Target cpu features.
59 bool HasAltivec = false;
60 bool HasMMA = false;
61 bool HasROPProtect = false;
62 bool HasPrivileged = false;
63 bool HasAIXSmallLocalExecTLS = false;
64 bool HasAIXSmallLocalDynamicTLS = false;
65 bool HasVSX = false;
66 bool UseCRBits = false;
67 bool HasP8Vector = false;
68 bool HasP8Crypto = false;
69 bool HasDirectMove = false;
70 bool HasHTM = false;
71 bool HasBPERMD = false;
72 bool HasExtDiv = false;
73 bool HasP9Vector = false;
74 bool HasSPE = false;
75 bool PairedVectorMemops = false;
76 bool HasP10Vector = false;
77 bool HasPCRelativeMemops = false;
78 bool HasPrefixInstrs = false;
79 bool IsISA2_06 = false;
80 bool IsISA2_07 = false;
81 bool IsISA3_0 = false;
82 bool IsISA3_1 = false;
83 bool HasQuadwordAtomics = false;
84 bool HasAIXShLibTLSModelOpt = false;
85 bool UseLongCalls = false;
86
87protected:
88 std::string ABI;
89
90public:
91 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
92 : TargetInfo(Triple) {
93 SuitableAlign = 128;
94 LongDoubleWidth = LongDoubleAlign = 128;
95 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
96 HasStrictFP = true;
97 HasIbm128 = true;
98 HasUnalignedAccess = true;
99 }
100
101 // Set the language option for altivec based on our value.
102 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
103
104 // Note: GCC recognizes the following additional cpus:
105 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
106 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
107 bool isValidCPUName(StringRef Name) const override;
108 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
109
110 bool setCPU(const std::string &Name) override {
111 bool CPUKnown = isValidCPUName(Name);
112 if (CPUKnown) {
113 CPU = Name;
114
115 // CPU identification.
116 ArchDefs =
117 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
118 .Case("440", ArchDefineName)
119 .Case("450", ArchDefineName | ArchDefine440)
120 .Case("601", ArchDefineName)
121 .Case("602", ArchDefineName | ArchDefinePpcgr)
122 .Case("603", ArchDefineName | ArchDefinePpcgr)
123 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
124 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
125 .Case("604", ArchDefineName | ArchDefinePpcgr)
126 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
127 .Case("620", ArchDefineName | ArchDefinePpcgr)
128 .Case("630", ArchDefineName | ArchDefinePpcgr)
129 .Case("7400", ArchDefineName | ArchDefinePpcgr)
130 .Case("7450", ArchDefineName | ArchDefinePpcgr)
131 .Case("750", ArchDefineName | ArchDefinePpcgr)
132 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
133 ArchDefinePpcsq)
134 .Case("a2", ArchDefineA2)
135 .Cases("power3", "pwr3", ArchDefinePpcgr)
136 .Cases("power4", "pwr4",
137 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
138 .Cases("power5", "pwr5",
139 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
140 ArchDefinePpcsq)
141 .Cases("power5x", "pwr5x",
142 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
143 ArchDefinePpcgr | ArchDefinePpcsq)
144 .Cases("power6", "pwr6",
145 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
146 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
147 .Cases("power6x", "pwr6x",
148 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
149 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
150 ArchDefinePpcsq)
151 .Cases("power7", "pwr7",
152 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
153 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
154 ArchDefinePpcsq)
155 // powerpc64le automatically defaults to at least power8.
156 .Cases("power8", "pwr8", "ppc64le",
157 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
158 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
159 ArchDefinePpcgr | ArchDefinePpcsq)
160 .Cases("power9", "pwr9",
161 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
162 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
163 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
164 .Cases("power10", "pwr10",
165 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
166 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
167 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
168 ArchDefinePpcsq)
169 .Case("future",
170 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
171 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
172 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
173 ArchDefinePpcgr | ArchDefinePpcsq)
174 .Cases("8548", "e500", ArchDefineE500)
175 .Default(ArchDefineNone);
176 }
177 return CPUKnown;
178 }
179
180 StringRef getABI() const override { return ABI; }
181
182 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
183
184 bool isCLZForZeroUndef() const override { return false; }
185
186 void getTargetDefines(const LangOptions &Opts,
187 MacroBuilder &Builder) const override;
188
189 bool
190 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
191 StringRef CPU,
192 const std::vector<std::string> &FeaturesVec) const override;
193
194 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
195 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
196
197 bool handleTargetFeatures(std::vector<std::string> &Features,
198 DiagnosticsEngine &Diags) override;
199
200 bool hasFeature(StringRef Feature) const override;
201
202 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
203 bool Enabled) const override;
204
205 bool supportsTargetAttributeTune() const override { return true; }
206
207 ArrayRef<const char *> getGCCRegNames() const override;
208
209 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
210
211 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
212
213 bool validateAsmConstraint(const char *&Name,
214 TargetInfo::ConstraintInfo &Info) const override {
215 switch (*Name) {
216 default:
217 return false;
218 case 'O': // Zero
219 break;
220 case 'f': // Floating point register
221 // Don't use floating point registers on soft float ABI.
222 if (FloatABI == SoftFloat)
223 return false;
224 [[fallthrough]];
225 case 'b': // Base register
226 Info.setAllowsRegister();
227 break;
228 // FIXME: The following are added to allow parsing.
229 // I just took a guess at what the actions should be.
230 // Also, is more specific checking needed? I.e. specific registers?
231 case 'd': // Floating point register (containing 64-bit value)
232 case 'v': // Altivec vector register
233 // Don't use floating point and altivec vector registers
234 // on soft float ABI
235 if (FloatABI == SoftFloat)
236 return false;
237 Info.setAllowsRegister();
238 break;
239 case 'w':
240 switch (Name[1]) {
241 case 'd': // VSX vector register to hold vector double data
242 case 'f': // VSX vector register to hold vector float data
243 case 's': // VSX vector register to hold scalar double data
244 case 'w': // VSX vector register to hold scalar double data
245 case 'a': // Any VSX register
246 case 'c': // An individual CR bit
247 case 'i': // FP or VSX register to hold 64-bit integers data
248 break;
249 default:
250 return false;
251 }
252 Info.setAllowsRegister();
253 Name++; // Skip over 'w'.
254 break;
255 case 'h': // `MQ', `CTR', or `LINK' register
256 case 'q': // `MQ' register
257 case 'c': // `CTR' register
258 case 'l': // `LINK' register
259 case 'x': // `CR' register (condition register) number 0
260 case 'y': // `CR' register (condition register)
261 case 'z': // `XER[CA]' carry bit (part of the XER register)
262 Info.setAllowsRegister();
263 break;
264 case 'I': // Signed 16-bit constant
265 case 'J': // Unsigned 16-bit constant shifted left 16 bits
266 // (use `L' instead for SImode constants)
267 case 'K': // Unsigned 16-bit constant
268 case 'L': // Signed 16-bit constant shifted left 16 bits
269 case 'M': // Constant larger than 31
270 case 'N': // Exact power of 2
271 case 'P': // Constant whose negation is a signed 16-bit constant
272 case 'G': // Floating point constant that can be loaded into a
273 // register with one instruction per word
274 case 'H': // Integer/Floating point constant that can be loaded
275 // into a register using three instructions
276 break;
277 case 'm': // Memory operand. Note that on PowerPC targets, m can
278 // include addresses that update the base register. It
279 // is therefore only safe to use `m' in an asm statement
280 // if that asm statement accesses the operand exactly once.
281 // The asm statement must also use `%U<opno>' as a
282 // placeholder for the "update" flag in the corresponding
283 // load or store instruction. For example:
284 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
285 // is correct but:
286 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
287 // is not. Use es rather than m if you don't want the base
288 // register to be updated.
289 case 'e':
290 if (Name[1] != 's')
291 return false;
292 // es: A "stable" memory operand; that is, one which does not
293 // include any automodification of the base register. Unlike
294 // `m', this constraint can be used in asm statements that
295 // might access the operand several times, or that might not
296 // access it at all.
297 Info.setAllowsMemory();
298 Name++; // Skip over 'e'.
299 break;
300 case 'Q': // Memory operand that is an offset from a register (it is
301 // usually better to use `m' or `es' in asm statements)
302 Info.setAllowsRegister();
303 [[fallthrough]];
304 case 'Z': // Memory operand that is an indexed or indirect from a
305 // register (it is usually better to use `m' or `es' in
306 // asm statements)
307 Info.setAllowsMemory();
308 break;
309 case 'a': // Address operand that is an indexed or indirect from a
310 // register (`p' is preferable for asm statements)
311 // TODO: Add full support for this constraint
312 return false;
313 case 'R': // AIX TOC entry
314 case 'S': // Constant suitable as a 64-bit mask operand
315 case 'T': // Constant suitable as a 32-bit mask operand
316 case 'U': // System V Release 4 small data area reference
317 case 't': // AND masks that can be performed by two rldic{l, r}
318 // instructions
319 case 'W': // Vector constant that does not require memory
320 case 'j': // Vector constant that is all zeros.
321 break;
322 // End FIXME.
323 }
324 return true;
325 }
326
327 std::string convertConstraint(const char *&Constraint) const override {
328 std::string R;
329 switch (*Constraint) {
330 case 'e':
331 case 'w':
332 // Two-character constraint; add "^" hint for later parsing.
333 R = std::string("^") + std::string(Constraint, 2);
334 Constraint++;
335 break;
336 default:
337 return TargetInfo::convertConstraint(Constraint);
338 }
339 return R;
340 }
341
342 std::string_view getClobbers() const override { return ""; }
343 int getEHDataRegisterNumber(unsigned RegNo) const override {
344 if (RegNo == 0)
345 return 3;
346 if (RegNo == 1)
347 return 4;
348 return -1;
349 }
350
351 bool hasSjLjLowering() const override { return true; }
352
353 const char *getLongDoubleMangling() const override {
354 if (LongDoubleWidth == 64)
355 return "e";
356 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
357 ? "g"
358 : "u9__ieee128";
359 }
360 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
361 const char *getIbm128Mangling() const override { return "g"; }
362
363 bool hasBitIntType() const override { return true; }
364
365 bool isSPRegName(StringRef RegName) const override {
366 return RegName == "r1" || RegName == "x1";
367 }
368
369 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
370 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
371 static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
372 static constexpr int MINIMUM_AIX_OS_MINOR = 2;
373 bool supportsCpuSupports() const override {
374 llvm::Triple Triple = getTriple();
375 // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports().
376 return Triple.isOSGlibc() ||
377 (Triple.isOSAIX() &&
378 !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
379 }
380
381 bool supportsCpuIs() const override {
382 llvm::Triple Triple = getTriple();
383 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
384 return Triple.isOSGlibc() ||
385 (Triple.isOSAIX() &&
386 !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
387 }
388 bool validateCpuSupports(StringRef Feature) const override;
389 bool validateCpuIs(StringRef Name) const override;
390};
391
392class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
393public:
394 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
395 : PPCTargetInfo(Triple, Opts) {
396 if (Triple.isOSAIX())
397 resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
398 else if (Triple.getArch() == llvm::Triple::ppcle)
399 resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
400 else
401 resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32");
402
403 switch (getTriple().getOS()) {
404 case llvm::Triple::Linux:
405 case llvm::Triple::FreeBSD:
406 case llvm::Triple::NetBSD:
407 SizeType = UnsignedInt;
408 PtrDiffType = SignedInt;
409 IntPtrType = SignedInt;
410 break;
411 case llvm::Triple::AIX:
412 SizeType = UnsignedLong;
413 PtrDiffType = SignedLong;
414 IntPtrType = SignedLong;
415 LongDoubleWidth = 64;
416 LongDoubleAlign = DoubleAlign = 32;
417 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
418 break;
419 default:
420 break;
421 }
422
423 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
424 Triple.isMusl()) {
425 LongDoubleWidth = LongDoubleAlign = 64;
426 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
427 }
428
429 // PPC32 supports atomics up to 4 bytes.
430 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
431 }
432
434 // This is the ELF definition
435 return TargetInfo::PowerABIBuiltinVaList;
436 }
437
438 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
439 return std::make_pair(32, 32);
440 }
441};
442
443// Note: ABI differences may eventually require us to have a separate
444// TargetInfo for little endian.
445class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
446public:
447 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
448 : PPCTargetInfo(Triple, Opts) {
449 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
450 IntMaxType = SignedLong;
451 Int64Type = SignedLong;
452 std::string DataLayout;
453
454 if (Triple.isOSAIX()) {
455 // TODO: Set appropriate ABI for AIX platform.
456 DataLayout = "E-m:a-Fi64-i64:64-n32:64";
457 LongDoubleWidth = 64;
458 LongDoubleAlign = DoubleAlign = 32;
459 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
460 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
461 DataLayout = "e-m:e-Fn32-i64:64-n32:64";
462 ABI = "elfv2";
463 } else {
464 DataLayout = "E-m:e";
465 if (Triple.isPPC64ELFv2ABI()) {
466 ABI = "elfv2";
467 DataLayout += "-Fn32";
468 } else {
469 ABI = "elfv1";
470 DataLayout += "-Fi64";
471 }
472 DataLayout += "-i64:64-n32:64";
473 }
474
475 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
476 LongDoubleWidth = LongDoubleAlign = 64;
477 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
478 }
479
480 if (Triple.isOSAIX() || Triple.isOSLinux())
481 DataLayout += "-S128-v256:256:256-v512:512:512";
482 resetDataLayout(DataLayout);
483
484 // Newer PPC64 instruction sets support atomics up to 16 bytes.
485 MaxAtomicPromoteWidth = 128;
486 // Baseline PPC64 supports inlining atomics up to 8 bytes.
487 MaxAtomicInlineWidth = 64;
488 }
489
490 void setMaxAtomicWidth() override {
491 // For power8 and up, backend is able to inline 16-byte atomic lock free
492 // code.
493 // TODO: We should allow AIX to inline quadword atomics in the future.
494 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
495 MaxAtomicInlineWidth = 128;
496 }
497
499 return TargetInfo::CharPtrBuiltinVaList;
500 }
501
502 // PPC64 Linux-specific ABI options.
503 bool setABI(const std::string &Name) override {
504 if (Name == "elfv1" || Name == "elfv2") {
505 ABI = Name;
506 return true;
507 }
508 return false;
509 }
510
512 switch (CC) {
513 case CC_Swift:
514 return CCCR_OK;
515 case CC_SwiftAsync:
516 return CCCR_Error;
517 default:
518 return CCCR_Warning;
519 }
520 }
521
522 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
523 return std::make_pair(128, 128);
524 }
525};
526
527class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
528 public AIXTargetInfo<PPC32TargetInfo> {
529public:
530 using AIXTargetInfo::AIXTargetInfo;
531 BuiltinVaListKind getBuiltinVaListKind() const override {
532 return TargetInfo::CharPtrBuiltinVaList;
533 }
534};
535
536class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
537 public AIXTargetInfo<PPC64TargetInfo> {
538public:
539 using AIXTargetInfo::AIXTargetInfo;
540};
541
542} // namespace targets
543} // namespace clang
544#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature.
Definition: Module.cpp:100
Defines the clang::TargetOptions class.
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:461
Exposes information about the current target.
Definition: TargetInfo.h:218
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:319
Options for controlling the target.
Definition: TargetOptions.h:26
BuiltinVaListKind getBuiltinVaListKind() const override
Definition: PPC.h:531
std::pair< unsigned, unsigned > hardwareInterferenceSizes() const override
The first value in the pair is the minimum offset between two objects to avoid false sharing (destruc...
Definition: PPC.h:438
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:433
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:394
std::pair< unsigned, unsigned > hardwareInterferenceSizes() const override
The first value in the pair is the minimum offset between two objects to avoid false sharing (destruc...
Definition: PPC.h:522
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:503
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: PPC.h:490
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:511
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:447
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:498
bool isSPRegName(StringRef RegName) const override
Definition: PPC.h:365
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:91
bool supportsTargetAttributeTune() const override
Determine whether this TargetInfo supports tune in target attribute.
Definition: PPC.h:205
bool supportsCpuIs() const override
Definition: PPC.h:381
const char * getLongDoubleMangling() const override
Return the mangled code of long double.
Definition: PPC.h:353
bool supportsCpuSupports() const override
Definition: PPC.h:373
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:213
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: PPC.h:343
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition: PPC.h:363
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:327
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:342
const char * getIbm128Mangling() const override
Return the mangled code of __ibm128.
Definition: PPC.h:361
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm....
Definition: PPC.h:351
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:184
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:180
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:110
const char * getFloat128Mangling() const override
Return the mangled code of __float128.
Definition: PPC.h:360
Defines the clang::TargetInfo interface.
The JSON file list parser is used to communicate input to InstallAPI.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:275
@ CC_Swift
Definition: Specifiers.h:290
@ CC_SwiftAsync
Definition: Specifiers.h:291