clang  13.0.0git
PPC.h
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1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28 
29  /// Flags for architecture specific defines.
30  typedef enum {
31  ArchDefineNone = 0,
32  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33  ArchDefinePpcgr = 1 << 1,
34  ArchDefinePpcsq = 1 << 2,
35  ArchDefine440 = 1 << 3,
36  ArchDefine603 = 1 << 4,
37  ArchDefine604 = 1 << 5,
38  ArchDefinePwr4 = 1 << 6,
39  ArchDefinePwr5 = 1 << 7,
40  ArchDefinePwr5x = 1 << 8,
41  ArchDefinePwr6 = 1 << 9,
42  ArchDefinePwr6x = 1 << 10,
43  ArchDefinePwr7 = 1 << 11,
44  ArchDefinePwr8 = 1 << 12,
45  ArchDefinePwr9 = 1 << 13,
46  ArchDefinePwr10 = 1 << 14,
47  ArchDefineFuture = 1 << 15,
48  ArchDefineA2 = 1 << 16,
49  ArchDefineE500 = 1 << 18
50  } ArchDefineTypes;
51 
52  ArchDefineTypes ArchDefs = ArchDefineNone;
53  static const Builtin::Info BuiltinInfo[];
54  static const char *const GCCRegNames[];
55  static const TargetInfo::GCCRegAlias GCCRegAliases[];
56  std::string CPU;
57  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58 
59  // Target cpu features.
60  bool HasAltivec = false;
61  bool HasMMA = false;
62  bool HasROPProtect = false;
63  bool HasPrivileged = false;
64  bool HasVSX = false;
65  bool HasP8Vector = false;
66  bool HasP8Crypto = false;
67  bool HasDirectMove = false;
68  bool HasHTM = false;
69  bool HasBPERMD = false;
70  bool HasExtDiv = false;
71  bool HasP9Vector = false;
72  bool HasSPE = false;
73  bool PairedVectorMemops = false;
74  bool HasP10Vector = false;
75  bool HasPCRelativeMemops = false;
76 
77 protected:
79 
80 public:
81  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
82  : TargetInfo(Triple) {
83  SuitableAlign = 128;
84  SimdDefaultAlign = 128;
85  LongDoubleWidth = LongDoubleAlign = 128;
86  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
87  HasStrictFP = true;
88  }
89 
90  // Set the language option for altivec based on our value.
91  void adjust(LangOptions &Opts) override;
92 
93  // Note: GCC recognizes the following additional cpus:
94  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
95  // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
96  bool isValidCPUName(StringRef Name) const override;
97  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
98 
99  bool setCPU(const std::string &Name) override {
100  bool CPUKnown = isValidCPUName(Name);
101  if (CPUKnown) {
102  CPU = Name;
103 
104  // CPU identification.
105  ArchDefs =
106  (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
107  .Case("440", ArchDefineName)
108  .Case("450", ArchDefineName | ArchDefine440)
109  .Case("601", ArchDefineName)
110  .Case("602", ArchDefineName | ArchDefinePpcgr)
111  .Case("603", ArchDefineName | ArchDefinePpcgr)
112  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
113  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
114  .Case("604", ArchDefineName | ArchDefinePpcgr)
115  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
116  .Case("620", ArchDefineName | ArchDefinePpcgr)
117  .Case("630", ArchDefineName | ArchDefinePpcgr)
118  .Case("7400", ArchDefineName | ArchDefinePpcgr)
119  .Case("7450", ArchDefineName | ArchDefinePpcgr)
120  .Case("750", ArchDefineName | ArchDefinePpcgr)
121  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
122  ArchDefinePpcsq)
123  .Case("a2", ArchDefineA2)
124  .Cases("power3", "pwr3", ArchDefinePpcgr)
125  .Cases("power4", "pwr4",
126  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
127  .Cases("power5", "pwr5",
128  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
129  ArchDefinePpcsq)
130  .Cases("power5x", "pwr5x",
131  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
132  ArchDefinePpcgr | ArchDefinePpcsq)
133  .Cases("power6", "pwr6",
134  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
135  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
136  .Cases("power6x", "pwr6x",
137  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
138  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
139  ArchDefinePpcsq)
140  .Cases("power7", "pwr7",
141  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
142  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
143  ArchDefinePpcsq)
144  // powerpc64le automatically defaults to at least power8.
145  .Cases("power8", "pwr8", "ppc64le",
146  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
147  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
148  ArchDefinePpcgr | ArchDefinePpcsq)
149  .Cases("power9", "pwr9",
150  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
151  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
152  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
153  .Cases("power10", "pwr10",
154  ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
155  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
156  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
157  ArchDefinePpcsq)
158  .Case("future",
159  ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
160  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
161  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
162  ArchDefinePpcgr | ArchDefinePpcsq)
163  .Cases("8548", "e500", ArchDefineE500)
164  .Default(ArchDefineNone);
165  }
166  return CPUKnown;
167  }
168 
169  StringRef getABI() const override { return ABI; }
170 
171  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
172 
173  bool isCLZForZeroUndef() const override { return false; }
174 
175  void getTargetDefines(const LangOptions &Opts,
176  MacroBuilder &Builder) const override;
177 
178  bool
179  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
180  StringRef CPU,
181  const std::vector<std::string> &FeaturesVec) const override;
182 
183  void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
184  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
185 
186  bool handleTargetFeatures(std::vector<std::string> &Features,
187  DiagnosticsEngine &Diags) override;
188 
189  bool hasFeature(StringRef Feature) const override;
190 
191  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
192  bool Enabled) const override;
193 
194  ArrayRef<const char *> getGCCRegNames() const override;
195 
196  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
197 
198  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
199 
200  bool validateAsmConstraint(const char *&Name,
201  TargetInfo::ConstraintInfo &Info) const override {
202  switch (*Name) {
203  default:
204  return false;
205  case 'O': // Zero
206  break;
207  case 'f': // Floating point register
208  // Don't use floating point registers on soft float ABI.
209  if (FloatABI == SoftFloat)
210  return false;
211  LLVM_FALLTHROUGH;
212  case 'b': // Base register
213  Info.setAllowsRegister();
214  break;
215  // FIXME: The following are added to allow parsing.
216  // I just took a guess at what the actions should be.
217  // Also, is more specific checking needed? I.e. specific registers?
218  case 'd': // Floating point register (containing 64-bit value)
219  case 'v': // Altivec vector register
220  // Don't use floating point and altivec vector registers
221  // on soft float ABI
222  if (FloatABI == SoftFloat)
223  return false;
224  Info.setAllowsRegister();
225  break;
226  case 'w':
227  switch (Name[1]) {
228  case 'd': // VSX vector register to hold vector double data
229  case 'f': // VSX vector register to hold vector float data
230  case 's': // VSX vector register to hold scalar double data
231  case 'w': // VSX vector register to hold scalar double data
232  case 'a': // Any VSX register
233  case 'c': // An individual CR bit
234  case 'i': // FP or VSX register to hold 64-bit integers data
235  break;
236  default:
237  return false;
238  }
239  Info.setAllowsRegister();
240  Name++; // Skip over 'w'.
241  break;
242  case 'h': // `MQ', `CTR', or `LINK' register
243  case 'q': // `MQ' register
244  case 'c': // `CTR' register
245  case 'l': // `LINK' register
246  case 'x': // `CR' register (condition register) number 0
247  case 'y': // `CR' register (condition register)
248  case 'z': // `XER[CA]' carry bit (part of the XER register)
249  Info.setAllowsRegister();
250  break;
251  case 'I': // Signed 16-bit constant
252  case 'J': // Unsigned 16-bit constant shifted left 16 bits
253  // (use `L' instead for SImode constants)
254  case 'K': // Unsigned 16-bit constant
255  case 'L': // Signed 16-bit constant shifted left 16 bits
256  case 'M': // Constant larger than 31
257  case 'N': // Exact power of 2
258  case 'P': // Constant whose negation is a signed 16-bit constant
259  case 'G': // Floating point constant that can be loaded into a
260  // register with one instruction per word
261  case 'H': // Integer/Floating point constant that can be loaded
262  // into a register using three instructions
263  break;
264  case 'm': // Memory operand. Note that on PowerPC targets, m can
265  // include addresses that update the base register. It
266  // is therefore only safe to use `m' in an asm statement
267  // if that asm statement accesses the operand exactly once.
268  // The asm statement must also use `%U<opno>' as a
269  // placeholder for the "update" flag in the corresponding
270  // load or store instruction. For example:
271  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
272  // is correct but:
273  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
274  // is not. Use es rather than m if you don't want the base
275  // register to be updated.
276  case 'e':
277  if (Name[1] != 's')
278  return false;
279  // es: A "stable" memory operand; that is, one which does not
280  // include any automodification of the base register. Unlike
281  // `m', this constraint can be used in asm statements that
282  // might access the operand several times, or that might not
283  // access it at all.
284  Info.setAllowsMemory();
285  Name++; // Skip over 'e'.
286  break;
287  case 'Q': // Memory operand that is an offset from a register (it is
288  // usually better to use `m' or `es' in asm statements)
289  Info.setAllowsRegister();
290  LLVM_FALLTHROUGH;
291  case 'Z': // Memory operand that is an indexed or indirect from a
292  // register (it is usually better to use `m' or `es' in
293  // asm statements)
294  Info.setAllowsMemory();
295  break;
296  case 'R': // AIX TOC entry
297  case 'a': // Address operand that is an indexed or indirect from a
298  // register (`p' is preferable for asm statements)
299  case 'S': // Constant suitable as a 64-bit mask operand
300  case 'T': // Constant suitable as a 32-bit mask operand
301  case 'U': // System V Release 4 small data area reference
302  case 't': // AND masks that can be performed by two rldic{l, r}
303  // instructions
304  case 'W': // Vector constant that does not require memory
305  case 'j': // Vector constant that is all zeros.
306  break;
307  // End FIXME.
308  }
309  return true;
310  }
311 
312  std::string convertConstraint(const char *&Constraint) const override {
313  std::string R;
314  switch (*Constraint) {
315  case 'e':
316  case 'w':
317  // Two-character constraint; add "^" hint for later parsing.
318  R = std::string("^") + std::string(Constraint, 2);
319  Constraint++;
320  break;
321  default:
322  return TargetInfo::convertConstraint(Constraint);
323  }
324  return R;
325  }
326 
327  const char *getClobbers() const override { return ""; }
328  int getEHDataRegisterNumber(unsigned RegNo) const override {
329  if (RegNo == 0)
330  return 3;
331  if (RegNo == 1)
332  return 4;
333  return -1;
334  }
335 
336  bool hasSjLjLowering() const override { return true; }
337 
338  const char *getLongDoubleMangling() const override {
339  if (LongDoubleWidth == 64)
340  return "e";
341  return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
342  ? "g"
343  : "u9__ieee128";
344  }
345  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
346 
347  bool hasExtIntType() const override { return true; }
348 
349  bool isSPRegName(StringRef RegName) const override {
350  return RegName.equals("r1") || RegName.equals("x1");
351  }
352 };
353 
354 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
355 public:
356  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
357  : PPCTargetInfo(Triple, Opts) {
358  if (Triple.isOSAIX())
359  resetDataLayout("E-m:a-p:32:32-i64:64-n32");
360  else if (Triple.getArch() == llvm::Triple::ppcle)
361  resetDataLayout("e-m:e-p:32:32-i64:64-n32");
362  else
363  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
364 
365  switch (getTriple().getOS()) {
366  case llvm::Triple::Linux:
367  case llvm::Triple::FreeBSD:
368  case llvm::Triple::NetBSD:
369  SizeType = UnsignedInt;
370  PtrDiffType = SignedInt;
371  IntPtrType = SignedInt;
372  break;
373  case llvm::Triple::AIX:
374  SizeType = UnsignedLong;
375  PtrDiffType = SignedLong;
376  IntPtrType = SignedLong;
377  LongDoubleWidth = 64;
378  LongDoubleAlign = DoubleAlign = 32;
379  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
380  break;
381  default:
382  break;
383  }
384 
385  if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
386  Triple.isMusl()) {
387  LongDoubleWidth = LongDoubleAlign = 64;
388  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
389  }
390 
391  // PPC32 supports atomics up to 4 bytes.
392  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
393  }
394 
396  // This is the ELF definition, and is overridden by the Darwin sub-target
398  }
399 };
400 
401 // Note: ABI differences may eventually require us to have a separate
402 // TargetInfo for little endian.
403 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
404 public:
405  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
406  : PPCTargetInfo(Triple, Opts) {
407  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
408  IntMaxType = SignedLong;
409  Int64Type = SignedLong;
410  std::string DataLayout = "";
411 
412  if (Triple.isOSAIX()) {
413  // TODO: Set appropriate ABI for AIX platform.
414  DataLayout = "E-m:a-i64:64-n32:64";
415  LongDoubleWidth = 64;
416  LongDoubleAlign = DoubleAlign = 32;
417  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
418  } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
419  DataLayout = "e-m:e-i64:64-n32:64";
420  ABI = "elfv2";
421  } else {
422  DataLayout = "E-m:e-i64:64-n32:64";
423  ABI = "elfv1";
424  }
425 
426  if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
427  LongDoubleWidth = LongDoubleAlign = 64;
428  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
429  }
430 
431  if (Triple.isOSAIX() || Triple.isOSLinux())
432  DataLayout += "-S128-v256:256:256-v512:512:512";
433  resetDataLayout(DataLayout);
434 
435  // PPC64 supports atomics up to 8 bytes.
436  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
437  }
438 
441  }
442 
443  // PPC64 Linux-specific ABI options.
444  bool setABI(const std::string &Name) override {
445  if (Name == "elfv1" || Name == "elfv2") {
446  ABI = Name;
447  return true;
448  }
449  return false;
450  }
451 
453  switch (CC) {
454  case CC_Swift:
455  return CCCR_OK;
456  default:
457  return CCCR_Warning;
458  }
459  }
460 };
461 
462 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
463  : public DarwinTargetInfo<PPC32TargetInfo> {
464 public:
465  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
466  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
467  HasAlignMac68kSupport = true;
468  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
469  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
470  LongLongAlign = 32;
471  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
472  }
473 
476  }
477 };
478 
479 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
480  : public DarwinTargetInfo<PPC64TargetInfo> {
481 public:
482  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
483  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
484  HasAlignMac68kSupport = true;
485  resetDataLayout("E-m:o-i64:64-n32:64", "_");
486  }
487 };
488 
489 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
490  public AIXTargetInfo<PPC32TargetInfo> {
491 public:
495  }
496 };
497 
498 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
499  public AIXTargetInfo<PPC64TargetInfo> {
500 public:
502 };
503 
504 } // namespace targets
505 } // namespace clang
506 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:482
string
string(SUBSTRING ${CMAKE_CURRENT_BINARY_DIR} 0 ${PATH_LIB_START} PATH_HEAD) string(SUBSTRING $
Definition: CMakeLists.txt:22
clang::targets::PPC64TargetInfo::checkCallingConvention
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:452
clang::targets::DarwinPPC64TargetInfo
Definition: PPC.h:479
clang::targets::AIXPPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:493
TargetInfo.h
clang::targets::PPCTargetInfo::getEHDataRegisterNumber
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: PPC.h:328
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:191
clang::TargetInfo
Exposes information about the current target.
Definition: TargetInfo.h:187
clang::targets::PPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:395
clang::targets::PPCTargetInfo::ABI
std::string ABI
Definition: PPC.h:78
clang::TargetInfo::BuiltinVaListKind
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:265
clang::TargetInfo::ConstraintInfo::setAllowsRegister
void setAllowsRegister()
Definition: TargetInfo.h:1001
clang::TargetInfo::ConstraintInfo::setAllowsMemory
void setAllowsMemory()
Definition: TargetInfo.h:1000
BuiltinInfo
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:20
clang::targets::AIXTargetInfo::AIXTargetInfo
AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: OSTargets.h:718
clang::targets::PPC64TargetInfo::PPC64TargetInfo
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:405
clang::driver::tools::ppc::FloatABI
FloatABI
Definition: PPC.h:25
clang::CC_Swift
@ CC_Swift
Definition: Specifiers.h:268
clang::targets::PPCTargetInfo::getLongDoubleMangling
const char * getLongDoubleMangling() const override
Return the mangled code of long double.
Definition: PPC.h:338
clang::targets::DarwinTargetInfo
Definition: OSTargets.h:78
clang::targets::PPC64TargetInfo
Definition: PPC.h:403
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition: X86.cpp:43
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:465
clang::targets::PPCTargetInfo::setCPU
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:99
clang::CallingConv
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:253
clang::targets::PPCTargetInfo::hasExtIntType
bool hasExtIntType() const override
Determine whether the _ExtInt type is supported on this target.
Definition: PPC.h:347
clang::targets::PPC64TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:439
clang::targets::PPCTargetInfo::getFloat128Mangling
const char * getFloat128Mangling() const override
Return the mangled code of __float128.
Definition: PPC.h:345
clang::targets::PPCTargetInfo::isSPRegName
bool isSPRegName(StringRef RegName) const override
Definition: PPC.h:349
clang::TargetInfo::GCCRegAlias
Definition: TargetInfo.h:1112
clang::targets::AIXPPC32TargetInfo
Definition: PPC.h:489
clang::targets::PPC64TargetInfo::setABI
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:444
TargetOptions.h
llvm::ArrayRef
Definition: LLVM.h:34
clang::TargetInfo::CharPtrBuiltinVaList
@ CharPtrBuiltinVaList
typedef char* __builtin_va_list;
Definition: TargetInfo.h:267
clang::targets::PPCTargetInfo::PPCTargetInfo
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:81
clang::targets::PPCTargetInfo::isCLZForZeroUndef
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:173
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:936
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:58
clang::targets::AIXTargetInfo
Definition: OSTargets.h:669
clang::targets::PPCTargetInfo
Definition: PPC.h:27
clang
Definition: CalledOnceCheck.h:17
clang::targets::PPC32TargetInfo
Definition: PPC.h:354
clang::Builtin::Info
Definition: Builtins.h:54
OSTargets.h
clang::targets::DarwinPPC32TargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:474
clang::targets::PPCTargetInfo::getClobbers
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:327
clang::TargetInfo::convertConstraint
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:1083
clang::targets::PPCTargetInfo::hasSjLjLowering
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm....
Definition: PPC.h:336
clang::targets::PPCTargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:200
clang::TargetOptions
Options for controlling the target.
Definition: TargetOptions.h:26
llvm::SmallVectorImpl
Definition: LLVM.h:39
AIX
clang::driver::toolchains::AIX AIX
Definition: AIX.cpp:18
clang::targets::PPC32TargetInfo::PPC32TargetInfo
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:356
clang::targets::PPCTargetInfo::getABI
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:169
clang::TargetInfo::PowerABIBuiltinVaList
@ PowerABIBuiltinVaList
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:283
clang::TargetInfo::CallingConvCheckResult
CallingConvCheckResult
Definition: TargetInfo.h:1423
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::DarwinPPC32TargetInfo
Definition: PPC.h:462
clang::targets::PPCTargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:312
hasFeature
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature.
Definition: Module.cpp:101
clang::targets::AIXPPC64TargetInfo
Definition: PPC.h:498