13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
32 ArchDefineName = 1 << 0,
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefineFuture = 1 << 15,
48 ArchDefineA2 = 1 << 16,
49 ArchDefineE500 = 1 << 18
52 ArchDefineTypes ArchDefs = ArchDefineNone;
57 enum PPCFloatABI { HardFloat, SoftFloat }
FloatABI;
60 bool HasAltivec =
false;
62 bool HasROPProtect =
false;
63 bool HasPrivileged =
false;
65 bool UseCRBits =
false;
66 bool HasP8Vector =
false;
67 bool HasP8Crypto =
false;
68 bool HasDirectMove =
false;
70 bool HasBPERMD =
false;
71 bool HasExtDiv =
false;
72 bool HasP9Vector =
false;
74 bool PairedVectorMemops =
false;
75 bool HasP10Vector =
false;
76 bool HasPCRelativeMemops =
false;
77 bool HasPrefixInstrs =
false;
78 bool IsISA2_06 =
false;
79 bool IsISA2_07 =
false;
80 bool IsISA3_0 =
false;
81 bool IsISA3_1 =
false;
82 bool HasQuadwordAtomics =
false;
91 SimdDefaultAlign = 128;
92 LongDoubleWidth = LongDoubleAlign = 128;
93 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
104 bool isValidCPUName(StringRef Name)
const override;
108 bool CPUKnown = isValidCPUName(Name);
114 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
115 .Case(
"440", ArchDefineName)
116 .Case(
"450", ArchDefineName | ArchDefine440)
117 .Case(
"601", ArchDefineName)
118 .Case(
"602", ArchDefineName | ArchDefinePpcgr)
119 .Case(
"603", ArchDefineName | ArchDefinePpcgr)
120 .Case(
"603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
121 .Case(
"603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
122 .Case(
"604", ArchDefineName | ArchDefinePpcgr)
123 .Case(
"604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
124 .Case(
"620", ArchDefineName | ArchDefinePpcgr)
125 .Case(
"630", ArchDefineName | ArchDefinePpcgr)
126 .Case(
"7400", ArchDefineName | ArchDefinePpcgr)
127 .Case(
"7450", ArchDefineName | ArchDefinePpcgr)
128 .Case(
"750", ArchDefineName | ArchDefinePpcgr)
129 .Case(
"970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
131 .Case(
"a2", ArchDefineA2)
132 .Cases(
"power3",
"pwr3", ArchDefinePpcgr)
133 .Cases(
"power4",
"pwr4",
134 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
135 .Cases(
"power5",
"pwr5",
136 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
138 .Cases(
"power5x",
"pwr5x",
139 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
140 ArchDefinePpcgr | ArchDefinePpcsq)
141 .Cases(
"power6",
"pwr6",
142 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
143 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
144 .Cases(
"power6x",
"pwr6x",
145 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
146 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
148 .Cases(
"power7",
"pwr7",
149 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
150 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
153 .Cases(
"power8",
"pwr8",
"ppc64le",
154 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
155 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
156 ArchDefinePpcgr | ArchDefinePpcsq)
157 .Cases(
"power9",
"pwr9",
158 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
159 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
160 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
161 .Cases(
"power10",
"pwr10",
162 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
163 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
164 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
167 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
168 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
169 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
170 ArchDefinePpcgr | ArchDefinePpcsq)
171 .Cases(
"8548",
"e500", ArchDefineE500)
172 .Default(ArchDefineNone);
177 StringRef
getABI()
const override {
return ABI; }
189 const std::vector<std::string> &FeaturesVec)
const override;
191 void addP10SpecificFeatures(llvm::StringMap<bool> &Features)
const;
192 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features)
const;
194 bool handleTargetFeatures(std::vector<std::string> &Features,
197 bool hasFeature(StringRef Feature)
const override;
199 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
200 bool Enabled)
const override;
322 switch (*Constraint) {
347 if (LongDoubleWidth == 64)
349 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
359 return RegName.equals(
"r1") || RegName.equals(
"x1");
367 if (Triple.isOSAIX())
368 resetDataLayout(
"E-m:a-p:32:32-i64:64-n32");
369 else if (Triple.getArch() == llvm::Triple::ppcle)
370 resetDataLayout(
"e-m:e-p:32:32-i64:64-n32");
372 resetDataLayout(
"E-m:e-p:32:32-i64:64-n32");
374 switch (getTriple().getOS()) {
375 case llvm::Triple::Linux:
376 case llvm::Triple::FreeBSD:
377 case llvm::Triple::NetBSD:
378 SizeType = UnsignedInt;
379 PtrDiffType = SignedInt;
380 IntPtrType = SignedInt;
386 LongDoubleWidth = 64;
387 LongDoubleAlign = DoubleAlign = 32;
388 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
394 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
396 LongDoubleWidth = LongDoubleAlign = 64;
397 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
401 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
416 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
421 if (Triple.isOSAIX()) {
423 DataLayout =
"E-m:a-i64:64-n32:64";
424 LongDoubleWidth = 64;
425 LongDoubleAlign = DoubleAlign = 32;
426 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
427 }
else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
428 DataLayout =
"e-m:e-i64:64-n32:64";
431 DataLayout =
"E-m:e-i64:64-n32:64";
435 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
436 LongDoubleWidth = LongDoubleAlign = 64;
437 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
440 if (Triple.isOSAIX() || Triple.isOSLinux())
441 DataLayout +=
"-S128-v256:256:256-v512:512:512";
442 resetDataLayout(DataLayout);
445 MaxAtomicPromoteWidth = 128;
447 MaxAtomicInlineWidth = 64;
454 if (!getTriple().isOSAIX() &&
hasFeature(
"quadword-atomics"))
455 MaxAtomicInlineWidth = 128;
464 if (Name ==
"elfv1" || Name ==
"elfv2") {
488 HasAlignMac68kSupport =
true;
489 BoolWidth = BoolAlign = 32;
490 PtrDiffType = SignedInt;
492 resetDataLayout(
"E-m:o-p:32:32-f64:32:64-n32",
"_");
505 HasAlignMac68kSupport =
true;
506 resetDataLayout(
"E-m:o-i64:64-n32:64",
"_");
527 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H