clang 22.0.0git
RISCV.h
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1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/RISCVISAInfo.h"
20#include "llvm/TargetParser/Triple.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26// RISC-V Target
28protected:
29 std::string ABI, CPU;
30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
31
32private:
33 bool FastScalarUnalignedAccess;
34 bool HasExperimental = false;
35
36public:
37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
38 : TargetInfo(Triple) {
39 BFloat16Width = 16;
40 BFloat16Align = 16;
41 BFloat16Format = &llvm::APFloat::BFloat();
42 LongDoubleWidth = 128;
43 LongDoubleAlign = 128;
44 LongDoubleFormat = &llvm::APFloat::IEEEquad();
45 SuitableAlign = 128;
48 HasRISCVVTypes = true;
49 MCountName = "_mcount";
50 HasFloat16 = true;
51 HasStrictFP = true;
52 }
53
54 bool setCPU(const std::string &Name) override {
55 if (!isValidCPUName(Name))
56 return false;
57 CPU = Name;
58 return true;
59 }
60
61 StringRef getABI() const override { return ABI; }
62 void getTargetDefines(const LangOptions &Opts,
63 MacroBuilder &Builder) const override;
64
66
70
71 std::string_view getClobbers() const override { return ""; }
72
73 StringRef getConstraintRegister(StringRef Constraint,
74 StringRef Expression) const override {
75 return Expression;
76 }
77
79
80 int getEHDataRegisterNumber(unsigned RegNo) const override {
81 if (RegNo == 0)
82 return 10;
83 else if (RegNo == 1)
84 return 11;
85 else
86 return -1;
87 }
88
90
91 bool validateAsmConstraint(const char *&Name,
92 TargetInfo::ConstraintInfo &Info) const override;
93
94 std::string convertConstraint(const char *&Constraint) const override;
95
96 bool
97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
98 StringRef CPU,
99 const std::vector<std::string> &FeaturesVec) const override;
100
101 std::optional<std::pair<unsigned, unsigned>>
102 getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode,
103 llvm::StringMap<bool> *FeatureMap = nullptr) const override;
104
105 bool hasFeature(StringRef Feature) const override;
106
107 bool handleTargetFeatures(std::vector<std::string> &Features,
108 DiagnosticsEngine &Diags) override;
109
110 bool hasBitIntType() const override { return true; }
111
112 bool hasBFloat16Type() const override { return true; }
113
115
116 bool useFP16ConversionIntrinsics() const override {
117 return false;
118 }
119
120 bool isValidCPUName(StringRef Name) const override;
121 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
122 bool isValidTuneCPUName(StringRef Name) const override;
123 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
124 bool supportsTargetAttributeTune() const override { return true; }
125 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
126 llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
127
128 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
129 return std::make_pair(32, 32);
130 }
131
132 bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
133 bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
134 bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
135 bool validateCpuSupports(StringRef Feature) const override;
136 bool validateCpuIs(StringRef CPUName) const override;
137 bool isValidFeatureName(StringRef Name) const override;
138
139 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
140 bool &HasSizeMismatch) const override;
141
143 // Always generate Zicfilp lpad insns
144 // Non-zicfilp CPUs would read them as NOP
145 return true;
146 }
147
148 bool
150 if (ISAInfo->hasExtension("zimop"))
151 return true;
153 }
154
156 return CFBranchLabelSchemeKind::FuncSig;
157 }
158
159 bool
161 DiagnosticsEngine &Diags) const override {
162 switch (Scheme) {
164 case CFBranchLabelSchemeKind::Unlabeled:
165 case CFBranchLabelSchemeKind::FuncSig:
166 return true;
167 }
169 }
170};
171class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
172public:
173 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
174 : RISCVTargetInfo(Triple, Opts) {
178 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
179 }
180
181 bool setABI(const std::string &Name) override {
182 if (Name == "ilp32e") {
183 ABI = Name;
184 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32");
185 return true;
186 }
187
188 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
189 ABI = Name;
190 return true;
191 }
192 return false;
193 }
194
195 void setMaxAtomicWidth() override {
197
198 if (ISAInfo->hasExtension("a"))
200 }
201};
202class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
203public:
204 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
205 : RISCVTargetInfo(Triple, Opts) {
208 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
209 }
210
211 bool setABI(const std::string &Name) override {
212 if (Name == "lp64e") {
213 ABI = Name;
214 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64");
215 return true;
216 }
217
218 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
219 ABI = Name;
220 return true;
221 }
222 return false;
223 }
224
225 void setMaxAtomicWidth() override {
227
228 if (ISAInfo->hasExtension("a"))
230 }
231};
232} // namespace targets
233} // namespace clang
234
235#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
Defines the clang::TargetOptions class.
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:231
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
TargetInfo(const llvm::Triple &T)
virtual bool checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const
Check if the target supports CFProtection return.
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
virtual bool checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme, DiagnosticsEngine &Diags) const
void resetDataLayout(StringRef DL, const char *UserLabelPrefix="")
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition TargetInfo.h:330
@ VoidPtrBuiltinVaList
typedef void* __builtin_va_list;
Definition TargetInfo.h:335
const char * MCountName
Definition TargetInfo.h:254
unsigned char MaxAtomicPromoteWidth
Definition TargetInfo.h:251
unsigned HasRISCVVTypes
Definition TargetInfo.h:277
unsigned char MaxAtomicInlineWidth
Definition TargetInfo.h:251
Options for controlling the target.
RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition RISCV.h:173
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition RISCV.h:181
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition RISCV.h:195
RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition RISCV.h:204
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition RISCV.h:225
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition RISCV.h:211
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition RISCV.cpp:621
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition RISCV.h:37
std::string convertConstraint(const char *&Constraint) const override
Definition RISCV.cpp:126
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition RISCV.cpp:146
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition RISCV.cpp:74
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const override
Validate register name used for global register variables.
Definition RISCV.cpp:625
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition RISCV.cpp:338
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition RISCV.h:67
std::unique_ptr< llvm::RISCVISAInfo > ISAInfo
Definition RISCV.h:30
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition RISCV.cpp:462
bool supportsCpuInit() const override
Definition RISCV.h:134
bool isValidTuneCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name for tuning.
Definition RISCV.cpp:457
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition RISCV.cpp:593
bool supportsCpuSupports() const override
Definition RISCV.h:132
ArrayRef< const char * > getGCCRegNames() const override
Definition RISCV.cpp:25
bool hasBFloat16Type() const override
Determine whether the _BFloat16 type is supported on this target.
Definition RISCV.h:112
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition RISCV.cpp:53
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition RISCV.cpp:451
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition RISCV.cpp:572
bool checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override
Check if the target supports CFProtection return.
Definition RISCV.h:149
bool validateCpuSupports(StringRef Feature) const override
Definition RISCV.cpp:615
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts, ArmStreamingKind Mode, llvm::StringMap< bool > *FeatureMap=nullptr) const override
Returns target-specific min and max values VScale_Range.
Definition RISCV.cpp:369
StringRef getABI() const override
Get the ABI currently in use.
Definition RISCV.h:61
std::pair< unsigned, unsigned > hardwareInterferenceSizes() const override
The first value in the pair is the minimum offset between two objects to avoid false sharing (destruc...
Definition RISCV.h:128
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition RISCV.h:80
CFBranchLabelSchemeKind getDefaultCFBranchLabelScheme() const override
Get the target default CFBranchLabelScheme scheme.
Definition RISCV.h:155
bool checkCFProtectionBranchSupported(DiagnosticsEngine &) const override
Check if the target supports CFProtection branch.
Definition RISCV.h:142
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features.
Definition RISCV.cpp:410
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition RISCV.h:71
StringRef getConstraintRegister(StringRef Constraint, StringRef Expression) const override
Extracts a register from the passed constraint (if it is a single-register constraint) and the asm la...
Definition RISCV.h:73
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition RISCV.cpp:329
bool supportsTargetAttributeTune() const override
Determine whether this TargetInfo supports tune in target attribute.
Definition RISCV.h:124
ParsedTargetAttr parseTargetAttr(StringRef Str) const override
Definition RISCV.cpp:497
bool hasFeature(StringRef Feature) const override
Return true if has this feature, need to sync with handleTargetFeatures.
Definition RISCV.cpp:393
bool validateCpuIs(StringRef CPUName) const override
Definition RISCV.cpp:637
bool useFP16ConversionIntrinsics() const override
Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used to convert to and from __fp...
Definition RISCV.h:116
bool isValidCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name.
Definition RISCV.cpp:446
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition RISCV.h:110
bool supportsCpuIs() const override
Definition RISCV.h:133
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition RISCV.h:54
bool checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme, DiagnosticsEngine &Diags) const override
Definition RISCV.h:160
Defines the clang::TargetInfo interface.
The JSON file list parser is used to communicate input to InstallAPI.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition Specifiers.h:278
Contains information gathered from parsing the contents of TargetAttr.
Definition TargetInfo.h:60
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
const llvm::fltSemantics * BFloat16Format
Definition TargetInfo.h:142