clang  16.0.0git
RISCV.h
Go to the documentation of this file.
1 //===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares RISCV TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15 
16 #include "clang/Basic/TargetInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/RISCVISAInfo.h"
21 
22 namespace clang {
23 namespace targets {
24 
25 // RISC-V Target
26 class RISCVTargetInfo : public TargetInfo {
27 protected:
29  std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
30  static const Builtin::Info BuiltinInfo[];
31 
32 public:
33  RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
34  : TargetInfo(Triple) {
35  LongDoubleWidth = 128;
36  LongDoubleAlign = 128;
37  LongDoubleFormat = &llvm::APFloat::IEEEquad();
38  SuitableAlign = 128;
41  HasRISCVVTypes = true;
42  MCountName = "_mcount";
43  HasFloat16 = true;
44  }
45 
46  bool setCPU(const std::string &Name) override {
47  if (!isValidCPUName(Name))
48  return false;
49  CPU = Name;
50  return true;
51  }
52 
53  StringRef getABI() const override { return ABI; }
54  void getTargetDefines(const LangOptions &Opts,
55  MacroBuilder &Builder) const override;
56 
58 
61  }
62 
63  const char *getClobbers() const override { return ""; }
64 
65  StringRef getConstraintRegister(StringRef Constraint,
66  StringRef Expression) const override {
67  return Expression;
68  }
69 
70  ArrayRef<const char *> getGCCRegNames() const override;
71 
72  int getEHDataRegisterNumber(unsigned RegNo) const override {
73  if (RegNo == 0)
74  return 10;
75  else if (RegNo == 1)
76  return 11;
77  else
78  return -1;
79  }
80 
82 
83  bool validateAsmConstraint(const char *&Name,
84  TargetInfo::ConstraintInfo &Info) const override;
85 
86  std::string convertConstraint(const char *&Constraint) const override;
87 
88  bool
89  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
90  StringRef CPU,
91  const std::vector<std::string> &FeaturesVec) const override;
92 
94  getVScaleRange(const LangOptions &LangOpts) const override;
95 
96  bool hasFeature(StringRef Feature) const override;
97 
98  bool handleTargetFeatures(std::vector<std::string> &Features,
99  DiagnosticsEngine &Diags) override;
100 
101  bool hasBitIntType() const override { return true; }
102 
103  bool useFP16ConversionIntrinsics() const override {
104  return false;
105  }
106 
107  bool isValidCPUName(StringRef Name) const override;
108  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
109  bool isValidTuneCPUName(StringRef Name) const override;
110  void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
111 };
112 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
113 public:
114  RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
115  : RISCVTargetInfo(Triple, Opts) {
116  IntPtrType = SignedInt;
117  PtrDiffType = SignedInt;
118  SizeType = UnsignedInt;
119  resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
120  }
121 
122  bool setABI(const std::string &Name) override {
123  if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
124  ABI = Name;
125  return true;
126  }
127  return false;
128  }
129 
130  void setMaxAtomicWidth() override {
131  MaxAtomicPromoteWidth = 128;
132 
133  if (ISAInfo->hasExtension("a"))
134  MaxAtomicInlineWidth = 32;
135  }
136 };
137 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
138 public:
139  RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
140  : RISCVTargetInfo(Triple, Opts) {
141  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
142  IntMaxType = Int64Type = SignedLong;
143  resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
144  }
145 
146  bool setABI(const std::string &Name) override {
147  if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
148  ABI = Name;
149  return true;
150  }
151  return false;
152  }
153 
154  void setMaxAtomicWidth() override {
155  MaxAtomicPromoteWidth = 128;
156 
157  if (ISAInfo->hasExtension("a"))
158  MaxAtomicInlineWidth = 64;
159  }
160 };
161 } // namespace targets
162 } // namespace clang
163 
164 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
clang::targets::RISCVTargetInfo::BuiltinInfo
static const Builtin::Info BuiltinInfo[]
Definition: RISCV.h:30
clang::targets::RISCVTargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: RISCV.cpp:313
clang::targets::RISCVTargetInfo::getEHDataRegisterNumber
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: RISCV.h:72
clang::targets::RISCV32TargetInfo::setMaxAtomicWidth
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:130
string
string(SUBSTRING ${CMAKE_CURRENT_BINARY_DIR} 0 ${PATH_LIB_START} PATH_HEAD) string(SUBSTRING $
Definition: CMakeLists.txt:22
clang::targets::RISCVTargetInfo::isValidTuneCPUName
bool isValidTuneCPUName(StringRef Name) const override
brief Determine whether this TargetInfo supports the given CPU name for
Definition: RISCV.cpp:319
clang::RISCV::SignedLong
@ SignedLong
Definition: RISCVVIntrinsicUtils.h:166
clang::targets::RISCVTargetInfo::getVScaleRange
Optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts) const override
Returns target-specific min and max values VScale_Range.
Definition: RISCV.cpp:250
TargetInfo.h
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
clang::TargetInfo
Exposes information about the current target.
Definition: TargetInfo.h:205
clang::TargetInfo::VoidPtrBuiltinVaList
@ VoidPtrBuiltinVaList
typedef void* __builtin_va_list;
Definition: TargetInfo.h:294
clang::TransferrableTargetInfo::WIntType
IntType WIntType
Definition: TargetInfo.h:150
clang::targets::RISCV64TargetInfo::setABI
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:146
clang::targets::RISCVTargetInfo::useFP16ConversionIntrinsics
bool useFP16ConversionIntrinsics() const override
Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used to convert to and from __fp...
Definition: RISCV.h:103
clang::targets::RISCVTargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition: RISCV.cpp:106
clang::targets::RISCVTargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: RISCV.cpp:215
llvm::Optional
Definition: LLVM.h:40
clang::targets::RISCVTargetInfo
Definition: RISCV.h:26
Expression
clang::targets::RISCVTargetInfo::RISCVTargetInfo
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: RISCV.h:33
clang::TargetInfo::BuiltinVaListKind
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:289
clang::targets::RISCVTargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features.
Definition: RISCV.cpp:286
clang::targets::RISCVTargetInfo::getABI
StringRef getABI() const override
Get the ABI currently in use.
Definition: RISCV.h:53
clang::targets::RISCVTargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: RISCV.cpp:67
clang::targets::RISCV64TargetInfo
Definition: RISCV.h:137
clang::targets::RISCVTargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition: RISCV.cpp:24
clang::targets::RISCVTargetInfo::getBuiltinVaListKind
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: RISCV.h:59
clang::targets::RISCVTargetInfo::isValidCPUName
bool isValidCPUName(StringRef Name) const override
brief Determine whether this TargetInfo supports the given CPU name.
Definition: RISCV.cpp:308
clang::targets::RISCV32TargetInfo::RISCV32TargetInfo
RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:114
clang::targets::RISCV32TargetInfo::setABI
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:122
clang::targets::RISCV32TargetInfo
Definition: RISCV.h:112
clang::TargetInfo::HasRISCVVTypes
unsigned HasRISCVVTypes
Definition: TargetInfo.h:250
clang::targets::RISCVTargetInfo::setCPU
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: RISCV.h:46
clang::targets::RISCVTargetInfo::hasFeature
bool hasFeature(StringRef Feature) const override
Return true if has this feature, need to sync with handleTargetFeatures.
Definition: RISCV.cpp:267
clang::targets::RISCVTargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: RISCV.cpp:325
TargetOptions.h
clang::TargetInfo::MCountName
const char * MCountName
Definition: TargetInfo.h:231
llvm::ArrayRef
Definition: LLVM.h:34
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:132
clang::targets::RISCVTargetInfo::ISAInfo
std::unique_ptr< llvm::RISCVISAInfo > ISAInfo
Definition: RISCV.h:29
clang::TargetInfo::ConstraintInfo
Definition: TargetInfo.h:1026
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:81
clang::TargetInfo::HasFloat16
bool HasFloat16
Definition: TargetInfo.h:220
clang
Definition: CalledOnceCheck.h:17
clang::Builtin::Info
Definition: Builtins.h:59
clang::TransferrableTargetInfo::SignedInt
@ SignedInt
Definition: TargetInfo.h:141
clang::targets::RISCVTargetInfo::CPU
std::string CPU
Definition: RISCV.h:28
clang::TransferrableTargetInfo::SuitableAlign
unsigned short SuitableAlign
Definition: TargetInfo.h:126
clang::TargetOptions
Options for controlling the target.
Definition: TargetOptions.h:26
clang::targets::RISCVTargetInfo::getClobbers
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: RISCV.h:63
llvm::SmallVectorImpl
Definition: Randstruct.h:18
clang::TransferrableTargetInfo::WCharType
IntType WCharType
Definition: TargetInfo.h:150
clang::targets::RISCVTargetInfo::getGCCRegAliases
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: RISCV.cpp:46
clang::targets::RISCV64TargetInfo::setMaxAtomicWidth
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:154
clang::MacroBuilder
Definition: MacroBuilder.h:23
clang::targets::RISCVTargetInfo::ABI
std::string ABI
Definition: RISCV.h:28
clang::targets::RISCVTargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: RISCV.cpp:120
clang::targets::RISCV64TargetInfo::RISCV64TargetInfo
RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:139
clang::targets::RISCVTargetInfo::getTargetBuiltins
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: RISCV.cpp:210
clang::TransferrableTargetInfo::LongDoubleWidth
unsigned char LongDoubleWidth
Definition: TargetInfo.h:91
clang::TransferrableTargetInfo::UnsignedInt
@ UnsignedInt
Definition: TargetInfo.h:142
clang::targets::RISCVTargetInfo::getConstraintRegister
StringRef getConstraintRegister(StringRef Constraint, StringRef Expression) const override
Extracts a register from the passed constraint (if it is a single-register constraint) and the asm la...
Definition: RISCV.h:65
clang::TransferrableTargetInfo::LongDoubleAlign
unsigned char LongDoubleAlign
Definition: TargetInfo.h:91
clang::targets::RISCVTargetInfo::hasBitIntType
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition: RISCV.h:101