clang 17.0.0git
RISCV.h
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1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/RISCVISAInfo.h"
20#include "llvm/TargetParser/Triple.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26// RISC-V Target
28protected:
29 std::string ABI, CPU;
30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
31
32public:
33 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
34 : TargetInfo(Triple) {
35 LongDoubleWidth = 128;
36 LongDoubleAlign = 128;
37 LongDoubleFormat = &llvm::APFloat::IEEEquad();
38 SuitableAlign = 128;
41 HasRISCVVTypes = true;
42 MCountName = "_mcount";
43 HasFloat16 = true;
44 HasStrictFP = true;
45 }
46
47 bool setCPU(const std::string &Name) override {
48 if (!isValidCPUName(Name))
49 return false;
50 CPU = Name;
51 return true;
52 }
53
54 StringRef getABI() const override { return ABI; }
55 void getTargetDefines(const LangOptions &Opts,
56 MacroBuilder &Builder) const override;
57
59
62 }
63
64 std::string_view getClobbers() const override { return ""; }
65
66 StringRef getConstraintRegister(StringRef Constraint,
67 StringRef Expression) const override {
68 return Expression;
69 }
70
72
73 int getEHDataRegisterNumber(unsigned RegNo) const override {
74 if (RegNo == 0)
75 return 10;
76 else if (RegNo == 1)
77 return 11;
78 else
79 return -1;
80 }
81
83
84 bool validateAsmConstraint(const char *&Name,
85 TargetInfo::ConstraintInfo &Info) const override;
86
87 std::string convertConstraint(const char *&Constraint) const override;
88
89 bool
90 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
91 StringRef CPU,
92 const std::vector<std::string> &FeaturesVec) const override;
93
94 std::optional<std::pair<unsigned, unsigned>>
95 getVScaleRange(const LangOptions &LangOpts) const override;
96
97 bool hasFeature(StringRef Feature) const override;
98
99 bool handleTargetFeatures(std::vector<std::string> &Features,
100 DiagnosticsEngine &Diags) override;
101
102 bool hasBitIntType() const override { return true; }
103
104 bool useFP16ConversionIntrinsics() const override {
105 return false;
106 }
107
108 bool isValidCPUName(StringRef Name) const override;
109 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
110 bool isValidTuneCPUName(StringRef Name) const override;
111 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
112};
113class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
114public:
115 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
116 : RISCVTargetInfo(Triple, Opts) {
117 IntPtrType = SignedInt;
118 PtrDiffType = SignedInt;
119 SizeType = UnsignedInt;
120 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
121 }
122
123 bool setABI(const std::string &Name) override {
124 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
125 ABI = Name;
126 return true;
127 }
128 return false;
129 }
130
131 void setMaxAtomicWidth() override {
132 MaxAtomicPromoteWidth = 128;
133
134 if (ISAInfo->hasExtension("a"))
135 MaxAtomicInlineWidth = 32;
136 }
137};
138class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
139public:
140 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
141 : RISCVTargetInfo(Triple, Opts) {
142 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
143 IntMaxType = Int64Type = SignedLong;
144 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
145 }
146
147 bool setABI(const std::string &Name) override {
148 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
149 ABI = Name;
150 return true;
151 }
152 return false;
153 }
154
155 void setMaxAtomicWidth() override {
156 MaxAtomicPromoteWidth = 128;
157
158 if (ISAInfo->hasExtension("a"))
159 MaxAtomicInlineWidth = 64;
160 }
161};
162} // namespace targets
163} // namespace clang
164
165#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
Defines the clang::TargetOptions class.
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:82
Exposes information about the current target.
Definition: TargetInfo.h:206
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:287
@ VoidPtrBuiltinVaList
typedef void* __builtin_va_list;
Definition: TargetInfo.h:292
const char * MCountName
Definition: TargetInfo.h:230
unsigned HasRISCVVTypes
Definition: TargetInfo.h:248
Options for controlling the target.
Definition: TargetOptions.h:26
RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:115
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:123
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:131
RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:140
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:155
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:147
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: RISCV.h:33
std::string convertConstraint(const char *&Constraint) const override
Definition: RISCV.cpp:107
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: RISCV.cpp:125
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: RISCV.cpp:222
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: RISCV.cpp:68
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: RISCV.cpp:227
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: RISCV.h:60
std::unique_ptr< llvm::RISCVISAInfo > ISAInfo
Definition: RISCV.h:30
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: RISCV.cpp:344
bool isValidTuneCPUName(StringRef Name) const override
brief Determine whether this TargetInfo supports the given CPU name for
Definition: RISCV.cpp:339
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts) const override
Returns target-specific min and max values VScale_Range.
Definition: RISCV.cpp:262
ArrayRef< const char * > getGCCRegNames() const override
Definition: RISCV.cpp:25
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: RISCV.cpp:47
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: RISCV.cpp:333
StringRef getABI() const override
Get the ABI currently in use.
Definition: RISCV.h:54
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: RISCV.h:73
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features.
Definition: RISCV.cpp:303
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: RISCV.h:64
StringRef getConstraintRegister(StringRef Constraint, StringRef Expression) const override
Extracts a register from the passed constraint (if it is a single-register constraint) and the asm la...
Definition: RISCV.h:66
bool hasFeature(StringRef Feature) const override
Return true if has this feature, need to sync with handleTargetFeatures.
Definition: RISCV.cpp:284
bool useFP16ConversionIntrinsics() const override
Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used to convert to and from __fp...
Definition: RISCV.h:104
bool isValidCPUName(StringRef Name) const override
brief Determine whether this TargetInfo supports the given CPU name.
Definition: RISCV.cpp:328
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition: RISCV.h:102
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: RISCV.h:47
Defines the clang::TargetInfo interface.
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:132