clang 19.0.0git
RISCV.h
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1//===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISC-V TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15
18#include "llvm/Support/Compiler.h"
19#include "llvm/TargetParser/RISCVISAInfo.h"
20#include "llvm/TargetParser/Triple.h"
21#include <optional>
22
23namespace clang {
24namespace targets {
25
26// RISC-V Target
28protected:
29 std::string ABI, CPU;
30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
31
32private:
33 bool FastUnalignedAccess;
34 bool HasExperimental = false;
35
36public:
37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
38 : TargetInfo(Triple) {
39 BFloat16Width = 16;
40 BFloat16Align = 16;
41 BFloat16Format = &llvm::APFloat::BFloat();
42 LongDoubleWidth = 128;
43 LongDoubleAlign = 128;
44 LongDoubleFormat = &llvm::APFloat::IEEEquad();
45 SuitableAlign = 128;
48 HasRISCVVTypes = true;
49 MCountName = "_mcount";
50 HasFloat16 = true;
51 HasStrictFP = true;
52 }
53
54 bool setCPU(const std::string &Name) override {
55 if (!isValidCPUName(Name))
56 return false;
57 CPU = Name;
58 return true;
59 }
60
61 StringRef getABI() const override { return ABI; }
62 void getTargetDefines(const LangOptions &Opts,
63 MacroBuilder &Builder) const override;
64
66
69 }
70
71 std::string_view getClobbers() const override { return ""; }
72
73 StringRef getConstraintRegister(StringRef Constraint,
74 StringRef Expression) const override {
75 return Expression;
76 }
77
79
80 int getEHDataRegisterNumber(unsigned RegNo) const override {
81 if (RegNo == 0)
82 return 10;
83 else if (RegNo == 1)
84 return 11;
85 else
86 return -1;
87 }
88
90
91 bool validateAsmConstraint(const char *&Name,
92 TargetInfo::ConstraintInfo &Info) const override;
93
94 std::string convertConstraint(const char *&Constraint) const override;
95
96 bool
97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
98 StringRef CPU,
99 const std::vector<std::string> &FeaturesVec) const override;
100
101 std::optional<std::pair<unsigned, unsigned>>
102 getVScaleRange(const LangOptions &LangOpts) const override;
103
104 bool hasFeature(StringRef Feature) const override;
105
106 bool handleTargetFeatures(std::vector<std::string> &Features,
107 DiagnosticsEngine &Diags) override;
108
109 bool hasBitIntType() const override { return true; }
110
111 bool hasBFloat16Type() const override { return true; }
112
114
115 bool useFP16ConversionIntrinsics() const override {
116 return false;
117 }
118
119 bool isValidCPUName(StringRef Name) const override;
120 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
121 bool isValidTuneCPUName(StringRef Name) const override;
122 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
123 bool supportsTargetAttributeTune() const override { return true; }
124 ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
125
126 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
127 return std::make_pair(32, 32);
128 }
129};
130class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
131public:
132 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
133 : RISCVTargetInfo(Triple, Opts) {
134 IntPtrType = SignedInt;
135 PtrDiffType = SignedInt;
136 SizeType = UnsignedInt;
137 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
138 }
139
140 bool setABI(const std::string &Name) override {
141 if (Name == "ilp32e") {
142 ABI = Name;
143 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32");
144 return true;
145 }
146
147 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
148 ABI = Name;
149 return true;
150 }
151 return false;
152 }
153
154 void setMaxAtomicWidth() override {
155 MaxAtomicPromoteWidth = 128;
156
157 if (ISAInfo->hasExtension("a"))
158 MaxAtomicInlineWidth = 32;
159 }
160};
161class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
162public:
163 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
164 : RISCVTargetInfo(Triple, Opts) {
165 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
166 IntMaxType = Int64Type = SignedLong;
167 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
168 }
169
170 bool setABI(const std::string &Name) override {
171 if (Name == "lp64e") {
172 ABI = Name;
173 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64");
174 return true;
175 }
176
177 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
178 ABI = Name;
179 return true;
180 }
181 return false;
182 }
183
184 void setMaxAtomicWidth() override {
185 MaxAtomicPromoteWidth = 128;
186
187 if (ISAInfo->hasExtension("a"))
188 MaxAtomicInlineWidth = 64;
189 }
190};
191} // namespace targets
192} // namespace clang
193
194#endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
Defines the clang::TargetOptions class.
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:461
Exposes information about the current target.
Definition: TargetInfo.h:218
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:319
@ VoidPtrBuiltinVaList
typedef void* __builtin_va_list;
Definition: TargetInfo.h:324
const char * MCountName
Definition: TargetInfo.h:245
unsigned HasRISCVVTypes
Definition: TargetInfo.h:270
Options for controlling the target.
Definition: TargetOptions.h:26
RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:132
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:140
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:154
RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: RISCV.h:163
void setMaxAtomicWidth() override
Set the maximum inline or promote width lock-free atomic operation for the given target.
Definition: RISCV.h:184
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: RISCV.h:170
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: RISCV.h:37
std::string convertConstraint(const char *&Constraint) const override
Definition: RISCV.cpp:114
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: RISCV.cpp:132
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: RISCV.cpp:240
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: RISCV.cpp:74
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: RISCV.cpp:245
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: RISCV.h:67
std::unique_ptr< llvm::RISCVISAInfo > ISAInfo
Definition: RISCV.h:30
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition: RISCV.cpp:386
bool isValidTuneCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name for tuning.
Definition: RISCV.cpp:381
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts) const override
Returns target-specific min and max values VScale_Range.
Definition: RISCV.cpp:295
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: RISCV.cpp:473
ArrayRef< const char * > getGCCRegNames() const override
Definition: RISCV.cpp:25
bool hasBFloat16Type() const override
Determine whether the _BFloat16 type is supported on this target.
Definition: RISCV.h:111
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: RISCV.cpp:53
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: RISCV.cpp:375
StringRef getABI() const override
Get the ABI currently in use.
Definition: RISCV.h:61
std::pair< unsigned, unsigned > hardwareInterferenceSizes() const override
The first value in the pair is the minimum offset between two objects to avoid false sharing (destruc...
Definition: RISCV.h:126
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: RISCV.h:80
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features.
Definition: RISCV.cpp:334
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: RISCV.h:71
StringRef getConstraintRegister(StringRef Constraint, StringRef Expression) const override
Extracts a register from the passed constraint (if it is a single-register constraint) and the asm la...
Definition: RISCV.h:73
bool supportsTargetAttributeTune() const override
Determine whether this TargetInfo supports tune in target attribute.
Definition: RISCV.h:123
ParsedTargetAttr parseTargetAttr(StringRef Str) const override
Definition: RISCV.cpp:409
bool hasFeature(StringRef Feature) const override
Return true if has this feature, need to sync with handleTargetFeatures.
Definition: RISCV.cpp:317
bool useFP16ConversionIntrinsics() const override
Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used to convert to and from __fp...
Definition: RISCV.h:115
bool isValidCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name.
Definition: RISCV.cpp:370
bool hasBitIntType() const override
Determine whether the _BitInt type is supported on this target.
Definition: RISCV.h:109
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: RISCV.h:54
Defines the clang::TargetInfo interface.
The JSON file list parser is used to communicate input to InstallAPI.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:275
Contains information gathered from parsing the contents of TargetAttr.
Definition: TargetInfo.h:57
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:139
const llvm::fltSemantics * BFloat16Format
Definition: TargetInfo.h:138