clang  8.0.0svn
Mips.cpp
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1 //===--- Mips.cpp - Tools Implementations -----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Mips.h"
11 #include "ToolChains/CommonArgs.h"
12 #include "clang/Driver/Driver.h"
14 #include "clang/Driver/Options.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/Option/ArgList.h"
17 
18 using namespace clang::driver;
19 using namespace clang::driver::tools;
20 using namespace clang;
21 using namespace llvm::opt;
22 
23 // Get CPU and ABI names. They are not independent
24 // so we have to calculate them together.
25 void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
26  StringRef &CPUName, StringRef &ABIName) {
27  const char *DefMips32CPU = "mips32r2";
28  const char *DefMips64CPU = "mips64r2";
29 
30  // MIPS32r6 is the default for mips(el)?-img-linux-gnu and MIPS64r6 is the
31  // default for mips64(el)?-img-linux-gnu.
32  if (Triple.getVendor() == llvm::Triple::ImaginationTechnologies &&
33  Triple.isGNUEnvironment()) {
34  DefMips32CPU = "mips32r6";
35  DefMips64CPU = "mips64r6";
36  }
37 
38  // MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
39  if (Triple.isAndroid()) {
40  DefMips32CPU = "mips32";
41  DefMips64CPU = "mips64r6";
42  }
43 
44  // MIPS3 is the default for mips64*-unknown-openbsd.
45  if (Triple.getOS() == llvm::Triple::OpenBSD)
46  DefMips64CPU = "mips3";
47 
48  // MIPS2 is the default for mips(el)?-unknown-freebsd.
49  // MIPS3 is the default for mips64(el)?-unknown-freebsd.
50  if (Triple.getOS() == llvm::Triple::FreeBSD) {
51  DefMips32CPU = "mips2";
52  DefMips64CPU = "mips3";
53  }
54 
55  if (Arg *A = Args.getLastArg(clang::driver::options::OPT_march_EQ,
56  options::OPT_mcpu_EQ))
57  CPUName = A->getValue();
58 
59  if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
60  ABIName = A->getValue();
61  // Convert a GNU style Mips ABI name to the name
62  // accepted by LLVM Mips backend.
63  ABIName = llvm::StringSwitch<llvm::StringRef>(ABIName)
64  .Case("32", "o32")
65  .Case("64", "n64")
66  .Default(ABIName);
67  }
68 
69  // Setup default CPU and ABI names.
70  if (CPUName.empty() && ABIName.empty()) {
71  switch (Triple.getArch()) {
72  default:
73  llvm_unreachable("Unexpected triple arch name");
74  case llvm::Triple::mips:
75  case llvm::Triple::mipsel:
76  CPUName = DefMips32CPU;
77  break;
78  case llvm::Triple::mips64:
79  case llvm::Triple::mips64el:
80  CPUName = DefMips64CPU;
81  break;
82  }
83  }
84 
85  if (ABIName.empty() &&
86  (Triple.getVendor() == llvm::Triple::MipsTechnologies ||
87  Triple.getVendor() == llvm::Triple::ImaginationTechnologies)) {
88  ABIName = llvm::StringSwitch<const char *>(CPUName)
89  .Case("mips1", "o32")
90  .Case("mips2", "o32")
91  .Case("mips3", "n64")
92  .Case("mips4", "n64")
93  .Case("mips5", "n64")
94  .Case("mips32", "o32")
95  .Case("mips32r2", "o32")
96  .Case("mips32r3", "o32")
97  .Case("mips32r5", "o32")
98  .Case("mips32r6", "o32")
99  .Case("mips64", "n64")
100  .Case("mips64r2", "n64")
101  .Case("mips64r3", "n64")
102  .Case("mips64r5", "n64")
103  .Case("mips64r6", "n64")
104  .Case("octeon", "n64")
105  .Case("p5600", "o32")
106  .Default("");
107  }
108 
109  if (ABIName.empty()) {
110  // Deduce ABI name from the target triple.
111  ABIName = Triple.isMIPS32() ? "o32" : "n64";
112  }
113 
114  if (CPUName.empty()) {
115  // Deduce CPU name from ABI name.
116  CPUName = llvm::StringSwitch<const char *>(ABIName)
117  .Case("o32", DefMips32CPU)
118  .Cases("n32", "n64", DefMips64CPU)
119  .Default("");
120  }
121 
122  // FIXME: Warn on inconsistent use of -march and -mabi.
123 }
124 
125 std::string mips::getMipsABILibSuffix(const ArgList &Args,
126  const llvm::Triple &Triple) {
127  StringRef CPUName, ABIName;
128  tools::mips::getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
129  return llvm::StringSwitch<std::string>(ABIName)
130  .Case("o32", "")
131  .Case("n32", "32")
132  .Case("n64", "64");
133 }
134 
135 // Convert ABI name to the GNU tools acceptable variant.
136 StringRef mips::getGnuCompatibleMipsABIName(StringRef ABI) {
137  return llvm::StringSwitch<llvm::StringRef>(ABI)
138  .Case("o32", "32")
139  .Case("n64", "64")
140  .Default(ABI);
141 }
142 
143 // Select the MIPS float ABI as determined by -msoft-float, -mhard-float,
144 // and -mfloat-abi=.
145 mips::FloatABI mips::getMipsFloatABI(const Driver &D, const ArgList &Args) {
147  if (Arg *A =
148  Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
149  options::OPT_mfloat_abi_EQ)) {
150  if (A->getOption().matches(options::OPT_msoft_float))
151  ABI = mips::FloatABI::Soft;
152  else if (A->getOption().matches(options::OPT_mhard_float))
153  ABI = mips::FloatABI::Hard;
154  else {
155  ABI = llvm::StringSwitch<mips::FloatABI>(A->getValue())
156  .Case("soft", mips::FloatABI::Soft)
157  .Case("hard", mips::FloatABI::Hard)
158  .Default(mips::FloatABI::Invalid);
159  if (ABI == mips::FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
160  D.Diag(clang::diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
161  ABI = mips::FloatABI::Hard;
162  }
163  }
164  }
165 
166  // If unspecified, choose the default based on the platform.
167  if (ABI == mips::FloatABI::Invalid) {
168  // Assume "hard", because it's a default value used by gcc.
169  // When we start to recognize specific target MIPS processors,
170  // we will be able to select the default more correctly.
171  ABI = mips::FloatABI::Hard;
172  }
173 
174  assert(ABI != mips::FloatABI::Invalid && "must select an ABI");
175  return ABI;
176 }
177 
178 void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
179  const ArgList &Args,
180  std::vector<StringRef> &Features) {
181  StringRef CPUName;
182  StringRef ABIName;
183  getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
184  ABIName = getGnuCompatibleMipsABIName(ABIName);
185 
186  // Historically, PIC code for MIPS was associated with -mabicalls, a.k.a
187  // SVR4 abicalls. Static code does not use SVR4 calling sequences. An ABI
188  // extension was developed by Richard Sandiford & Code Sourcery to support
189  // static code calling PIC code (CPIC). For O32 and N32 this means we have
190  // several combinations of PIC/static and abicalls. Pure static, static
191  // with the CPIC extension, and pure PIC code.
192 
193  // At final link time, O32 and N32 with CPIC will have another section
194  // added to the binary which contains the stub functions to perform
195  // any fixups required for PIC code.
196 
197  // For N64, the situation is more regular: code can either be static
198  // (non-abicalls) or PIC (abicalls). GCC has traditionally picked PIC code
199  // code for N64. Since Clang has already built the relocation model portion
200  // of the commandline, we pick add +noabicalls feature in the N64 static
201  // case.
202 
203  // The is another case to be accounted for: -msym32, which enforces that all
204  // symbols have 32 bits in size. In this case, N64 can in theory use CPIC
205  // but it is unsupported.
206 
207  // The combinations for N64 are:
208  // a) Static without abicalls and 64bit symbols.
209  // b) Static with abicalls and 32bit symbols.
210  // c) PIC with abicalls and 64bit symbols.
211 
212  // For case (a) we need to add +noabicalls for N64.
213 
214  bool IsN64 = ABIName == "64";
215  bool IsPIC = false;
216  bool NonPIC = false;
217 
218  Arg *LastPICArg = Args.getLastArg(options::OPT_fPIC, options::OPT_fno_PIC,
219  options::OPT_fpic, options::OPT_fno_pic,
220  options::OPT_fPIE, options::OPT_fno_PIE,
221  options::OPT_fpie, options::OPT_fno_pie);
222  if (LastPICArg) {
223  Option O = LastPICArg->getOption();
224  NonPIC =
225  (O.matches(options::OPT_fno_PIC) || O.matches(options::OPT_fno_pic) ||
226  O.matches(options::OPT_fno_PIE) || O.matches(options::OPT_fno_pie));
227  IsPIC =
228  (O.matches(options::OPT_fPIC) || O.matches(options::OPT_fpic) ||
229  O.matches(options::OPT_fPIE) || O.matches(options::OPT_fpie));
230  }
231 
232  bool UseAbiCalls = false;
233 
234  Arg *ABICallsArg =
235  Args.getLastArg(options::OPT_mabicalls, options::OPT_mno_abicalls);
236  UseAbiCalls =
237  !ABICallsArg || ABICallsArg->getOption().matches(options::OPT_mabicalls);
238 
239  if (IsN64 && NonPIC && (!ABICallsArg || UseAbiCalls)) {
240  D.Diag(diag::warn_drv_unsupported_pic_with_mabicalls)
241  << LastPICArg->getAsString(Args) << (!ABICallsArg ? 0 : 1);
242  NonPIC = false;
243  }
244 
245  if (ABICallsArg && !UseAbiCalls && IsPIC) {
246  D.Diag(diag::err_drv_unsupported_noabicalls_pic);
247  }
248 
249  if (!UseAbiCalls)
250  Features.push_back("+noabicalls");
251  else
252  Features.push_back("-noabicalls");
253 
254  if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
255  options::OPT_mno_long_calls)) {
256  if (A->getOption().matches(options::OPT_mno_long_calls))
257  Features.push_back("-long-calls");
258  else if (!UseAbiCalls)
259  Features.push_back("+long-calls");
260  else
261  D.Diag(diag::warn_drv_unsupported_longcalls) << (ABICallsArg ? 0 : 1);
262  }
263 
265  if (FloatABI == mips::FloatABI::Soft) {
266  // FIXME: Note, this is a hack. We need to pass the selected float
267  // mode to the MipsTargetInfoBase to define appropriate macros there.
268  // Now it is the only method.
269  Features.push_back("+soft-float");
270  }
271 
272  if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
273  StringRef Val = StringRef(A->getValue());
274  if (Val == "2008") {
276  Features.push_back("+nan2008");
277  else {
278  Features.push_back("-nan2008");
279  D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
280  }
281  } else if (Val == "legacy") {
282  if (mips::getIEEE754Standard(CPUName) & mips::Legacy)
283  Features.push_back("-nan2008");
284  else {
285  Features.push_back("+nan2008");
286  D.Diag(diag::warn_target_unsupported_nanlegacy) << CPUName;
287  }
288  } else
289  D.Diag(diag::err_drv_unsupported_option_argument)
290  << A->getOption().getName() << Val;
291  }
292 
293  if (Arg *A = Args.getLastArg(options::OPT_mabs_EQ)) {
294  StringRef Val = StringRef(A->getValue());
295  if (Val == "2008") {
296  if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
297  Features.push_back("+abs2008");
298  } else {
299  Features.push_back("-abs2008");
300  D.Diag(diag::warn_target_unsupported_abs2008) << CPUName;
301  }
302  } else if (Val == "legacy") {
303  if (mips::getIEEE754Standard(CPUName) & mips::Legacy) {
304  Features.push_back("-abs2008");
305  } else {
306  Features.push_back("+abs2008");
307  D.Diag(diag::warn_target_unsupported_abslegacy) << CPUName;
308  }
309  } else {
310  D.Diag(diag::err_drv_unsupported_option_argument)
311  << A->getOption().getName() << Val;
312  }
313  }
314 
315  AddTargetFeature(Args, Features, options::OPT_msingle_float,
316  options::OPT_mdouble_float, "single-float");
317  AddTargetFeature(Args, Features, options::OPT_mips16, options::OPT_mno_mips16,
318  "mips16");
319  AddTargetFeature(Args, Features, options::OPT_mmicromips,
320  options::OPT_mno_micromips, "micromips");
321  AddTargetFeature(Args, Features, options::OPT_mdsp, options::OPT_mno_dsp,
322  "dsp");
323  AddTargetFeature(Args, Features, options::OPT_mdspr2, options::OPT_mno_dspr2,
324  "dspr2");
325  AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
326  "msa");
327 
328  // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
329  // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
330  // nooddspreg.
331  if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
332  options::OPT_mfp64)) {
333  if (A->getOption().matches(options::OPT_mfp32))
334  Features.push_back("-fp64");
335  else if (A->getOption().matches(options::OPT_mfpxx)) {
336  Features.push_back("+fpxx");
337  Features.push_back("+nooddspreg");
338  } else
339  Features.push_back("+fp64");
340  } else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
341  Features.push_back("+fpxx");
342  Features.push_back("+nooddspreg");
343  } else if (mips::isFP64ADefault(Triple, CPUName)) {
344  Features.push_back("+fp64");
345  Features.push_back("+nooddspreg");
346  }
347 
348  AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
349  options::OPT_modd_spreg, "nooddspreg");
350  AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4,
351  "nomadd4");
352  AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, "mt");
353  AddTargetFeature(Args, Features, options::OPT_mcrc, options::OPT_mno_crc,
354  "crc");
355  AddTargetFeature(Args, Features, options::OPT_mvirt, options::OPT_mno_virt,
356  "virt");
357  AddTargetFeature(Args, Features, options::OPT_mginv, options::OPT_mno_ginv,
358  "ginv");
359 
360  if (Arg *A = Args.getLastArg(options::OPT_mindirect_jump_EQ)) {
361  StringRef Val = StringRef(A->getValue());
362  if (Val == "hazard") {
363  Arg *B =
364  Args.getLastArg(options::OPT_mmicromips, options::OPT_mno_micromips);
365  Arg *C = Args.getLastArg(options::OPT_mips16, options::OPT_mno_mips16);
366 
367  if (B && B->getOption().matches(options::OPT_mmicromips))
368  D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
369  << "hazard" << "micromips";
370  else if (C && C->getOption().matches(options::OPT_mips16))
371  D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
372  << "hazard" << "mips16";
373  else if (mips::supportsIndirectJumpHazardBarrier(CPUName))
374  Features.push_back("+use-indirect-jump-hazard");
375  else
376  D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
377  << "hazard" << CPUName;
378  } else
379  D.Diag(diag::err_drv_unknown_indirect_jump_opt) << Val;
380  }
381 }
382 
384  // Strictly speaking, mips32r2 and mips64r2 do not conform to the
385  // IEEE754-2008 standard. Support for this standard was first introduced
386  // in Release 3. However, other compilers have traditionally allowed it
387  // for Release 2 so we should do the same.
388  return (IEEE754Standard)llvm::StringSwitch<int>(CPU)
389  .Case("mips1", Legacy)
390  .Case("mips2", Legacy)
391  .Case("mips3", Legacy)
392  .Case("mips4", Legacy)
393  .Case("mips5", Legacy)
394  .Case("mips32", Legacy)
395  .Case("mips32r2", Legacy | Std2008)
396  .Case("mips32r3", Legacy | Std2008)
397  .Case("mips32r5", Legacy | Std2008)
398  .Case("mips32r6", Std2008)
399  .Case("mips64", Legacy)
400  .Case("mips64r2", Legacy | Std2008)
401  .Case("mips64r3", Legacy | Std2008)
402  .Case("mips64r5", Legacy | Std2008)
403  .Case("mips64r6", Std2008)
404  .Default(Std2008);
405 }
406 
407 bool mips::hasCompactBranches(StringRef &CPU) {
408  // mips32r6 and mips64r6 have compact branches.
409  return llvm::StringSwitch<bool>(CPU)
410  .Case("mips32r6", true)
411  .Case("mips64r6", true)
412  .Default(false);
413 }
414 
415 bool mips::hasMipsAbiArg(const ArgList &Args, const char *Value) {
416  Arg *A = Args.getLastArg(options::OPT_mabi_EQ);
417  return A && (A->getValue() == StringRef(Value));
418 }
419 
420 bool mips::isUCLibc(const ArgList &Args) {
421  Arg *A = Args.getLastArg(options::OPT_m_libc_Group);
422  return A && A->getOption().matches(options::OPT_muclibc);
423 }
424 
425 bool mips::isNaN2008(const ArgList &Args, const llvm::Triple &Triple) {
426  if (Arg *NaNArg = Args.getLastArg(options::OPT_mnan_EQ))
427  return llvm::StringSwitch<bool>(NaNArg->getValue())
428  .Case("2008", true)
429  .Case("legacy", false)
430  .Default(false);
431 
432  // NaN2008 is the default for MIPS32r6/MIPS64r6.
433  return llvm::StringSwitch<bool>(getCPUName(Args, Triple))
434  .Cases("mips32r6", "mips64r6", true)
435  .Default(false);
436 
437  return false;
438 }
439 
440 bool mips::isFP64ADefault(const llvm::Triple &Triple, StringRef CPUName) {
441  if (!Triple.isAndroid())
442  return false;
443 
444  // Android MIPS32R6 defaults to FP64A.
445  return llvm::StringSwitch<bool>(CPUName)
446  .Case("mips32r6", true)
447  .Default(false);
448 }
449 
450 bool mips::isFPXXDefault(const llvm::Triple &Triple, StringRef CPUName,
451  StringRef ABIName, mips::FloatABI FloatABI) {
452  if (Triple.getVendor() != llvm::Triple::ImaginationTechnologies &&
453  Triple.getVendor() != llvm::Triple::MipsTechnologies &&
454  !Triple.isAndroid())
455  return false;
456 
457  if (ABIName != "32")
458  return false;
459 
460  // FPXX shouldn't be used if either -msoft-float or -mfloat-abi=soft is
461  // present.
462  if (FloatABI == mips::FloatABI::Soft)
463  return false;
464 
465  return llvm::StringSwitch<bool>(CPUName)
466  .Cases("mips2", "mips3", "mips4", "mips5", true)
467  .Cases("mips32", "mips32r2", "mips32r3", "mips32r5", true)
468  .Cases("mips64", "mips64r2", "mips64r3", "mips64r5", true)
469  .Default(false);
470 }
471 
472 bool mips::shouldUseFPXX(const ArgList &Args, const llvm::Triple &Triple,
473  StringRef CPUName, StringRef ABIName,
475  bool UseFPXX = isFPXXDefault(Triple, CPUName, ABIName, FloatABI);
476 
477  // FPXX shouldn't be used if -msingle-float is present.
478  if (Arg *A = Args.getLastArg(options::OPT_msingle_float,
479  options::OPT_mdouble_float))
480  if (A->getOption().matches(options::OPT_msingle_float))
481  UseFPXX = false;
482 
483  return UseFPXX;
484 }
485 
487  // Supporting the hazard barrier method of dealing with indirect
488  // jumps requires MIPSR2 support.
489  return llvm::StringSwitch<bool>(CPU)
490  .Case("mips32r2", true)
491  .Case("mips32r3", true)
492  .Case("mips32r5", true)
493  .Case("mips32r6", true)
494  .Case("mips64r2", true)
495  .Case("mips64r3", true)
496  .Case("mips64r5", true)
497  .Case("mips64r6", true)
498  .Case("octeon", true)
499  .Case("p5600", true)
500  .Default(false);
501 }
bool shouldUseFPXX(const llvm::opt::ArgList &Args, const llvm::Triple &Triple, StringRef CPUName, StringRef ABIName, mips::FloatABI FloatABI)
DiagnosticBuilder Diag(unsigned DiagID) const
Definition: Driver.h:110
void AddTargetFeature(const llvm::opt::ArgList &Args, std::vector< StringRef > &Features, llvm::opt::OptSpecifier OnOpt, llvm::opt::OptSpecifier OffOpt, StringRef FeatureName)
std::string getCPUName(const llvm::opt::ArgList &Args, const llvm::Triple &T, bool FromAs=false)
IEEE754Standard getIEEE754Standard(StringRef &CPU)
Definition: Mips.cpp:383
bool isNaN2008(const llvm::opt::ArgList &Args, const llvm::Triple &Triple)
Driver - Encapsulate logic for constructing compilation processes from a set of gcc-driver-like comma...
Definition: Driver.h:59
bool hasMipsAbiArg(const llvm::opt::ArgList &Args, const char *Value)
mips::FloatABI getMipsFloatABI(const Driver &D, const llvm::opt::ArgList &Args)
void getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, std::vector< StringRef > &Features)
bool isUCLibc(const llvm::opt::ArgList &Args)
bool isFPXXDefault(const llvm::Triple &Triple, StringRef CPUName, StringRef ABIName, mips::FloatABI FloatABI)
Definition: Mips.cpp:450
bool supportsIndirectJumpHazardBarrier(StringRef &CPU)
Definition: Mips.cpp:486
Dataflow Directional Tag Classes.
bool hasCompactBranches(StringRef &CPU)
Definition: Mips.cpp:407
StringRef getGnuCompatibleMipsABIName(StringRef ABI)
Definition: Mips.cpp:136
bool isFP64ADefault(const llvm::Triple &Triple, StringRef CPUName)
Definition: Mips.cpp:440
void getMipsCPUAndABI(const llvm::opt::ArgList &Args, const llvm::Triple &Triple, StringRef &CPUName, StringRef &ABIName)
std::string getMipsABILibSuffix(const llvm::opt::ArgList &Args, const llvm::Triple &Triple)