9#ifndef __CLANG_GPU_INTRINSICS_H__
10#define __CLANG_GPU_INTRINSICS_H__
12#if defined(__HIP__) || defined(__CUDA__)
16 "__clang_gpu_intrinsics.h must be included via __clang_gpu_device_functions.h"
23template <
typename __T>
24__GPU_DEVICE__ __T __gpu_shuffle_idx_impl(__T
__v,
unsigned int __idx,
26 if constexpr (
sizeof(__T) ==
sizeof(
unsigned long long)) {
27 return __builtin_bit_cast(
29 __builtin_bit_cast(
unsigned long long,
__v),
32 return __builtin_bit_cast(
34 __builtin_bit_cast(
unsigned int,
__v),
39template <
typename __T>
40__GPU_DEVICE__ __T __shfl(MAYBE_UNDEF __T __var,
int __src_lane,
41 int __width = warpSize) {
42 return __gpu_shuffle_idx_impl(
43 __var, (
unsigned int)(__src_lane & (__width - 1)), __width);
45template <
typename __T>
46__GPU_DEVICE__ __T __shfl_up(MAYBE_UNDEF __T __var,
unsigned int __delta,
47 int __width = warpSize) {
49 int __tgt = __rel -
int(__delta);
50 return __gpu_shuffle_idx_impl(
51 __var, (
unsigned int)(__tgt < 0 ? __rel : __tgt), __width);
53template <
typename __T>
54__GPU_DEVICE__ __T __shfl_down(MAYBE_UNDEF __T __var,
unsigned int __delta,
55 int __width = warpSize) {
57 int __tgt = __rel +
int(__delta);
58 return __gpu_shuffle_idx_impl(
59 __var, (
unsigned int)(__tgt >= __width ? __rel : __tgt), __width);
61template <
typename __T>
62__GPU_DEVICE__ __T __shfl_xor(MAYBE_UNDEF __T __var,
int __lane_mask,
63 int __width = warpSize) {
65 int __tgt = __rel ^ __lane_mask;
66 return __gpu_shuffle_idx_impl(
67 __var, (
unsigned int)(__tgt >= __width ? __rel : __tgt), __width);
74__GPU_DEVICE__
void __syncwarp(
unsigned long long __mask = -1) {
75 __scoped_atomic_thread_fence(__ATOMIC_RELEASE, __MEMORY_SCOPE_WVFRNT);
77 __scoped_atomic_thread_fence(__ATOMIC_ACQUIRE, __MEMORY_SCOPE_WVFRNT);
84template <
typename __MaskT>
85__GPU_DEVICE__
unsigned long long __ballot_sync(__MaskT __mask,
int __pred) {
86 return __ballot(__pred) & (
unsigned long long)__mask;
88template <
typename __MaskT>
89__GPU_DEVICE__
int __all_sync(__MaskT __mask,
int __pred) {
90 return __ballot_sync(__mask, __pred) == (
unsigned long long)__mask;
92template <
typename __MaskT>
93__GPU_DEVICE__
int __any_sync(__MaskT __mask,
int __pred) {
94 return __ballot_sync(__mask, __pred) != 0ull;
97template <
typename __MaskT,
typename __T>
98__GPU_DEVICE__ __T __shfl_sync(__MaskT __mask, MAYBE_UNDEF __T __var,
99 int __src_lane,
int __width = warpSize) {
101 return __shfl(__var, __src_lane, __width);
103template <
typename __MaskT,
typename __T>
104__GPU_DEVICE__ __T __shfl_up_sync(__MaskT __mask, MAYBE_UNDEF __T __var,
105 unsigned int __delta,
106 int __width = warpSize) {
108 return __shfl_up(__var, __delta, __width);
110template <
typename __MaskT,
typename __T>
111__GPU_DEVICE__ __T __shfl_down_sync(__MaskT __mask, MAYBE_UNDEF __T __var,
112 unsigned int __delta,
113 int __width = warpSize) {
115 return __shfl_down(__var, __delta, __width);
117template <
typename __MaskT,
typename __T>
118__GPU_DEVICE__ __T __shfl_xor_sync(__MaskT __mask, MAYBE_UNDEF __T __var,
119 int __lane_mask,
int __width = warpSize) {
121 return __shfl_xor(__var, __lane_mask, __width);
128template <
typename __T>
129__GPU_DEVICE__
unsigned long long __match_any(__T
__value) {
130 if constexpr (
sizeof(__T) ==
sizeof(
unsigned long long)) {
132 __builtin_bit_cast(
unsigned long long,
__value));
135 __builtin_bit_cast(
unsigned int,
__value));
138template <
typename __MaskT,
typename __T>
139__GPU_DEVICE__
unsigned long long __match_any_sync(__MaskT __mask,
141 return __match_any(
__value) & (
unsigned long long)__mask;
144template <
typename __T>
145__GPU_DEVICE__
unsigned long long __match_all(__T
__value,
int *__pred) {
146 unsigned long long __r;
147 if constexpr (
sizeof(__T) ==
sizeof(
unsigned long long)) {
149 __builtin_bit_cast(
unsigned long long,
__value));
152 __builtin_bit_cast(
unsigned int,
__value));
157template <
typename __MaskT,
typename __T>
158__GPU_DEVICE__
unsigned long long __match_all_sync(__MaskT __mask, __T
__value,
161 return __match_all(
__value, __pred);
168template <
typename __MaskT>
169__GPU_DEVICE__
unsigned int __reduce_add_sync(__MaskT __mask,
170 unsigned int __val) {
171 return __gpu_lane_add_u32((
unsigned long long)__mask, __val);
173template <
typename __MaskT>
174__GPU_DEVICE__
int __reduce_add_sync(__MaskT __mask,
int __val) {
176 __gpu_lane_add_u32((
unsigned long long)__mask, (
unsigned int)__val));
178template <
typename __MaskT>
179__GPU_DEVICE__
unsigned int __reduce_min_sync(__MaskT __mask,
180 unsigned int __val) {
181 return __gpu_lane_min_u32((
unsigned long long)__mask, __val);
183template <
typename __MaskT>
184__GPU_DEVICE__
int __reduce_min_sync(__MaskT __mask,
int __val) {
185 unsigned int __r = __gpu_lane_min_u32((
unsigned long long)__mask,
186 (
unsigned int)__val ^ 0x80000000u);
187 return int(__r ^ 0x80000000u);
189template <
typename __MaskT>
190__GPU_DEVICE__
unsigned int __reduce_max_sync(__MaskT __mask,
191 unsigned int __val) {
192 return __gpu_lane_max_u32((
unsigned long long)__mask, __val);
194template <
typename __MaskT>
195__GPU_DEVICE__
int __reduce_max_sync(__MaskT __mask,
int __val) {
196 unsigned int __r = __gpu_lane_max_u32((
unsigned long long)__mask,
197 (
unsigned int)__val ^ 0x80000000u);
198 return int(__r ^ 0x80000000u);
200template <
typename __MaskT>
201__GPU_DEVICE__
unsigned int __reduce_and_sync(__MaskT __mask,
202 unsigned int __val) {
203 return __gpu_lane_and_u32((
unsigned long long)__mask, __val);
205template <
typename __MaskT>
206__GPU_DEVICE__
unsigned int __reduce_or_sync(__MaskT __mask,
207 unsigned int __val) {
208 return __gpu_lane_or_u32((
unsigned long long)__mask, __val);
210template <
typename __MaskT>
211__GPU_DEVICE__
unsigned int __reduce_xor_sync(__MaskT __mask,
212 unsigned int __val) {
213 return __gpu_lane_xor_u32((
unsigned long long)__mask, __val);
220__GPU_DEVICE__
unsigned int
221__funnelshift_l(
unsigned int __lo,
unsigned int __hi,
unsigned int __shift) {
222 unsigned int __s = __shift & 31u;
223 return (
unsigned int)((((
unsigned long long)__hi << 32 | __lo) << __s) >> 32);
225__GPU_DEVICE__
unsigned int
226__funnelshift_lc(
unsigned int __lo,
unsigned int __hi,
unsigned int __shift) {
227 unsigned int __s = __shift >= 32u ? 32u : __shift;
228 return (
unsigned int)((((
unsigned long long)__hi << 32 | __lo) << __s) >> 32);
230__GPU_DEVICE__
unsigned int
231__funnelshift_r(
unsigned int __lo,
unsigned int __hi,
unsigned int __shift) {
232 unsigned int __s = __shift & 31u;
233 return (
unsigned int)(((
unsigned long long)__hi << 32 | __lo) >> __s);
235__GPU_DEVICE__
unsigned int
236__funnelshift_rc(
unsigned int __lo,
unsigned int __hi,
unsigned int __shift) {
237 unsigned int __s = __shift >= 32u ? 32u : __shift;
238 return (
unsigned int)(((
unsigned long long)__hi << 32 | __lo) >> __s);
__DEVICE__ unsigned int __ballot(int __a)
__device__ unsigned __funnelshift_lc(unsigned low32, unsigned high32, unsigned shiftWidth)
__device__ unsigned __funnelshift_rc(unsigned low32, unsigned high32, unsigned shiftWidth)
__device__ unsigned __funnelshift_r(unsigned low32, unsigned high32, unsigned shiftWidth)
__device__ unsigned __funnelshift_l(unsigned low32, unsigned high32, unsigned shiftWidth)
static _DEFAULT_FN_ATTRS __inline__ uint32_t __gpu_lane_id(void)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_lane_mask(void)
static _DEFAULT_FN_ATTRS __inline__ uint32_t __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t __idx, uint32_t __x, uint32_t __width)
static _DEFAULT_FN_ATTRS __inline__ void __gpu_sync_lane(uint64_t __lane_mask)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x, uint32_t __width)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_match_all_u32(uint64_t __lane_mask, uint32_t __x)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_match_all_u64(uint64_t __lane_mask, uint64_t __x)
static _DEFAULT_FN_ATTRS __inline__ uint64_t __gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x)
static __inline__ void unsigned int __value