22#include "llvm/IR/LegacyPassManager.h"
23#include "llvm/IR/Module.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/TargetParser/Triple.h"
34 llvm::Error &Err, std::list<PartialTranslationUnit> &
PTUs)
45 llvm::Error &Err, std::list<PartialTranslationUnit> &
PTUs)
48 DeviceCI(DeviceInstance) {
51 if (!llvm::Triple(
TargetOpts.Triple).isAMDGCN()) {
52 Err = llvm::joinErrors(
54 llvm::make_error<llvm::StringError>(
55 "Invalid HIP architecture for target '" + TargetOpts.Triple +
"'",
56 llvm::inconvertibleErrorCode()));
62IncrementalHIPDeviceParser::GenerateDeviceObject() {
63 auto &PTU =
PTUs.back();
66 CodeGenOptsForObj.DisableLLVMPasses =
true;
68 ObjectContent.clear();
69 auto ObjOS = std::make_unique<llvm::raw_svector_ostream>(ObjectContent);
75 return llvm::make_error<llvm::StringError>(
76 "Backend code generation failed for HIP device code.",
77 llvm::inconvertibleErrorCode());
79 return llvm::StringRef(ObjectContent.data(), ObjectContent.size());
89 return llvm::make_error<llvm::StringError>(
90 "HIP offload binary generation is not supported yet.",
91 llvm::inconvertibleErrorCode());
100 llvm::Error &Err, std::list<PartialTranslationUnit> &
PTUs)
106 if (!
Arch.starts_with(
"sm_") ||
Arch.substr(3).getAsInteger(10, SMVersion)) {
107 Err = llvm::joinErrors(std::move(Err), llvm::make_error<llvm::StringError>(
108 "Invalid CUDA architecture",
109 llvm::inconvertibleErrorCode()));
115 auto &PTU =
PTUs.back();
118 const llvm::Target *
Target = llvm::TargetRegistry::lookupTarget(
119 PTU.TheModule->getTargetTriple(),
Error);
121 return llvm::make_error<llvm::StringError>(std::move(
Error),
123 llvm::TargetOptions TO = llvm::TargetOptions();
124 std::unique_ptr<llvm::TargetMachine> TM(
Target->createTargetMachine(
126 llvm::Reloc::Model::PIC_));
129 llvm::raw_svector_ostream dest(PTXCode);
131 llvm::legacy::PassManager PM;
132 if (TM->addPassesToEmitFile(PM, dest,
nullptr,
133 llvm::CodeGenFileType::AssemblyFile)) {
134 return llvm::make_error<llvm::StringError>(
135 "NVPTX backend cannot produce PTX code.",
136 llvm::inconvertibleErrorCode());
139 PM.run(*PTU.TheModule);
142 while (PTXCode.size() % 8)
144 return PTXCode.str();
147llvm::Error IncrementalCUDADeviceParser::GenerateFatbinary() {
149 AddressSize64 = 0x01,
157 struct FatBinInnerHeader {
179 :
Kind(1 ), unknown02(0x0101), HeaderSize(sizeof(*this)),
180 DataSize(DataSize), unknown0c(0), CompressedSize(0),
181 SubHeaderSize(HeaderSize - 8), VersionMinor(2), VersionMajor(4),
182 CudaArch(CudaArch), unknown20(0), unknown24(0), Flags(Flags),
183 unknown2c(0), unknown30(0), unknown34(0), UncompressedSize(0),
184 unknown3c(0), unknown40(0), unknown44(0) {}
187 struct FatBinHeader {
195 : Magic(0xba55ed50), Version(1), HeaderSize(sizeof(*this)),
196 DataSize(DataSize), unknown0c(0) {}
199 FatBinHeader OuterHeader(
sizeof(FatBinInnerHeader) + PTXCode.size());
200 FatbinContent.append((
char *)&OuterHeader,
201 ((
char *)&OuterHeader) + OuterHeader.HeaderSize);
203 FatBinInnerHeader InnerHeader(PTXCode.size(), SMVersion,
204 FatBinFlags::AddressSize64 |
205 FatBinFlags::HostLinux);
206 FatbinContent.append((
char *)&InnerHeader,
207 ((
char *)&InnerHeader) + InnerHeader.HeaderSize);
209 FatbinContent.append(PTXCode.begin(), PTXCode.end());
211 const PartialTranslationUnit &PTU =
PTUs.back();
213 std::string FatbinFileName =
"/" + PTU.TheModule->getName().str() +
".fatbin";
215 VFS->addFile(FatbinFileName, 0,
216 llvm::MemoryBuffer::getMemBuffer(
217 llvm::StringRef(FatbinContent.data(), FatbinContent.size()),
220 CodeGenOpts.OffloadBinaryToEmbedFile = std::move(FatbinFileName);
222 FatbinContent.clear();
224 return llvm::Error::success();
230 return PTX.takeError();
232 return GenerateFatbinary();
Defines the clang::TargetOptions class.
CodeGenOptions - Track various options which control how the code is optimized and passed to the back...
CompilerInstance - Helper class for managing a single instance of the Clang compiler.
DiagnosticsEngine & getDiagnostics() const
Get the current diagnostics engine.
IntrusiveRefCntPtr< llvm::vfs::FileSystem > getVirtualFileSystemPtr() const
CodeGenOptions & getCodeGenOpts()
bool hasErrorOccurred() const
A custom action enabling the incremental processing functionality.
IncrementalCUDADeviceParser(CompilerInstance &DeviceInstance, CompilerInstance &HostInstance, IncrementalAction *DeviceAct, llvm::IntrusiveRefCntPtr< llvm::vfs::InMemoryFileSystem > VFS, llvm::Error &Err, std::list< PartialTranslationUnit > &PTUs)
~IncrementalCUDADeviceParser() override
llvm::Error GenerateOffloadBinary() override
IncrementalDeviceParser(CompilerInstance &DeviceInstance, CompilerInstance &HostInstance, IncrementalAction *DeviceAct, llvm::IntrusiveRefCntPtr< llvm::vfs::InMemoryFileSystem > VFS, llvm::Error &Err, std::list< PartialTranslationUnit > &PTUs)
CodeGenOptions & CodeGenOpts
~IncrementalDeviceParser() override
llvm::IntrusiveRefCntPtr< llvm::vfs::InMemoryFileSystem > VFS
const TargetOptions & TargetOpts
IncrementalHIPDeviceParser(CompilerInstance &DeviceInstance, CompilerInstance &HostInstance, IncrementalAction *DeviceAct, llvm::IntrusiveRefCntPtr< llvm::vfs::InMemoryFileSystem > VFS, llvm::Error &Err, std::list< PartialTranslationUnit > &PTUs)
~IncrementalHIPDeviceParser() override
llvm::Error GenerateOffloadBinary() override
IncrementalParser(CompilerInstance &Instance, IncrementalAction *Act, llvm::Error &Err, std::list< PartialTranslationUnit > &PTUs)
std::list< PartialTranslationUnit > & PTUs
std::string CPU
If given, the name of the target CPU to generate code for.
Top level wrappers for InstallAPI frontend operations.
void emitBackendOutput(CompilerInstance &CI, CodeGenOptions &CGOpts, llvm::Module *M, BackendAction Action, llvm::IntrusiveRefCntPtr< llvm::vfs::FileSystem > VFS, std::unique_ptr< raw_pwrite_stream > OS, BackendConsumer *BC=nullptr)
@ Backend_EmitObj
Emit native object files.
__builtin_bitreverse32 uint32_t __builtin_riscv_aaddu_u32 __builtin_riscv_asubu_u32 __builtin_elementwise_add_sat __builtin_elementwise_sub_sat int32_t uint32_t uint32_t __builtin_riscv_mhacc_i32 __builtin_riscv_mhaccu_u32 __builtin_riscv_mhaccsu_i32 __builtin_riscv_mulq_i32 __builtin_riscv_mqwacc_i64 __packed_splat4 uint16_t