clang 22.0.0git
CIRGenAtomic.cpp File Reference

Go to the source code of this file.

Functions

static Address emitValToTemp (CIRGenFunction &cgf, Expr *e)
static bool isFullSizeType (CIRGenModule &cgm, mlir::Type ty, uint64_t expectedSize)
 Does a store of the given IR type modify the full expected width?
static void emitAtomicCmpXchg (CIRGenFunction &cgf, AtomicExpr *e, bool isWeak, Address dest, Address ptr, Address val1, Address val2, uint64_t size, cir::MemOrder successOrder, cir::MemOrder failureOrder)
static void emitAtomicCmpXchgFailureSet (CIRGenFunction &cgf, AtomicExpr *e, bool isWeak, Address dest, Address ptr, Address val1, Address val2, Expr *failureOrderExpr, uint64_t size, cir::MemOrder successOrder)
static void emitAtomicOp (CIRGenFunction &cgf, AtomicExpr *expr, Address dest, Address ptr, Address val1, Address val2, Expr *isWeakExpr, Expr *failureOrderExpr, int64_t size, cir::MemOrder order)
static bool isMemOrderValid (uint64_t order, bool isStore, bool isLoad)

Function Documentation

◆ emitAtomicCmpXchg()

◆ emitAtomicCmpXchgFailureSet()

◆ emitAtomicOp()

◆ emitValToTemp()

◆ isFullSizeType()

bool isFullSizeType ( CIRGenModule & cgm,
mlir::Type ty,
uint64_t expectedSize )
static

Does a store of the given IR type modify the full expected width?

Definition at line 142 of file CIRGenAtomic.cpp.

References clang::CIRGen::CIRGenModule::getDataLayout(), and cir::CIRDataLayout::getTypeStoreSize().

◆ isMemOrderValid()

bool isMemOrderValid ( uint64_t order,
bool isStore,
bool isLoad )
static