clang  7.0.0svn
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "TargetInfo.h"
16 #include "ABIInfo.h"
17 #include "CGBlocks.h"
18 #include "CGCXXABI.h"
19 #include "CGValue.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
33 
34 using namespace clang;
35 using namespace CodeGen;
36 
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
41 //
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
47 //
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
52  ASTContext &Context,
53  llvm::LLVMContext &LLVMContext) {
54  // Alignment and Size are measured in bits.
55  const uint64_t Size = Context.getTypeSize(Ty);
56  const uint64_t Alignment = Context.getTypeAlign(Ty);
57  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
60 }
61 
63  llvm::Value *Array,
65  unsigned FirstIndex,
66  unsigned LastIndex) {
67  // Alternatively, we could emit this as a loop in the source.
68  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
69  llvm::Value *Cell =
70  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
72  }
73 }
74 
78 }
79 
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82  llvm::Type *Padding) const {
83  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84  ByRef, Realign, Padding);
85 }
86 
89  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90  /*ByRef*/ false, Realign);
91 }
92 
94  QualType Ty) const {
95  return Address::invalid();
96 }
97 
99 
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
102 ///
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
105 ///
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
114  ArrayRef<llvm::Type*> scalarTypes,
115  unsigned maxAllRegisters) {
116  unsigned intCount = 0, fpCount = 0;
117  for (llvm::Type *type : scalarTypes) {
118  if (type->isPointerTy()) {
119  intCount++;
120  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
123  } else {
124  assert(type->isVectorTy() || type->isFloatingPointTy());
125  fpCount++;
126  }
127  }
128 
129  return (intCount + fpCount > maxAllRegisters);
130 }
131 
133  llvm::Type *eltTy,
134  unsigned numElts) const {
135  // The default implementation of this assumes that the target guarantees
136  // 128-bit SIMD support but nothing more.
137  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
138 }
139 
141  CGCXXABI &CXXABI) {
142  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
143  if (!RD)
144  return CGCXXABI::RAA_Default;
145  return CXXABI.getRecordArgABI(RD);
146 }
147 
149  CGCXXABI &CXXABI) {
150  const RecordType *RT = T->getAs<RecordType>();
151  if (!RT)
152  return CGCXXABI::RAA_Default;
153  return getRecordArgABI(RT, CXXABI);
154 }
155 
156 /// Pass transparent unions as if they were the type of the first element. Sema
157 /// should ensure that all elements of the union have the same "machine type".
159  if (const RecordType *UT = Ty->getAsUnionType()) {
160  const RecordDecl *UD = UT->getDecl();
161  if (UD->hasAttr<TransparentUnionAttr>()) {
162  assert(!UD->field_empty() && "sema created an empty transparent union");
163  return UD->field_begin()->getType();
164  }
165  }
166  return Ty;
167 }
168 
170  return CGT.getCXXABI();
171 }
172 
174  return CGT.getContext();
175 }
176 
177 llvm::LLVMContext &ABIInfo::getVMContext() const {
178  return CGT.getLLVMContext();
179 }
180 
181 const llvm::DataLayout &ABIInfo::getDataLayout() const {
182  return CGT.getDataLayout();
183 }
184 
186  return CGT.getTarget();
187 }
188 
190  return CGT.getCodeGenOpts();
191 }
192 
193 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
194 
196  return false;
197 }
198 
200  uint64_t Members) const {
201  return false;
202 }
203 
204 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
205  raw_ostream &OS = llvm::errs();
206  OS << "(ABIArgInfo Kind=";
207  switch (TheKind) {
208  case Direct:
209  OS << "Direct Type=";
210  if (llvm::Type *Ty = getCoerceToType())
211  Ty->print(OS);
212  else
213  OS << "null";
214  break;
215  case Extend:
216  OS << "Extend";
217  break;
218  case Ignore:
219  OS << "Ignore";
220  break;
221  case InAlloca:
222  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
223  break;
224  case Indirect:
225  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
226  << " ByVal=" << getIndirectByVal()
227  << " Realign=" << getIndirectRealign();
228  break;
229  case Expand:
230  OS << "Expand";
231  break;
232  case CoerceAndExpand:
233  OS << "CoerceAndExpand Type=";
234  getCoerceAndExpandType()->print(OS);
235  break;
236  }
237  OS << ")\n";
238 }
239 
240 // Dynamically round a pointer up to a multiple of the given alignment.
242  llvm::Value *Ptr,
243  CharUnits Align) {
244  llvm::Value *PtrAsInt = Ptr;
245  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
246  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
247  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
248  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
249  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
250  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
251  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
252  Ptr->getType(),
253  Ptr->getName() + ".aligned");
254  return PtrAsInt;
255 }
256 
257 /// Emit va_arg for a platform using the common void* representation,
258 /// where arguments are simply emitted in an array of slots on the stack.
259 ///
260 /// This version implements the core direct-value passing rules.
261 ///
262 /// \param SlotSize - The size and alignment of a stack slot.
263 /// Each argument will be allocated to a multiple of this number of
264 /// slots, and all the slots will be aligned to this value.
265 /// \param AllowHigherAlign - The slot alignment is not a cap;
266 /// an argument type with an alignment greater than the slot size
267 /// will be emitted on a higher-alignment address, potentially
268 /// leaving one or more empty slots behind as padding. If this
269 /// is false, the returned address might be less-aligned than
270 /// DirectAlign.
272  Address VAListAddr,
273  llvm::Type *DirectTy,
274  CharUnits DirectSize,
275  CharUnits DirectAlign,
276  CharUnits SlotSize,
277  bool AllowHigherAlign) {
278  // Cast the element type to i8* if necessary. Some platforms define
279  // va_list as a struct containing an i8* instead of just an i8*.
280  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
281  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
282 
283  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
284 
285  // If the CC aligns values higher than the slot size, do so if needed.
286  Address Addr = Address::invalid();
287  if (AllowHigherAlign && DirectAlign > SlotSize) {
288  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
289  DirectAlign);
290  } else {
291  Addr = Address(Ptr, SlotSize);
292  }
293 
294  // Advance the pointer past the argument, then store that back.
295  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
296  llvm::Value *NextPtr =
297  CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
298  "argp.next");
299  CGF.Builder.CreateStore(NextPtr, VAListAddr);
300 
301  // If the argument is smaller than a slot, and this is a big-endian
302  // target, the argument will be right-adjusted in its slot.
303  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
304  !DirectTy->isStructTy()) {
305  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
306  }
307 
308  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
309  return Addr;
310 }
311 
312 /// Emit va_arg for a platform using the common void* representation,
313 /// where arguments are simply emitted in an array of slots on the stack.
314 ///
315 /// \param IsIndirect - Values of this type are passed indirectly.
316 /// \param ValueInfo - The size and alignment of this type, generally
317 /// computed with getContext().getTypeInfoInChars(ValueTy).
318 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
319 /// Each argument will be allocated to a multiple of this number of
320 /// slots, and all the slots will be aligned to this value.
321 /// \param AllowHigherAlign - The slot alignment is not a cap;
322 /// an argument type with an alignment greater than the slot size
323 /// will be emitted on a higher-alignment address, potentially
324 /// leaving one or more empty slots behind as padding.
326  QualType ValueTy, bool IsIndirect,
327  std::pair<CharUnits, CharUnits> ValueInfo,
328  CharUnits SlotSizeAndAlign,
329  bool AllowHigherAlign) {
330  // The size and alignment of the value that was passed directly.
331  CharUnits DirectSize, DirectAlign;
332  if (IsIndirect) {
333  DirectSize = CGF.getPointerSize();
334  DirectAlign = CGF.getPointerAlign();
335  } else {
336  DirectSize = ValueInfo.first;
337  DirectAlign = ValueInfo.second;
338  }
339 
340  // Cast the address we've calculated to the right type.
341  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
342  if (IsIndirect)
343  DirectTy = DirectTy->getPointerTo(0);
344 
345  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
346  DirectSize, DirectAlign,
347  SlotSizeAndAlign,
348  AllowHigherAlign);
349 
350  if (IsIndirect) {
351  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
352  }
353 
354  return Addr;
355 
356 }
357 
359  Address Addr1, llvm::BasicBlock *Block1,
360  Address Addr2, llvm::BasicBlock *Block2,
361  const llvm::Twine &Name = "") {
362  assert(Addr1.getType() == Addr2.getType());
363  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
364  PHI->addIncoming(Addr1.getPointer(), Block1);
365  PHI->addIncoming(Addr2.getPointer(), Block2);
366  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
367  return Address(PHI, Align);
368 }
369 
371 
372 // If someone can figure out a general rule for this, that would be great.
373 // It's probably just doomed to be platform-dependent, though.
375  // Verified for:
376  // x86-64 FreeBSD, Linux, Darwin
377  // x86-32 FreeBSD, Linux, Darwin
378  // PowerPC Linux, Darwin
379  // ARM Darwin (*not* EABI)
380  // AArch64 Linux
381  return 32;
382 }
383 
385  const FunctionNoProtoType *fnType) const {
386  // The following conventions are known to require this to be false:
387  // x86_stdcall
388  // MIPS
389  // For everything else, we just prefer false unless we opt out.
390  return false;
391 }
392 
393 void
395  llvm::SmallString<24> &Opt) const {
396  // This assumes the user is passing a library name like "rt" instead of a
397  // filename like "librt.a/so", and that they don't care whether it's static or
398  // dynamic.
399  Opt = "-l";
400  Opt += Lib;
401 }
402 
404  // OpenCL kernels are called via an explicit runtime API with arguments
405  // set with clSetKernelArg(), not as normal sub-functions.
406  // Return SPIR_KERNEL by default as the kernel calling convention to
407  // ensure the fingerprint is fixed such way that each OpenCL argument
408  // gets one matching argument in the produced kernel function argument
409  // list to enable feasible implementation of clSetKernelArg() with
410  // aggregates etc. In case we would use the default C calling conv here,
411  // clSetKernelArg() might break depending on the target-specific
412  // conventions; different targets might split structs passed as values
413  // to multiple function arguments etc.
414  return llvm::CallingConv::SPIR_KERNEL;
415 }
416 
418  llvm::PointerType *T, QualType QT) const {
419  return llvm::ConstantPointerNull::get(T);
420 }
421 
423  const VarDecl *D) const {
424  assert(!CGM.getLangOpts().OpenCL &&
425  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
426  "Address space agnostic languages only");
427  return D ? D->getType().getAddressSpace() : LangAS::Default;
428 }
429 
431  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
432  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
433  // Since target may map different address spaces in AST to the same address
434  // space, an address space conversion may end up as a bitcast.
435  if (auto *C = dyn_cast<llvm::Constant>(Src))
436  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
437  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
438 }
439 
440 llvm::Constant *
442  LangAS SrcAddr, LangAS DestAddr,
443  llvm::Type *DestTy) const {
444  // Since target may map different address spaces in AST to the same address
445  // space, an address space conversion may end up as a bitcast.
446  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
447 }
448 
450 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
451  return C.getOrInsertSyncScopeID(""); /* default sync scope */
452 }
453 
454 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
455 
456 /// isEmptyField - Return true iff a the field is "empty", that is it
457 /// is an unnamed bit-field or an (array of) empty record(s).
458 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
459  bool AllowArrays) {
460  if (FD->isUnnamedBitfield())
461  return true;
462 
463  QualType FT = FD->getType();
464 
465  // Constant arrays of empty records count as empty, strip them off.
466  // Constant arrays of zero length always count as empty.
467  if (AllowArrays)
468  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
469  if (AT->getSize() == 0)
470  return true;
471  FT = AT->getElementType();
472  }
473 
474  const RecordType *RT = FT->getAs<RecordType>();
475  if (!RT)
476  return false;
477 
478  // C++ record fields are never empty, at least in the Itanium ABI.
479  //
480  // FIXME: We should use a predicate for whether this behavior is true in the
481  // current ABI.
482  if (isa<CXXRecordDecl>(RT->getDecl()))
483  return false;
484 
485  return isEmptyRecord(Context, FT, AllowArrays);
486 }
487 
488 /// isEmptyRecord - Return true iff a structure contains only empty
489 /// fields. Note that a structure with a flexible array member is not
490 /// considered empty.
491 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
492  const RecordType *RT = T->getAs<RecordType>();
493  if (!RT)
494  return false;
495  const RecordDecl *RD = RT->getDecl();
496  if (RD->hasFlexibleArrayMember())
497  return false;
498 
499  // If this is a C++ record, check the bases first.
500  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
501  for (const auto &I : CXXRD->bases())
502  if (!isEmptyRecord(Context, I.getType(), true))
503  return false;
504 
505  for (const auto *I : RD->fields())
506  if (!isEmptyField(Context, I, AllowArrays))
507  return false;
508  return true;
509 }
510 
511 /// isSingleElementStruct - Determine if a structure is a "single
512 /// element struct", i.e. it has exactly one non-empty field or
513 /// exactly one field which is itself a single element
514 /// struct. Structures with flexible array members are never
515 /// considered single element structs.
516 ///
517 /// \return The field declaration for the single non-empty field, if
518 /// it exists.
519 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
520  const RecordType *RT = T->getAs<RecordType>();
521  if (!RT)
522  return nullptr;
523 
524  const RecordDecl *RD = RT->getDecl();
525  if (RD->hasFlexibleArrayMember())
526  return nullptr;
527 
528  const Type *Found = nullptr;
529 
530  // If this is a C++ record, check the bases first.
531  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
532  for (const auto &I : CXXRD->bases()) {
533  // Ignore empty records.
534  if (isEmptyRecord(Context, I.getType(), true))
535  continue;
536 
537  // If we already found an element then this isn't a single-element struct.
538  if (Found)
539  return nullptr;
540 
541  // If this is non-empty and not a single element struct, the composite
542  // cannot be a single element struct.
543  Found = isSingleElementStruct(I.getType(), Context);
544  if (!Found)
545  return nullptr;
546  }
547  }
548 
549  // Check for single element.
550  for (const auto *FD : RD->fields()) {
551  QualType FT = FD->getType();
552 
553  // Ignore empty fields.
554  if (isEmptyField(Context, FD, true))
555  continue;
556 
557  // If we already found an element then this isn't a single-element
558  // struct.
559  if (Found)
560  return nullptr;
561 
562  // Treat single element arrays as the element.
563  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
564  if (AT->getSize().getZExtValue() != 1)
565  break;
566  FT = AT->getElementType();
567  }
568 
569  if (!isAggregateTypeForABI(FT)) {
570  Found = FT.getTypePtr();
571  } else {
572  Found = isSingleElementStruct(FT, Context);
573  if (!Found)
574  return nullptr;
575  }
576  }
577 
578  // We don't consider a struct a single-element struct if it has
579  // padding beyond the element type.
580  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
581  return nullptr;
582 
583  return Found;
584 }
585 
586 namespace {
587 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
588  const ABIArgInfo &AI) {
589  // This default implementation defers to the llvm backend's va_arg
590  // instruction. It can handle only passing arguments directly
591  // (typically only handled in the backend for primitive types), or
592  // aggregates passed indirectly by pointer (NOTE: if the "byval"
593  // flag has ABI impact in the callee, this implementation cannot
594  // work.)
595 
596  // Only a few cases are covered here at the moment -- those needed
597  // by the default abi.
598  llvm::Value *Val;
599 
600  if (AI.isIndirect()) {
601  assert(!AI.getPaddingType() &&
602  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
603  assert(
604  !AI.getIndirectRealign() &&
605  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
606 
607  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
608  CharUnits TyAlignForABI = TyInfo.second;
609 
610  llvm::Type *BaseTy =
611  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
612  llvm::Value *Addr =
613  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
614  return Address(Addr, TyAlignForABI);
615  } else {
616  assert((AI.isDirect() || AI.isExtend()) &&
617  "Unexpected ArgInfo Kind in generic VAArg emitter!");
618 
619  assert(!AI.getInReg() &&
620  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
621  assert(!AI.getPaddingType() &&
622  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
623  assert(!AI.getDirectOffset() &&
624  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
625  assert(!AI.getCoerceToType() &&
626  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
627 
628  Address Temp = CGF.CreateMemTemp(Ty, "varet");
629  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
630  CGF.Builder.CreateStore(Val, Temp);
631  return Temp;
632  }
633 }
634 
635 /// DefaultABIInfo - The default implementation for ABI specific
636 /// details. This implementation provides information which results in
637 /// self-consistent and sensible LLVM IR generation, but does not
638 /// conform to any particular ABI.
639 class DefaultABIInfo : public ABIInfo {
640 public:
641  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
642 
645 
646  void computeInfo(CGFunctionInfo &FI) const override {
647  if (!getCXXABI().classifyReturnType(FI))
649  for (auto &I : FI.arguments())
650  I.info = classifyArgumentType(I.type);
651  }
652 
653  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
654  QualType Ty) const override {
655  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
656  }
657 };
658 
659 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
660 public:
661  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
662  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
663 };
664 
667 
668  if (isAggregateTypeForABI(Ty)) {
669  // Records with non-trivial destructors/copy-constructors should not be
670  // passed by value.
673 
674  return getNaturalAlignIndirect(Ty);
675  }
676 
677  // Treat an enum type as its underlying type.
678  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
679  Ty = EnumTy->getDecl()->getIntegerType();
680 
683 }
684 
686  if (RetTy->isVoidType())
687  return ABIArgInfo::getIgnore();
688 
689  if (isAggregateTypeForABI(RetTy))
690  return getNaturalAlignIndirect(RetTy);
691 
692  // Treat an enum type as its underlying type.
693  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
694  RetTy = EnumTy->getDecl()->getIntegerType();
695 
696  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
698 }
699 
700 //===----------------------------------------------------------------------===//
701 // WebAssembly ABI Implementation
702 //
703 // This is a very simple ABI that relies a lot on DefaultABIInfo.
704 //===----------------------------------------------------------------------===//
705 
706 class WebAssemblyABIInfo final : public DefaultABIInfo {
707 public:
708  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
709  : DefaultABIInfo(CGT) {}
710 
711 private:
714 
715  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
716  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
717  // overload them.
718  void computeInfo(CGFunctionInfo &FI) const override {
719  if (!getCXXABI().classifyReturnType(FI))
721  for (auto &Arg : FI.arguments())
722  Arg.info = classifyArgumentType(Arg.type);
723  }
724 
725  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
726  QualType Ty) const override;
727 };
728 
729 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
730 public:
731  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
732  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
733 };
734 
735 /// \brief Classify argument of given type \p Ty.
738 
739  if (isAggregateTypeForABI(Ty)) {
740  // Records with non-trivial destructors/copy-constructors should not be
741  // passed by value.
742  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
744  // Ignore empty structs/unions.
745  if (isEmptyRecord(getContext(), Ty, true))
746  return ABIArgInfo::getIgnore();
747  // Lower single-element structs to just pass a regular value. TODO: We
748  // could do reasonable-size multiple-element structs too, using getExpand(),
749  // though watch out for things like bitfields.
750  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
751  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
752  }
753 
754  // Otherwise just do the default thing.
756 }
757 
759  if (isAggregateTypeForABI(RetTy)) {
760  // Records with non-trivial destructors/copy-constructors should not be
761  // returned by value.
762  if (!getRecordArgABI(RetTy, getCXXABI())) {
763  // Ignore empty structs/unions.
764  if (isEmptyRecord(getContext(), RetTy, true))
765  return ABIArgInfo::getIgnore();
766  // Lower single-element structs to just return a regular value. TODO: We
767  // could do reasonable-size multiple-element structs too, using
768  // ABIArgInfo::getDirect().
769  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
770  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
771  }
772  }
773 
774  // Otherwise just do the default thing.
776 }
777 
778 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
779  QualType Ty) const {
780  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
781  getContext().getTypeInfoInChars(Ty),
783  /*AllowHigherAlign=*/ true);
784 }
785 
786 //===----------------------------------------------------------------------===//
787 // le32/PNaCl bitcode ABI Implementation
788 //
789 // This is a simplified version of the x86_32 ABI. Arguments and return values
790 // are always passed on the stack.
791 //===----------------------------------------------------------------------===//
792 
793 class PNaClABIInfo : public ABIInfo {
794  public:
795  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
796 
799 
800  void computeInfo(CGFunctionInfo &FI) const override;
802  Address VAListAddr, QualType Ty) const override;
803 };
804 
805 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
806  public:
807  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
808  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
809 };
810 
811 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
812  if (!getCXXABI().classifyReturnType(FI))
814 
815  for (auto &I : FI.arguments())
816  I.info = classifyArgumentType(I.type);
817 }
818 
819 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
820  QualType Ty) const {
821  // The PNaCL ABI is a bit odd, in that varargs don't use normal
822  // function classification. Structs get passed directly for varargs
823  // functions, through a rewriting transform in
824  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
825  // this target to actually support a va_arg instructions with an
826  // aggregate type, unlike other targets.
827  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
828 }
829 
830 /// \brief Classify argument of given type \p Ty.
832  if (isAggregateTypeForABI(Ty)) {
835  return getNaturalAlignIndirect(Ty);
836  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
837  // Treat an enum type as its underlying type.
838  Ty = EnumTy->getDecl()->getIntegerType();
839  } else if (Ty->isFloatingType()) {
840  // Floating-point types don't go inreg.
841  return ABIArgInfo::getDirect();
842  }
843 
846 }
847 
849  if (RetTy->isVoidType())
850  return ABIArgInfo::getIgnore();
851 
852  // In the PNaCl ABI we always return records/structures on the stack.
853  if (isAggregateTypeForABI(RetTy))
854  return getNaturalAlignIndirect(RetTy);
855 
856  // Treat an enum type as its underlying type.
857  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
858  RetTy = EnumTy->getDecl()->getIntegerType();
859 
860  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
862 }
863 
864 /// IsX86_MMXType - Return true if this is an MMX type.
865 bool IsX86_MMXType(llvm::Type *IRType) {
866  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
867  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
868  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
869  IRType->getScalarSizeInBits() != 64;
870 }
871 
872 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
873  StringRef Constraint,
874  llvm::Type* Ty) {
875  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
876  .Cases("y", "&y", "^Ym", true)
877  .Default(false);
878  if (IsMMXCons && Ty->isVectorTy()) {
879  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
880  // Invalid MMX constraint
881  return nullptr;
882  }
883 
884  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
885  }
886 
887  // No operation needed
888  return Ty;
889 }
890 
891 /// Returns true if this type can be passed in SSE registers with the
892 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
893 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
894  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
895  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
896  if (BT->getKind() == BuiltinType::LongDouble) {
897  if (&Context.getTargetInfo().getLongDoubleFormat() ==
898  &llvm::APFloat::x87DoubleExtended())
899  return false;
900  }
901  return true;
902  }
903  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
904  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
905  // registers specially.
906  unsigned VecSize = Context.getTypeSize(VT);
907  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
908  return true;
909  }
910  return false;
911 }
912 
913 /// Returns true if this aggregate is small enough to be passed in SSE registers
914 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
915 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
916  return NumMembers <= 4;
917 }
918 
919 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
920 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
921  auto AI = ABIArgInfo::getDirect(T);
922  AI.setInReg(true);
923  AI.setCanBeFlattened(false);
924  return AI;
925 }
926 
927 //===----------------------------------------------------------------------===//
928 // X86-32 ABI Implementation
929 //===----------------------------------------------------------------------===//
930 
931 /// \brief Similar to llvm::CCState, but for Clang.
932 struct CCState {
933  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
934 
935  unsigned CC;
936  unsigned FreeRegs;
937  unsigned FreeSSERegs;
938 };
939 
940 enum {
941  // Vectorcall only allows the first 6 parameters to be passed in registers.
942  VectorcallMaxParamNumAsReg = 6
943 };
944 
945 /// X86_32ABIInfo - The X86-32 ABI information.
946 class X86_32ABIInfo : public SwiftABIInfo {
947  enum Class {
948  Integer,
949  Float
950  };
951 
952  static const unsigned MinABIStackAlignInBytes = 4;
953 
954  bool IsDarwinVectorABI;
955  bool IsRetSmallStructInRegABI;
956  bool IsWin32StructABI;
957  bool IsSoftFloatABI;
958  bool IsMCUABI;
959  unsigned DefaultNumRegisterParameters;
960 
961  static bool isRegisterSize(unsigned Size) {
962  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
963  }
964 
965  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
966  // FIXME: Assumes vectorcall is in use.
967  return isX86VectorTypeForVectorCall(getContext(), Ty);
968  }
969 
971  uint64_t NumMembers) const override {
972  // FIXME: Assumes vectorcall is in use.
973  return isX86VectorCallAggregateSmallEnough(NumMembers);
974  }
975 
976  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
977 
978  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
979  /// such that the argument will be passed in memory.
980  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
981 
982  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
983 
984  /// \brief Return the alignment to use for the given type on the stack.
985  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
986 
987  Class classify(QualType Ty) const;
988  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
989  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
990 
991  /// \brief Updates the number of available free registers, returns
992  /// true if any registers were allocated.
993  bool updateFreeRegs(QualType Ty, CCState &State) const;
994 
995  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
996  bool &NeedsPadding) const;
997  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
998 
999  bool canExpandIndirectArgument(QualType Ty) const;
1000 
1001  /// \brief Rewrite the function info so that all memory arguments use
1002  /// inalloca.
1003  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1004 
1005  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1006  CharUnits &StackOffset, ABIArgInfo &Info,
1007  QualType Type) const;
1008  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1009  bool &UsedInAlloca) const;
1010 
1011 public:
1012 
1013  void computeInfo(CGFunctionInfo &FI) const override;
1014  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1015  QualType Ty) const override;
1016 
1017  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1018  bool RetSmallStructInRegABI, bool Win32StructABI,
1019  unsigned NumRegisterParameters, bool SoftFloatABI)
1020  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1021  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1022  IsWin32StructABI(Win32StructABI),
1023  IsSoftFloatABI(SoftFloatABI),
1024  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1025  DefaultNumRegisterParameters(NumRegisterParameters) {}
1026 
1027  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1028  bool asReturnValue) const override {
1029  // LLVM's x86-32 lowering currently only assigns up to three
1030  // integer registers and three fp registers. Oddly, it'll use up to
1031  // four vector registers for vectors, but those can overlap with the
1032  // scalar registers.
1033  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1034  }
1035 
1036  bool isSwiftErrorInRegister() const override {
1037  // x86-32 lowering does not support passing swifterror in a register.
1038  return false;
1039  }
1040 };
1041 
1042 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1043 public:
1044  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1045  bool RetSmallStructInRegABI, bool Win32StructABI,
1046  unsigned NumRegisterParameters, bool SoftFloatABI)
1047  : TargetCodeGenInfo(new X86_32ABIInfo(
1048  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1049  NumRegisterParameters, SoftFloatABI)) {}
1050 
1051  static bool isStructReturnInRegABI(
1052  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1053 
1054  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1055  CodeGen::CodeGenModule &CGM) const override;
1056 
1057  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1058  // Darwin uses different dwarf register numbers for EH.
1059  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1060  return 4;
1061  }
1062 
1063  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1064  llvm::Value *Address) const override;
1065 
1066  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1067  StringRef Constraint,
1068  llvm::Type* Ty) const override {
1069  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1070  }
1071 
1072  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1073  std::string &Constraints,
1074  std::vector<llvm::Type *> &ResultRegTypes,
1075  std::vector<llvm::Type *> &ResultTruncRegTypes,
1076  std::vector<LValue> &ResultRegDests,
1077  std::string &AsmString,
1078  unsigned NumOutputs) const override;
1079 
1080  llvm::Constant *
1081  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1082  unsigned Sig = (0xeb << 0) | // jmp rel8
1083  (0x06 << 8) | // .+0x08
1084  ('v' << 16) |
1085  ('2' << 24);
1086  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1087  }
1088 
1089  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1090  return "movl\t%ebp, %ebp"
1091  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1092  }
1093 };
1094 
1095 }
1096 
1097 /// Rewrite input constraint references after adding some output constraints.
1098 /// In the case where there is one output and one input and we add one output,
1099 /// we need to replace all operand references greater than or equal to 1:
1100 /// mov $0, $1
1101 /// mov eax, $1
1102 /// The result will be:
1103 /// mov $0, $2
1104 /// mov eax, $2
1105 static void rewriteInputConstraintReferences(unsigned FirstIn,
1106  unsigned NumNewOuts,
1107  std::string &AsmString) {
1108  std::string Buf;
1109  llvm::raw_string_ostream OS(Buf);
1110  size_t Pos = 0;
1111  while (Pos < AsmString.size()) {
1112  size_t DollarStart = AsmString.find('$', Pos);
1113  if (DollarStart == std::string::npos)
1114  DollarStart = AsmString.size();
1115  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1116  if (DollarEnd == std::string::npos)
1117  DollarEnd = AsmString.size();
1118  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1119  Pos = DollarEnd;
1120  size_t NumDollars = DollarEnd - DollarStart;
1121  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1122  // We have an operand reference.
1123  size_t DigitStart = Pos;
1124  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1125  if (DigitEnd == std::string::npos)
1126  DigitEnd = AsmString.size();
1127  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1128  unsigned OperandIndex;
1129  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1130  if (OperandIndex >= FirstIn)
1131  OperandIndex += NumNewOuts;
1132  OS << OperandIndex;
1133  } else {
1134  OS << OperandStr;
1135  }
1136  Pos = DigitEnd;
1137  }
1138  }
1139  AsmString = std::move(OS.str());
1140 }
1141 
1142 /// Add output constraints for EAX:EDX because they are return registers.
1143 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1144  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1145  std::vector<llvm::Type *> &ResultRegTypes,
1146  std::vector<llvm::Type *> &ResultTruncRegTypes,
1147  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1148  unsigned NumOutputs) const {
1149  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1150 
1151  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1152  // larger.
1153  if (!Constraints.empty())
1154  Constraints += ',';
1155  if (RetWidth <= 32) {
1156  Constraints += "={eax}";
1157  ResultRegTypes.push_back(CGF.Int32Ty);
1158  } else {
1159  // Use the 'A' constraint for EAX:EDX.
1160  Constraints += "=A";
1161  ResultRegTypes.push_back(CGF.Int64Ty);
1162  }
1163 
1164  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1165  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1166  ResultTruncRegTypes.push_back(CoerceTy);
1167 
1168  // Coerce the integer by bitcasting the return slot pointer.
1169  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1170  CoerceTy->getPointerTo()));
1171  ResultRegDests.push_back(ReturnSlot);
1172 
1173  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1174 }
1175 
1176 /// shouldReturnTypeInRegister - Determine if the given type should be
1177 /// returned in a register (for the Darwin and MCU ABI).
1178 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1179  ASTContext &Context) const {
1180  uint64_t Size = Context.getTypeSize(Ty);
1181 
1182  // For i386, type must be register sized.
1183  // For the MCU ABI, it only needs to be <= 8-byte
1184  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1185  return false;
1186 
1187  if (Ty->isVectorType()) {
1188  // 64- and 128- bit vectors inside structures are not returned in
1189  // registers.
1190  if (Size == 64 || Size == 128)
1191  return false;
1192 
1193  return true;
1194  }
1195 
1196  // If this is a builtin, pointer, enum, complex type, member pointer, or
1197  // member function pointer it is ok.
1198  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1199  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1200  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1201  return true;
1202 
1203  // Arrays are treated like records.
1204  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1205  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1206 
1207  // Otherwise, it must be a record type.
1208  const RecordType *RT = Ty->getAs<RecordType>();
1209  if (!RT) return false;
1210 
1211  // FIXME: Traverse bases here too.
1212 
1213  // Structure types are passed in register if all fields would be
1214  // passed in a register.
1215  for (const auto *FD : RT->getDecl()->fields()) {
1216  // Empty fields are ignored.
1217  if (isEmptyField(Context, FD, true))
1218  continue;
1219 
1220  // Check fields recursively.
1221  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1222  return false;
1223  }
1224  return true;
1225 }
1226 
1227 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1228  // Treat complex types as the element type.
1229  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1230  Ty = CTy->getElementType();
1231 
1232  // Check for a type which we know has a simple scalar argument-passing
1233  // convention without any padding. (We're specifically looking for 32
1234  // and 64-bit integer and integer-equivalents, float, and double.)
1235  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1236  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1237  return false;
1238 
1239  uint64_t Size = Context.getTypeSize(Ty);
1240  return Size == 32 || Size == 64;
1241 }
1242 
1243 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1244  uint64_t &Size) {
1245  for (const auto *FD : RD->fields()) {
1246  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1247  // argument is smaller than 32-bits, expanding the struct will create
1248  // alignment padding.
1249  if (!is32Or64BitBasicType(FD->getType(), Context))
1250  return false;
1251 
1252  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1253  // how to expand them yet, and the predicate for telling if a bitfield still
1254  // counts as "basic" is more complicated than what we were doing previously.
1255  if (FD->isBitField())
1256  return false;
1257 
1258  Size += Context.getTypeSize(FD->getType());
1259  }
1260  return true;
1261 }
1262 
1263 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1264  uint64_t &Size) {
1265  // Don't do this if there are any non-empty bases.
1266  for (const CXXBaseSpecifier &Base : RD->bases()) {
1267  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1268  Size))
1269  return false;
1270  }
1271  if (!addFieldSizes(Context, RD, Size))
1272  return false;
1273  return true;
1274 }
1275 
1276 /// Test whether an argument type which is to be passed indirectly (on the
1277 /// stack) would have the equivalent layout if it was expanded into separate
1278 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1279 /// optimizations.
1280 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1281  // We can only expand structure types.
1282  const RecordType *RT = Ty->getAs<RecordType>();
1283  if (!RT)
1284  return false;
1285  const RecordDecl *RD = RT->getDecl();
1286  uint64_t Size = 0;
1287  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1288  if (!IsWin32StructABI) {
1289  // On non-Windows, we have to conservatively match our old bitcode
1290  // prototypes in order to be ABI-compatible at the bitcode level.
1291  if (!CXXRD->isCLike())
1292  return false;
1293  } else {
1294  // Don't do this for dynamic classes.
1295  if (CXXRD->isDynamicClass())
1296  return false;
1297  }
1298  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1299  return false;
1300  } else {
1301  if (!addFieldSizes(getContext(), RD, Size))
1302  return false;
1303  }
1304 
1305  // We can do this if there was no alignment padding.
1306  return Size == getContext().getTypeSize(Ty);
1307 }
1308 
1309 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1310  // If the return value is indirect, then the hidden argument is consuming one
1311  // integer register.
1312  if (State.FreeRegs) {
1313  --State.FreeRegs;
1314  if (!IsMCUABI)
1315  return getNaturalAlignIndirectInReg(RetTy);
1316  }
1317  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1318 }
1319 
1321  CCState &State) const {
1322  if (RetTy->isVoidType())
1323  return ABIArgInfo::getIgnore();
1324 
1325  const Type *Base = nullptr;
1326  uint64_t NumElts = 0;
1327  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1328  State.CC == llvm::CallingConv::X86_RegCall) &&
1329  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1330  // The LLVM struct type for such an aggregate should lower properly.
1331  return ABIArgInfo::getDirect();
1332  }
1333 
1334  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1335  // On Darwin, some vectors are returned in registers.
1336  if (IsDarwinVectorABI) {
1337  uint64_t Size = getContext().getTypeSize(RetTy);
1338 
1339  // 128-bit vectors are a special case; they are returned in
1340  // registers and we need to make sure to pick a type the LLVM
1341  // backend will like.
1342  if (Size == 128)
1343  return ABIArgInfo::getDirect(llvm::VectorType::get(
1344  llvm::Type::getInt64Ty(getVMContext()), 2));
1345 
1346  // Always return in register if it fits in a general purpose
1347  // register, or if it is 64 bits and has a single element.
1348  if ((Size == 8 || Size == 16 || Size == 32) ||
1349  (Size == 64 && VT->getNumElements() == 1))
1350  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1351  Size));
1352 
1353  return getIndirectReturnResult(RetTy, State);
1354  }
1355 
1356  return ABIArgInfo::getDirect();
1357  }
1358 
1359  if (isAggregateTypeForABI(RetTy)) {
1360  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1361  // Structures with flexible arrays are always indirect.
1362  if (RT->getDecl()->hasFlexibleArrayMember())
1363  return getIndirectReturnResult(RetTy, State);
1364  }
1365 
1366  // If specified, structs and unions are always indirect.
1367  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1368  return getIndirectReturnResult(RetTy, State);
1369 
1370  // Ignore empty structs/unions.
1371  if (isEmptyRecord(getContext(), RetTy, true))
1372  return ABIArgInfo::getIgnore();
1373 
1374  // Small structures which are register sized are generally returned
1375  // in a register.
1376  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1377  uint64_t Size = getContext().getTypeSize(RetTy);
1378 
1379  // As a special-case, if the struct is a "single-element" struct, and
1380  // the field is of type "float" or "double", return it in a
1381  // floating-point register. (MSVC does not apply this special case.)
1382  // We apply a similar transformation for pointer types to improve the
1383  // quality of the generated IR.
1384  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1385  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1386  || SeltTy->hasPointerRepresentation())
1387  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1388 
1389  // FIXME: We should be able to narrow this integer in cases with dead
1390  // padding.
1391  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1392  }
1393 
1394  return getIndirectReturnResult(RetTy, State);
1395  }
1396 
1397  // Treat an enum type as its underlying type.
1398  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1399  RetTy = EnumTy->getDecl()->getIntegerType();
1400 
1401  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1402  : ABIArgInfo::getDirect());
1403 }
1404 
1405 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1406  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1407 }
1408 
1409 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1410  const RecordType *RT = Ty->getAs<RecordType>();
1411  if (!RT)
1412  return 0;
1413  const RecordDecl *RD = RT->getDecl();
1414 
1415  // If this is a C++ record, check the bases first.
1416  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1417  for (const auto &I : CXXRD->bases())
1418  if (!isRecordWithSSEVectorType(Context, I.getType()))
1419  return false;
1420 
1421  for (const auto *i : RD->fields()) {
1422  QualType FT = i->getType();
1423 
1424  if (isSSEVectorType(Context, FT))
1425  return true;
1426 
1427  if (isRecordWithSSEVectorType(Context, FT))
1428  return true;
1429  }
1430 
1431  return false;
1432 }
1433 
1434 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1435  unsigned Align) const {
1436  // Otherwise, if the alignment is less than or equal to the minimum ABI
1437  // alignment, just use the default; the backend will handle this.
1438  if (Align <= MinABIStackAlignInBytes)
1439  return 0; // Use default alignment.
1440 
1441  // On non-Darwin, the stack type alignment is always 4.
1442  if (!IsDarwinVectorABI) {
1443  // Set explicit alignment, since we may need to realign the top.
1444  return MinABIStackAlignInBytes;
1445  }
1446 
1447  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1448  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1450  return 16;
1451 
1452  return MinABIStackAlignInBytes;
1453 }
1454 
1455 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1456  CCState &State) const {
1457  if (!ByVal) {
1458  if (State.FreeRegs) {
1459  --State.FreeRegs; // Non-byval indirects just use one pointer.
1460  if (!IsMCUABI)
1461  return getNaturalAlignIndirectInReg(Ty);
1462  }
1463  return getNaturalAlignIndirect(Ty, false);
1464  }
1465 
1466  // Compute the byval alignment.
1467  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1468  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1469  if (StackAlign == 0)
1470  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1471 
1472  // If the stack alignment is less than the type alignment, realign the
1473  // argument.
1474  bool Realign = TypeAlign > StackAlign;
1476  /*ByVal=*/true, Realign);
1477 }
1478 
1479 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1480  const Type *T = isSingleElementStruct(Ty, getContext());
1481  if (!T)
1482  T = Ty.getTypePtr();
1483 
1484  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1485  BuiltinType::Kind K = BT->getKind();
1486  if (K == BuiltinType::Float || K == BuiltinType::Double)
1487  return Float;
1488  }
1489  return Integer;
1490 }
1491 
1492 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1493  if (!IsSoftFloatABI) {
1494  Class C = classify(Ty);
1495  if (C == Float)
1496  return false;
1497  }
1498 
1499  unsigned Size = getContext().getTypeSize(Ty);
1500  unsigned SizeInRegs = (Size + 31) / 32;
1501 
1502  if (SizeInRegs == 0)
1503  return false;
1504 
1505  if (!IsMCUABI) {
1506  if (SizeInRegs > State.FreeRegs) {
1507  State.FreeRegs = 0;
1508  return false;
1509  }
1510  } else {
1511  // The MCU psABI allows passing parameters in-reg even if there are
1512  // earlier parameters that are passed on the stack. Also,
1513  // it does not allow passing >8-byte structs in-register,
1514  // even if there are 3 free registers available.
1515  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1516  return false;
1517  }
1518 
1519  State.FreeRegs -= SizeInRegs;
1520  return true;
1521 }
1522 
1523 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1524  bool &InReg,
1525  bool &NeedsPadding) const {
1526  // On Windows, aggregates other than HFAs are never passed in registers, and
1527  // they do not consume register slots. Homogenous floating-point aggregates
1528  // (HFAs) have already been dealt with at this point.
1529  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1530  return false;
1531 
1532  NeedsPadding = false;
1533  InReg = !IsMCUABI;
1534 
1535  if (!updateFreeRegs(Ty, State))
1536  return false;
1537 
1538  if (IsMCUABI)
1539  return true;
1540 
1541  if (State.CC == llvm::CallingConv::X86_FastCall ||
1542  State.CC == llvm::CallingConv::X86_VectorCall ||
1543  State.CC == llvm::CallingConv::X86_RegCall) {
1544  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1545  NeedsPadding = true;
1546 
1547  return false;
1548  }
1549 
1550  return true;
1551 }
1552 
1553 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1554  if (!updateFreeRegs(Ty, State))
1555  return false;
1556 
1557  if (IsMCUABI)
1558  return false;
1559 
1560  if (State.CC == llvm::CallingConv::X86_FastCall ||
1561  State.CC == llvm::CallingConv::X86_VectorCall ||
1562  State.CC == llvm::CallingConv::X86_RegCall) {
1563  if (getContext().getTypeSize(Ty) > 32)
1564  return false;
1565 
1566  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1567  Ty->isReferenceType());
1568  }
1569 
1570  return true;
1571 }
1572 
1574  CCState &State) const {
1575  // FIXME: Set alignment on indirect arguments.
1576 
1578 
1579  // Check with the C++ ABI first.
1580  const RecordType *RT = Ty->getAs<RecordType>();
1581  if (RT) {
1583  if (RAA == CGCXXABI::RAA_Indirect) {
1584  return getIndirectResult(Ty, false, State);
1585  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1586  // The field index doesn't matter, we'll fix it up later.
1587  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1588  }
1589  }
1590 
1591  // Regcall uses the concept of a homogenous vector aggregate, similar
1592  // to other targets.
1593  const Type *Base = nullptr;
1594  uint64_t NumElts = 0;
1595  if (State.CC == llvm::CallingConv::X86_RegCall &&
1596  isHomogeneousAggregate(Ty, Base, NumElts)) {
1597 
1598  if (State.FreeSSERegs >= NumElts) {
1599  State.FreeSSERegs -= NumElts;
1600  if (Ty->isBuiltinType() || Ty->isVectorType())
1601  return ABIArgInfo::getDirect();
1602  return ABIArgInfo::getExpand();
1603  }
1604  return getIndirectResult(Ty, /*ByVal=*/false, State);
1605  }
1606 
1607  if (isAggregateTypeForABI(Ty)) {
1608  // Structures with flexible arrays are always indirect.
1609  // FIXME: This should not be byval!
1610  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1611  return getIndirectResult(Ty, true, State);
1612 
1613  // Ignore empty structs/unions on non-Windows.
1614  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1615  return ABIArgInfo::getIgnore();
1616 
1617  llvm::LLVMContext &LLVMContext = getVMContext();
1618  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1619  bool NeedsPadding = false;
1620  bool InReg;
1621  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1622  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1623  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1624  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1625  if (InReg)
1626  return ABIArgInfo::getDirectInReg(Result);
1627  else
1628  return ABIArgInfo::getDirect(Result);
1629  }
1630  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1631 
1632  // Expand small (<= 128-bit) record types when we know that the stack layout
1633  // of those arguments will match the struct. This is important because the
1634  // LLVM backend isn't smart enough to remove byval, which inhibits many
1635  // optimizations.
1636  // Don't do this for the MCU if there are still free integer registers
1637  // (see X86_64 ABI for full explanation).
1638  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1639  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1641  State.CC == llvm::CallingConv::X86_FastCall ||
1642  State.CC == llvm::CallingConv::X86_VectorCall ||
1643  State.CC == llvm::CallingConv::X86_RegCall,
1644  PaddingType);
1645 
1646  return getIndirectResult(Ty, true, State);
1647  }
1648 
1649  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1650  // On Darwin, some vectors are passed in memory, we handle this by passing
1651  // it as an i8/i16/i32/i64.
1652  if (IsDarwinVectorABI) {
1653  uint64_t Size = getContext().getTypeSize(Ty);
1654  if ((Size == 8 || Size == 16 || Size == 32) ||
1655  (Size == 64 && VT->getNumElements() == 1))
1656  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1657  Size));
1658  }
1659 
1660  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1661  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1662 
1663  return ABIArgInfo::getDirect();
1664  }
1665 
1666 
1667  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1668  Ty = EnumTy->getDecl()->getIntegerType();
1669 
1670  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1671 
1672  if (Ty->isPromotableIntegerType()) {
1673  if (InReg)
1674  return ABIArgInfo::getExtendInReg(Ty);
1675  return ABIArgInfo::getExtend(Ty);
1676  }
1677 
1678  if (InReg)
1679  return ABIArgInfo::getDirectInReg();
1680  return ABIArgInfo::getDirect();
1681 }
1682 
1683 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1684  bool &UsedInAlloca) const {
1685  // Vectorcall x86 works subtly different than in x64, so the format is
1686  // a bit different than the x64 version. First, all vector types (not HVAs)
1687  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1688  // This differs from the x64 implementation, where the first 6 by INDEX get
1689  // registers.
1690  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1691  // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1692  // first take up the remaining YMM/XMM registers. If insufficient registers
1693  // remain but an integer register (ECX/EDX) is available, it will be passed
1694  // in that, else, on the stack.
1695  for (auto &I : FI.arguments()) {
1696  // First pass do all the vector types.
1697  const Type *Base = nullptr;
1698  uint64_t NumElts = 0;
1699  const QualType& Ty = I.type;
1700  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1701  isHomogeneousAggregate(Ty, Base, NumElts)) {
1702  if (State.FreeSSERegs >= NumElts) {
1703  State.FreeSSERegs -= NumElts;
1704  I.info = ABIArgInfo::getDirect();
1705  } else {
1706  I.info = classifyArgumentType(Ty, State);
1707  }
1708  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1709  }
1710  }
1711 
1712  for (auto &I : FI.arguments()) {
1713  // Second pass, do the rest!
1714  const Type *Base = nullptr;
1715  uint64_t NumElts = 0;
1716  const QualType& Ty = I.type;
1717  bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1718 
1719  if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1720  // Assign true HVAs (non vector/native FP types).
1721  if (State.FreeSSERegs >= NumElts) {
1722  State.FreeSSERegs -= NumElts;
1723  I.info = getDirectX86Hva();
1724  } else {
1725  I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1726  }
1727  } else if (!IsHva) {
1728  // Assign all Non-HVAs, so this will exclude Vector/FP args.
1729  I.info = classifyArgumentType(Ty, State);
1730  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1731  }
1732  }
1733 }
1734 
1735 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1736  CCState State(FI.getCallingConvention());
1737  if (IsMCUABI)
1738  State.FreeRegs = 3;
1739  else if (State.CC == llvm::CallingConv::X86_FastCall)
1740  State.FreeRegs = 2;
1741  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1742  State.FreeRegs = 2;
1743  State.FreeSSERegs = 6;
1744  } else if (FI.getHasRegParm())
1745  State.FreeRegs = FI.getRegParm();
1746  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1747  State.FreeRegs = 5;
1748  State.FreeSSERegs = 8;
1749  } else
1750  State.FreeRegs = DefaultNumRegisterParameters;
1751 
1752  if (!getCXXABI().classifyReturnType(FI)) {
1754  } else if (FI.getReturnInfo().isIndirect()) {
1755  // The C++ ABI is not aware of register usage, so we have to check if the
1756  // return value was sret and put it in a register ourselves if appropriate.
1757  if (State.FreeRegs) {
1758  --State.FreeRegs; // The sret parameter consumes a register.
1759  if (!IsMCUABI)
1760  FI.getReturnInfo().setInReg(true);
1761  }
1762  }
1763 
1764  // The chain argument effectively gives us another free register.
1765  if (FI.isChainCall())
1766  ++State.FreeRegs;
1767 
1768  bool UsedInAlloca = false;
1769  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1770  computeVectorCallArgs(FI, State, UsedInAlloca);
1771  } else {
1772  // If not vectorcall, revert to normal behavior.
1773  for (auto &I : FI.arguments()) {
1774  I.info = classifyArgumentType(I.type, State);
1775  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1776  }
1777  }
1778 
1779  // If we needed to use inalloca for any argument, do a second pass and rewrite
1780  // all the memory arguments to use inalloca.
1781  if (UsedInAlloca)
1782  rewriteWithInAlloca(FI);
1783 }
1784 
1785 void
1786 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1787  CharUnits &StackOffset, ABIArgInfo &Info,
1788  QualType Type) const {
1789  // Arguments are always 4-byte-aligned.
1790  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1791 
1792  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1793  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1794  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1795  StackOffset += getContext().getTypeSizeInChars(Type);
1796 
1797  // Insert padding bytes to respect alignment.
1798  CharUnits FieldEnd = StackOffset;
1799  StackOffset = FieldEnd.alignTo(FieldAlign);
1800  if (StackOffset != FieldEnd) {
1801  CharUnits NumBytes = StackOffset - FieldEnd;
1802  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1803  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1804  FrameFields.push_back(Ty);
1805  }
1806 }
1807 
1808 static bool isArgInAlloca(const ABIArgInfo &Info) {
1809  // Leave ignored and inreg arguments alone.
1810  switch (Info.getKind()) {
1811  case ABIArgInfo::InAlloca:
1812  return true;
1813  case ABIArgInfo::Indirect:
1814  assert(Info.getIndirectByVal());
1815  return true;
1816  case ABIArgInfo::Ignore:
1817  return false;
1818  case ABIArgInfo::Direct:
1819  case ABIArgInfo::Extend:
1820  if (Info.getInReg())
1821  return false;
1822  return true;
1823  case ABIArgInfo::Expand:
1825  // These are aggregate types which are never passed in registers when
1826  // inalloca is involved.
1827  return true;
1828  }
1829  llvm_unreachable("invalid enum");
1830 }
1831 
1832 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1833  assert(IsWin32StructABI && "inalloca only supported on win32");
1834 
1835  // Build a packed struct type for all of the arguments in memory.
1836  SmallVector<llvm::Type *, 6> FrameFields;
1837 
1838  // The stack alignment is always 4.
1839  CharUnits StackAlign = CharUnits::fromQuantity(4);
1840 
1841  CharUnits StackOffset;
1842  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1843 
1844  // Put 'this' into the struct before 'sret', if necessary.
1845  bool IsThisCall =
1846  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1847  ABIArgInfo &Ret = FI.getReturnInfo();
1848  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1849  isArgInAlloca(I->info)) {
1850  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1851  ++I;
1852  }
1853 
1854  // Put the sret parameter into the inalloca struct if it's in memory.
1855  if (Ret.isIndirect() && !Ret.getInReg()) {
1857  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1858  // On Windows, the hidden sret parameter is always returned in eax.
1859  Ret.setInAllocaSRet(IsWin32StructABI);
1860  }
1861 
1862  // Skip the 'this' parameter in ecx.
1863  if (IsThisCall)
1864  ++I;
1865 
1866  // Put arguments passed in memory into the struct.
1867  for (; I != E; ++I) {
1868  if (isArgInAlloca(I->info))
1869  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1870  }
1871 
1872  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1873  /*isPacked=*/true),
1874  StackAlign);
1875 }
1876 
1877 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1878  Address VAListAddr, QualType Ty) const {
1879 
1880  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1881 
1882  // x86-32 changes the alignment of certain arguments on the stack.
1883  //
1884  // Just messing with TypeInfo like this works because we never pass
1885  // anything indirectly.
1887  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1888 
1889  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1891  /*AllowHigherAlign*/ true);
1892 }
1893 
1894 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1895  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1896  assert(Triple.getArch() == llvm::Triple::x86);
1897 
1898  switch (Opts.getStructReturnConvention()) {
1900  break;
1901  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1902  return false;
1903  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1904  return true;
1905  }
1906 
1907  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1908  return true;
1909 
1910  switch (Triple.getOS()) {
1911  case llvm::Triple::DragonFly:
1912  case llvm::Triple::FreeBSD:
1913  case llvm::Triple::OpenBSD:
1914  case llvm::Triple::Win32:
1915  return true;
1916  default:
1917  return false;
1918  }
1919 }
1920 
1921 void X86_32TargetCodeGenInfo::setTargetAttributes(
1922  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1923  if (GV->isDeclaration())
1924  return;
1925  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1926  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1927  // Get the LLVM function.
1928  llvm::Function *Fn = cast<llvm::Function>(GV);
1929 
1930  // Now add the 'alignstack' attribute with a value of 16.
1931  llvm::AttrBuilder B;
1932  B.addStackAlignmentAttr(16);
1933  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
1934  }
1935  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1936  llvm::Function *Fn = cast<llvm::Function>(GV);
1937  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1938  }
1939  }
1940 }
1941 
1942 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1944  llvm::Value *Address) const {
1945  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1946 
1947  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1948 
1949  // 0-7 are the eight integer registers; the order is different
1950  // on Darwin (for EH), but the range is the same.
1951  // 8 is %eip.
1952  AssignToArrayRange(Builder, Address, Four8, 0, 8);
1953 
1954  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1955  // 12-16 are st(0..4). Not sure why we stop at 4.
1956  // These have size 16, which is sizeof(long double) on
1957  // platforms with 8-byte alignment for that type.
1958  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1959  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1960 
1961  } else {
1962  // 9 is %eflags, which doesn't get a size on Darwin for some
1963  // reason.
1964  Builder.CreateAlignedStore(
1965  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1966  CharUnits::One());
1967 
1968  // 11-16 are st(0..5). Not sure why we stop at 5.
1969  // These have size 12, which is sizeof(long double) on
1970  // platforms with 4-byte alignment for that type.
1971  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1972  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1973  }
1974 
1975  return false;
1976 }
1977 
1978 //===----------------------------------------------------------------------===//
1979 // X86-64 ABI Implementation
1980 //===----------------------------------------------------------------------===//
1981 
1982 
1983 namespace {
1984 /// The AVX ABI level for X86 targets.
1985 enum class X86AVXABILevel {
1986  None,
1987  AVX,
1988  AVX512
1989 };
1990 
1991 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1992 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1993  switch (AVXLevel) {
1994  case X86AVXABILevel::AVX512:
1995  return 512;
1996  case X86AVXABILevel::AVX:
1997  return 256;
1998  case X86AVXABILevel::None:
1999  return 128;
2000  }
2001  llvm_unreachable("Unknown AVXLevel");
2002 }
2003 
2004 /// X86_64ABIInfo - The X86_64 ABI information.
2005 class X86_64ABIInfo : public SwiftABIInfo {
2006  enum Class {
2007  Integer = 0,
2008  SSE,
2009  SSEUp,
2010  X87,
2011  X87Up,
2012  ComplexX87,
2013  NoClass,
2014  Memory
2015  };
2016 
2017  /// merge - Implement the X86_64 ABI merging algorithm.
2018  ///
2019  /// Merge an accumulating classification \arg Accum with a field
2020  /// classification \arg Field.
2021  ///
2022  /// \param Accum - The accumulating classification. This should
2023  /// always be either NoClass or the result of a previous merge
2024  /// call. In addition, this should never be Memory (the caller
2025  /// should just return Memory for the aggregate).
2026  static Class merge(Class Accum, Class Field);
2027 
2028  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2029  ///
2030  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2031  /// final MEMORY or SSE classes when necessary.
2032  ///
2033  /// \param AggregateSize - The size of the current aggregate in
2034  /// the classification process.
2035  ///
2036  /// \param Lo - The classification for the parts of the type
2037  /// residing in the low word of the containing object.
2038  ///
2039  /// \param Hi - The classification for the parts of the type
2040  /// residing in the higher words of the containing object.
2041  ///
2042  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2043 
2044  /// classify - Determine the x86_64 register classes in which the
2045  /// given type T should be passed.
2046  ///
2047  /// \param Lo - The classification for the parts of the type
2048  /// residing in the low word of the containing object.
2049  ///
2050  /// \param Hi - The classification for the parts of the type
2051  /// residing in the high word of the containing object.
2052  ///
2053  /// \param OffsetBase - The bit offset of this type in the
2054  /// containing object. Some parameters are classified different
2055  /// depending on whether they straddle an eightbyte boundary.
2056  ///
2057  /// \param isNamedArg - Whether the argument in question is a "named"
2058  /// argument, as used in AMD64-ABI 3.5.7.
2059  ///
2060  /// If a word is unused its result will be NoClass; if a type should
2061  /// be passed in Memory then at least the classification of \arg Lo
2062  /// will be Memory.
2063  ///
2064  /// The \arg Lo class will be NoClass iff the argument is ignored.
2065  ///
2066  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2067  /// also be ComplexX87.
2068  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2069  bool isNamedArg) const;
2070 
2071  llvm::Type *GetByteVectorType(QualType Ty) const;
2072  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2073  unsigned IROffset, QualType SourceTy,
2074  unsigned SourceOffset) const;
2075  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2076  unsigned IROffset, QualType SourceTy,
2077  unsigned SourceOffset) const;
2078 
2079  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2080  /// such that the argument will be returned in memory.
2081  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2082 
2083  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2084  /// such that the argument will be passed in memory.
2085  ///
2086  /// \param freeIntRegs - The number of free integer registers remaining
2087  /// available.
2088  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2089 
2090  ABIArgInfo classifyReturnType(QualType RetTy) const;
2091 
2092  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2093  unsigned &neededInt, unsigned &neededSSE,
2094  bool isNamedArg) const;
2095 
2096  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2097  unsigned &NeededSSE) const;
2098 
2099  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2100  unsigned &NeededSSE) const;
2101 
2102  bool IsIllegalVectorType(QualType Ty) const;
2103 
2104  /// The 0.98 ABI revision clarified a lot of ambiguities,
2105  /// unfortunately in ways that were not always consistent with
2106  /// certain previous compilers. In particular, platforms which
2107  /// required strict binary compatibility with older versions of GCC
2108  /// may need to exempt themselves.
2109  bool honorsRevision0_98() const {
2110  return !getTarget().getTriple().isOSDarwin();
2111  }
2112 
2113  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2114  /// classify it as INTEGER (for compatibility with older clang compilers).
2115  bool classifyIntegerMMXAsSSE() const {
2116  // Clang <= 3.8 did not do this.
2117  if (getCodeGenOpts().getClangABICompat() <=
2119  return false;
2120 
2121  const llvm::Triple &Triple = getTarget().getTriple();
2122  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2123  return false;
2124  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2125  return false;
2126  return true;
2127  }
2128 
2129  X86AVXABILevel AVXLevel;
2130  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2131  // 64-bit hardware.
2132  bool Has64BitPointers;
2133 
2134 public:
2135  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2136  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2137  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2138  }
2139 
2140  bool isPassedUsingAVXType(QualType type) const {
2141  unsigned neededInt, neededSSE;
2142  // The freeIntRegs argument doesn't matter here.
2143  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2144  /*isNamedArg*/true);
2145  if (info.isDirect()) {
2146  llvm::Type *ty = info.getCoerceToType();
2147  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2148  return (vectorTy->getBitWidth() > 128);
2149  }
2150  return false;
2151  }
2152 
2153  void computeInfo(CGFunctionInfo &FI) const override;
2154 
2155  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2156  QualType Ty) const override;
2157  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2158  QualType Ty) const override;
2159 
2160  bool has64BitPointers() const {
2161  return Has64BitPointers;
2162  }
2163 
2164  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2165  bool asReturnValue) const override {
2166  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2167  }
2168  bool isSwiftErrorInRegister() const override {
2169  return true;
2170  }
2171 };
2172 
2173 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2174 class WinX86_64ABIInfo : public SwiftABIInfo {
2175 public:
2176  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2177  : SwiftABIInfo(CGT),
2178  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2179 
2180  void computeInfo(CGFunctionInfo &FI) const override;
2181 
2182  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2183  QualType Ty) const override;
2184 
2185  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2186  // FIXME: Assumes vectorcall is in use.
2187  return isX86VectorTypeForVectorCall(getContext(), Ty);
2188  }
2189 
2190  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2191  uint64_t NumMembers) const override {
2192  // FIXME: Assumes vectorcall is in use.
2193  return isX86VectorCallAggregateSmallEnough(NumMembers);
2194  }
2195 
2196  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2197  bool asReturnValue) const override {
2198  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2199  }
2200 
2201  bool isSwiftErrorInRegister() const override {
2202  return true;
2203  }
2204 
2205 private:
2206  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2207  bool IsVectorCall, bool IsRegCall) const;
2208  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2209  const ABIArgInfo &current) const;
2210  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2211  bool IsVectorCall, bool IsRegCall) const;
2212 
2213  bool IsMingw64;
2214 };
2215 
2216 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2217 public:
2218  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2219  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2220 
2221  const X86_64ABIInfo &getABIInfo() const {
2222  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2223  }
2224 
2225  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2226  return 7;
2227  }
2228 
2229  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2230  llvm::Value *Address) const override {
2231  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2232 
2233  // 0-15 are the 16 integer registers.
2234  // 16 is %rip.
2235  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2236  return false;
2237  }
2238 
2239  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2240  StringRef Constraint,
2241  llvm::Type* Ty) const override {
2242  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2243  }
2244 
2245  bool isNoProtoCallVariadic(const CallArgList &args,
2246  const FunctionNoProtoType *fnType) const override {
2247  // The default CC on x86-64 sets %al to the number of SSA
2248  // registers used, and GCC sets this when calling an unprototyped
2249  // function, so we override the default behavior. However, don't do
2250  // that when AVX types are involved: the ABI explicitly states it is
2251  // undefined, and it doesn't work in practice because of how the ABI
2252  // defines varargs anyway.
2253  if (fnType->getCallConv() == CC_C) {
2254  bool HasAVXType = false;
2255  for (CallArgList::const_iterator
2256  it = args.begin(), ie = args.end(); it != ie; ++it) {
2257  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2258  HasAVXType = true;
2259  break;
2260  }
2261  }
2262 
2263  if (!HasAVXType)
2264  return true;
2265  }
2266 
2267  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2268  }
2269 
2270  llvm::Constant *
2271  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2272  unsigned Sig = (0xeb << 0) | // jmp rel8
2273  (0x06 << 8) | // .+0x08
2274  ('v' << 16) |
2275  ('2' << 24);
2276  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2277  }
2278 
2279  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2280  CodeGen::CodeGenModule &CGM) const override {
2281  if (GV->isDeclaration())
2282  return;
2283  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2284  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2285  // Get the LLVM function.
2286  auto *Fn = cast<llvm::Function>(GV);
2287 
2288  // Now add the 'alignstack' attribute with a value of 16.
2289  llvm::AttrBuilder B;
2290  B.addStackAlignmentAttr(16);
2291  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
2292  }
2293  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2294  llvm::Function *Fn = cast<llvm::Function>(GV);
2295  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2296  }
2297  }
2298  }
2299 };
2300 
2301 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2302 public:
2303  PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2304  : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2305 
2306  void getDependentLibraryOption(llvm::StringRef Lib,
2307  llvm::SmallString<24> &Opt) const override {
2308  Opt = "\01";
2309  // If the argument contains a space, enclose it in quotes.
2310  if (Lib.find(" ") != StringRef::npos)
2311  Opt += "\"" + Lib.str() + "\"";
2312  else
2313  Opt += Lib;
2314  }
2315 };
2316 
2317 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2318  // If the argument does not end in .lib, automatically add the suffix.
2319  // If the argument contains a space, enclose it in quotes.
2320  // This matches the behavior of MSVC.
2321  bool Quote = (Lib.find(" ") != StringRef::npos);
2322  std::string ArgStr = Quote ? "\"" : "";
2323  ArgStr += Lib;
2324  if (!Lib.endswith_lower(".lib"))
2325  ArgStr += ".lib";
2326  ArgStr += Quote ? "\"" : "";
2327  return ArgStr;
2328 }
2329 
2330 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2331 public:
2332  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2333  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2334  unsigned NumRegisterParameters)
2335  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2336  Win32StructABI, NumRegisterParameters, false) {}
2337 
2338  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2339  CodeGen::CodeGenModule &CGM) const override;
2340 
2341  void getDependentLibraryOption(llvm::StringRef Lib,
2342  llvm::SmallString<24> &Opt) const override {
2343  Opt = "/DEFAULTLIB:";
2344  Opt += qualifyWindowsLibrary(Lib);
2345  }
2346 
2347  void getDetectMismatchOption(llvm::StringRef Name,
2348  llvm::StringRef Value,
2349  llvm::SmallString<32> &Opt) const override {
2350  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2351  }
2352 };
2353 
2354 static void addStackProbeSizeTargetAttribute(const Decl *D,
2355  llvm::GlobalValue *GV,
2356  CodeGen::CodeGenModule &CGM) {
2357  if (D && isa<FunctionDecl>(D)) {
2358  if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2359  llvm::Function *Fn = cast<llvm::Function>(GV);
2360 
2361  Fn->addFnAttr("stack-probe-size",
2362  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2363  }
2364  }
2365 }
2366 
2367 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2368  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2369  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2370  if (GV->isDeclaration())
2371  return;
2372  addStackProbeSizeTargetAttribute(D, GV, CGM);
2373 }
2374 
2375 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2376 public:
2377  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2378  X86AVXABILevel AVXLevel)
2379  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2380 
2381  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2382  CodeGen::CodeGenModule &CGM) const override;
2383 
2384  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2385  return 7;
2386  }
2387 
2388  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2389  llvm::Value *Address) const override {
2390  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2391 
2392  // 0-15 are the 16 integer registers.
2393  // 16 is %rip.
2394  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2395  return false;
2396  }
2397 
2398  void getDependentLibraryOption(llvm::StringRef Lib,
2399  llvm::SmallString<24> &Opt) const override {
2400  Opt = "/DEFAULTLIB:";
2401  Opt += qualifyWindowsLibrary(Lib);
2402  }
2403 
2404  void getDetectMismatchOption(llvm::StringRef Name,
2405  llvm::StringRef Value,
2406  llvm::SmallString<32> &Opt) const override {
2407  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2408  }
2409 };
2410 
2411 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2412  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2414  if (GV->isDeclaration())
2415  return;
2416  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2417  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2418  // Get the LLVM function.
2419  auto *Fn = cast<llvm::Function>(GV);
2420 
2421  // Now add the 'alignstack' attribute with a value of 16.
2422  llvm::AttrBuilder B;
2423  B.addStackAlignmentAttr(16);
2424  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
2425  }
2426  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2427  llvm::Function *Fn = cast<llvm::Function>(GV);
2428  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2429  }
2430  }
2431 
2432  addStackProbeSizeTargetAttribute(D, GV, CGM);
2433 }
2434 }
2435 
2436 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2437  Class &Hi) const {
2438  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2439  //
2440  // (a) If one of the classes is Memory, the whole argument is passed in
2441  // memory.
2442  //
2443  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2444  // memory.
2445  //
2446  // (c) If the size of the aggregate exceeds two eightbytes and the first
2447  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2448  // argument is passed in memory. NOTE: This is necessary to keep the
2449  // ABI working for processors that don't support the __m256 type.
2450  //
2451  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2452  //
2453  // Some of these are enforced by the merging logic. Others can arise
2454  // only with unions; for example:
2455  // union { _Complex double; unsigned; }
2456  //
2457  // Note that clauses (b) and (c) were added in 0.98.
2458  //
2459  if (Hi == Memory)
2460  Lo = Memory;
2461  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2462  Lo = Memory;
2463  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2464  Lo = Memory;
2465  if (Hi == SSEUp && Lo != SSE)
2466  Hi = SSE;
2467 }
2468 
2469 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2470  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2471  // classified recursively so that always two fields are
2472  // considered. The resulting class is calculated according to
2473  // the classes of the fields in the eightbyte:
2474  //
2475  // (a) If both classes are equal, this is the resulting class.
2476  //
2477  // (b) If one of the classes is NO_CLASS, the resulting class is
2478  // the other class.
2479  //
2480  // (c) If one of the classes is MEMORY, the result is the MEMORY
2481  // class.
2482  //
2483  // (d) If one of the classes is INTEGER, the result is the
2484  // INTEGER.
2485  //
2486  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2487  // MEMORY is used as class.
2488  //
2489  // (f) Otherwise class SSE is used.
2490 
2491  // Accum should never be memory (we should have returned) or
2492  // ComplexX87 (because this cannot be passed in a structure).
2493  assert((Accum != Memory && Accum != ComplexX87) &&
2494  "Invalid accumulated classification during merge.");
2495  if (Accum == Field || Field == NoClass)
2496  return Accum;
2497  if (Field == Memory)
2498  return Memory;
2499  if (Accum == NoClass)
2500  return Field;
2501  if (Accum == Integer || Field == Integer)
2502  return Integer;
2503  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2504  Accum == X87 || Accum == X87Up)
2505  return Memory;
2506  return SSE;
2507 }
2508 
2509 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2510  Class &Lo, Class &Hi, bool isNamedArg) const {
2511  // FIXME: This code can be simplified by introducing a simple value class for
2512  // Class pairs with appropriate constructor methods for the various
2513  // situations.
2514 
2515  // FIXME: Some of the split computations are wrong; unaligned vectors
2516  // shouldn't be passed in registers for example, so there is no chance they
2517  // can straddle an eightbyte. Verify & simplify.
2518 
2519  Lo = Hi = NoClass;
2520 
2521  Class &Current = OffsetBase < 64 ? Lo : Hi;
2522  Current = Memory;
2523 
2524  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2525  BuiltinType::Kind k = BT->getKind();
2526 
2527  if (k == BuiltinType::Void) {
2528  Current = NoClass;
2529  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2530  Lo = Integer;
2531  Hi = Integer;
2532  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2533  Current = Integer;
2534  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2535  Current = SSE;
2536  } else if (k == BuiltinType::LongDouble) {
2537  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2538  if (LDF == &llvm::APFloat::IEEEquad()) {
2539  Lo = SSE;
2540  Hi = SSEUp;
2541  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2542  Lo = X87;
2543  Hi = X87Up;
2544  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2545  Current = SSE;
2546  } else
2547  llvm_unreachable("unexpected long double representation!");
2548  }
2549  // FIXME: _Decimal32 and _Decimal64 are SSE.
2550  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2551  return;
2552  }
2553 
2554  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2555  // Classify the underlying integer type.
2556  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2557  return;
2558  }
2559 
2560  if (Ty->hasPointerRepresentation()) {
2561  Current = Integer;
2562  return;
2563  }
2564 
2565  if (Ty->isMemberPointerType()) {
2566  if (Ty->isMemberFunctionPointerType()) {
2567  if (Has64BitPointers) {
2568  // If Has64BitPointers, this is an {i64, i64}, so classify both
2569  // Lo and Hi now.
2570  Lo = Hi = Integer;
2571  } else {
2572  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2573  // straddles an eightbyte boundary, Hi should be classified as well.
2574  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2575  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2576  if (EB_FuncPtr != EB_ThisAdj) {
2577  Lo = Hi = Integer;
2578  } else {
2579  Current = Integer;
2580  }
2581  }
2582  } else {
2583  Current = Integer;
2584  }
2585  return;
2586  }
2587 
2588  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2589  uint64_t Size = getContext().getTypeSize(VT);
2590  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2591  // gcc passes the following as integer:
2592  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2593  // 2 bytes - <2 x char>, <1 x short>
2594  // 1 byte - <1 x char>
2595  Current = Integer;
2596 
2597  // If this type crosses an eightbyte boundary, it should be
2598  // split.
2599  uint64_t EB_Lo = (OffsetBase) / 64;
2600  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2601  if (EB_Lo != EB_Hi)
2602  Hi = Lo;
2603  } else if (Size == 64) {
2604  QualType ElementType = VT->getElementType();
2605 
2606  // gcc passes <1 x double> in memory. :(
2607  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2608  return;
2609 
2610  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2611  // pass them as integer. For platforms where clang is the de facto
2612  // platform compiler, we must continue to use integer.
2613  if (!classifyIntegerMMXAsSSE() &&
2614  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2615  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2616  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2617  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2618  Current = Integer;
2619  else
2620  Current = SSE;
2621 
2622  // If this type crosses an eightbyte boundary, it should be
2623  // split.
2624  if (OffsetBase && OffsetBase != 64)
2625  Hi = Lo;
2626  } else if (Size == 128 ||
2627  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2628  // Arguments of 256-bits are split into four eightbyte chunks. The
2629  // least significant one belongs to class SSE and all the others to class
2630  // SSEUP. The original Lo and Hi design considers that types can't be
2631  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2632  // This design isn't correct for 256-bits, but since there're no cases
2633  // where the upper parts would need to be inspected, avoid adding
2634  // complexity and just consider Hi to match the 64-256 part.
2635  //
2636  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2637  // registers if they are "named", i.e. not part of the "..." of a
2638  // variadic function.
2639  //
2640  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2641  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2642  Lo = SSE;
2643  Hi = SSEUp;
2644  }
2645  return;
2646  }
2647 
2648  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2649  QualType ET = getContext().getCanonicalType(CT->getElementType());
2650 
2651  uint64_t Size = getContext().getTypeSize(Ty);
2652  if (ET->isIntegralOrEnumerationType()) {
2653  if (Size <= 64)
2654  Current = Integer;
2655  else if (Size <= 128)
2656  Lo = Hi = Integer;
2657  } else if (ET == getContext().FloatTy) {
2658  Current = SSE;
2659  } else if (ET == getContext().DoubleTy) {
2660  Lo = Hi = SSE;
2661  } else if (ET == getContext().LongDoubleTy) {
2662  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2663  if (LDF == &llvm::APFloat::IEEEquad())
2664  Current = Memory;
2665  else if (LDF == &llvm::APFloat::x87DoubleExtended())
2666  Current = ComplexX87;
2667  else if (LDF == &llvm::APFloat::IEEEdouble())
2668  Lo = Hi = SSE;
2669  else
2670  llvm_unreachable("unexpected long double representation!");
2671  }
2672 
2673  // If this complex type crosses an eightbyte boundary then it
2674  // should be split.
2675  uint64_t EB_Real = (OffsetBase) / 64;
2676  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2677  if (Hi == NoClass && EB_Real != EB_Imag)
2678  Hi = Lo;
2679 
2680  return;
2681  }
2682 
2683  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2684  // Arrays are treated like structures.
2685 
2686  uint64_t Size = getContext().getTypeSize(Ty);
2687 
2688  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2689  // than eight eightbytes, ..., it has class MEMORY.
2690  if (Size > 512)
2691  return;
2692 
2693  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2694  // fields, it has class MEMORY.
2695  //
2696  // Only need to check alignment of array base.
2697  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2698  return;
2699 
2700  // Otherwise implement simplified merge. We could be smarter about
2701  // this, but it isn't worth it and would be harder to verify.
2702  Current = NoClass;
2703  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2704  uint64_t ArraySize = AT->getSize().getZExtValue();
2705 
2706  // The only case a 256-bit wide vector could be used is when the array
2707  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2708  // to work for sizes wider than 128, early check and fallback to memory.
2709  //
2710  if (Size > 128 &&
2711  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2712  return;
2713 
2714  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2715  Class FieldLo, FieldHi;
2716  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2717  Lo = merge(Lo, FieldLo);
2718  Hi = merge(Hi, FieldHi);
2719  if (Lo == Memory || Hi == Memory)
2720  break;
2721  }
2722 
2723  postMerge(Size, Lo, Hi);
2724  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2725  return;
2726  }
2727 
2728  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2729  uint64_t Size = getContext().getTypeSize(Ty);
2730 
2731  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2732  // than eight eightbytes, ..., it has class MEMORY.
2733  if (Size > 512)
2734  return;
2735 
2736  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2737  // copy constructor or a non-trivial destructor, it is passed by invisible
2738  // reference.
2739  if (getRecordArgABI(RT, getCXXABI()))
2740  return;
2741 
2742  const RecordDecl *RD = RT->getDecl();
2743 
2744  // Assume variable sized types are passed in memory.
2745  if (RD->hasFlexibleArrayMember())
2746  return;
2747 
2748  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2749 
2750  // Reset Lo class, this will be recomputed.
2751  Current = NoClass;
2752 
2753  // If this is a C++ record, classify the bases first.
2754  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2755  for (const auto &I : CXXRD->bases()) {
2756  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2757  "Unexpected base class!");
2758  const CXXRecordDecl *Base =
2759  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2760 
2761  // Classify this field.
2762  //
2763  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2764  // single eightbyte, each is classified separately. Each eightbyte gets
2765  // initialized to class NO_CLASS.
2766  Class FieldLo, FieldHi;
2767  uint64_t Offset =
2768  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2769  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2770  Lo = merge(Lo, FieldLo);
2771  Hi = merge(Hi, FieldHi);
2772  if (Lo == Memory || Hi == Memory) {
2773  postMerge(Size, Lo, Hi);
2774  return;
2775  }
2776  }
2777  }
2778 
2779  // Classify the fields one at a time, merging the results.
2780  unsigned idx = 0;
2781  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2782  i != e; ++i, ++idx) {
2783  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2784  bool BitField = i->isBitField();
2785 
2786  // Ignore padding bit-fields.
2787  if (BitField && i->isUnnamedBitfield())
2788  continue;
2789 
2790  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2791  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2792  //
2793  // The only case a 256-bit wide vector could be used is when the struct
2794  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2795  // to work for sizes wider than 128, early check and fallback to memory.
2796  //
2797  if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2798  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2799  Lo = Memory;
2800  postMerge(Size, Lo, Hi);
2801  return;
2802  }
2803  // Note, skip this test for bit-fields, see below.
2804  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2805  Lo = Memory;
2806  postMerge(Size, Lo, Hi);
2807  return;
2808  }
2809 
2810  // Classify this field.
2811  //
2812  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2813  // exceeds a single eightbyte, each is classified
2814  // separately. Each eightbyte gets initialized to class
2815  // NO_CLASS.
2816  Class FieldLo, FieldHi;
2817 
2818  // Bit-fields require special handling, they do not force the
2819  // structure to be passed in memory even if unaligned, and
2820  // therefore they can straddle an eightbyte.
2821  if (BitField) {
2822  assert(!i->isUnnamedBitfield());
2823  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2824  uint64_t Size = i->getBitWidthValue(getContext());
2825 
2826  uint64_t EB_Lo = Offset / 64;
2827  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2828 
2829  if (EB_Lo) {
2830  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2831  FieldLo = NoClass;
2832  FieldHi = Integer;
2833  } else {
2834  FieldLo = Integer;
2835  FieldHi = EB_Hi ? Integer : NoClass;
2836  }
2837  } else
2838  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2839  Lo = merge(Lo, FieldLo);
2840  Hi = merge(Hi, FieldHi);
2841  if (Lo == Memory || Hi == Memory)
2842  break;
2843  }
2844 
2845  postMerge(Size, Lo, Hi);
2846  }
2847 }
2848 
2849 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2850  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2851  // place naturally.
2852  if (!isAggregateTypeForABI(Ty)) {
2853  // Treat an enum type as its underlying type.
2854  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2855  Ty = EnumTy->getDecl()->getIntegerType();
2856 
2858  : ABIArgInfo::getDirect());
2859  }
2860 
2861  return getNaturalAlignIndirect(Ty);
2862 }
2863 
2864 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2865  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2866  uint64_t Size = getContext().getTypeSize(VecTy);
2867  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2868  if (Size <= 64 || Size > LargestVector)
2869  return true;
2870  }
2871 
2872  return false;
2873 }
2874 
2875 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2876  unsigned freeIntRegs) const {
2877  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2878  // place naturally.
2879  //
2880  // This assumption is optimistic, as there could be free registers available
2881  // when we need to pass this argument in memory, and LLVM could try to pass
2882  // the argument in the free register. This does not seem to happen currently,
2883  // but this code would be much safer if we could mark the argument with
2884  // 'onstack'. See PR12193.
2885  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2886  // Treat an enum type as its underlying type.
2887  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2888  Ty = EnumTy->getDecl()->getIntegerType();
2889 
2891  : ABIArgInfo::getDirect());
2892  }
2893 
2896 
2897  // Compute the byval alignment. We specify the alignment of the byval in all
2898  // cases so that the mid-level optimizer knows the alignment of the byval.
2899  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2900 
2901  // Attempt to avoid passing indirect results using byval when possible. This
2902  // is important for good codegen.
2903  //
2904  // We do this by coercing the value into a scalar type which the backend can
2905  // handle naturally (i.e., without using byval).
2906  //
2907  // For simplicity, we currently only do this when we have exhausted all of the
2908  // free integer registers. Doing this when there are free integer registers
2909  // would require more care, as we would have to ensure that the coerced value
2910  // did not claim the unused register. That would require either reording the
2911  // arguments to the function (so that any subsequent inreg values came first),
2912  // or only doing this optimization when there were no following arguments that
2913  // might be inreg.
2914  //
2915  // We currently expect it to be rare (particularly in well written code) for
2916  // arguments to be passed on the stack when there are still free integer
2917  // registers available (this would typically imply large structs being passed
2918  // by value), so this seems like a fair tradeoff for now.
2919  //
2920  // We can revisit this if the backend grows support for 'onstack' parameter
2921  // attributes. See PR12193.
2922  if (freeIntRegs == 0) {
2923  uint64_t Size = getContext().getTypeSize(Ty);
2924 
2925  // If this type fits in an eightbyte, coerce it into the matching integral
2926  // type, which will end up on the stack (with alignment 8).
2927  if (Align == 8 && Size <= 64)
2928  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2929  Size));
2930  }
2931 
2933 }
2934 
2935 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2936 /// register. Pick an LLVM IR type that will be passed as a vector register.
2937 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2938  // Wrapper structs/arrays that only contain vectors are passed just like
2939  // vectors; strip them off if present.
2940  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2941  Ty = QualType(InnerTy, 0);
2942 
2943  llvm::Type *IRType = CGT.ConvertType(Ty);
2944  if (isa<llvm::VectorType>(IRType) ||
2945  IRType->getTypeID() == llvm::Type::FP128TyID)
2946  return IRType;
2947 
2948  // We couldn't find the preferred IR vector type for 'Ty'.
2949  uint64_t Size = getContext().getTypeSize(Ty);
2950  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2951 
2952  // Return a LLVM IR vector type based on the size of 'Ty'.
2953  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2954  Size / 64);
2955 }
2956 
2957 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2958 /// is known to either be off the end of the specified type or being in
2959 /// alignment padding. The user type specified is known to be at most 128 bits
2960 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2961 /// classification that put one of the two halves in the INTEGER class.
2962 ///
2963 /// It is conservatively correct to return false.
2964 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2965  unsigned EndBit, ASTContext &Context) {
2966  // If the bytes being queried are off the end of the type, there is no user
2967  // data hiding here. This handles analysis of builtins, vectors and other
2968  // types that don't contain interesting padding.
2969  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2970  if (TySize <= StartBit)
2971  return true;
2972 
2973  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2974  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2975  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2976 
2977  // Check each element to see if the element overlaps with the queried range.
2978  for (unsigned i = 0; i != NumElts; ++i) {
2979  // If the element is after the span we care about, then we're done..
2980  unsigned EltOffset = i*EltSize;
2981  if (EltOffset >= EndBit) break;
2982 
2983  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2984  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2985  EndBit-EltOffset, Context))
2986  return false;
2987  }
2988  // If it overlaps no elements, then it is safe to process as padding.
2989  return true;
2990  }
2991 
2992  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2993  const RecordDecl *RD = RT->getDecl();
2994  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2995 
2996  // If this is a C++ record, check the bases first.
2997  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2998  for (const auto &I : CXXRD->bases()) {
2999  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3000  "Unexpected base class!");
3001  const CXXRecordDecl *Base =
3002  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3003 
3004  // If the base is after the span we care about, ignore it.
3005  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3006  if (BaseOffset >= EndBit) continue;
3007 
3008  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3009  if (!BitsContainNoUserData(I.getType(), BaseStart,
3010  EndBit-BaseOffset, Context))
3011  return false;
3012  }
3013  }
3014 
3015  // Verify that no field has data that overlaps the region of interest. Yes
3016  // this could be sped up a lot by being smarter about queried fields,
3017  // however we're only looking at structs up to 16 bytes, so we don't care
3018  // much.
3019  unsigned idx = 0;
3020  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3021  i != e; ++i, ++idx) {
3022  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3023 
3024  // If we found a field after the region we care about, then we're done.
3025  if (FieldOffset >= EndBit) break;
3026 
3027  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3028  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3029  Context))
3030  return false;
3031  }
3032 
3033  // If nothing in this record overlapped the area of interest, then we're
3034  // clean.
3035  return true;
3036  }
3037 
3038  return false;
3039 }
3040 
3041 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3042 /// float member at the specified offset. For example, {int,{float}} has a
3043 /// float at offset 4. It is conservatively correct for this routine to return
3044 /// false.
3045 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3046  const llvm::DataLayout &TD) {
3047  // Base case if we find a float.
3048  if (IROffset == 0 && IRType->isFloatTy())
3049  return true;
3050 
3051  // If this is a struct, recurse into the field at the specified offset.
3052  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3053  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3054  unsigned Elt = SL->getElementContainingOffset(IROffset);
3055  IROffset -= SL->getElementOffset(Elt);
3056  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3057  }
3058 
3059  // If this is an array, recurse into the field at the specified offset.
3060  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3061  llvm::Type *EltTy = ATy->getElementType();
3062  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3063  IROffset -= IROffset/EltSize*EltSize;
3064  return ContainsFloatAtOffset(EltTy, IROffset, TD);
3065  }
3066 
3067  return false;
3068 }
3069 
3070 
3071 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3072 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3073 llvm::Type *X86_64ABIInfo::
3074 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3075  QualType SourceTy, unsigned SourceOffset) const {
3076  // The only three choices we have are either double, <2 x float>, or float. We
3077  // pass as float if the last 4 bytes is just padding. This happens for
3078  // structs that contain 3 floats.
3079  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3080  SourceOffset*8+64, getContext()))
3081  return llvm::Type::getFloatTy(getVMContext());
3082 
3083  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3084  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3085  // case.
3086  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3087  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3088  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3089 
3090  return llvm::Type::getDoubleTy(getVMContext());
3091 }
3092 
3093 
3094 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3095 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3096 /// about the high or low part of an up-to-16-byte struct. This routine picks
3097 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3098 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3099 /// etc).
3100 ///
3101 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3102 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3103 /// the 8-byte value references. PrefType may be null.
3104 ///
3105 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3106 /// an offset into this that we're processing (which is always either 0 or 8).
3107 ///
3108 llvm::Type *X86_64ABIInfo::
3109 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3110  QualType SourceTy, unsigned SourceOffset) const {
3111  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3112  // returning an 8-byte unit starting with it. See if we can safely use it.
3113  if (IROffset == 0) {
3114  // Pointers and int64's always fill the 8-byte unit.
3115  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3116  IRType->isIntegerTy(64))
3117  return IRType;
3118 
3119  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3120  // goodness in the source type is just tail padding. This is allowed to
3121  // kick in for struct {double,int} on the int, but not on
3122  // struct{double,int,int} because we wouldn't return the second int. We
3123  // have to do this analysis on the source type because we can't depend on
3124  // unions being lowered a specific way etc.
3125  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3126  IRType->isIntegerTy(32) ||
3127  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3128  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3129  cast<llvm::IntegerType>(IRType)->getBitWidth();
3130 
3131  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3132  SourceOffset*8+64, getContext()))
3133  return IRType;
3134  }
3135  }
3136 
3137  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3138  // If this is a struct, recurse into the field at the specified offset.
3139  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3140  if (IROffset < SL->getSizeInBytes()) {
3141  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3142  IROffset -= SL->getElementOffset(FieldIdx);
3143 
3144  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3145  SourceTy, SourceOffset);
3146  }
3147  }
3148 
3149  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3150  llvm::Type *EltTy = ATy->getElementType();
3151  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3152  unsigned EltOffset = IROffset/EltSize*EltSize;
3153  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3154  SourceOffset);
3155  }
3156 
3157  // Okay, we don't have any better idea of what to pass, so we pass this in an
3158  // integer register that isn't too big to fit the rest of the struct.
3159  unsigned TySizeInBytes =
3160  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3161 
3162  assert(TySizeInBytes != SourceOffset && "Empty field?");
3163 
3164  // It is always safe to classify this as an integer type up to i64 that
3165  // isn't larger than the structure.
3166  return llvm::IntegerType::get(getVMContext(),
3167  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3168 }
3169 
3170 
3171 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3172 /// be used as elements of a two register pair to pass or return, return a
3173 /// first class aggregate to represent them. For example, if the low part of
3174 /// a by-value argument should be passed as i32* and the high part as float,
3175 /// return {i32*, float}.
3176 static llvm::Type *
3178  const llvm::DataLayout &TD) {
3179  // In order to correctly satisfy the ABI, we need to the high part to start
3180  // at offset 8. If the high and low parts we inferred are both 4-byte types
3181  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3182  // the second element at offset 8. Check for this:
3183  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3184  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3185  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3186  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3187 
3188  // To handle this, we have to increase the size of the low part so that the
3189  // second element will start at an 8 byte offset. We can't increase the size
3190  // of the second element because it might make us access off the end of the
3191  // struct.
3192  if (HiStart != 8) {
3193  // There are usually two sorts of types the ABI generation code can produce
3194  // for the low part of a pair that aren't 8 bytes in size: float or
3195  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3196  // NaCl).
3197  // Promote these to a larger type.
3198  if (Lo->isFloatTy())
3199  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3200  else {
3201  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3202  && "Invalid/unknown lo type");
3203  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3204  }
3205  }
3206 
3207  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3208 
3209  // Verify that the second element is at an 8-byte offset.
3210  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3211  "Invalid x86-64 argument pair!");
3212  return Result;
3213 }
3214 
3216 classifyReturnType(QualType RetTy) const {
3217  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3218  // classification algorithm.
3219  X86_64ABIInfo::Class Lo, Hi;
3220  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3221 
3222  // Check some invariants.
3223  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3224  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3225 
3226  llvm::Type *ResType = nullptr;
3227  switch (Lo) {
3228  case NoClass:
3229  if (Hi == NoClass)
3230  return ABIArgInfo::getIgnore();
3231  // If the low part is just padding, it takes no register, leave ResType
3232  // null.
3233  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3234  "Unknown missing lo part");
3235  break;
3236 
3237  case SSEUp:
3238  case X87Up:
3239  llvm_unreachable("Invalid classification for lo word.");
3240 
3241  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3242  // hidden argument.
3243  case Memory:
3244  return getIndirectReturnResult(RetTy);
3245 
3246  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3247  // available register of the sequence %rax, %rdx is used.
3248  case Integer:
3249  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3250 
3251  // If we have a sign or zero extended integer, make sure to return Extend
3252  // so that the parameter gets the right LLVM IR attributes.
3253  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3254  // Treat an enum type as its underlying type.
3255  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3256  RetTy = EnumTy->getDecl()->getIntegerType();
3257 
3258  if (RetTy->isIntegralOrEnumerationType() &&
3259  RetTy->isPromotableIntegerType())
3260  return ABIArgInfo::getExtend(RetTy);
3261  }
3262  break;
3263 
3264  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3265  // available SSE register of the sequence %xmm0, %xmm1 is used.
3266  case SSE:
3267  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3268  break;
3269 
3270  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3271  // returned on the X87 stack in %st0 as 80-bit x87 number.
3272  case X87:
3273  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3274  break;
3275 
3276  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3277  // part of the value is returned in %st0 and the imaginary part in
3278  // %st1.
3279  case ComplexX87:
3280  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3281  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3282  llvm::Type::getX86_FP80Ty(getVMContext()));
3283  break;
3284  }
3285 
3286  llvm::Type *HighPart = nullptr;
3287  switch (Hi) {
3288  // Memory was handled previously and X87 should
3289  // never occur as a hi class.
3290  case Memory:
3291  case X87:
3292  llvm_unreachable("Invalid classification for hi word.");
3293 
3294  case ComplexX87: // Previously handled.
3295  case NoClass:
3296  break;
3297 
3298  case Integer:
3299  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3300  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3301  return ABIArgInfo::getDirect(HighPart, 8);
3302  break;
3303  case SSE:
3304  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3305  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3306  return ABIArgInfo::getDirect(HighPart, 8);
3307  break;
3308 
3309  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3310  // is passed in the next available eightbyte chunk if the last used
3311  // vector register.
3312  //
3313  // SSEUP should always be preceded by SSE, just widen.
3314  case SSEUp:
3315  assert(Lo == SSE && "Unexpected SSEUp classification.");
3316  ResType = GetByteVectorType(RetTy);
3317  break;
3318 
3319  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3320  // returned together with the previous X87 value in %st0.
3321  case X87Up:
3322  // If X87Up is preceded by X87, we don't need to do
3323  // anything. However, in some cases with unions it may not be
3324  // preceded by X87. In such situations we follow gcc and pass the
3325  // extra bits in an SSE reg.
3326  if (Lo != X87) {
3327  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3328  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3329  return ABIArgInfo::getDirect(HighPart, 8);
3330  }
3331  break;
3332  }
3333 
3334  // If a high part was specified, merge it together with the low part. It is
3335  // known to pass in the high eightbyte of the result. We do this by forming a
3336  // first class struct aggregate with the high and low part: {low, high}
3337  if (HighPart)
3338  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3339 
3340  return ABIArgInfo::getDirect(ResType);
3341 }
3342 
3344  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3345  bool isNamedArg)
3346  const
3347 {
3349 
3350  X86_64ABIInfo::Class Lo, Hi;
3351  classify(Ty, 0, Lo, Hi, isNamedArg);
3352 
3353  // Check some invariants.
3354  // FIXME: Enforce these by construction.
3355  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3356  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3357 
3358  neededInt = 0;
3359  neededSSE = 0;
3360  llvm::Type *ResType = nullptr;
3361  switch (Lo) {
3362  case NoClass:
3363  if (Hi == NoClass)
3364  return ABIArgInfo::getIgnore();
3365  // If the low part is just padding, it takes no register, leave ResType
3366  // null.
3367  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3368  "Unknown missing lo part");
3369  break;
3370 
3371  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3372  // on the stack.
3373  case Memory:
3374 
3375  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3376  // COMPLEX_X87, it is passed in memory.
3377  case X87:
3378  case ComplexX87:
3380  ++neededInt;
3381  return getIndirectResult(Ty, freeIntRegs);
3382 
3383  case SSEUp:
3384  case X87Up:
3385  llvm_unreachable("Invalid classification for lo word.");
3386 
3387  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3388  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3389  // and %r9 is used.
3390  case Integer:
3391  ++neededInt;
3392 
3393  // Pick an 8-byte type based on the preferred type.
3394  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3395 
3396  // If we have a sign or zero extended integer, make sure to return Extend
3397  // so that the parameter gets the right LLVM IR attributes.
3398  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3399  // Treat an enum type as its underlying type.
3400  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3401  Ty = EnumTy->getDecl()->getIntegerType();
3402 
3403  if (Ty->isIntegralOrEnumerationType() &&
3405  return ABIArgInfo::getExtend(Ty);
3406  }
3407 
3408  break;
3409 
3410  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3411  // available SSE register is used, the registers are taken in the
3412  // order from %xmm0 to %xmm7.
3413  case SSE: {
3414  llvm::Type *IRType = CGT.ConvertType(Ty);
3415  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3416  ++neededSSE;
3417  break;
3418  }
3419  }
3420 
3421  llvm::Type *HighPart = nullptr;
3422  switch (Hi) {
3423  // Memory was handled previously, ComplexX87 and X87 should
3424  // never occur as hi classes, and X87Up must be preceded by X87,
3425  // which is passed in memory.
3426  case Memory:
3427  case X87:
3428  case ComplexX87:
3429  llvm_unreachable("Invalid classification for hi word.");
3430 
3431  case NoClass: break;
3432 
3433  case Integer:
3434  ++neededInt;
3435  // Pick an 8-byte type based on the preferred type.
3436  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3437 
3438  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3439  return ABIArgInfo::getDirect(HighPart, 8);
3440  break;
3441 
3442  // X87Up generally doesn't occur here (long double is passed in
3443  // memory), except in situations involving unions.
3444  case X87Up:
3445  case SSE:
3446  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3447 
3448  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3449  return ABIArgInfo::getDirect(HighPart, 8);
3450 
3451  ++neededSSE;
3452  break;
3453 
3454  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3455  // eightbyte is passed in the upper half of the last used SSE
3456  // register. This only happens when 128-bit vectors are passed.
3457  case SSEUp:
3458  assert(Lo == SSE && "Unexpected SSEUp classification");
3459  ResType = GetByteVectorType(Ty);
3460  break;
3461  }
3462 
3463  // If a high part was specified, merge it together with the low part. It is
3464  // known to pass in the high eightbyte of the result. We do this by forming a
3465  // first class struct aggregate with the high and low part: {low, high}
3466  if (HighPart)
3467  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3468 
3469  return ABIArgInfo::getDirect(ResType);
3470 }
3471 
3472 ABIArgInfo
3473 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3474  unsigned &NeededSSE) const {
3475  auto RT = Ty->getAs<RecordType>();
3476  assert(RT && "classifyRegCallStructType only valid with struct types");
3477 
3478  if (RT->getDecl()->hasFlexibleArrayMember())
3479  return getIndirectReturnResult(Ty);
3480 
3481  // Sum up bases
3482  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3483  if (CXXRD->isDynamicClass()) {
3484  NeededInt = NeededSSE = 0;
3485  return getIndirectReturnResult(Ty);
3486  }
3487 
3488  for (const auto &I : CXXRD->bases())
3489  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3490  .isIndirect()) {
3491  NeededInt = NeededSSE = 0;
3492  return getIndirectReturnResult(Ty);
3493  }
3494  }
3495 
3496  // Sum up members
3497  for (const auto *FD : RT->getDecl()->fields()) {
3498  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3499  if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3500  .isIndirect()) {
3501  NeededInt = NeededSSE = 0;
3502  return getIndirectReturnResult(Ty);
3503  }
3504  } else {
3505  unsigned LocalNeededInt, LocalNeededSSE;
3506  if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3507  LocalNeededSSE, true)
3508  .isIndirect()) {
3509  NeededInt = NeededSSE = 0;
3510  return getIndirectReturnResult(Ty);
3511  }
3512  NeededInt += LocalNeededInt;
3513  NeededSSE += LocalNeededSSE;
3514  }
3515  }
3516 
3517  return ABIArgInfo::getDirect();
3518 }
3519 
3520 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3521  unsigned &NeededInt,
3522  unsigned &NeededSSE) const {
3523 
3524  NeededInt = 0;
3525  NeededSSE = 0;
3526 
3527  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3528 }
3529 
3530 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3531 
3532  const unsigned CallingConv = FI.getCallingConvention();
3533  // It is possible to force Win64 calling convention on any x86_64 target by
3534  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3535  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3536  if (CallingConv == llvm::CallingConv::Win64) {
3537  WinX86_64ABIInfo Win64ABIInfo(CGT);
3538  Win64ABIInfo.computeInfo(FI);
3539  return;
3540  }
3541 
3542  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3543 
3544  // Keep track of the number of assigned registers.
3545  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3546  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3547  unsigned NeededInt, NeededSSE;
3548 
3549  if (!getCXXABI().classifyReturnType(FI)) {
3550  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3551  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3552  FI.getReturnInfo() =
3553  classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3554  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3555  FreeIntRegs -= NeededInt;
3556  FreeSSERegs -= NeededSSE;
3557  } else {
3558  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3559  }
3560  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3561  // Complex Long Double Type is passed in Memory when Regcall
3562  // calling convention is used.
3563  const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3566  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3567  } else
3569  }
3570 
3571  // If the return value is indirect, then the hidden argument is consuming one
3572  // integer register.
3573  if (FI.getReturnInfo().isIndirect())
3574  --FreeIntRegs;
3575 
3576  // The chain argument effectively gives us another free register.
3577  if (FI.isChainCall())
3578  ++FreeIntRegs;
3579 
3580  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3581  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3582  // get assigned (in left-to-right order) for passing as follows...
3583  unsigned ArgNo = 0;
3584  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3585  it != ie; ++it, ++ArgNo) {
3586  bool IsNamedArg = ArgNo < NumRequiredArgs;
3587 
3588  if (IsRegCall && it->type->isStructureOrClassType())
3589  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3590  else
3591  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3592  NeededSSE, IsNamedArg);
3593 
3594  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3595  // eightbyte of an argument, the whole argument is passed on the
3596  // stack. If registers have already been assigned for some
3597  // eightbytes of such an argument, the assignments get reverted.
3598  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3599  FreeIntRegs -= NeededInt;
3600  FreeSSERegs -= NeededSSE;
3601  } else {
3602  it->info = getIndirectResult(it->type, FreeIntRegs);
3603  }
3604  }
3605 }
3606 
3608  Address VAListAddr, QualType Ty) {
3609  Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3610  VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3611  llvm::Value *overflow_arg_area =
3612  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3613 
3614  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3615  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3616  // It isn't stated explicitly in the standard, but in practice we use
3617  // alignment greater than 16 where necessary.
3618  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3619  if (Align > CharUnits::fromQuantity(8)) {
3620  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3621  Align);
3622  }
3623 
3624  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3625  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3626  llvm::Value *Res =
3627  CGF.Builder.CreateBitCast(overflow_arg_area,
3628  llvm::PointerType::getUnqual(LTy));
3629 
3630  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3631  // l->overflow_arg_area + sizeof(type).
3632  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3633  // an 8 byte boundary.
3634 
3635  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3636  llvm::Value *Offset =
3637  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3638  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3639  "overflow_arg_area.next");
3640  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3641 
3642  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3643  return Address(Res, Align);
3644 }
3645 
3646 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3647  QualType Ty) const {
3648  // Assume that va_list type is correct; should be pointer to LLVM type:
3649  // struct {
3650  // i32 gp_offset;
3651  // i32 fp_offset;
3652  // i8* overflow_arg_area;
3653  // i8* reg_save_area;
3654  // };
3655  unsigned neededInt, neededSSE;
3656 
3657  Ty = getContext().getCanonicalType(Ty);
3658  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3659  /*isNamedArg*/false);
3660 
3661  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3662  // in the registers. If not go to step 7.
3663  if (!neededInt && !neededSSE)
3664  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3665 
3666  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3667  // general purpose registers needed to pass type and num_fp to hold
3668  // the number of floating point registers needed.
3669 
3670  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3671  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3672  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3673  //
3674  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3675  // register save space).
3676 
3677  llvm::Value *InRegs = nullptr;
3678  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3679  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3680  if (neededInt) {
3681  gp_offset_p =
3682  CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3683  "gp_offset_p");
3684  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3685  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3686  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3687  }
3688 
3689  if (neededSSE) {
3690  fp_offset_p =
3691  CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3692  "fp_offset_p");
3693  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3694  llvm::Value *FitsInFP =
3695  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3696  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3697  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3698  }
3699 
3700  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3701  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3702  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3703  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3704 
3705  // Emit code to load the value if it was passed in registers.
3706 
3707  CGF.EmitBlock(InRegBlock);
3708 
3709  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3710  // an offset of l->gp_offset and/or l->fp_offset. This may require
3711  // copying to a temporary location in case the parameter is passed
3712  // in different register classes or requires an alignment greater
3713  // than 8 for general purpose registers and 16 for XMM registers.
3714  //
3715  // FIXME: This really results in shameful code when we end up needing to
3716  // collect arguments from different places; often what should result in a
3717  // simple assembling of a structure from scattered addresses has many more
3718  // loads than necessary. Can we clean this up?
3719  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3720  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3721  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3722  "reg_save_area");
3723 
3724  Address RegAddr = Address::invalid();
3725  if (neededInt && neededSSE) {
3726  // FIXME: Cleanup.
3727  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3728  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3729  Address Tmp = CGF.CreateMemTemp(Ty);
3730  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3731  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3732  llvm::Type *TyLo = ST->getElementType(0);
3733  llvm::Type *TyHi = ST->getElementType(1);
3734  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3735  "Unexpected ABI info for mixed regs");
3736  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3737  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3738  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3739  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3740  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3741  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3742 
3743  // Copy the first element.
3744  // FIXME: Our choice of alignment here and below is probably pessimistic.
3746  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3747  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3748  CGF.Builder.CreateStore(V,
3749  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3750 
3751  // Copy the second element.
3752  V = CGF.Builder.CreateAlignedLoad(
3753  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3754  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3756  getDataLayout().getStructLayout(ST)->getElementOffset(1));
3757  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3758 
3759  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3760  } else if (neededInt) {
3761  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3763  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3764 
3765  // Copy to a temporary if necessary to ensure the appropriate alignment.
3766  std::pair<CharUnits, CharUnits> SizeAlign =
3768  uint64_t TySize = SizeAlign.first.getQuantity();
3769  CharUnits TyAlign = SizeAlign.second;
3770 
3771  // Copy into a temporary if the type is more aligned than the
3772  // register save area.
3773  if (TyAlign.getQuantity() > 8) {
3774  Address Tmp = CGF.CreateMemTemp(Ty);
3775  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3776  RegAddr = Tmp;
3777  }
3778 
3779  } else if (neededSSE == 1) {
3780  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3782  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3783  } else {
3784  assert(neededSSE == 2 && "Invalid number of needed registers!");
3785  // SSE registers are spaced 16 bytes apart in the register save
3786  // area, we need to collect the two eightbytes together.
3787  // The ABI isn't explicit about this, but it seems reasonable
3788  // to assume that the slots are 16-byte aligned, since the stack is
3789  // naturally 16-byte aligned and the prologue is expected to store
3790  // all the SSE registers to the RSA.
3791  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3793  Address RegAddrHi =
3794  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3796  llvm::Type *ST = AI.canHaveCoerceToType()
3797  ? AI.getCoerceToType()
3798  : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3799  llvm::Value *V;
3800  Address Tmp = CGF.CreateMemTemp(Ty);
3801  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3803  RegAddrLo, ST->getStructElementType(0)));
3804  CGF.Builder.CreateStore(V,
3805  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3807  RegAddrHi, ST->getStructElementType(1)));
3808  CGF.Builder.CreateStore(V,
3810 
3811  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3812  }
3813 
3814  // AMD64-ABI 3.5.7p5: Step 5. Set:
3815  // l->gp_offset = l->gp_offset + num_gp * 8
3816  // l->fp_offset = l->fp_offset + num_fp * 16.
3817  if (neededInt) {
3818  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3819  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3820  gp_offset_p);
3821  }
3822  if (neededSSE) {
3823  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3824  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3825  fp_offset_p);
3826  }
3827  CGF.EmitBranch(ContBlock);
3828 
3829  // Emit code to load the value if it was passed in memory.
3830 
3831  CGF.EmitBlock(InMemBlock);
3832  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3833 
3834  // Return the appropriate result.
3835 
3836  CGF.EmitBlock(ContBlock);
3837  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3838  "vaarg.addr");
3839  return ResAddr;
3840 }
3841 
3842 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3843  QualType Ty) const {
3844  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3845  CGF.getContext().getTypeInfoInChars(Ty),
3847  /*allowHigherAlign*/ false);
3848 }
3849 
3850 ABIArgInfo
3851 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3852  const ABIArgInfo &current) const {
3853  // Assumes vectorCall calling convention.
3854  const Type *Base = nullptr;
3855  uint64_t NumElts = 0;
3856 
3857  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3858  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3859  FreeSSERegs -= NumElts;
3860  return getDirectX86Hva();
3861  }
3862  return current;
3863 }
3864 
3865 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3866  bool IsReturnType, bool IsVectorCall,
3867  bool IsRegCall) const {
3868 
3869  if (Ty->isVoidType())
3870  return ABIArgInfo::getIgnore();
3871 
3872  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3873  Ty = EnumTy->getDecl()->getIntegerType();
3874 
3875  TypeInfo Info = getContext().getTypeInfo(Ty);
3876  uint64_t Width = Info.Width;
3878 
3879  const RecordType *RT = Ty->getAs<RecordType>();
3880  if (RT) {
3881  if (!IsReturnType) {
3884  }
3885 
3886  if (RT->getDecl()->hasFlexibleArrayMember())
3887  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3888 
3889  }
3890 
3891  const Type *Base = nullptr;
3892  uint64_t NumElts = 0;
3893  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3894  // other targets.
3895  if ((IsVectorCall || IsRegCall) &&
3896  isHomogeneousAggregate(Ty, Base, NumElts)) {
3897  if (IsRegCall) {
3898  if (FreeSSERegs >= NumElts) {
3899  FreeSSERegs -= NumElts;
3900  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3901  return ABIArgInfo::getDirect();
3902  return ABIArgInfo::getExpand();
3903  }
3904  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3905  } else if (IsVectorCall) {
3906  if (FreeSSERegs >= NumElts &&
3907  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3908  FreeSSERegs -= NumElts;
3909  return ABIArgInfo::getDirect();
3910  } else if (IsReturnType) {
3911  return ABIArgInfo::getExpand();
3912  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3913  // HVAs are delayed and reclassified in the 2nd step.
3914  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3915  }
3916  }
3917  }
3918 
3919  if (Ty->isMemberPointerType()) {
3920  // If the member pointer is represented by an LLVM int or ptr, pass it
3921  // directly.
3922  llvm::Type *LLTy = CGT.ConvertType(Ty);
3923  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3924  return ABIArgInfo::getDirect();
3925  }
3926 
3927  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3928  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3929  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3930  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3931  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3932 
3933  // Otherwise, coerce it to a small integer.
3934  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3935  }
3936 
3937  // Bool type is always extended to the ABI, other builtin types are not
3938  // extended.
3939  const BuiltinType *BT = Ty->getAs<BuiltinType>();
3940  if (BT && BT->getKind() == BuiltinType::Bool)
3941  return ABIArgInfo::getExtend(Ty);
3942 
3943  // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3944  // passes them indirectly through memory.
3945  if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3946  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3947  if (LDF == &llvm::APFloat::x87DoubleExtended())
3948  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3949  }
3950 
3951  return ABIArgInfo::getDirect();
3952 }
3953 
3954 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3955  unsigned FreeSSERegs,
3956  bool IsVectorCall,
3957  bool IsRegCall) const {
3958  unsigned Count = 0;
3959  for (auto &I : FI.arguments()) {
3960  // Vectorcall in x64 only permits the first 6 arguments to be passed
3961  // as XMM/YMM registers.
3962  if (Count < VectorcallMaxParamNumAsReg)
3963  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3964  else {
3965  // Since these cannot be passed in registers, pretend no registers
3966  // are left.
3967  unsigned ZeroSSERegsAvail = 0;
3968  I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3969  IsVectorCall, IsRegCall);
3970  }
3971  ++Count;
3972  }
3973 
3974  for (auto &I : FI.arguments()) {
3975  I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3976  }
3977 }
3978 
3979 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3980  bool IsVectorCall =
3981  FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3982  bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3983 
3984  unsigned FreeSSERegs = 0;
3985  if (IsVectorCall) {
3986  // We can use up to 4 SSE return registers with vectorcall.
3987  FreeSSERegs = 4;
3988  } else if (IsRegCall) {
3989  // RegCall gives us 16 SSE registers.
3990  FreeSSERegs = 16;
3991  }
3992 
3993  if (!getCXXABI().classifyReturnType(FI))
3994  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3995  IsVectorCall, IsRegCall);
3996 
3997  if (IsVectorCall) {
3998  // We can use up to 6 SSE register parameters with vectorcall.
3999  FreeSSERegs = 6;
4000  } else if (IsRegCall) {
4001  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4002  FreeSSERegs = 16;
4003  }
4004 
4005  if (IsVectorCall) {
4006  computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4007  } else {
4008  for (auto &I : FI.arguments())
4009  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4010  }
4011 
4012 }
4013 
4014 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4015  QualType Ty) const {
4016 
4017  bool IsIndirect = false;
4018 
4019  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4020  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4021  if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4022  uint64_t Width = getContext().getTypeSize(Ty);
4023  IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4024  }
4025 
4026  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4027  CGF.getContext().getTypeInfoInChars(Ty),
4029  /*allowHigherAlign*/ false);
4030 }
4031 
4032 // PowerPC-32
4033 namespace {
4034 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4035 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4036  bool IsSoftFloatABI;
4037 
4038  CharUnits getParamTypeAlignment(QualType Ty) const;
4039 
4040 public:
4041  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4042  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4043 
4044  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4045  QualType Ty) const override;
4046 };
4047 
4048 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4049 public:
4050  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4051  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4052 
4053  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4054  // This is recovered from gcc output.
4055  return 1; // r1 is the dedicated stack pointer
4056  }
4057 
4058  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4059  llvm::Value *Address) const override;
4060 };
4061 }
4062 
4063 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4064  // Complex types are passed just like their elements
4065  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4066  Ty = CTy->getElementType();
4067 
4068  if (Ty->isVectorType())
4069  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4070  : 4);
4071 
4072  // For single-element float/vector structs, we consider the whole type
4073  // to have the same alignment requirements as its single element.
4074  const Type *AlignTy = nullptr;
4075  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4076  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4077  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4078  (BT && BT->isFloatingPoint()))
4079  AlignTy = EltType;
4080  }
4081 
4082  if (AlignTy)
4083  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4084  return CharUnits::fromQuantity(4);
4085 }
4086 
4087 // TODO: this implementation is now likely redundant with
4088 // DefaultABIInfo::EmitVAArg.
4089 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4090  QualType Ty) const {
4091  if (getTarget().getTriple().isOSDarwin()) {
4092  auto TI = getContext().getTypeInfoInChars(Ty);
4093  TI.second = getParamTypeAlignment(Ty);
4094 
4095  CharUnits SlotSize = CharUnits::fromQuantity(4);
4096  return emitVoidPtrVAArg(CGF, VAList, Ty,
4097  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4098  /*AllowHigherAlign=*/true);
4099  }
4100 
4101  const unsigned OverflowLimit = 8;
4102  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4103  // TODO: Implement this. For now ignore.
4104  (void)CTy;
4105  return Address::invalid(); // FIXME?
4106  }
4107 
4108  // struct __va_list_tag {
4109  // unsigned char gpr;
4110  // unsigned char fpr;
4111  // unsigned short reserved;
4112  // void *overflow_arg_area;
4113  // void *reg_save_area;
4114  // };
4115 
4116  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4117  bool isInt =
4118  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4119  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4120 
4121  // All aggregates are passed indirectly? That doesn't seem consistent
4122  // with the argument-lowering code.
4123  bool isIndirect = Ty->isAggregateType();
4124 
4125  CGBuilderTy &Builder = CGF.Builder;
4126 
4127  // The calling convention either uses 1-2 GPRs or 1 FPR.
4128  Address NumRegsAddr = Address::invalid();
4129  if (isInt || IsSoftFloatABI) {
4130  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4131  } else {
4132  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4133  }
4134 
4135  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4136 
4137  // "Align" the register count when TY is i64.
4138  if (isI64 || (isF64 && IsSoftFloatABI)) {
4139  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4140  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4141  }
4142 
4143  llvm::Value *CC =
4144  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4145 
4146  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4147  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4148  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4149 
4150  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4151 
4152  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4153  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4154 
4155  // Case 1: consume registers.
4156  Address RegAddr = Address::invalid();
4157  {
4158  CGF.EmitBlock(UsingRegs);
4159 
4160  Address RegSaveAreaPtr =
4161  Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4162  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4164  assert(RegAddr.getElementType() == CGF.Int8Ty);
4165 
4166  // Floating-point registers start after the general-purpose registers.
4167  if (!(isInt || IsSoftFloatABI)) {
4168  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4170  }
4171 
4172  // Get the address of the saved value by scaling the number of
4173  // registers we've used by the number of
4174  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4175  llvm::Value *RegOffset =
4176  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4177  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4178  RegAddr.getPointer(), RegOffset),
4179  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4180  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4181 
4182  // Increase the used-register count.
4183  NumRegs =
4184  Builder.CreateAdd(NumRegs,
4185  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4186  Builder.CreateStore(NumRegs, NumRegsAddr);
4187 
4188  CGF.EmitBranch(Cont);
4189  }
4190 
4191  // Case 2: consume space in the overflow area.
4192  Address MemAddr = Address::invalid();
4193  {
4194  CGF.EmitBlock(UsingOverflow);
4195 
4196  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4197 
4198  // Everything in the overflow area is rounded up to a size of at least 4.
4199  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4200 
4201  CharUnits Size;
4202  if (!isIndirect) {
4203  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4204  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4205  } else {
4206  Size = CGF.getPointerSize();
4207  }
4208 
4209  Address OverflowAreaAddr =
4210  Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4211  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4212  OverflowAreaAlign);
4213  // Round up address of argument to alignment
4214  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4215  if (Align > OverflowAreaAlign) {
4216  llvm::Value *Ptr = OverflowArea.getPointer();
4217  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4218  Align);
4219  }
4220 
4221  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4222 
4223  // Increase the overflow area.
4224  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4225  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4226  CGF.EmitBranch(Cont);
4227  }
4228 
4229  CGF.EmitBlock(Cont);
4230 
4231  // Merge the cases with a phi.
4232  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4233  "vaarg.addr");
4234 
4235  // Load the pointer if the argument was passed indirectly.
4236  if (isIndirect) {
4237  Result = Address(Builder.CreateLoad(Result, "aggr"),
4239  }
4240 
4241  return Result;
4242 }
4243 
4244 bool
4245 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4246  llvm::Value *Address) const {
4247  // This is calculated from the LLVM and GCC tables and verified
4248  // against gcc output. AFAIK all ABIs use the same encoding.
4249 
4250  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4251 
4252  llvm::IntegerType *i8 = CGF.Int8Ty;
4253  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4254  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4255  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4256 
4257  // 0-31: r0-31, the 4-byte general-purpose registers
4258  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4259 
4260  // 32-63: fp0-31, the 8-byte floating-point registers
4261  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4262 
4263  // 64-76 are various 4-byte special-purpose registers:
4264  // 64: mq
4265  // 65: lr
4266  // 66: ctr
4267  // 67: ap
4268  // 68-75 cr0-7
4269  // 76: xer
4270  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4271 
4272  // 77-108: v0-31, the 16-byte vector registers
4273  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4274 
4275  // 109: vrsave
4276  // 110: vscr
4277  // 111: spe_acc
4278  // 112: spefscr
4279  // 113: sfp
4280  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4281 
4282  return false;
4283 }
4284 
4285 // PowerPC-64
4286 
4287 namespace {
4288 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4289 class PPC64_SVR4_ABIInfo : public ABIInfo {
4290 public:
4291  enum ABIKind {
4292  ELFv1 = 0,
4293  ELFv2
4294  };
4295 
4296 private:
4297  static const unsigned GPRBits = 64;
4298  ABIKind Kind;
4299  bool HasQPX;
4300  bool IsSoftFloatABI;
4301 
4302  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4303  // will be passed in a QPX register.
4304  bool IsQPXVectorTy(const Type *Ty) const {
4305  if (!HasQPX)
4306  return false;
4307 
4308  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4309  unsigned NumElements = VT->getNumElements();
4310  if (NumElements == 1)
4311  return false;
4312 
4313  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4314  if (getContext().getTypeSize(Ty) <= 256)
4315  return true;
4316  } else if (VT->getElementType()->
4317  isSpecificBuiltinType(BuiltinType::Float)) {
4318  if (getContext().getTypeSize(Ty) <= 128)
4319  return true;
4320  }
4321  }
4322 
4323  return false;
4324  }
4325 
4326  bool IsQPXVectorTy(QualType Ty) const {
4327  return IsQPXVectorTy(Ty.getTypePtr());
4328  }
4329 
4330 public:
4331  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4332  bool SoftFloatABI)
4333  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4334  IsSoftFloatABI(SoftFloatABI) {}
4335 
4336  bool isPromotableTypeForABI(QualType Ty) const;
4337  CharUnits getParamTypeAlignment(QualType Ty) const;
4338 
4339  ABIArgInfo classifyReturnType(QualType RetTy) const;
4341 
4342  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4343  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4344  uint64_t Members) const override;
4345 
4346  // TODO: We can add more logic to computeInfo to improve performance.
4347  // Example: For aggregate arguments that fit in a register, we could
4348  // use getDirectInReg (as is done below for structs containing a single
4349  // floating-point value) to avoid pushing them to memory on function
4350  // entry. This would require changing the logic in PPCISelLowering
4351  // when lowering the parameters in the caller and args in the callee.
4352  void computeInfo(CGFunctionInfo &FI) const override {
4353  if (!getCXXABI().classifyReturnType(FI))
4355  for (auto &I : FI.arguments()) {
4356  // We rely on the default argument classification for the most part.
4357  // One exception: An aggregate containing a single floating-point
4358  // or vector item must be passed in a register if one is available.
4359  const Type *T = isSingleElementStruct(I.type, getContext());
4360  if (T) {
4361  const BuiltinType *BT = T->getAs<BuiltinType>();
4362  if (IsQPXVectorTy(T) ||
4363  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4364  (BT && BT->isFloatingPoint())) {
4365  QualType QT(T, 0);
4366  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4367  continue;
4368  }
4369  }
4370  I.info = classifyArgumentType(I.type);
4371  }
4372  }
4373 
4374  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4375  QualType Ty) const override;
4376 };
4377 
4378 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4379 
4380 public:
4381  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4382  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4383  bool SoftFloatABI)
4384  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4385  SoftFloatABI)) {}
4386 
4387  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4388  // This is recovered from gcc output.
4389  return 1; // r1 is the dedicated stack pointer
4390  }
4391 
4392  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4393  llvm::Value *Address) const override;
4394 };
4395 
4396 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4397 public:
4398  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4399 
4400  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4401  // This is recovered from gcc output.
4402  return 1; // r1 is the dedicated stack pointer
4403  }
4404 
4405  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4406  llvm::Value *Address) const override;
4407 };
4408 
4409 }
4410 
4411 // Return true if the ABI requires Ty to be passed sign- or zero-
4412 // extended to 64 bits.
4413 bool
4414 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4415  // Treat an enum type as its underlying type.
4416  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4417  Ty = EnumTy->getDecl()->getIntegerType();
4418 
4419  // Promotable integer types are required to be promoted by the ABI.
4420  if (Ty->isPromotableIntegerType())
4421  return true;
4422 
4423  // In addition to the usual promotable integer types, we also need to
4424  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4425  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4426  switch (BT->getKind()) {
4427  case BuiltinType::Int:
4428  case BuiltinType::UInt:
4429  return true;
4430  default:
4431  break;
4432  }
4433 
4434  return false;
4435 }
4436 
4437 /// isAlignedParamType - Determine whether a type requires 16-byte or
4438 /// higher alignment in the parameter area. Always returns at least 8.
4439 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4440  // Complex types are passed just like their elements.
4441  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4442  Ty = CTy->getElementType();
4443 
4444  // Only vector types of size 16 bytes need alignment (larger types are
4445  // passed via reference, smaller types are not aligned).
4446  if (IsQPXVectorTy(Ty)) {
4447  if (getContext().getTypeSize(Ty) > 128)
4448  return CharUnits::fromQuantity(32);
4449 
4450  return CharUnits::fromQuantity(16);
4451  } else if (Ty->isVectorType()) {
4452  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4453  }
4454 
4455  // For single-element float/vector structs, we consider the whole type
4456  // to have the same alignment requirements as its single element.
4457  const Type *AlignAsType = nullptr;
4458  const Type *EltType = isSingleElementStruct(Ty, getContext());
4459  if (EltType) {
4460  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4461  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4462  getContext().getTypeSize(EltType) == 128) ||
4463  (BT && BT->isFloatingPoint()))
4464  AlignAsType = EltType;
4465  }
4466 
4467  // Likewise for ELFv2 homogeneous aggregates.
4468  const Type *Base = nullptr;
4469  uint64_t Members = 0;
4470  if (!AlignAsType && Kind == ELFv2 &&
4471  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4472  AlignAsType = Base;
4473 
4474  // With special case aggregates, only vector base types need alignment.
4475  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4476  if (getContext().getTypeSize(AlignAsType) > 128)
4477  return CharUnits::fromQuantity(32);
4478 
4479  return CharUnits::fromQuantity(16);
4480  } else if (AlignAsType) {
4481  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4482  }
4483 
4484  // Otherwise, we only need alignment for any aggregate type that
4485  // has an alignment requirement of >= 16 bytes.
4486  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4487  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4488  return CharUnits::fromQuantity(32);
4489  return CharUnits::fromQuantity(16);
4490  }
4491 
4492  return CharUnits::fromQuantity(8);
4493 }
4494 
4495 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4496 /// aggregate. Base is set to the base element type, and Members is set
4497 /// to the number of base elements.
4499  uint64_t &Members) const {
4500  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4501  uint64_t NElements = AT->getSize().getZExtValue();
4502  if (NElements == 0)
4503  return false;
4504  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4505  return false;
4506  Members *= NElements;
4507  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4508  const RecordDecl *RD = RT->getDecl();
4509  if (RD->hasFlexibleArrayMember())
4510  return false;
4511 
4512  Members = 0;
4513 
4514  // If this is a C++ record, check the bases first.
4515  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4516  for (const auto &I : CXXRD->bases()) {
4517  // Ignore empty records.
4518  if (isEmptyRecord(getContext(), I.getType(), true))
4519  continue;
4520 
4521  uint64_t FldMembers;
4522  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4523  return false;
4524 
4525  Members += FldMembers;
4526  }
4527  }
4528 
4529  for (const auto *FD : RD->fields()) {
4530  // Ignore (non-zero arrays of) empty records.
4531  QualType FT = FD->getType();
4532  while (const ConstantArrayType *AT =
4533  getContext().getAsConstantArrayType(FT)) {
4534  if (AT->getSize().getZExtValue() == 0)
4535  return false;
4536  FT = AT->getElementType();
4537  }
4538  if (isEmptyRecord(getContext(), FT, true))
4539  continue;
4540 
4541  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4542  if (getContext().getLangOpts().CPlusPlus &&
4543  FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4544  continue;
4545 
4546  uint64_t FldMembers;
4547  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4548  return false;
4549 
4550  Members = (RD->isUnion() ?
4551  std::max(Members, FldMembers) : Members + FldMembers);
4552  }
4553 
4554  if (!Base)
4555  return false;
4556 
4557  // Ensure there is no padding.
4558  if (getContext().getTypeSize(Base) * Members !=
4559  getContext().getTypeSize(Ty))
4560  return false;
4561  } else {
4562  Members = 1;
4563  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4564  Members = 2;
4565  Ty = CT->getElementType();
4566  }
4567 
4568  // Most ABIs only support float, double, and some vector type widths.
4570  return false;
4571 
4572  // The base type must be the same for all members. Types that
4573  // agree in both total size and mode (float vs. vector) are
4574  // treated as being equivalent here.
4575  const Type *TyPtr = Ty.getTypePtr();
4576  if (!Base) {
4577  Base = TyPtr;
4578  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4579  // so make sure to widen it explicitly.
4580  if (const VectorType *VT = Base->getAs<VectorType>()) {
4581  QualType EltTy = VT->getElementType();
4582  unsigned NumElements =
4583  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4584  Base = getContext()
4585  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4586  .getTypePtr();
4587  }
4588  }
4589 
4590  if (Base->isVectorType() != TyPtr->isVectorType() ||
4591  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4592  return false;
4593  }
4594  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4595 }
4596 
4597 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4598  // Homogeneous aggregates for ELFv2 must have base types of float,
4599  // double, long double, or 128-bit vectors.
4600  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4601  if (BT->getKind() == BuiltinType::Float ||
4602  BT->getKind() == BuiltinType::Double ||
4603  BT->getKind() == BuiltinType::LongDouble) {
4604  if (IsSoftFloatABI)
4605  return false;
4606  return true;
4607  }
4608  }
4609  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4610  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4611  return true;
4612  }
4613  return false;
4614 }
4615 
4616 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4617  const Type *Base, uint64_t Members) const {
4618  // Vector types require one register, floating point types require one
4619  // or two registers depending on their size.
4620  uint32_t NumRegs =
4621  Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4622 
4623  // Homogeneous Aggregates may occupy at most 8 registers.
4624  return Members * NumRegs <= 8;
4625 }
4626 
4627 ABIArgInfo
4630 
4631  if (Ty->isAnyComplexType())
4632  return ABIArgInfo::getDirect();
4633 
4634  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4635  // or via reference (larger than 16 bytes).
4636  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4637  uint64_t Size = getContext().getTypeSize(Ty);
4638  if (Size > 128)
4639  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4640  else if (Size < 128) {
4641  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4642  return ABIArgInfo::getDirect(CoerceTy);
4643  }
4644  }
4645 
4646  if (isAggregateTypeForABI(Ty)) {
4649 
4650  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4651  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4652 
4653  // ELFv2 homogeneous aggregates are passed as array types.
4654  const Type *Base = nullptr;
4655  uint64_t Members = 0;
4656  if (Kind == ELFv2 &&
4657  isHomogeneousAggregate(Ty, Base, Members)) {
4658  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4659  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4660  return ABIArgInfo::getDirect(CoerceTy);
4661  }
4662 
4663  // If an aggregate may end up fully in registers, we do not
4664  // use the ByVal method, but pass the aggregate as array.
4665  // This is usually beneficial since we avoid forcing the
4666  // back-end to store the argument to memory.
4667  uint64_t Bits = getContext().getTypeSize(Ty);
4668  if (Bits > 0 && Bits <= 8 * GPRBits) {
4669  llvm::Type *CoerceTy;
4670 
4671  // Types up to 8 bytes are passed as integer type (which will be
4672  // properly aligned in the argument save area doubleword).
4673  if (Bits <= GPRBits)
4674  CoerceTy =
4675  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4676  // Larger types are passed as arrays, with the base type selected
4677  // according to the required alignment in the save area.
4678  else {
4679  uint64_t RegBits = ABIAlign * 8;
4680  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4681  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4682  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4683  }
4684 
4685  return ABIArgInfo::getDirect(CoerceTy);
4686  }
4687 
4688  // All other aggregates are passed ByVal.
4690  /*ByVal=*/true,
4691  /*Realign=*/TyAlign > ABIAlign);
4692  }
4693 
4694  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4695  : ABIArgInfo::getDirect());
4696 }
4697 
4698 ABIArgInfo
4700  if (RetTy->isVoidType())
4701  return ABIArgInfo::getIgnore();
4702 
4703  if (RetTy->isAnyComplexType())
4704  return ABIArgInfo::getDirect();
4705 
4706  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4707  // or via reference (larger than 16 bytes).
4708  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4709  uint64_t Size = getContext().getTypeSize(RetTy);
4710  if (Size > 128)
4711  return getNaturalAlignIndirect(RetTy);
4712  else if (Size < 128) {
4713  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4714  return ABIArgInfo::getDirect(CoerceTy);
4715  }
4716  }
4717 
4718  if (isAggregateTypeForABI(RetTy)) {
4719  // ELFv2 homogeneous aggregates are returned as array types.
4720  const Type *Base = nullptr;
4721  uint64_t Members = 0;
4722  if (Kind == ELFv2 &&
4723  isHomogeneousAggregate(RetTy, Base, Members)) {
4724  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4725  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4726  return ABIArgInfo::getDirect(CoerceTy);
4727  }
4728 
4729  // ELFv2 small aggregates are returned in up to two registers.
4730  uint64_t Bits = getContext().getTypeSize(RetTy);
4731  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4732  if (Bits == 0)
4733  return ABIArgInfo::getIgnore();
4734 
4735  llvm::Type *CoerceTy;
4736  if (Bits > GPRBits) {
4737  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4738  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4739  } else
4740  CoerceTy =
4741  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4742  return ABIArgInfo::getDirect(CoerceTy);
4743  }
4744 
4745  // All other aggregates are returned indirectly.
4746  return getNaturalAlignIndirect(RetTy);
4747  }
4748 
4749  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4750  : ABIArgInfo::getDirect());
4751 }
4752 
4753 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4754 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4755  QualType Ty) const {
4756  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4757  TypeInfo.second = getParamTypeAlignment(Ty);
4758 
4759  CharUnits SlotSize = CharUnits::fromQuantity(8);
4760 
4761  // If we have a complex type and the base type is smaller than 8 bytes,
4762  // the ABI calls for the real and imaginary parts to be right-adjusted
4763  // in separate doublewords. However, Clang expects us to produce a
4764  // pointer to a structure with the two parts packed tightly. So generate
4765  // loads of the real and imaginary parts relative to the va_list pointer,
4766  // and store them to a temporary structure.
4767  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4768  CharUnits EltSize = TypeInfo.first / 2;
4769  if (EltSize < SlotSize) {
4770  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4771  SlotSize * 2, SlotSize,
4772  SlotSize, /*AllowHigher*/ true);
4773 
4774  Address RealAddr = Addr;
4775  Address ImagAddr = RealAddr;
4776  if (CGF.CGM.getDataLayout().isBigEndian()) {
4777  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4778  SlotSize - EltSize);
4779  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4780  2 * SlotSize - EltSize);
4781  } else {
4782  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4783  }
4784 
4785  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4786  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4787  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4788  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4789  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4790 
4791  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4792  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4793  /*init*/ true);
4794  return Temp;
4795  }
4796  }
4797 
4798  // Otherwise, just use the general rule.
4799  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4800  TypeInfo, SlotSize, /*AllowHigher*/ true);
4801 }
4802 
4803 static bool
4805  llvm::Value *Address) {
4806  // This is calculated from the LLVM and GCC tables and verified
4807  // against gcc output. AFAIK all ABIs use the same encoding.
4808 
4809  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4810 
4811  llvm::IntegerType *i8 = CGF.Int8Ty;
4812  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4813  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4814  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4815 
4816  // 0-31: r0-31, the 8-byte general-purpose registers
4817  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4818 
4819  // 32-63: fp0-31, the 8-byte floating-point registers
4820  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4821 
4822  // 64-67 are various 8-byte special-purpose registers:
4823  // 64: mq
4824  // 65: lr
4825  // 66: ctr
4826  // 67: ap
4827  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4828 
4829  // 68-76 are various 4-byte special-purpose registers:
4830  // 68-75 cr0-7
4831  // 76: xer
4832  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4833 
4834  // 77-108: v0-31, the 16-byte vector registers
4835  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4836 
4837  // 109: vrsave
4838  // 110: vscr
4839  // 111: spe_acc
4840  // 112: spefscr
4841  // 113: sfp
4842  // 114: tfhar
4843  // 115: tfiar
4844  // 116: texasr
4845  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4846 
4847  return false;
4848 }
4849 
4850 bool
4851 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4853  llvm::Value *Address) const {
4854 
4855  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4856 }
4857 
4858 bool
4859 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4860  llvm::Value *Address) const {
4861 
4862  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4863 }
4864 
4865 //===----------------------------------------------------------------------===//
4866 // AArch64 ABI Implementation
4867 //===----------------------------------------------------------------------===//
4868 
4869 namespace {
4870 
4871 class AArch64ABIInfo : public SwiftABIInfo {
4872 public:
4873  enum ABIKind {
4874  AAPCS = 0,
4875  DarwinPCS,
4876  Win64
4877  };
4878 
4879 private:
4880  ABIKind Kind;
4881 
4882 public:
4883  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4884  : SwiftABIInfo(CGT), Kind(Kind) {}
4885 
4886 private:
4887  ABIKind getABIKind() const { return Kind; }
4888  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4889 
4890  ABIArgInfo classifyReturnType(QualType RetTy) const;
4892  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4893  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4894  uint64_t Members) const override;
4895 
4896  bool isIllegalVectorType(QualType Ty) const;
4897 
4898  void computeInfo(CGFunctionInfo &FI) const override {
4899  if (!getCXXABI().classifyReturnType(FI))
4901 
4902  for (auto &it : FI.arguments())
4903  it.info = classifyArgumentType(it.type);
4904  }
4905 
4906  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4907  CodeGenFunction &CGF) const;
4908 
4909  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4910  CodeGenFunction &CGF) const;
4911 
4912  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4913  QualType Ty) const override {
4914  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4915  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4916  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4917  }
4918 
4919  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4920  QualType Ty) const override;
4921 
4922  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4923  bool asReturnValue) const override {
4924  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4925  }
4926  bool isSwiftErrorInRegister() const override {
4927  return true;
4928  }
4929 
4930  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4931  unsigned elts) const override;
4932 };
4933 
4934 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4935 public:
4936  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4937  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4938 
4939  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4940  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4941  }
4942 
4943  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4944  return 31;
4945  }
4946 
4947  bool doesReturnSlotInterfereWithArgs() const override { return false; }
4948 };
4949 
4950 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
4951 public:
4952  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
4953  : AArch64TargetCodeGenInfo(CGT, K) {}
4954 
4955  void getDependentLibraryOption(llvm::StringRef Lib,
4956  llvm::SmallString<24> &Opt) const override {
4957  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
4958  }
4959 
4960  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
4961  llvm::SmallString<32> &Opt) const override {
4962  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
4963  }
4964 };
4965 }
4966 
4969 
4970  // Handle illegal vector types here.
4971  if (isIllegalVectorType(Ty)) {
4972  uint64_t Size = getContext().getTypeSize(Ty);
4973  // Android promotes <2 x i8> to i16, not i32
4974  if (isAndroid() && (Size <= 16)) {
4975  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4976  return ABIArgInfo::getDirect(ResType);
4977  }
4978  if (Size <= 32) {
4979  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4980  return ABIArgInfo::getDirect(ResType);
4981  }
4982  if (Size == 64) {
4983  llvm::Type *ResType =
4984  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4985  return ABIArgInfo::getDirect(ResType);
4986  }
4987  if (Size == 128) {
4988  llvm::Type *ResType =
4989  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4990  return ABIArgInfo::getDirect(ResType);
4991  }
4992  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4993  }
4994 
4995  if (!isAggregateTypeForABI(Ty)) {
4996  // Treat an enum type as its underlying type.
4997  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4998  Ty = EnumTy->getDecl()->getIntegerType();
4999 
5000  return (Ty->isPromotableIntegerType() && isDarwinPCS()
5001  ? ABIArgInfo::getExtend(Ty)
5002  : ABIArgInfo::getDirect());
5003  }
5004 
5005  // Structures with either a non-trivial destructor or a non-trivial
5006  // copy constructor are always indirect.
5008  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5010  }
5011 
5012  // Empty records are always ignored on Darwin, but actually passed in C++ mode
5013  // elsewhere for GNU compatibility.
5014  uint64_t Size = getContext().getTypeSize(Ty);
5015  bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5016  if (IsEmpty || Size == 0) {
5017  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5018  return ABIArgInfo::getIgnore();
5019 
5020  // GNU C mode. The only argument that gets ignored is an empty one with size
5021  // 0.
5022  if (IsEmpty && Size == 0)
5023  return ABIArgInfo::getIgnore();
5024  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5025  }
5026 
5027  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5028  const Type *Base = nullptr;
5029  uint64_t Members = 0;
5030  if (isHomogeneousAggregate(Ty, Base, Members)) {
5031  return ABIArgInfo::getDirect(
5032  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5033  }
5034 
5035  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5036  if (Size <= 128) {
5037  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5038  // same size and alignment.
5039  if (getTarget().isRenderScriptTarget()) {
5040  return coerceToIntArray(Ty, getContext(), getVMContext());
5041  }
5042  unsigned Alignment = getContext().getTypeAlign(Ty);
5043  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5044 
5045  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5046  // For aggregates with 16-byte alignment, we use i128.
5047  if (Alignment < 128 && Size == 128) {
5048  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5049  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5050  }
5051  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5052  }
5053 
5054  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5055 }
5056 
5058  if (RetTy->isVoidType())
5059  return ABIArgInfo::getIgnore();
5060 
5061  // Large vector types should be returned via memory.
5062  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5063  return getNaturalAlignIndirect(RetTy);
5064 
5065  if (!isAggregateTypeForABI(RetTy)) {
5066  // Treat an enum type as its underlying type.
5067  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5068  RetTy = EnumTy->getDecl()->getIntegerType();
5069 
5070  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5071  ? ABIArgInfo::getExtend(RetTy)
5072  : ABIArgInfo::getDirect());
5073  }
5074 
5075  uint64_t Size = getContext().getTypeSize(RetTy);
5076  if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5077  return ABIArgInfo::getIgnore();
5078 
5079  const Type *Base = nullptr;
5080  uint64_t Members = 0;
5081  if (isHomogeneousAggregate(RetTy, Base, Members))
5082  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5083  return ABIArgInfo::getDirect();
5084 
5085  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5086  if (Size <= 128) {
5087  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5088  // same size and alignment.
5089  if (getTarget().isRenderScriptTarget()) {
5090  return coerceToIntArray(RetTy, getContext(), getVMContext());
5091  }
5092  unsigned Alignment = getContext().getTypeAlign(RetTy);
5093  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5094 
5095  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5096  // For aggregates with 16-byte alignment, we use i128.
5097  if (Alignment < 128 && Size == 128) {
5098  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5099  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5100  }
5101  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5102  }
5103 
5104  return getNaturalAlignIndirect(RetTy);
5105 }
5106 
5107 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5108 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5109  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5110  // Check whether VT is legal.
5111  unsigned NumElements = VT->getNumElements();
5112  uint64_t Size = getContext().getTypeSize(VT);
5113  // NumElements should be power of 2.
5114  if (!llvm::isPowerOf2_32(NumElements))
5115  return true;
5116  return Size != 64 && (Size != 128 || NumElements == 1);
5117  }
5118  return false;
5119 }
5120 
5121 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5122  llvm::Type *eltTy,
5123  unsigned elts) const {
5124  if (!llvm::isPowerOf2_32(elts))
5125  return false;
5126  if (totalSize.getQuantity() != 8 &&
5127  (totalSize.getQuantity() != 16 || elts == 1))
5128  return false;
5129  return true;
5130 }
5131 
5132 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5133  // Homogeneous aggregates for AAPCS64 must have base types of a floating
5134  // point type or a short-vector type. This is the same as the 32-bit ABI,
5135  // but with the difference that any floating-point type is allowed,
5136  // including __fp16.
5137  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5138  if (BT->isFloatingPoint())
5139  return true;
5140  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5141  unsigned VecSize = getContext().getTypeSize(VT);
5142  if (VecSize == 64 || VecSize == 128)
5143  return true;
5144  }
5145  return false;
5146 }
5147 
5148 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5149  uint64_t Members) const {
5150  return Members <= 4;
5151 }
5152 
5153 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5154  QualType Ty,
5155  CodeGenFunction &CGF) const {
5157  bool IsIndirect = AI.isIndirect();
5158 
5159  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5160  if (IsIndirect)
5161  BaseTy = llvm::PointerType::getUnqual(BaseTy);
5162  else if (AI.getCoerceToType())
5163  BaseTy = AI.getCoerceToType();
5164 
5165  unsigned NumRegs = 1;
5166  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5167  BaseTy = ArrTy->getElementType();
5168  NumRegs = ArrTy->getNumElements();
5169  }
5170  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5171 
5172  // The AArch64 va_list type and handling is specified in the Procedure Call
5173  // Standard, section B.4:
5174  //
5175  // struct {
5176  // void *__stack;
5177  // void *__gr_top;
5178  // void *__vr_top;
5179  // int __gr_offs;
5180  // int __vr_offs;
5181  // };
5182 
5183  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5184  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5185  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5186  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5187 
5188  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5189  CharUnits TyAlign = TyInfo.second;
5190 
5191  Address reg_offs_p = Address::invalid();
5192  llvm::Value *reg_offs = nullptr;
5193  int reg_top_index;
5194  CharUnits reg_top_offset;
5195  int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5196  if (!IsFPR) {
5197  // 3 is the field number of __gr_offs
5198  reg_offs_p =
5199  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5200  "gr_offs_p");
5201  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5202  reg_top_index = 1; // field number for __gr_top
5203  reg_top_offset = CharUnits::fromQuantity(8);
5204  RegSize = llvm::alignTo(RegSize, 8);
5205  } else {
5206  // 4 is the field number of __vr_offs.
5207  reg_offs_p =
5208  CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5209  "vr_offs_p");
5210  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5211  reg_top_index = 2; // field number for __vr_top
5212  reg_top_offset = CharUnits::fromQuantity(16);
5213  RegSize = 16 * NumRegs;
5214  }
5215 
5216  //=======================================
5217  // Find out where argument was passed
5218  //=======================================
5219 
5220  // If reg_offs >= 0 we're already using the stack for this type of
5221  // argument. We don't want to keep updating reg_offs (in case it overflows,
5222  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5223  // whatever they get).
5224  llvm::Value *UsingStack = nullptr;
5225  UsingStack = CGF.Builder.CreateICmpSGE(
5226  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5227 
5228  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5229 
5230  // Otherwise, at least some kind of argument could go in these registers, the
5231  // question is whether this particular type is too big.
5232  CGF.EmitBlock(MaybeRegBlock);
5233 
5234  // Integer arguments may need to correct register alignment (for example a
5235  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5236  // align __gr_offs to calculate the potential address.
5237  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5238  int Align = TyAlign.getQuantity();
5239 
5240  reg_offs = CGF.Builder.CreateAdd(
5241  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5242  "align_regoffs");
5243  reg_offs = CGF.Builder.CreateAnd(
5244  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5245  "aligned_regoffs");
5246  }
5247 
5248  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5249  // The fact that this is done unconditionally reflects the fact that
5250  // allocating an argument to the stack also uses up all the remaining
5251  // registers of the appropriate kind.
5252  llvm::Value *NewOffset = nullptr;
5253  NewOffset = CGF.Builder.CreateAdd(
5254  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5255  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5256 
5257  // Now we're in a position to decide whether this argument really was in
5258  // registers or not.
5259  llvm::Value *InRegs = nullptr;
5260  InRegs = CGF.Builder.CreateICmpSLE(
5261  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5262 
5263  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5264 
5265  //=======================================
5266  // Argument was in registers
5267  //=======================================
5268 
5269  // Now we emit the code for if the argument was originally passed in
5270  // registers. First start the appropriate block:
5271  CGF.EmitBlock(InRegBlock);
5272 
5273  llvm::Value *reg_top = nullptr;
5274  Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5275  reg_top_offset, "reg_top_p");
5276  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5277  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5278  CharUnits::fromQuantity(IsFPR ? 16 : 8));
5279  Address RegAddr = Address::invalid();
5280  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5281 
5282  if (IsIndirect) {
5283  // If it's been passed indirectly (actually a struct), whatever we find from
5284  // stored registers or on the stack will actually be a struct **.
5285  MemTy = llvm::PointerType::getUnqual(MemTy);
5286  }
5287 
5288  const Type *Base = nullptr;
5289  uint64_t NumMembers = 0;
5290  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5291  if (IsHFA && NumMembers > 1) {
5292  // Homogeneous aggregates passed in registers will have their elements split
5293  // and stored 16-bytes apart regardless of size (they're notionally in qN,
5294  // qN+1, ...). We reload and store into a temporary local variable
5295  // contiguously.
5296  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5297  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5298  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5299  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5300  Address Tmp = CGF.CreateTempAlloca(HFATy,
5301  std::max(TyAlign, BaseTyInfo.second));
5302 
5303  // On big-endian platforms, the value will be right-aligned in its slot.
5304  int Offset = 0;
5305  if (CGF.CGM.getDataLayout().isBigEndian() &&
5306  BaseTyInfo.first.getQuantity() < 16)
5307  Offset = 16 - BaseTyInfo.first.getQuantity();
5308 
5309  for (unsigned i = 0; i < NumMembers; ++i) {
5310  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5311  Address LoadAddr =
5312  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5313  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5314 
5315  Address StoreAddr =
5316  CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5317 
5318  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5319  CGF.Builder.CreateStore(Elem, StoreAddr);
5320  }
5321 
5322  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5323  } else {
5324  // Otherwise the object is contiguous in memory.
5325 
5326  // It might be right-aligned in its slot.
5327  CharUnits SlotSize = BaseAddr.getAlignment();
5328  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5329  (IsHFA || !isAggregateTypeForABI(Ty)) &&
5330  TyInfo.first < SlotSize) {
5331  CharUnits Offset = SlotSize - TyInfo.first;
5332  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5333  }
5334 
5335  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5336  }
5337 
5338  CGF.EmitBranch(ContBlock);
5339 
5340  //=======================================
5341  // Argument was on the stack
5342  //=======================================
5343  CGF.EmitBlock(OnStackBlock);
5344 
5345  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5346  CharUnits::Zero(), "stack_p");
5347  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5348 
5349  // Again, stack arguments may need realignment. In this case both integer and
5350  // floating-point ones might be affected.
5351  if (!IsIndirect && TyAlign.getQuantity() > 8) {
5352  int Align = TyAlign.getQuantity();
5353 
5354  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5355 
5356  OnStackPtr = CGF.Builder.CreateAdd(
5357  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5358  "align_stack");
5359  OnStackPtr = CGF.Builder.CreateAnd(
5360  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5361  "align_stack");
5362 
5363  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5364  }
5365  Address OnStackAddr(OnStackPtr,
5366  std::max(CharUnits::fromQuantity(8), TyAlign));
5367 
5368  // All stack slots are multiples of 8 bytes.
5369  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5370  CharUnits StackSize;
5371  if (IsIndirect)
5372  StackSize = StackSlotSize;
5373  else
5374  StackSize = TyInfo.first.alignTo(StackSlotSize);
5375 
5376  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5377  llvm::Value *NewStack =
5378  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5379 
5380  // Write the new value of __stack for the next call to va_arg
5381  CGF.Builder.CreateStore(NewStack, stack_p);
5382 
5383  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5384  TyInfo.first < StackSlotSize) {
5385  CharUnits Offset = StackSlotSize - TyInfo.first;
5386  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5387  }
5388 
5389  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5390 
5391  CGF.EmitBranch(ContBlock);
5392 
5393  //=======================================
5394  // Tidy up
5395  //=======================================
5396  CGF.EmitBlock(ContBlock);
5397 
5398  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5399  OnStackAddr, OnStackBlock, "vaargs.addr");
5400 
5401  if (IsIndirect)
5402  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5403  TyInfo.second);
5404 
5405  return ResAddr;
5406 }
5407 
5408 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5409  CodeGenFunction &CGF) const {
5410  // The backend's lowering doesn't support va_arg for aggregates or
5411  // illegal vector types. Lower VAArg here for these cases and use
5412  // the LLVM va_arg instruction for everything else.
5413  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5414  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5415 
5416  CharUnits SlotSize = CharUnits::fromQuantity(8);
5417 
5418  // Empty records are ignored for parameter passing purposes.
5419  if (isEmptyRecord(getContext(), Ty, true)) {
5420  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5421  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5422  return Addr;
5423  }
5424 
5425  // The size of the actual thing passed, which might end up just
5426  // being a pointer for indirect types.
5427  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5428 
5429  // Arguments bigger than 16 bytes which aren't homogeneous
5430  // aggregates should be passed indirectly.
5431  bool IsIndirect = false;
5432  if (TyInfo.first.getQuantity() > 16) {
5433  const Type *Base = nullptr;
5434  uint64_t Members = 0;
5435  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5436  }
5437 
5438  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5439  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5440 }
5441 
5442 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5443  QualType Ty) const {
5444  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5445  CGF.getContext().getTypeInfoInChars(Ty),
5447  /*allowHigherAlign*/ false);
5448 }
5449 
5450 //===----------------------------------------------------------------------===//
5451 // ARM ABI Implementation
5452 //===----------------------------------------------------------------------===//
5453 
5454 namespace {
5455 
5456 class ARMABIInfo : public SwiftABIInfo {
5457 public:
5458  enum ABIKind {
5459  APCS = 0,
5460  AAPCS = 1,
5461  AAPCS_VFP = 2,
5462  AAPCS16_VFP = 3,
5463  };
5464 
5465 private:
5466  ABIKind Kind;
5467 
5468 public:
5469  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5470  : SwiftABIInfo(CGT), Kind(_Kind) {
5471  setCCs();
5472  }
5473 
5474  bool isEABI() const {
5475  switch (getTarget().getTriple().getEnvironment()) {
5476  case llvm::Triple::Android:
5477  case llvm::Triple::EABI:
5478  case llvm::Triple::EABIHF:
5479  case llvm::Triple::GNUEABI:
5480  case llvm::Triple::GNUEABIHF:
5481  case llvm::Triple::MuslEABI:
5482  case llvm::Triple::MuslEABIHF:
5483  return true;
5484  default:
5485  return false;
5486  }
5487  }
5488 
5489  bool isEABIHF() const {
5490  switch (getTarget().getTriple().getEnvironment()) {
5491  case llvm::Triple::EABIHF:
5492  case llvm::Triple::GNUEABIHF:
5493  case llvm::Triple::MuslEABIHF:
5494  return true;
5495  default:
5496  return false;
5497  }
5498  }
5499 
5500  ABIKind getABIKind() const { return Kind; }
5501 
5502 private:
5503  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5504  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5505  bool isIllegalVectorType(QualType Ty) const;
5506 
5507  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5508  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5509  uint64_t Members) const override;
5510 
5511  void computeInfo(CGFunctionInfo &FI) const override;
5512 
5513  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5514  QualType Ty) const override;
5515 
5516  llvm::CallingConv::ID getLLVMDefaultCC() const;
5517  llvm::CallingConv::ID getABIDefaultCC() const;
5518  void setCCs();
5519 
5520  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5521  bool asReturnValue) const override {
5522  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5523  }
5524  bool isSwiftErrorInRegister() const override {
5525  return true;
5526  }
5527  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5528  unsigned elts) const override;
5529 };
5530 
5531 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5532 public:
5533  ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5534  :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5535 
5536  const ARMABIInfo &getABIInfo() const {
5537  return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5538  }
5539 
5540  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5541  return 13;
5542  }
5543 
5544  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5545  return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5546  }
5547 
5548  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5549  llvm::Value *Address) const override {
5550  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5551 
5552  // 0-15 are the 16 integer registers.
5553  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5554  return false;
5555  }
5556 
5557  unsigned getSizeOfUnwindException() const override {
5558  if (getABIInfo().isEABI()) return 88;
5560  }
5561 
5562  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5563  CodeGen::CodeGenModule &CGM) const override {
5564  if (GV->isDeclaration())
5565  return;
5566  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5567  if (!FD)
5568  return;
5569 
5570  const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5571  if (!Attr)
5572  return;
5573 
5574  const char *Kind;
5575  switch (Attr->getInterrupt()) {
5576  case ARMInterruptAttr::Generic: Kind = ""; break;
5577  case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5578  case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5579  case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5580  case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5581  case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5582  }
5583 
5584  llvm::Function *Fn = cast<llvm::Function>(GV);
5585 
5586  Fn->addFnAttr("interrupt", Kind);
5587 
5588  ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5589  if (ABI == ARMABIInfo::APCS)
5590  return;
5591 
5592  // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5593  // however this is not necessarily true on taking any interrupt. Instruct
5594  // the backend to perform a realignment as part of the function prologue.
5595  llvm::AttrBuilder B;
5596  B.addStackAlignmentAttr(8);
5597  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5598  }
5599 };
5600 
5601 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5602 public:
5603  WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5604  : ARMTargetCodeGenInfo(CGT, K) {}
5605 
5606  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5607  CodeGen::CodeGenModule &CGM) const override;
5608 
5609  void getDependentLibraryOption(llvm::StringRef Lib,
5610  llvm::SmallString<24> &Opt) const override {
5611  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5612  }
5613 
5614  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5615  llvm::SmallString<32> &Opt) const override {
5616  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5617  }
5618 };
5619 
5620 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5621  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5622  ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5623  if (GV->isDeclaration())
5624  return;
5625  addStackProbeSizeTargetAttribute(D, GV, CGM);
5626 }
5627 }
5628 
5629 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5630  if (!getCXXABI().classifyReturnType(FI))
5631  FI.getReturnInfo() =
5633 
5634  for (auto &I : FI.arguments())
5635  I.info = classifyArgumentType(I.type, FI.isVariadic());
5636 
5637  // Always honor user-specified calling convention.
5639  return;
5640