clang 22.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 UpdatedFeaturesVec.push_back(Feature);
178 }
179
180 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
181 return false;
182
183 // Can't do this earlier because we need to be able to explicitly enable
184 // or disable these features and the things that they depend upon.
185
186 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
187 auto I = Features.find("sse4.2");
188 if (I != Features.end() && I->getValue() &&
189 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
190 Features["popcnt"] = true;
191
192 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
193 // then enable MMX.
194 I = Features.find("sse");
195 if (I != Features.end() && I->getValue() &&
196 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
197 Features["mmx"] = true;
198
199 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
200 I = Features.find("avx");
201 if (I != Features.end() && I->getValue() &&
202 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
203 Features["xsave"] = true;
204
205 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
206 I = Features.find("sse4.2");
207 if (I != Features.end() && I->getValue() &&
208 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
209 Features["crc32"] = true;
210
211 return true;
212}
213
214void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
215 StringRef Name, bool Enabled) const {
216 if (Name == "sse4") {
217 // We can get here via the __target__ attribute since that's not controlled
218 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
219 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
220 // disabled.
221 if (Enabled)
222 Name = "sse4.2";
223 else
224 Name = "sse4.1";
225 }
226
227 Features[Name] = Enabled;
228 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
229}
230
231/// handleTargetFeatures - Perform initialization based on the user
232/// configured set of features.
233bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
234 DiagnosticsEngine &Diags) {
235 for (const auto &Feature : Features) {
236 if (Feature[0] != '+')
237 continue;
238
239 if (Feature == "+mmx") {
240 HasMMX = true;
241 } else if (Feature == "+aes") {
242 HasAES = true;
243 } else if (Feature == "+vaes") {
244 HasVAES = true;
245 } else if (Feature == "+pclmul") {
246 HasPCLMUL = true;
247 } else if (Feature == "+vpclmulqdq") {
248 HasVPCLMULQDQ = true;
249 } else if (Feature == "+lzcnt") {
250 HasLZCNT = true;
251 } else if (Feature == "+rdrnd") {
252 HasRDRND = true;
253 } else if (Feature == "+fsgsbase") {
254 HasFSGSBASE = true;
255 } else if (Feature == "+bmi") {
256 HasBMI = true;
257 } else if (Feature == "+bmi2") {
258 HasBMI2 = true;
259 } else if (Feature == "+popcnt") {
260 HasPOPCNT = true;
261 } else if (Feature == "+rtm") {
262 HasRTM = true;
263 } else if (Feature == "+prfchw") {
264 HasPRFCHW = true;
265 } else if (Feature == "+rdseed") {
266 HasRDSEED = true;
267 } else if (Feature == "+adx") {
268 HasADX = true;
269 } else if (Feature == "+tbm") {
270 HasTBM = true;
271 } else if (Feature == "+lwp") {
272 HasLWP = true;
273 } else if (Feature == "+fma") {
274 HasFMA = true;
275 } else if (Feature == "+f16c") {
276 HasF16C = true;
277 } else if (Feature == "+gfni") {
278 HasGFNI = true;
279 } else if (Feature == "+avx10.1") {
280 HasAVX10_1 = true;
281 } else if (Feature == "+avx10.2") {
282 HasAVX10_2 = true;
283 HasFullBFloat16 = true;
284 } else if (Feature == "+avx512cd") {
285 HasAVX512CD = true;
286 } else if (Feature == "+avx512vpopcntdq") {
287 HasAVX512VPOPCNTDQ = true;
288 } else if (Feature == "+avx512vnni") {
289 HasAVX512VNNI = true;
290 } else if (Feature == "+avx512bf16") {
291 HasAVX512BF16 = true;
292 } else if (Feature == "+avx512fp16") {
293 HasAVX512FP16 = true;
294 HasFastHalfType = true;
295 } else if (Feature == "+avx512dq") {
296 HasAVX512DQ = true;
297 } else if (Feature == "+avx512bitalg") {
298 HasAVX512BITALG = true;
299 } else if (Feature == "+avx512bw") {
300 HasAVX512BW = true;
301 } else if (Feature == "+avx512vl") {
302 HasAVX512VL = true;
303 } else if (Feature == "+avx512vbmi") {
304 HasAVX512VBMI = true;
305 } else if (Feature == "+avx512vbmi2") {
306 HasAVX512VBMI2 = true;
307 } else if (Feature == "+avx512ifma") {
308 HasAVX512IFMA = true;
309 } else if (Feature == "+avx512vp2intersect") {
310 HasAVX512VP2INTERSECT = true;
311 } else if (Feature == "+sha") {
312 HasSHA = true;
313 } else if (Feature == "+sha512") {
314 HasSHA512 = true;
315 } else if (Feature == "+shstk") {
316 HasSHSTK = true;
317 } else if (Feature == "+sm3") {
318 HasSM3 = true;
319 } else if (Feature == "+sm4") {
320 HasSM4 = true;
321 } else if (Feature == "+movbe") {
322 HasMOVBE = true;
323 } else if (Feature == "+movrs") {
324 HasMOVRS = true;
325 } else if (Feature == "+sgx") {
326 HasSGX = true;
327 } else if (Feature == "+cx8") {
328 HasCX8 = true;
329 } else if (Feature == "+cx16") {
330 HasCX16 = true;
331 } else if (Feature == "+fxsr") {
332 HasFXSR = true;
333 } else if (Feature == "+xsave") {
334 HasXSAVE = true;
335 } else if (Feature == "+xsaveopt") {
336 HasXSAVEOPT = true;
337 } else if (Feature == "+xsavec") {
338 HasXSAVEC = true;
339 } else if (Feature == "+xsaves") {
340 HasXSAVES = true;
341 } else if (Feature == "+mwaitx") {
342 HasMWAITX = true;
343 } else if (Feature == "+pku") {
344 HasPKU = true;
345 } else if (Feature == "+clflushopt") {
346 HasCLFLUSHOPT = true;
347 } else if (Feature == "+clwb") {
348 HasCLWB = true;
349 } else if (Feature == "+wbnoinvd") {
350 HasWBNOINVD = true;
351 } else if (Feature == "+prefetchi") {
352 HasPREFETCHI = true;
353 } else if (Feature == "+clzero") {
354 HasCLZERO = true;
355 } else if (Feature == "+cldemote") {
356 HasCLDEMOTE = true;
357 } else if (Feature == "+rdpid") {
358 HasRDPID = true;
359 } else if (Feature == "+rdpru") {
360 HasRDPRU = true;
361 } else if (Feature == "+kl") {
362 HasKL = true;
363 } else if (Feature == "+widekl") {
364 HasWIDEKL = true;
365 } else if (Feature == "+retpoline-external-thunk") {
366 HasRetpolineExternalThunk = true;
367 } else if (Feature == "+sahf") {
368 HasLAHFSAHF = true;
369 } else if (Feature == "+waitpkg") {
370 HasWAITPKG = true;
371 } else if (Feature == "+movdiri") {
372 HasMOVDIRI = true;
373 } else if (Feature == "+movdir64b") {
374 HasMOVDIR64B = true;
375 } else if (Feature == "+pconfig") {
376 HasPCONFIG = true;
377 } else if (Feature == "+ptwrite") {
378 HasPTWRITE = true;
379 } else if (Feature == "+invpcid") {
380 HasINVPCID = true;
381 } else if (Feature == "+enqcmd") {
382 HasENQCMD = true;
383 } else if (Feature == "+hreset") {
384 HasHRESET = true;
385 } else if (Feature == "+amx-bf16") {
386 HasAMXBF16 = true;
387 } else if (Feature == "+amx-fp16") {
388 HasAMXFP16 = true;
389 } else if (Feature == "+amx-int8") {
390 HasAMXINT8 = true;
391 } else if (Feature == "+amx-tile") {
392 HasAMXTILE = true;
393 } else if (Feature == "+amx-complex") {
394 HasAMXCOMPLEX = true;
395 } else if (Feature == "+amx-fp8") {
396 HasAMXFP8 = true;
397 } else if (Feature == "+amx-movrs") {
398 HasAMXMOVRS = true;
399 } else if (Feature == "+amx-transpose") {
400 HasAMXTRANSPOSE = true;
401 } else if (Feature == "+amx-avx512") {
402 HasAMXAVX512 = true;
403 } else if (Feature == "+amx-tf32") {
404 HasAMXTF32 = true;
405 } else if (Feature == "+cmpccxadd") {
406 HasCMPCCXADD = true;
407 } else if (Feature == "+raoint") {
408 HasRAOINT = true;
409 } else if (Feature == "+avxifma") {
410 HasAVXIFMA = true;
411 } else if (Feature == "+avxneconvert") {
412 HasAVXNECONVERT= true;
413 } else if (Feature == "+avxvnni") {
414 HasAVXVNNI = true;
415 } else if (Feature == "+avxvnniint16") {
416 HasAVXVNNIINT16 = true;
417 } else if (Feature == "+avxvnniint8") {
418 HasAVXVNNIINT8 = true;
419 } else if (Feature == "+serialize") {
420 HasSERIALIZE = true;
421 } else if (Feature == "+tsxldtrk") {
422 HasTSXLDTRK = true;
423 } else if (Feature == "+uintr") {
424 HasUINTR = true;
425 } else if (Feature == "+usermsr") {
426 HasUSERMSR = true;
427 } else if (Feature == "+crc32") {
428 HasCRC32 = true;
429 } else if (Feature == "+x87") {
430 HasX87 = true;
431 } else if (Feature == "+fullbf16") {
432 HasFullBFloat16 = true;
433 } else if (Feature == "+egpr") {
434 HasEGPR = true;
435 } else if (Feature == "+inline-asm-use-gpr32") {
436 HasInlineAsmUseGPR32 = true;
437 } else if (Feature == "+push2pop2") {
438 HasPush2Pop2 = true;
439 } else if (Feature == "+ppx") {
440 HasPPX = true;
441 } else if (Feature == "+ndd") {
442 HasNDD = true;
443 } else if (Feature == "+ccmp") {
444 HasCCMP = true;
445 } else if (Feature == "+nf") {
446 HasNF = true;
447 } else if (Feature == "+cf") {
448 HasCF = true;
449 } else if (Feature == "+zu") {
450 HasZU = true;
451 } else if (Feature == "+branch-hint") {
452 HasBranchHint = true;
453 }
454
455 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
456 .Case("+avx512f", AVX512F)
457 .Case("+avx2", AVX2)
458 .Case("+avx", AVX)
459 .Case("+sse4.2", SSE42)
460 .Case("+sse4.1", SSE41)
461 .Case("+ssse3", SSSE3)
462 .Case("+sse3", SSE3)
463 .Case("+sse2", SSE2)
464 .Case("+sse", SSE1)
465 .Default(NoSSE);
466 SSELevel = std::max(SSELevel, Level);
467
468 HasFloat16 = SSELevel >= SSE2;
469
470 // X86 target has bfloat16 emulation support in the backend, where
471 // bfloat16 is treated as a 32-bit float, arithmetic operations are
472 // performed in 32-bit, and the result is converted back to bfloat16.
473 // Truncation and extension between bfloat16 and 32-bit float are supported
474 // by the compiler-rt library. However, native bfloat16 support is currently
475 // not available in the X86 target. Hence, HasFullBFloat16 will be false
476 // until native bfloat16 support is available. HasFullBFloat16 is used to
477 // determine whether to automatically use excess floating point precision
478 // for bfloat16 arithmetic operations in the front-end.
479 HasBFloat16 = SSELevel >= SSE2;
480
481 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
482 .Case("+xop", XOP)
483 .Case("+fma4", FMA4)
484 .Case("+sse4a", SSE4A)
485 .Default(NoXOP);
486 XOPLevel = std::max(XOPLevel, XLevel);
487 }
488
489 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
490 // matches the selected sse level.
491 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
492 (FPMath == FP_387 && SSELevel >= SSE1)) {
493 Diags.Report(diag::err_target_unsupported_fpmath)
494 << (FPMath == FP_SSE ? "sse" : "387");
495 return false;
496 }
497
498 // FIXME: We should allow long double type on 32-bits to match with GCC.
499 // This requires backend to be able to lower f80 without x87 first.
500 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
501 HasLongDouble = false;
502
503 return true;
504}
505
506/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
507/// definitions for this particular subtarget.
508void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
509 MacroBuilder &Builder) const {
510 // Inline assembly supports X86 flag outputs.
511 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
512
513 std::string CodeModel = getTargetOpts().CodeModel;
514 if (CodeModel == "default")
515 CodeModel = "small";
516 Builder.defineMacro("__code_model_" + CodeModel + "__");
517
518 // Target identification.
519 if (getTriple().getArch() == llvm::Triple::x86_64) {
520 Builder.defineMacro("__amd64__");
521 Builder.defineMacro("__amd64");
522 Builder.defineMacro("__x86_64");
523 Builder.defineMacro("__x86_64__");
524 if (getTriple().getArchName() == "x86_64h") {
525 Builder.defineMacro("__x86_64h");
526 Builder.defineMacro("__x86_64h__");
527 }
528 } else {
529 DefineStd(Builder, "i386", Opts);
530 }
531
532 Builder.defineMacro("__SEG_GS");
533 Builder.defineMacro("__SEG_FS");
534 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
535 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
536
537 // Subtarget options.
538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
539 // truly should be based on -mtune options.
540 using namespace llvm::X86;
541 switch (CPU) {
542 case CK_None:
543 break;
544 case CK_i386:
545 // The rest are coming from the i386 define above.
546 Builder.defineMacro("__tune_i386__");
547 break;
548 case CK_i486:
549 case CK_WinChipC6:
550 case CK_WinChip2:
551 case CK_C3:
552 defineCPUMacros(Builder, "i486");
553 break;
554 case CK_PentiumMMX:
555 Builder.defineMacro("__pentium_mmx__");
556 Builder.defineMacro("__tune_pentium_mmx__");
557 [[fallthrough]];
558 case CK_i586:
559 case CK_Pentium:
560 defineCPUMacros(Builder, "i586");
561 defineCPUMacros(Builder, "pentium");
562 break;
563 case CK_Pentium3:
564 case CK_PentiumM:
565 Builder.defineMacro("__tune_pentium3__");
566 [[fallthrough]];
567 case CK_Pentium2:
568 case CK_C3_2:
569 Builder.defineMacro("__tune_pentium2__");
570 [[fallthrough]];
571 case CK_PentiumPro:
572 case CK_i686:
573 defineCPUMacros(Builder, "i686");
574 defineCPUMacros(Builder, "pentiumpro");
575 break;
576 case CK_Pentium4:
577 defineCPUMacros(Builder, "pentium4");
578 break;
579 case CK_Yonah:
580 case CK_Prescott:
581 case CK_Nocona:
582 defineCPUMacros(Builder, "nocona");
583 break;
584 case CK_Core2:
585 case CK_Penryn:
586 defineCPUMacros(Builder, "core2");
587 break;
588 case CK_Bonnell:
589 defineCPUMacros(Builder, "atom");
590 break;
591 case CK_Silvermont:
592 defineCPUMacros(Builder, "slm");
593 break;
594 case CK_Goldmont:
595 defineCPUMacros(Builder, "goldmont");
596 break;
597 case CK_GoldmontPlus:
598 defineCPUMacros(Builder, "goldmont_plus");
599 break;
600 case CK_Tremont:
601 defineCPUMacros(Builder, "tremont");
602 break;
603 // Gracemont and later atom-cores use P-core cpu macros.
604 case CK_Gracemont:
605 case CK_Nehalem:
606 case CK_Westmere:
607 case CK_SandyBridge:
608 case CK_IvyBridge:
609 case CK_Haswell:
610 case CK_Broadwell:
611 case CK_SkylakeClient:
612 case CK_SkylakeServer:
613 case CK_Cascadelake:
614 case CK_Cooperlake:
615 case CK_Cannonlake:
616 case CK_IcelakeClient:
617 case CK_Rocketlake:
618 case CK_IcelakeServer:
619 case CK_Tigerlake:
620 case CK_SapphireRapids:
621 case CK_Alderlake:
622 case CK_Raptorlake:
623 case CK_Meteorlake:
624 case CK_Arrowlake:
625 case CK_ArrowlakeS:
626 case CK_Lunarlake:
627 case CK_Pantherlake:
628 case CK_Sierraforest:
629 case CK_Grandridge:
630 case CK_Graniterapids:
631 case CK_GraniterapidsD:
632 case CK_Emeraldrapids:
633 case CK_Clearwaterforest:
634 case CK_Diamondrapids:
635 // FIXME: Historically, we defined this legacy name, it would be nice to
636 // remove it at some point. We've never exposed fine-grained names for
637 // recent primary x86 CPUs, and we should keep it that way.
638 defineCPUMacros(Builder, "corei7");
639 break;
640 case CK_KNL:
641 defineCPUMacros(Builder, "knl");
642 break;
643 case CK_KNM:
644 break;
645 case CK_Lakemont:
646 defineCPUMacros(Builder, "i586", /*Tuning*/false);
647 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
648 Builder.defineMacro("__tune_lakemont__");
649 break;
650 case CK_K6_2:
651 Builder.defineMacro("__k6_2__");
652 Builder.defineMacro("__tune_k6_2__");
653 [[fallthrough]];
654 case CK_K6_3:
655 if (CPU != CK_K6_2) { // In case of fallthrough
656 // FIXME: GCC may be enabling these in cases where some other k6
657 // architecture is specified but -m3dnow is explicitly provided. The
658 // exact semantics need to be determined and emulated here.
659 Builder.defineMacro("__k6_3__");
660 Builder.defineMacro("__tune_k6_3__");
661 }
662 [[fallthrough]];
663 case CK_K6:
664 defineCPUMacros(Builder, "k6");
665 break;
666 case CK_Athlon:
667 case CK_AthlonXP:
668 defineCPUMacros(Builder, "athlon");
669 if (SSELevel != NoSSE) {
670 Builder.defineMacro("__athlon_sse__");
671 Builder.defineMacro("__tune_athlon_sse__");
672 }
673 break;
674 case CK_K8:
675 case CK_K8SSE3:
676 case CK_x86_64:
677 defineCPUMacros(Builder, "k8");
678 break;
679 case CK_x86_64_v2:
680 case CK_x86_64_v3:
681 case CK_x86_64_v4:
682 break;
683 case CK_AMDFAM10:
684 defineCPUMacros(Builder, "amdfam10");
685 break;
686 case CK_BTVER1:
687 defineCPUMacros(Builder, "btver1");
688 break;
689 case CK_BTVER2:
690 defineCPUMacros(Builder, "btver2");
691 break;
692 case CK_BDVER1:
693 defineCPUMacros(Builder, "bdver1");
694 break;
695 case CK_BDVER2:
696 defineCPUMacros(Builder, "bdver2");
697 break;
698 case CK_BDVER3:
699 defineCPUMacros(Builder, "bdver3");
700 break;
701 case CK_BDVER4:
702 defineCPUMacros(Builder, "bdver4");
703 break;
704 case CK_ZNVER1:
705 defineCPUMacros(Builder, "znver1");
706 break;
707 case CK_ZNVER2:
708 defineCPUMacros(Builder, "znver2");
709 break;
710 case CK_ZNVER3:
711 defineCPUMacros(Builder, "znver3");
712 break;
713 case CK_ZNVER4:
714 defineCPUMacros(Builder, "znver4");
715 break;
716 case CK_ZNVER5:
717 defineCPUMacros(Builder, "znver5");
718 break;
719 case CK_Geode:
720 defineCPUMacros(Builder, "geode");
721 break;
722 }
723
724 // Target properties.
725 Builder.defineMacro("__REGISTER_PREFIX__", "");
726
727 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
728 // functions in glibc header files that use FP Stack inline asm which the
729 // backend can't deal with (PR879).
730 Builder.defineMacro("__NO_MATH_INLINES");
731
732 if (HasAES)
733 Builder.defineMacro("__AES__");
734
735 if (HasVAES)
736 Builder.defineMacro("__VAES__");
737
738 if (HasPCLMUL)
739 Builder.defineMacro("__PCLMUL__");
740
741 if (HasVPCLMULQDQ)
742 Builder.defineMacro("__VPCLMULQDQ__");
743
744 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
745 // the feature flag only applies to 64-bit mode.
746 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
747 Builder.defineMacro("__LAHF_SAHF__");
748
749 if (HasLZCNT)
750 Builder.defineMacro("__LZCNT__");
751
752 if (HasRDRND)
753 Builder.defineMacro("__RDRND__");
754
755 if (HasFSGSBASE)
756 Builder.defineMacro("__FSGSBASE__");
757
758 if (HasBMI)
759 Builder.defineMacro("__BMI__");
760
761 if (HasBMI2)
762 Builder.defineMacro("__BMI2__");
763
764 if (HasPOPCNT)
765 Builder.defineMacro("__POPCNT__");
766
767 if (HasRTM)
768 Builder.defineMacro("__RTM__");
769
770 if (HasPRFCHW)
771 Builder.defineMacro("__PRFCHW__");
772
773 if (HasRDSEED)
774 Builder.defineMacro("__RDSEED__");
775
776 if (HasADX)
777 Builder.defineMacro("__ADX__");
778
779 if (HasTBM)
780 Builder.defineMacro("__TBM__");
781
782 if (HasLWP)
783 Builder.defineMacro("__LWP__");
784
785 if (HasMWAITX)
786 Builder.defineMacro("__MWAITX__");
787
788 if (HasMOVBE)
789 Builder.defineMacro("__MOVBE__");
790
791 switch (XOPLevel) {
792 case XOP:
793 Builder.defineMacro("__XOP__");
794 [[fallthrough]];
795 case FMA4:
796 Builder.defineMacro("__FMA4__");
797 [[fallthrough]];
798 case SSE4A:
799 Builder.defineMacro("__SSE4A__");
800 [[fallthrough]];
801 case NoXOP:
802 break;
803 }
804
805 if (HasFMA)
806 Builder.defineMacro("__FMA__");
807
808 if (HasF16C)
809 Builder.defineMacro("__F16C__");
810
811 if (HasGFNI)
812 Builder.defineMacro("__GFNI__");
813
814 if (HasAVX10_1) {
815 Builder.defineMacro("__AVX10_1__");
816 Builder.defineMacro("__AVX10_1_512__");
817 }
818 if (HasAVX10_2) {
819 Builder.defineMacro("__AVX10_2__");
820 Builder.defineMacro("__AVX10_2_512__");
821 }
822 if (HasAVX512CD)
823 Builder.defineMacro("__AVX512CD__");
824 if (HasAVX512VPOPCNTDQ)
825 Builder.defineMacro("__AVX512VPOPCNTDQ__");
826 if (HasAVX512VNNI)
827 Builder.defineMacro("__AVX512VNNI__");
828 if (HasAVX512BF16)
829 Builder.defineMacro("__AVX512BF16__");
830 if (HasAVX512FP16)
831 Builder.defineMacro("__AVX512FP16__");
832 if (HasAVX512DQ)
833 Builder.defineMacro("__AVX512DQ__");
834 if (HasAVX512BITALG)
835 Builder.defineMacro("__AVX512BITALG__");
836 if (HasAVX512BW)
837 Builder.defineMacro("__AVX512BW__");
838 if (HasAVX512VL) {
839 Builder.defineMacro("__AVX512VL__");
840 }
841 if (HasAVX512VBMI)
842 Builder.defineMacro("__AVX512VBMI__");
843 if (HasAVX512VBMI2)
844 Builder.defineMacro("__AVX512VBMI2__");
845 if (HasAVX512IFMA)
846 Builder.defineMacro("__AVX512IFMA__");
847 if (HasAVX512VP2INTERSECT)
848 Builder.defineMacro("__AVX512VP2INTERSECT__");
849 if (HasSHA)
850 Builder.defineMacro("__SHA__");
851 if (HasSHA512)
852 Builder.defineMacro("__SHA512__");
853
854 if (HasFXSR)
855 Builder.defineMacro("__FXSR__");
856 if (HasXSAVE)
857 Builder.defineMacro("__XSAVE__");
858 if (HasXSAVEOPT)
859 Builder.defineMacro("__XSAVEOPT__");
860 if (HasXSAVEC)
861 Builder.defineMacro("__XSAVEC__");
862 if (HasXSAVES)
863 Builder.defineMacro("__XSAVES__");
864 if (HasPKU)
865 Builder.defineMacro("__PKU__");
866 if (HasCLFLUSHOPT)
867 Builder.defineMacro("__CLFLUSHOPT__");
868 if (HasCLWB)
869 Builder.defineMacro("__CLWB__");
870 if (HasWBNOINVD)
871 Builder.defineMacro("__WBNOINVD__");
872 if (HasSHSTK)
873 Builder.defineMacro("__SHSTK__");
874 if (HasSGX)
875 Builder.defineMacro("__SGX__");
876 if (HasSM3)
877 Builder.defineMacro("__SM3__");
878 if (HasSM4)
879 Builder.defineMacro("__SM4__");
880 if (HasPREFETCHI)
881 Builder.defineMacro("__PREFETCHI__");
882 if (HasCLZERO)
883 Builder.defineMacro("__CLZERO__");
884 if (HasKL)
885 Builder.defineMacro("__KL__");
886 if (HasWIDEKL)
887 Builder.defineMacro("__WIDEKL__");
888 if (HasRDPID)
889 Builder.defineMacro("__RDPID__");
890 if (HasRDPRU)
891 Builder.defineMacro("__RDPRU__");
892 if (HasCLDEMOTE)
893 Builder.defineMacro("__CLDEMOTE__");
894 if (HasWAITPKG)
895 Builder.defineMacro("__WAITPKG__");
896 if (HasMOVDIRI)
897 Builder.defineMacro("__MOVDIRI__");
898 if (HasMOVDIR64B)
899 Builder.defineMacro("__MOVDIR64B__");
900 if (HasMOVRS)
901 Builder.defineMacro("__MOVRS__");
902 if (HasPCONFIG)
903 Builder.defineMacro("__PCONFIG__");
904 if (HasPTWRITE)
905 Builder.defineMacro("__PTWRITE__");
906 if (HasINVPCID)
907 Builder.defineMacro("__INVPCID__");
908 if (HasENQCMD)
909 Builder.defineMacro("__ENQCMD__");
910 if (HasHRESET)
911 Builder.defineMacro("__HRESET__");
912 if (HasAMXTILE)
913 Builder.defineMacro("__AMX_TILE__");
914 if (HasAMXINT8)
915 Builder.defineMacro("__AMX_INT8__");
916 if (HasAMXBF16)
917 Builder.defineMacro("__AMX_BF16__");
918 if (HasAMXFP16)
919 Builder.defineMacro("__AMX_FP16__");
920 if (HasAMXCOMPLEX)
921 Builder.defineMacro("__AMX_COMPLEX__");
922 if (HasAMXFP8)
923 Builder.defineMacro("__AMX_FP8__");
924 if (HasAMXMOVRS)
925 Builder.defineMacro("__AMX_MOVRS__");
926 if (HasAMXTRANSPOSE)
927 Builder.defineMacro("__AMX_TRANSPOSE__");
928 if (HasAMXAVX512)
929 Builder.defineMacro("__AMX_AVX512__");
930 if (HasAMXTF32)
931 Builder.defineMacro("__AMX_TF32__");
932 if (HasCMPCCXADD)
933 Builder.defineMacro("__CMPCCXADD__");
934 if (HasRAOINT)
935 Builder.defineMacro("__RAOINT__");
936 if (HasAVXIFMA)
937 Builder.defineMacro("__AVXIFMA__");
938 if (HasAVXNECONVERT)
939 Builder.defineMacro("__AVXNECONVERT__");
940 if (HasAVXVNNI)
941 Builder.defineMacro("__AVXVNNI__");
942 if (HasAVXVNNIINT16)
943 Builder.defineMacro("__AVXVNNIINT16__");
944 if (HasAVXVNNIINT8)
945 Builder.defineMacro("__AVXVNNIINT8__");
946 if (HasSERIALIZE)
947 Builder.defineMacro("__SERIALIZE__");
948 if (HasTSXLDTRK)
949 Builder.defineMacro("__TSXLDTRK__");
950 if (HasUINTR)
951 Builder.defineMacro("__UINTR__");
952 if (HasUSERMSR)
953 Builder.defineMacro("__USERMSR__");
954 if (HasCRC32)
955 Builder.defineMacro("__CRC32__");
956 if (HasEGPR)
957 Builder.defineMacro("__EGPR__");
958 if (HasPush2Pop2)
959 Builder.defineMacro("__PUSH2POP2__");
960 if (HasPPX)
961 Builder.defineMacro("__PPX__");
962 if (HasNDD)
963 Builder.defineMacro("__NDD__");
964 if (HasCCMP)
965 Builder.defineMacro("__CCMP__");
966 if (HasNF)
967 Builder.defineMacro("__NF__");
968 if (HasCF)
969 Builder.defineMacro("__CF__");
970 if (HasZU)
971 Builder.defineMacro("__ZU__");
972 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF && HasZU)
973 Builder.defineMacro("__APX_F__");
974 if (HasEGPR && HasInlineAsmUseGPR32)
975 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
976
977 // Each case falls through to the previous one here.
978 switch (SSELevel) {
979 case AVX512F:
980 Builder.defineMacro("__AVX512F__");
981 [[fallthrough]];
982 case AVX2:
983 Builder.defineMacro("__AVX2__");
984 [[fallthrough]];
985 case AVX:
986 Builder.defineMacro("__AVX__");
987 [[fallthrough]];
988 case SSE42:
989 Builder.defineMacro("__SSE4_2__");
990 [[fallthrough]];
991 case SSE41:
992 Builder.defineMacro("__SSE4_1__");
993 [[fallthrough]];
994 case SSSE3:
995 Builder.defineMacro("__SSSE3__");
996 [[fallthrough]];
997 case SSE3:
998 Builder.defineMacro("__SSE3__");
999 [[fallthrough]];
1000 case SSE2:
1001 Builder.defineMacro("__SSE2__");
1002 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1003 [[fallthrough]];
1004 case SSE1:
1005 Builder.defineMacro("__SSE__");
1006 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1007 [[fallthrough]];
1008 case NoSSE:
1009 break;
1010 }
1011
1012 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1013 switch (SSELevel) {
1014 case AVX512F:
1015 case AVX2:
1016 case AVX:
1017 case SSE42:
1018 case SSE41:
1019 case SSSE3:
1020 case SSE3:
1021 case SSE2:
1022 Builder.defineMacro("_M_IX86_FP", Twine(2));
1023 break;
1024 case SSE1:
1025 Builder.defineMacro("_M_IX86_FP", Twine(1));
1026 break;
1027 default:
1028 Builder.defineMacro("_M_IX86_FP", Twine(0));
1029 break;
1030 }
1031 }
1032
1033 // Each case falls through to the previous one here.
1034 if (HasMMX) {
1035 Builder.defineMacro("__MMX__");
1036 }
1037
1038 if (CPU >= CK_i486 || CPU == CK_None) {
1039 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1040 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1041 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1042 }
1043 if (HasCX8)
1044 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1045 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1046 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1047
1048 if (HasFloat128)
1049 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1050
1051 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1052 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1053 Opts.CFProtectionBranch});
1054}
1055
1056bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1057 return llvm::StringSwitch<bool>(Name)
1058 .Case("adx", true)
1059 .Case("aes", true)
1060 .Case("amx-avx512", true)
1061 .Case("amx-bf16", true)
1062 .Case("amx-complex", true)
1063 .Case("amx-fp16", true)
1064 .Case("amx-fp8", true)
1065 .Case("amx-int8", true)
1066 .Case("amx-movrs", true)
1067 .Case("amx-tf32", true)
1068 .Case("amx-tile", true)
1069 .Case("amx-transpose", true)
1070 .Case("avx", true)
1071 .Case("avx10.1", true)
1072 .Case("avx10.2", true)
1073 .Case("avx2", true)
1074 .Case("avx512f", true)
1075 .Case("avx512cd", true)
1076 .Case("avx512vpopcntdq", true)
1077 .Case("avx512vnni", true)
1078 .Case("avx512bf16", true)
1079 .Case("avx512fp16", true)
1080 .Case("avx512dq", true)
1081 .Case("avx512bitalg", true)
1082 .Case("avx512bw", true)
1083 .Case("avx512vl", true)
1084 .Case("avx512vbmi", true)
1085 .Case("avx512vbmi2", true)
1086 .Case("avx512ifma", true)
1087 .Case("avx512vp2intersect", true)
1088 .Case("avxifma", true)
1089 .Case("avxneconvert", true)
1090 .Case("avxvnni", true)
1091 .Case("avxvnniint16", true)
1092 .Case("avxvnniint8", true)
1093 .Case("bmi", true)
1094 .Case("bmi2", true)
1095 .Case("cldemote", true)
1096 .Case("clflushopt", true)
1097 .Case("clwb", true)
1098 .Case("clzero", true)
1099 .Case("cmpccxadd", true)
1100 .Case("crc32", true)
1101 .Case("cx16", true)
1102 .Case("enqcmd", true)
1103 .Case("f16c", true)
1104 .Case("fma", true)
1105 .Case("fma4", true)
1106 .Case("fsgsbase", true)
1107 .Case("fxsr", true)
1108 .Case("general-regs-only", true)
1109 .Case("gfni", true)
1110 .Case("hreset", true)
1111 .Case("invpcid", true)
1112 .Case("kl", true)
1113 .Case("widekl", true)
1114 .Case("lwp", true)
1115 .Case("lzcnt", true)
1116 .Case("mmx", true)
1117 .Case("movbe", true)
1118 .Case("movrs", true)
1119 .Case("movdiri", true)
1120 .Case("movdir64b", true)
1121 .Case("mwaitx", true)
1122 .Case("pclmul", true)
1123 .Case("pconfig", true)
1124 .Case("pku", true)
1125 .Case("popcnt", true)
1126 .Case("prefer-256-bit", true)
1127 .Case("prefetchi", true)
1128 .Case("prfchw", true)
1129 .Case("ptwrite", true)
1130 .Case("raoint", true)
1131 .Case("rdpid", true)
1132 .Case("rdpru", true)
1133 .Case("rdrnd", true)
1134 .Case("rdseed", true)
1135 .Case("rtm", true)
1136 .Case("sahf", true)
1137 .Case("serialize", true)
1138 .Case("sgx", true)
1139 .Case("sha", true)
1140 .Case("sha512", true)
1141 .Case("shstk", true)
1142 .Case("sm3", true)
1143 .Case("sm4", true)
1144 .Case("sse", true)
1145 .Case("sse2", true)
1146 .Case("sse3", true)
1147 .Case("ssse3", true)
1148 .Case("sse4", true)
1149 .Case("sse4.1", true)
1150 .Case("sse4.2", true)
1151 .Case("sse4a", true)
1152 .Case("tbm", true)
1153 .Case("tsxldtrk", true)
1154 .Case("uintr", true)
1155 .Case("usermsr", true)
1156 .Case("vaes", true)
1157 .Case("vpclmulqdq", true)
1158 .Case("wbnoinvd", true)
1159 .Case("waitpkg", true)
1160 .Case("x87", true)
1161 .Case("xop", true)
1162 .Case("xsave", true)
1163 .Case("xsavec", true)
1164 .Case("xsaves", true)
1165 .Case("xsaveopt", true)
1166 .Case("egpr", true)
1167 .Case("push2pop2", true)
1168 .Case("ppx", true)
1169 .Case("ndd", true)
1170 .Case("ccmp", true)
1171 .Case("nf", true)
1172 .Case("cf", true)
1173 .Case("zu", true)
1174 .Default(false);
1175}
1176
1177bool X86TargetInfo::hasFeature(StringRef Feature) const {
1178 return llvm::StringSwitch<bool>(Feature)
1179 .Case("adx", HasADX)
1180 .Case("aes", HasAES)
1181 .Case("amx-avx512", HasAMXAVX512)
1182 .Case("amx-bf16", HasAMXBF16)
1183 .Case("amx-complex", HasAMXCOMPLEX)
1184 .Case("amx-fp16", HasAMXFP16)
1185 .Case("amx-fp8", HasAMXFP8)
1186 .Case("amx-int8", HasAMXINT8)
1187 .Case("amx-movrs", HasAMXMOVRS)
1188 .Case("amx-tf32", HasAMXTF32)
1189 .Case("amx-tile", HasAMXTILE)
1190 .Case("amx-transpose", HasAMXTRANSPOSE)
1191 .Case("avx", SSELevel >= AVX)
1192 .Case("avx10.1", HasAVX10_1)
1193 .Case("avx10.2", HasAVX10_2)
1194 .Case("avx2", SSELevel >= AVX2)
1195 .Case("avx512f", SSELevel >= AVX512F)
1196 .Case("avx512cd", HasAVX512CD)
1197 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1198 .Case("avx512vnni", HasAVX512VNNI)
1199 .Case("avx512bf16", HasAVX512BF16)
1200 .Case("avx512fp16", HasAVX512FP16)
1201 .Case("avx512dq", HasAVX512DQ)
1202 .Case("avx512bitalg", HasAVX512BITALG)
1203 .Case("avx512bw", HasAVX512BW)
1204 .Case("avx512vl", HasAVX512VL)
1205 .Case("avx512vbmi", HasAVX512VBMI)
1206 .Case("avx512vbmi2", HasAVX512VBMI2)
1207 .Case("avx512ifma", HasAVX512IFMA)
1208 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1209 .Case("avxifma", HasAVXIFMA)
1210 .Case("avxneconvert", HasAVXNECONVERT)
1211 .Case("avxvnni", HasAVXVNNI)
1212 .Case("avxvnniint16", HasAVXVNNIINT16)
1213 .Case("avxvnniint8", HasAVXVNNIINT8)
1214 .Case("bmi", HasBMI)
1215 .Case("bmi2", HasBMI2)
1216 .Case("cldemote", HasCLDEMOTE)
1217 .Case("clflushopt", HasCLFLUSHOPT)
1218 .Case("clwb", HasCLWB)
1219 .Case("clzero", HasCLZERO)
1220 .Case("cmpccxadd", HasCMPCCXADD)
1221 .Case("crc32", HasCRC32)
1222 .Case("cx8", HasCX8)
1223 .Case("cx16", HasCX16)
1224 .Case("enqcmd", HasENQCMD)
1225 .Case("f16c", HasF16C)
1226 .Case("fma", HasFMA)
1227 .Case("fma4", XOPLevel >= FMA4)
1228 .Case("fsgsbase", HasFSGSBASE)
1229 .Case("fxsr", HasFXSR)
1230 .Case("gfni", HasGFNI)
1231 .Case("hreset", HasHRESET)
1232 .Case("invpcid", HasINVPCID)
1233 .Case("kl", HasKL)
1234 .Case("widekl", HasWIDEKL)
1235 .Case("lwp", HasLWP)
1236 .Case("lzcnt", HasLZCNT)
1237 .Case("mmx", HasMMX)
1238 .Case("movbe", HasMOVBE)
1239 .Case("movrs", HasMOVRS)
1240 .Case("movdiri", HasMOVDIRI)
1241 .Case("movdir64b", HasMOVDIR64B)
1242 .Case("mwaitx", HasMWAITX)
1243 .Case("pclmul", HasPCLMUL)
1244 .Case("pconfig", HasPCONFIG)
1245 .Case("pku", HasPKU)
1246 .Case("popcnt", HasPOPCNT)
1247 .Case("prefetchi", HasPREFETCHI)
1248 .Case("prfchw", HasPRFCHW)
1249 .Case("ptwrite", HasPTWRITE)
1250 .Case("raoint", HasRAOINT)
1251 .Case("rdpid", HasRDPID)
1252 .Case("rdpru", HasRDPRU)
1253 .Case("rdrnd", HasRDRND)
1254 .Case("rdseed", HasRDSEED)
1255 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1256 .Case("rtm", HasRTM)
1257 .Case("sahf", HasLAHFSAHF)
1258 .Case("serialize", HasSERIALIZE)
1259 .Case("sgx", HasSGX)
1260 .Case("sha", HasSHA)
1261 .Case("sha512", HasSHA512)
1262 .Case("shstk", HasSHSTK)
1263 .Case("sm3", HasSM3)
1264 .Case("sm4", HasSM4)
1265 .Case("sse", SSELevel >= SSE1)
1266 .Case("sse2", SSELevel >= SSE2)
1267 .Case("sse3", SSELevel >= SSE3)
1268 .Case("ssse3", SSELevel >= SSSE3)
1269 .Case("sse4.1", SSELevel >= SSE41)
1270 .Case("sse4.2", SSELevel >= SSE42)
1271 .Case("sse4a", XOPLevel >= SSE4A)
1272 .Case("tbm", HasTBM)
1273 .Case("tsxldtrk", HasTSXLDTRK)
1274 .Case("uintr", HasUINTR)
1275 .Case("usermsr", HasUSERMSR)
1276 .Case("vaes", HasVAES)
1277 .Case("vpclmulqdq", HasVPCLMULQDQ)
1278 .Case("wbnoinvd", HasWBNOINVD)
1279 .Case("waitpkg", HasWAITPKG)
1280 .Case("x86", true)
1281 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1282 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1283 .Case("x87", HasX87)
1284 .Case("xop", XOPLevel >= XOP)
1285 .Case("xsave", HasXSAVE)
1286 .Case("xsavec", HasXSAVEC)
1287 .Case("xsaves", HasXSAVES)
1288 .Case("xsaveopt", HasXSAVEOPT)
1289 .Case("fullbf16", HasFullBFloat16)
1290 .Case("egpr", HasEGPR)
1291 .Case("push2pop2", HasPush2Pop2)
1292 .Case("ppx", HasPPX)
1293 .Case("ndd", HasNDD)
1294 .Case("ccmp", HasCCMP)
1295 .Case("nf", HasNF)
1296 .Case("cf", HasCF)
1297 .Case("zu", HasZU)
1298 .Case("branch-hint", HasBranchHint)
1299 .Default(false);
1300}
1301
1302// We can't use a generic validation scheme for the features accepted here
1303// versus subtarget features accepted in the target attribute because the
1304// bitfield structure that's initialized in the runtime only supports the
1305// below currently rather than the full range of subtarget features. (See
1306// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1307bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1308 return llvm::StringSwitch<bool>(FeatureStr)
1309#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1310#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true)
1311#include "llvm/TargetParser/X86TargetParser.def"
1312 .Default(false);
1313}
1314
1315static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1316 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1317#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1318 .Case(STR, llvm::X86::FEATURE_##ENUM)
1319
1320#include "llvm/TargetParser/X86TargetParser.def"
1321 ;
1322 // Note, this function should only be used after ensuring the value is
1323 // correct, so it asserts if the value is out of range.
1324}
1325
1326llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1327 auto getPriority = [](StringRef Feature) -> unsigned {
1328 // Valid CPUs have a 'key feature' that compares just better than its key
1329 // feature.
1330 using namespace llvm::X86;
1331 CPUKind Kind = parseArchX86(Feature);
1332 if (Kind != CK_None) {
1333 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1334 return (getFeaturePriority(KeyFeature) << 1) + 1;
1335 }
1336 // Now we know we have a feature, so get its priority and shift it a few so
1337 // that we have sufficient room for the CPUs (above).
1338 return getFeaturePriority(getFeature(Feature)) << 1;
1339 };
1340
1341 unsigned Priority = 0;
1342 for (StringRef Feature : Features)
1343 if (!Feature.empty())
1344 Priority = std::max(Priority, getPriority(Feature));
1345 return llvm::APInt(32, Priority);
1346}
1347
1348bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1349 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1350}
1351
1352char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1353 return llvm::X86::getCPUDispatchMangling(Name);
1354}
1355
1356void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1357 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1358 SmallVector<StringRef, 32> TargetCPUFeatures;
1359 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1360 for (auto &F : TargetCPUFeatures)
1361 Features.push_back(F);
1362}
1363
1364// We can't use a generic validation scheme for the cpus accepted here
1365// versus subtarget cpus accepted in the target attribute because the
1366// variables intitialized by the runtime only support the below currently
1367// rather than the full range of cpus.
1368bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1369 return llvm::StringSwitch<bool>(FeatureStr)
1370#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1371#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1372#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1373#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1374#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1375#include "llvm/TargetParser/X86TargetParser.def"
1376 .Default(false);
1377}
1378
1379static unsigned matchAsmCCConstraint(const char *Name) {
1380 auto RV = llvm::StringSwitch<unsigned>(Name)
1381 .Case("@cca", 4)
1382 .Case("@ccae", 5)
1383 .Case("@ccb", 4)
1384 .Case("@ccbe", 5)
1385 .Case("@ccc", 4)
1386 .Case("@cce", 4)
1387 .Case("@ccz", 4)
1388 .Case("@ccg", 4)
1389 .Case("@ccge", 5)
1390 .Case("@ccl", 4)
1391 .Case("@ccle", 5)
1392 .Case("@ccna", 5)
1393 .Case("@ccnae", 6)
1394 .Case("@ccnb", 5)
1395 .Case("@ccnbe", 6)
1396 .Case("@ccnc", 5)
1397 .Case("@ccne", 5)
1398 .Case("@ccnz", 5)
1399 .Case("@ccng", 5)
1400 .Case("@ccnge", 6)
1401 .Case("@ccnl", 5)
1402 .Case("@ccnle", 6)
1403 .Case("@ccno", 5)
1404 .Case("@ccnp", 5)
1405 .Case("@ccns", 5)
1406 .Case("@cco", 4)
1407 .Case("@ccp", 4)
1408 .Case("@ccs", 4)
1409 .Default(0);
1410 return RV;
1411}
1412
1413bool X86TargetInfo::validateAsmConstraint(
1414 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1415 switch (*Name) {
1416 default:
1417 return false;
1418 // Constant constraints.
1419 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1420 // instructions.
1421 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1422 // x86_64 instructions.
1423 case 's':
1424 Info.setRequiresImmediate();
1425 return true;
1426 case 'I':
1427 Info.setRequiresImmediate(0, 31);
1428 return true;
1429 case 'J':
1430 Info.setRequiresImmediate(0, 63);
1431 return true;
1432 case 'K':
1433 Info.setRequiresImmediate(-128, 127);
1434 return true;
1435 case 'L':
1436 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1437 return true;
1438 case 'M':
1439 Info.setRequiresImmediate(0, 3);
1440 return true;
1441 case 'N':
1442 Info.setRequiresImmediate(0, 255);
1443 return true;
1444 case 'O':
1445 Info.setRequiresImmediate(0, 127);
1446 return true;
1447 case 'W':
1448 switch (*++Name) {
1449 default:
1450 return false;
1451 case 's':
1452 Info.setAllowsRegister();
1453 return true;
1454 }
1455 // Register constraints.
1456 case 'Y': // 'Y' is the first character for several 2-character constraints.
1457 // Shift the pointer to the second character of the constraint.
1458 Name++;
1459 switch (*Name) {
1460 default:
1461 return false;
1462 case 'z': // First SSE register.
1463 case '2':
1464 case 't': // Any SSE register, when SSE2 is enabled.
1465 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1466 case 'm': // Any MMX register, when inter-unit moves enabled.
1467 case 'k': // AVX512 arch mask registers: k1-k7.
1468 Info.setAllowsRegister();
1469 return true;
1470 }
1471 case 'f': // Any x87 floating point stack register.
1472 // Constraint 'f' cannot be used for output operands.
1473 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1474 return false;
1475 Info.setAllowsRegister();
1476 return true;
1477 case 'a': // eax.
1478 case 'b': // ebx.
1479 case 'c': // ecx.
1480 case 'd': // edx.
1481 case 'S': // esi.
1482 case 'D': // edi.
1483 case 'A': // edx:eax.
1484 case 't': // Top of floating point stack.
1485 case 'u': // Second from top of floating point stack.
1486 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1487 case 'y': // Any MMX register.
1488 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1489 case 'x': // Any SSE register.
1490 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1491 // for intermideate k reg operations).
1492 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1493 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1494 case 'l': // "Index" registers: any general register that can be used as an
1495 // index in a base+index memory access.
1496 Info.setAllowsRegister();
1497 return true;
1498 // Floating point constant constraints.
1499 case 'C': // SSE floating point constant.
1500 case 'G': // x87 floating point constant.
1501 return true;
1502 case 'j':
1503 Name++;
1504 switch (*Name) {
1505 default:
1506 return false;
1507 case 'r':
1508 Info.setAllowsRegister();
1509 return true;
1510 case 'R':
1511 Info.setAllowsRegister();
1512 return true;
1513 }
1514 case '@':
1515 // CC condition changes.
1516 if (auto Len = matchAsmCCConstraint(Name)) {
1517 Name += Len - 1;
1518 Info.setAllowsRegister();
1519 return true;
1520 }
1521 return false;
1522 }
1523}
1524
1525// Below is based on the following information:
1526// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1527// | Processor Name | Cache Line Size (Bytes) | Source |
1528// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1529// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1530// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1531// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1532// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1533// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1534// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1535// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1536// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1537// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1538// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1539// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1540// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1541// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1542// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1543// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1544// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1545// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1546// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1547std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1548 using namespace llvm::X86;
1549 switch (CPU) {
1550 // i386
1551 case CK_i386:
1552 // i486
1553 case CK_i486:
1554 case CK_WinChipC6:
1555 case CK_WinChip2:
1556 case CK_C3:
1557 // Lakemont
1558 case CK_Lakemont:
1559 return 16;
1560
1561 // i586
1562 case CK_i586:
1563 case CK_Pentium:
1564 case CK_PentiumMMX:
1565 // i686
1566 case CK_PentiumPro:
1567 case CK_i686:
1568 case CK_Pentium2:
1569 case CK_Pentium3:
1570 case CK_PentiumM:
1571 case CK_C3_2:
1572 // K6
1573 case CK_K6:
1574 case CK_K6_2:
1575 case CK_K6_3:
1576 // Geode
1577 case CK_Geode:
1578 return 32;
1579
1580 // Netburst
1581 case CK_Pentium4:
1582 case CK_Prescott:
1583 case CK_Nocona:
1584 // Atom
1585 case CK_Bonnell:
1586 case CK_Silvermont:
1587 case CK_Goldmont:
1588 case CK_GoldmontPlus:
1589 case CK_Tremont:
1590 case CK_Gracemont:
1591
1592 case CK_Westmere:
1593 case CK_SandyBridge:
1594 case CK_IvyBridge:
1595 case CK_Haswell:
1596 case CK_Broadwell:
1597 case CK_SkylakeClient:
1598 case CK_SkylakeServer:
1599 case CK_Cascadelake:
1600 case CK_Nehalem:
1601 case CK_Cooperlake:
1602 case CK_Cannonlake:
1603 case CK_Tigerlake:
1604 case CK_SapphireRapids:
1605 case CK_IcelakeClient:
1606 case CK_Rocketlake:
1607 case CK_IcelakeServer:
1608 case CK_Alderlake:
1609 case CK_Raptorlake:
1610 case CK_Meteorlake:
1611 case CK_Arrowlake:
1612 case CK_ArrowlakeS:
1613 case CK_Lunarlake:
1614 case CK_Pantherlake:
1615 case CK_Sierraforest:
1616 case CK_Grandridge:
1617 case CK_Graniterapids:
1618 case CK_GraniterapidsD:
1619 case CK_Emeraldrapids:
1620 case CK_Clearwaterforest:
1621 case CK_Diamondrapids:
1622 case CK_KNL:
1623 case CK_KNM:
1624 // K7
1625 case CK_Athlon:
1626 case CK_AthlonXP:
1627 // K8
1628 case CK_K8:
1629 case CK_K8SSE3:
1630 case CK_AMDFAM10:
1631 // Bobcat
1632 case CK_BTVER1:
1633 case CK_BTVER2:
1634 // Bulldozer
1635 case CK_BDVER1:
1636 case CK_BDVER2:
1637 case CK_BDVER3:
1638 case CK_BDVER4:
1639 // Zen
1640 case CK_ZNVER1:
1641 case CK_ZNVER2:
1642 case CK_ZNVER3:
1643 case CK_ZNVER4:
1644 case CK_ZNVER5:
1645 // Deprecated
1646 case CK_x86_64:
1647 case CK_x86_64_v2:
1648 case CK_x86_64_v3:
1649 case CK_x86_64_v4:
1650 case CK_Yonah:
1651 case CK_Penryn:
1652 case CK_Core2:
1653 return 64;
1654
1655 // The following currently have unknown cache line sizes (but they are probably all 64):
1656 // Core
1657 case CK_None:
1658 return std::nullopt;
1659 }
1660 llvm_unreachable("Unknown CPU kind");
1661}
1662
1663bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1664 StringRef Constraint,
1665 unsigned Size) const {
1666 // Strip off constraint modifiers.
1667 Constraint = Constraint.ltrim("=+&");
1668
1669 return validateOperandSize(FeatureMap, Constraint, Size);
1670}
1671
1672bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1673 StringRef Constraint,
1674 unsigned Size) const {
1675 return validateOperandSize(FeatureMap, Constraint, Size);
1676}
1677
1678bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1679 StringRef Constraint,
1680 unsigned Size) const {
1681 switch (Constraint[0]) {
1682 default:
1683 break;
1684 case 'k':
1685 // Registers k0-k7 (AVX512) size limit is 64 bit.
1686 case 'y':
1687 return Size <= 64;
1688 case 'f':
1689 case 't':
1690 case 'u':
1691 return Size <= 128;
1692 case 'Y':
1693 // 'Y' is the first character for several 2-character constraints.
1694 switch (Constraint[1]) {
1695 default:
1696 return false;
1697 case 'm':
1698 // 'Ym' is synonymous with 'y'.
1699 case 'k':
1700 return Size <= 64;
1701 case 'z':
1702 // XMM0/YMM/ZMM0
1703 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1704 // ZMM0 can be used if target supports AVX512F.
1705 return Size <= 512U;
1706 else if (hasFeatureEnabled(FeatureMap, "avx"))
1707 // YMM0 can be used if target supports AVX.
1708 return Size <= 256U;
1709 else if (hasFeatureEnabled(FeatureMap, "sse"))
1710 return Size <= 128U;
1711 return false;
1712 case 'i':
1713 case 't':
1714 case '2':
1715 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1716 if (SSELevel < SSE2)
1717 return false;
1718 break;
1719 }
1720 break;
1721 case 'v':
1722 case 'x':
1723 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1724 // 512-bit zmm registers can be used if target supports AVX512F.
1725 return Size <= 512U;
1726 else if (hasFeatureEnabled(FeatureMap, "avx"))
1727 // 256-bit ymm registers can be used if target supports AVX.
1728 return Size <= 256U;
1729 return Size <= 128U;
1730
1731 }
1732
1733 return true;
1734}
1735
1736std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1737 switch (*Constraint) {
1738 case '@':
1739 if (auto Len = matchAsmCCConstraint(Constraint)) {
1740 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1741 Constraint += Len - 1;
1742 return Converted;
1743 }
1744 return std::string(1, *Constraint);
1745 case 'a':
1746 return std::string("{ax}");
1747 case 'b':
1748 return std::string("{bx}");
1749 case 'c':
1750 return std::string("{cx}");
1751 case 'd':
1752 return std::string("{dx}");
1753 case 'S':
1754 return std::string("{si}");
1755 case 'D':
1756 return std::string("{di}");
1757 case 'p': // Keep 'p' constraint (address).
1758 return std::string("p");
1759 case 't': // top of floating point stack.
1760 return std::string("{st}");
1761 case 'u': // second from top of floating point stack.
1762 return std::string("{st(1)}"); // second from top of floating point stack.
1763 case 'W':
1764 assert(Constraint[1] == 's');
1765 return '^' + std::string(Constraint++, 2);
1766 case 'Y':
1767 switch (Constraint[1]) {
1768 default:
1769 // Break from inner switch and fall through (copy single char),
1770 // continue parsing after copying the current constraint into
1771 // the return string.
1772 break;
1773 case 'k':
1774 case 'm':
1775 case 'i':
1776 case 't':
1777 case 'z':
1778 case '2':
1779 // "^" hints llvm that this is a 2 letter constraint.
1780 // "Constraint++" is used to promote the string iterator
1781 // to the next constraint.
1782 return std::string("^") + std::string(Constraint++, 2);
1783 }
1784 [[fallthrough]];
1785 case 'j':
1786 switch (Constraint[1]) {
1787 default:
1788 // Break from inner switch and fall through (copy single char),
1789 // continue parsing after copying the current constraint into
1790 // the return string.
1791 break;
1792 case 'r':
1793 case 'R':
1794 // "^" hints llvm that this is a 2 letter constraint.
1795 // "Constraint++" is used to promote the string iterator
1796 // to the next constraint.
1797 return std::string("^") + std::string(Constraint++, 2);
1798 }
1799 [[fallthrough]];
1800 default:
1801 return std::string(1, *Constraint);
1802 }
1803}
1804
1805void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1806 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1807 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1808}
1809
1810void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1811 llvm::X86::fillValidTuneCPUList(Values);
1812}
1813
1817
1821
1822llvm::SmallVector<Builtin::InfosShard>
1823X86_32TargetInfo::getTargetBuiltins() const {
1824 return {
1825 {&X86::BuiltinStrings, X86::BuiltinInfos},
1826 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1827 };
1828}
1829
1830llvm::SmallVector<Builtin::InfosShard>
1831X86_64TargetInfo::getTargetBuiltins() const {
1832 return {
1833 {&X86::BuiltinStrings, X86::BuiltinInfos},
1834 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1835 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1836 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1837 "__builtin_ia32_"},
1838 };
1839}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1467
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:219
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1315
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:231
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1529
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:434
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:323
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1288
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1417
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:562
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:233
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1547
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1413
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1326
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1814
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1352
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1736
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:508
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1356
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1368
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1663
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1678
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1810
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1348
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1307
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1056
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1177
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:214
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:184
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1805
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1818
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1672
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1823
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1831
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:78
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1186
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
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