clang 22.0.0git
X86.cpp
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1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {{"al", "ah", "eax", "rax"}, 0},
102 {{"bl", "bh", "ebx", "rbx"}, 3},
103 {{"cl", "ch", "ecx", "rcx"}, 2},
104 {{"dl", "dh", "edx", "rdx"}, 1},
105 {{"esi", "rsi"}, 4},
106 {{"edi", "rdi"}, 5},
107 {{"esp", "rsp"}, 7},
108 {{"ebp", "rbp"}, 6},
109 {{"r8d", "r8w", "r8b"}, 38},
110 {{"r9d", "r9w", "r9b"}, 39},
111 {{"r10d", "r10w", "r10b"}, 40},
112 {{"r11d", "r11w", "r11b"}, 41},
113 {{"r12d", "r12w", "r12b"}, 42},
114 {{"r13d", "r13w", "r13b"}, 43},
115 {{"r14d", "r14w", "r14b"}, 44},
116 {{"r15d", "r15w", "r15b"}, 45},
117 {{"r16d", "r16w", "r16b"}, 165},
118 {{"r17d", "r17w", "r17b"}, 166},
119 {{"r18d", "r18w", "r18b"}, 167},
120 {{"r19d", "r19w", "r19b"}, 168},
121 {{"r20d", "r20w", "r20b"}, 169},
122 {{"r21d", "r21w", "r21b"}, 170},
123 {{"r22d", "r22w", "r22b"}, 171},
124 {{"r23d", "r23w", "r23b"}, 172},
125 {{"r24d", "r24w", "r24b"}, 173},
126 {{"r25d", "r25w", "r25b"}, 174},
127 {{"r26d", "r26w", "r26b"}, 175},
128 {{"r27d", "r27w", "r27b"}, 176},
129 {{"r28d", "r28w", "r28b"}, 177},
130 {{"r29d", "r29w", "r29b"}, 178},
131 {{"r30d", "r30w", "r30b"}, 179},
132 {{"r31d", "r31w", "r31b"}, 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, "sse2", true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, F, true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back("-x87");
172 UpdatedFeaturesVec.push_back("-mmx");
173 UpdatedFeaturesVec.push_back("-sse");
174 continue;
175 }
176
177 UpdatedFeaturesVec.push_back(Feature);
178 }
179
180 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
181 return false;
182
183 // Can't do this earlier because we need to be able to explicitly enable
184 // or disable these features and the things that they depend upon.
185
186 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
187 auto I = Features.find("sse4.2");
188 if (I != Features.end() && I->getValue() &&
189 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
190 Features["popcnt"] = true;
191
192 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
193 // then enable MMX.
194 I = Features.find("sse");
195 if (I != Features.end() && I->getValue() &&
196 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
197 Features["mmx"] = true;
198
199 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
200 I = Features.find("avx");
201 if (I != Features.end() && I->getValue() &&
202 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
203 Features["xsave"] = true;
204
205 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
206 I = Features.find("sse4.2");
207 if (I != Features.end() && I->getValue() &&
208 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
209 Features["crc32"] = true;
210
211 return true;
212}
213
214void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
215 StringRef Name, bool Enabled) const {
216 if (Name == "sse4") {
217 // We can get here via the __target__ attribute since that's not controlled
218 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
219 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
220 // disabled.
221 if (Enabled)
222 Name = "sse4.2";
223 else
224 Name = "sse4.1";
225 }
226
227 Features[Name] = Enabled;
228 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
229}
230
231/// handleTargetFeatures - Perform initialization based on the user
232/// configured set of features.
233bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
234 DiagnosticsEngine &Diags) {
235 for (const auto &Feature : Features) {
236 if (Feature[0] != '+')
237 continue;
238
239 if (Feature == "+mmx") {
240 HasMMX = true;
241 } else if (Feature == "+aes") {
242 HasAES = true;
243 } else if (Feature == "+vaes") {
244 HasVAES = true;
245 } else if (Feature == "+pclmul") {
246 HasPCLMUL = true;
247 } else if (Feature == "+vpclmulqdq") {
248 HasVPCLMULQDQ = true;
249 } else if (Feature == "+lzcnt") {
250 HasLZCNT = true;
251 } else if (Feature == "+rdrnd") {
252 HasRDRND = true;
253 } else if (Feature == "+fsgsbase") {
254 HasFSGSBASE = true;
255 } else if (Feature == "+bmi") {
256 HasBMI = true;
257 } else if (Feature == "+bmi2") {
258 HasBMI2 = true;
259 } else if (Feature == "+popcnt") {
260 HasPOPCNT = true;
261 } else if (Feature == "+rtm") {
262 HasRTM = true;
263 } else if (Feature == "+prfchw") {
264 HasPRFCHW = true;
265 } else if (Feature == "+rdseed") {
266 HasRDSEED = true;
267 } else if (Feature == "+adx") {
268 HasADX = true;
269 } else if (Feature == "+tbm") {
270 HasTBM = true;
271 } else if (Feature == "+lwp") {
272 HasLWP = true;
273 } else if (Feature == "+fma") {
274 HasFMA = true;
275 } else if (Feature == "+f16c") {
276 HasF16C = true;
277 } else if (Feature == "+gfni") {
278 HasGFNI = true;
279 } else if (Feature == "+avx10.1") {
280 HasAVX10_1 = true;
281 } else if (Feature == "+avx10.2") {
282 HasAVX10_2 = true;
283 HasFullBFloat16 = true;
284 } else if (Feature == "+avx512cd") {
285 HasAVX512CD = true;
286 } else if (Feature == "+avx512vpopcntdq") {
287 HasAVX512VPOPCNTDQ = true;
288 } else if (Feature == "+avx512vnni") {
289 HasAVX512VNNI = true;
290 } else if (Feature == "+avx512bf16") {
291 HasAVX512BF16 = true;
292 } else if (Feature == "+avx512fp16") {
293 HasAVX512FP16 = true;
294 HasFastHalfType = true;
295 } else if (Feature == "+avx512dq") {
296 HasAVX512DQ = true;
297 } else if (Feature == "+avx512bitalg") {
298 HasAVX512BITALG = true;
299 } else if (Feature == "+avx512bw") {
300 HasAVX512BW = true;
301 } else if (Feature == "+avx512vl") {
302 HasAVX512VL = true;
303 } else if (Feature == "+avx512vbmi") {
304 HasAVX512VBMI = true;
305 } else if (Feature == "+avx512vbmi2") {
306 HasAVX512VBMI2 = true;
307 } else if (Feature == "+avx512ifma") {
308 HasAVX512IFMA = true;
309 } else if (Feature == "+avx512vp2intersect") {
310 HasAVX512VP2INTERSECT = true;
311 } else if (Feature == "+sha") {
312 HasSHA = true;
313 } else if (Feature == "+sha512") {
314 HasSHA512 = true;
315 } else if (Feature == "+shstk") {
316 HasSHSTK = true;
317 } else if (Feature == "+sm3") {
318 HasSM3 = true;
319 } else if (Feature == "+sm4") {
320 HasSM4 = true;
321 } else if (Feature == "+movbe") {
322 HasMOVBE = true;
323 } else if (Feature == "+movrs") {
324 HasMOVRS = true;
325 } else if (Feature == "+sgx") {
326 HasSGX = true;
327 } else if (Feature == "+cx8") {
328 HasCX8 = true;
329 } else if (Feature == "+cx16") {
330 HasCX16 = true;
331 } else if (Feature == "+fxsr") {
332 HasFXSR = true;
333 } else if (Feature == "+xsave") {
334 HasXSAVE = true;
335 } else if (Feature == "+xsaveopt") {
336 HasXSAVEOPT = true;
337 } else if (Feature == "+xsavec") {
338 HasXSAVEC = true;
339 } else if (Feature == "+xsaves") {
340 HasXSAVES = true;
341 } else if (Feature == "+mwaitx") {
342 HasMWAITX = true;
343 } else if (Feature == "+pku") {
344 HasPKU = true;
345 } else if (Feature == "+clflushopt") {
346 HasCLFLUSHOPT = true;
347 } else if (Feature == "+clwb") {
348 HasCLWB = true;
349 } else if (Feature == "+wbnoinvd") {
350 HasWBNOINVD = true;
351 } else if (Feature == "+prefetchi") {
352 HasPREFETCHI = true;
353 } else if (Feature == "+clzero") {
354 HasCLZERO = true;
355 } else if (Feature == "+cldemote") {
356 HasCLDEMOTE = true;
357 } else if (Feature == "+rdpid") {
358 HasRDPID = true;
359 } else if (Feature == "+rdpru") {
360 HasRDPRU = true;
361 } else if (Feature == "+kl") {
362 HasKL = true;
363 } else if (Feature == "+widekl") {
364 HasWIDEKL = true;
365 } else if (Feature == "+retpoline-external-thunk") {
366 HasRetpolineExternalThunk = true;
367 } else if (Feature == "+sahf") {
368 HasLAHFSAHF = true;
369 } else if (Feature == "+waitpkg") {
370 HasWAITPKG = true;
371 } else if (Feature == "+movdiri") {
372 HasMOVDIRI = true;
373 } else if (Feature == "+movdir64b") {
374 HasMOVDIR64B = true;
375 } else if (Feature == "+pconfig") {
376 HasPCONFIG = true;
377 } else if (Feature == "+ptwrite") {
378 HasPTWRITE = true;
379 } else if (Feature == "+invpcid") {
380 HasINVPCID = true;
381 } else if (Feature == "+enqcmd") {
382 HasENQCMD = true;
383 } else if (Feature == "+hreset") {
384 HasHRESET = true;
385 } else if (Feature == "+amx-bf16") {
386 HasAMXBF16 = true;
387 } else if (Feature == "+amx-fp16") {
388 HasAMXFP16 = true;
389 } else if (Feature == "+amx-int8") {
390 HasAMXINT8 = true;
391 } else if (Feature == "+amx-tile") {
392 HasAMXTILE = true;
393 } else if (Feature == "+amx-complex") {
394 HasAMXCOMPLEX = true;
395 } else if (Feature == "+amx-fp8") {
396 HasAMXFP8 = true;
397 } else if (Feature == "+amx-movrs") {
398 HasAMXMOVRS = true;
399 } else if (Feature == "+amx-transpose") {
400 HasAMXTRANSPOSE = true;
401 } else if (Feature == "+amx-avx512") {
402 HasAMXAVX512 = true;
403 } else if (Feature == "+amx-tf32") {
404 HasAMXTF32 = true;
405 } else if (Feature == "+cmpccxadd") {
406 HasCMPCCXADD = true;
407 } else if (Feature == "+raoint") {
408 HasRAOINT = true;
409 } else if (Feature == "+avxifma") {
410 HasAVXIFMA = true;
411 } else if (Feature == "+avxneconvert") {
412 HasAVXNECONVERT= true;
413 } else if (Feature == "+avxvnni") {
414 HasAVXVNNI = true;
415 } else if (Feature == "+avxvnniint16") {
416 HasAVXVNNIINT16 = true;
417 } else if (Feature == "+avxvnniint8") {
418 HasAVXVNNIINT8 = true;
419 } else if (Feature == "+serialize") {
420 HasSERIALIZE = true;
421 } else if (Feature == "+tsxldtrk") {
422 HasTSXLDTRK = true;
423 } else if (Feature == "+uintr") {
424 HasUINTR = true;
425 } else if (Feature == "+usermsr") {
426 HasUSERMSR = true;
427 } else if (Feature == "+crc32") {
428 HasCRC32 = true;
429 } else if (Feature == "+x87") {
430 HasX87 = true;
431 } else if (Feature == "+fullbf16") {
432 HasFullBFloat16 = true;
433 } else if (Feature == "+egpr") {
434 HasEGPR = true;
435 } else if (Feature == "+inline-asm-use-gpr32") {
436 HasInlineAsmUseGPR32 = true;
437 } else if (Feature == "+push2pop2") {
438 HasPush2Pop2 = true;
439 } else if (Feature == "+ppx") {
440 HasPPX = true;
441 } else if (Feature == "+ndd") {
442 HasNDD = true;
443 } else if (Feature == "+ccmp") {
444 HasCCMP = true;
445 } else if (Feature == "+nf") {
446 HasNF = true;
447 } else if (Feature == "+cf") {
448 HasCF = true;
449 } else if (Feature == "+zu") {
450 HasZU = true;
451 } else if (Feature == "+branch-hint") {
452 HasBranchHint = true;
453 }
454
455 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
456 .Case("+avx512f", AVX512F)
457 .Case("+avx2", AVX2)
458 .Case("+avx", AVX)
459 .Case("+sse4.2", SSE42)
460 .Case("+sse4.1", SSE41)
461 .Case("+ssse3", SSSE3)
462 .Case("+sse3", SSE3)
463 .Case("+sse2", SSE2)
464 .Case("+sse", SSE1)
465 .Default(NoSSE);
466 SSELevel = std::max(SSELevel, Level);
467
468 HasFloat16 = SSELevel >= SSE2;
469
470 // X86 target has bfloat16 emulation support in the backend, where
471 // bfloat16 is treated as a 32-bit float, arithmetic operations are
472 // performed in 32-bit, and the result is converted back to bfloat16.
473 // Truncation and extension between bfloat16 and 32-bit float are supported
474 // by the compiler-rt library. However, native bfloat16 support is currently
475 // not available in the X86 target. Hence, HasFullBFloat16 will be false
476 // until native bfloat16 support is available. HasFullBFloat16 is used to
477 // determine whether to automatically use excess floating point precision
478 // for bfloat16 arithmetic operations in the front-end.
479 HasBFloat16 = SSELevel >= SSE2;
480
481 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
482 .Case("+xop", XOP)
483 .Case("+fma4", FMA4)
484 .Case("+sse4a", SSE4A)
485 .Default(NoXOP);
486 XOPLevel = std::max(XOPLevel, XLevel);
487 }
488
489 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
490 // matches the selected sse level.
491 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
492 (FPMath == FP_387 && SSELevel >= SSE1)) {
493 Diags.Report(diag::err_target_unsupported_fpmath)
494 << (FPMath == FP_SSE ? "sse" : "387");
495 return false;
496 }
497
498 // FIXME: We should allow long double type on 32-bits to match with GCC.
499 // This requires backend to be able to lower f80 without x87 first.
500 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
501 HasLongDouble = false;
502
503 return true;
504}
505
506/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
507/// definitions for this particular subtarget.
508void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
509 MacroBuilder &Builder) const {
510 // Inline assembly supports X86 flag outputs.
511 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
512
513 std::string CodeModel = getTargetOpts().CodeModel;
514 if (CodeModel == "default")
515 CodeModel = "small";
516 Builder.defineMacro("__code_model_" + CodeModel + "__");
517
518 // Target identification.
519 if (getTriple().getArch() == llvm::Triple::x86_64) {
520 Builder.defineMacro("__amd64__");
521 Builder.defineMacro("__amd64");
522 Builder.defineMacro("__x86_64");
523 Builder.defineMacro("__x86_64__");
524 if (getTriple().getArchName() == "x86_64h") {
525 Builder.defineMacro("__x86_64h");
526 Builder.defineMacro("__x86_64h__");
527 }
528 } else {
529 DefineStd(Builder, "i386", Opts);
530 }
531
532 Builder.defineMacro("__SEG_GS");
533 Builder.defineMacro("__SEG_FS");
534 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
535 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
536
537 // Subtarget options.
538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
539 // truly should be based on -mtune options.
540 using namespace llvm::X86;
541 switch (CPU) {
542 case CK_None:
543 break;
544 case CK_i386:
545 // The rest are coming from the i386 define above.
546 Builder.defineMacro("__tune_i386__");
547 break;
548 case CK_i486:
549 case CK_WinChipC6:
550 case CK_WinChip2:
551 case CK_C3:
552 defineCPUMacros(Builder, "i486");
553 break;
554 case CK_PentiumMMX:
555 Builder.defineMacro("__pentium_mmx__");
556 Builder.defineMacro("__tune_pentium_mmx__");
557 [[fallthrough]];
558 case CK_i586:
559 case CK_Pentium:
560 defineCPUMacros(Builder, "i586");
561 defineCPUMacros(Builder, "pentium");
562 break;
563 case CK_Pentium3:
564 case CK_PentiumM:
565 Builder.defineMacro("__tune_pentium3__");
566 [[fallthrough]];
567 case CK_Pentium2:
568 case CK_C3_2:
569 Builder.defineMacro("__tune_pentium2__");
570 [[fallthrough]];
571 case CK_PentiumPro:
572 case CK_i686:
573 defineCPUMacros(Builder, "i686");
574 defineCPUMacros(Builder, "pentiumpro");
575 break;
576 case CK_Pentium4:
577 defineCPUMacros(Builder, "pentium4");
578 break;
579 case CK_Yonah:
580 case CK_Prescott:
581 case CK_Nocona:
582 defineCPUMacros(Builder, "nocona");
583 break;
584 case CK_Core2:
585 case CK_Penryn:
586 defineCPUMacros(Builder, "core2");
587 break;
588 case CK_Bonnell:
589 defineCPUMacros(Builder, "atom");
590 break;
591 case CK_Silvermont:
592 defineCPUMacros(Builder, "slm");
593 break;
594 case CK_Goldmont:
595 defineCPUMacros(Builder, "goldmont");
596 break;
597 case CK_GoldmontPlus:
598 defineCPUMacros(Builder, "goldmont_plus");
599 break;
600 case CK_Tremont:
601 defineCPUMacros(Builder, "tremont");
602 break;
603 // Gracemont and later atom-cores use P-core cpu macros.
604 case CK_Gracemont:
605 case CK_Nehalem:
606 case CK_Westmere:
607 case CK_SandyBridge:
608 case CK_IvyBridge:
609 case CK_Haswell:
610 case CK_Broadwell:
611 case CK_SkylakeClient:
612 case CK_SkylakeServer:
613 case CK_Cascadelake:
614 case CK_Cooperlake:
615 case CK_Cannonlake:
616 case CK_IcelakeClient:
617 case CK_Rocketlake:
618 case CK_IcelakeServer:
619 case CK_Tigerlake:
620 case CK_SapphireRapids:
621 case CK_Alderlake:
622 case CK_Raptorlake:
623 case CK_Meteorlake:
624 case CK_Arrowlake:
625 case CK_ArrowlakeS:
626 case CK_Lunarlake:
627 case CK_Pantherlake:
628 case CK_Wildcatlake:
629 case CK_Sierraforest:
630 case CK_Grandridge:
631 case CK_Graniterapids:
632 case CK_GraniterapidsD:
633 case CK_Emeraldrapids:
634 case CK_Clearwaterforest:
635 case CK_Diamondrapids:
636 // FIXME: Historically, we defined this legacy name, it would be nice to
637 // remove it at some point. We've never exposed fine-grained names for
638 // recent primary x86 CPUs, and we should keep it that way.
639 defineCPUMacros(Builder, "corei7");
640 break;
641 case CK_KNL:
642 defineCPUMacros(Builder, "knl");
643 break;
644 case CK_KNM:
645 break;
646 case CK_Lakemont:
647 defineCPUMacros(Builder, "i586", /*Tuning*/false);
648 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
649 Builder.defineMacro("__tune_lakemont__");
650 break;
651 case CK_K6_2:
652 Builder.defineMacro("__k6_2__");
653 Builder.defineMacro("__tune_k6_2__");
654 [[fallthrough]];
655 case CK_K6_3:
656 if (CPU != CK_K6_2) { // In case of fallthrough
657 // FIXME: GCC may be enabling these in cases where some other k6
658 // architecture is specified but -m3dnow is explicitly provided. The
659 // exact semantics need to be determined and emulated here.
660 Builder.defineMacro("__k6_3__");
661 Builder.defineMacro("__tune_k6_3__");
662 }
663 [[fallthrough]];
664 case CK_K6:
665 defineCPUMacros(Builder, "k6");
666 break;
667 case CK_Athlon:
668 case CK_AthlonXP:
669 defineCPUMacros(Builder, "athlon");
670 if (SSELevel != NoSSE) {
671 Builder.defineMacro("__athlon_sse__");
672 Builder.defineMacro("__tune_athlon_sse__");
673 }
674 break;
675 case CK_K8:
676 case CK_K8SSE3:
677 case CK_x86_64:
678 defineCPUMacros(Builder, "k8");
679 break;
680 case CK_x86_64_v2:
681 case CK_x86_64_v3:
682 case CK_x86_64_v4:
683 break;
684 case CK_AMDFAM10:
685 defineCPUMacros(Builder, "amdfam10");
686 break;
687 case CK_BTVER1:
688 defineCPUMacros(Builder, "btver1");
689 break;
690 case CK_BTVER2:
691 defineCPUMacros(Builder, "btver2");
692 break;
693 case CK_BDVER1:
694 defineCPUMacros(Builder, "bdver1");
695 break;
696 case CK_BDVER2:
697 defineCPUMacros(Builder, "bdver2");
698 break;
699 case CK_BDVER3:
700 defineCPUMacros(Builder, "bdver3");
701 break;
702 case CK_BDVER4:
703 defineCPUMacros(Builder, "bdver4");
704 break;
705 case CK_ZNVER1:
706 defineCPUMacros(Builder, "znver1");
707 break;
708 case CK_ZNVER2:
709 defineCPUMacros(Builder, "znver2");
710 break;
711 case CK_ZNVER3:
712 defineCPUMacros(Builder, "znver3");
713 break;
714 case CK_ZNVER4:
715 defineCPUMacros(Builder, "znver4");
716 break;
717 case CK_ZNVER5:
718 defineCPUMacros(Builder, "znver5");
719 break;
720 case CK_Geode:
721 defineCPUMacros(Builder, "geode");
722 break;
723 }
724
725 // Target properties.
726 Builder.defineMacro("__REGISTER_PREFIX__", "");
727
728 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
729 // functions in glibc header files that use FP Stack inline asm which the
730 // backend can't deal with (PR879).
731 Builder.defineMacro("__NO_MATH_INLINES");
732
733 if (HasAES)
734 Builder.defineMacro("__AES__");
735
736 if (HasVAES)
737 Builder.defineMacro("__VAES__");
738
739 if (HasPCLMUL)
740 Builder.defineMacro("__PCLMUL__");
741
742 if (HasVPCLMULQDQ)
743 Builder.defineMacro("__VPCLMULQDQ__");
744
745 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
746 // the feature flag only applies to 64-bit mode.
747 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
748 Builder.defineMacro("__LAHF_SAHF__");
749
750 if (HasLZCNT)
751 Builder.defineMacro("__LZCNT__");
752
753 if (HasRDRND)
754 Builder.defineMacro("__RDRND__");
755
756 if (HasFSGSBASE)
757 Builder.defineMacro("__FSGSBASE__");
758
759 if (HasBMI)
760 Builder.defineMacro("__BMI__");
761
762 if (HasBMI2)
763 Builder.defineMacro("__BMI2__");
764
765 if (HasPOPCNT)
766 Builder.defineMacro("__POPCNT__");
767
768 if (HasRTM)
769 Builder.defineMacro("__RTM__");
770
771 if (HasPRFCHW)
772 Builder.defineMacro("__PRFCHW__");
773
774 if (HasRDSEED)
775 Builder.defineMacro("__RDSEED__");
776
777 if (HasADX)
778 Builder.defineMacro("__ADX__");
779
780 if (HasTBM)
781 Builder.defineMacro("__TBM__");
782
783 if (HasLWP)
784 Builder.defineMacro("__LWP__");
785
786 if (HasMWAITX)
787 Builder.defineMacro("__MWAITX__");
788
789 if (HasMOVBE)
790 Builder.defineMacro("__MOVBE__");
791
792 switch (XOPLevel) {
793 case XOP:
794 Builder.defineMacro("__XOP__");
795 [[fallthrough]];
796 case FMA4:
797 Builder.defineMacro("__FMA4__");
798 [[fallthrough]];
799 case SSE4A:
800 Builder.defineMacro("__SSE4A__");
801 [[fallthrough]];
802 case NoXOP:
803 break;
804 }
805
806 if (HasFMA)
807 Builder.defineMacro("__FMA__");
808
809 if (HasF16C)
810 Builder.defineMacro("__F16C__");
811
812 if (HasGFNI)
813 Builder.defineMacro("__GFNI__");
814
815 if (HasAVX10_1) {
816 Builder.defineMacro("__AVX10_1__");
817 Builder.defineMacro("__AVX10_1_512__");
818 }
819 if (HasAVX10_2) {
820 Builder.defineMacro("__AVX10_2__");
821 Builder.defineMacro("__AVX10_2_512__");
822 }
823 if (HasAVX512CD)
824 Builder.defineMacro("__AVX512CD__");
825 if (HasAVX512VPOPCNTDQ)
826 Builder.defineMacro("__AVX512VPOPCNTDQ__");
827 if (HasAVX512VNNI)
828 Builder.defineMacro("__AVX512VNNI__");
829 if (HasAVX512BF16)
830 Builder.defineMacro("__AVX512BF16__");
831 if (HasAVX512FP16)
832 Builder.defineMacro("__AVX512FP16__");
833 if (HasAVX512DQ)
834 Builder.defineMacro("__AVX512DQ__");
835 if (HasAVX512BITALG)
836 Builder.defineMacro("__AVX512BITALG__");
837 if (HasAVX512BW)
838 Builder.defineMacro("__AVX512BW__");
839 if (HasAVX512VL) {
840 Builder.defineMacro("__AVX512VL__");
841 }
842 if (HasAVX512VBMI)
843 Builder.defineMacro("__AVX512VBMI__");
844 if (HasAVX512VBMI2)
845 Builder.defineMacro("__AVX512VBMI2__");
846 if (HasAVX512IFMA)
847 Builder.defineMacro("__AVX512IFMA__");
848 if (HasAVX512VP2INTERSECT)
849 Builder.defineMacro("__AVX512VP2INTERSECT__");
850 if (HasSHA)
851 Builder.defineMacro("__SHA__");
852 if (HasSHA512)
853 Builder.defineMacro("__SHA512__");
854
855 if (HasFXSR)
856 Builder.defineMacro("__FXSR__");
857 if (HasXSAVE)
858 Builder.defineMacro("__XSAVE__");
859 if (HasXSAVEOPT)
860 Builder.defineMacro("__XSAVEOPT__");
861 if (HasXSAVEC)
862 Builder.defineMacro("__XSAVEC__");
863 if (HasXSAVES)
864 Builder.defineMacro("__XSAVES__");
865 if (HasPKU)
866 Builder.defineMacro("__PKU__");
867 if (HasCLFLUSHOPT)
868 Builder.defineMacro("__CLFLUSHOPT__");
869 if (HasCLWB)
870 Builder.defineMacro("__CLWB__");
871 if (HasWBNOINVD)
872 Builder.defineMacro("__WBNOINVD__");
873 if (HasSHSTK)
874 Builder.defineMacro("__SHSTK__");
875 if (HasSGX)
876 Builder.defineMacro("__SGX__");
877 if (HasSM3)
878 Builder.defineMacro("__SM3__");
879 if (HasSM4)
880 Builder.defineMacro("__SM4__");
881 if (HasPREFETCHI)
882 Builder.defineMacro("__PREFETCHI__");
883 if (HasCLZERO)
884 Builder.defineMacro("__CLZERO__");
885 if (HasKL)
886 Builder.defineMacro("__KL__");
887 if (HasWIDEKL)
888 Builder.defineMacro("__WIDEKL__");
889 if (HasRDPID)
890 Builder.defineMacro("__RDPID__");
891 if (HasRDPRU)
892 Builder.defineMacro("__RDPRU__");
893 if (HasCLDEMOTE)
894 Builder.defineMacro("__CLDEMOTE__");
895 if (HasWAITPKG)
896 Builder.defineMacro("__WAITPKG__");
897 if (HasMOVDIRI)
898 Builder.defineMacro("__MOVDIRI__");
899 if (HasMOVDIR64B)
900 Builder.defineMacro("__MOVDIR64B__");
901 if (HasMOVRS)
902 Builder.defineMacro("__MOVRS__");
903 if (HasPCONFIG)
904 Builder.defineMacro("__PCONFIG__");
905 if (HasPTWRITE)
906 Builder.defineMacro("__PTWRITE__");
907 if (HasINVPCID)
908 Builder.defineMacro("__INVPCID__");
909 if (HasENQCMD)
910 Builder.defineMacro("__ENQCMD__");
911 if (HasHRESET)
912 Builder.defineMacro("__HRESET__");
913 if (HasAMXTILE)
914 Builder.defineMacro("__AMX_TILE__");
915 if (HasAMXINT8)
916 Builder.defineMacro("__AMX_INT8__");
917 if (HasAMXBF16)
918 Builder.defineMacro("__AMX_BF16__");
919 if (HasAMXFP16)
920 Builder.defineMacro("__AMX_FP16__");
921 if (HasAMXCOMPLEX)
922 Builder.defineMacro("__AMX_COMPLEX__");
923 if (HasAMXFP8)
924 Builder.defineMacro("__AMX_FP8__");
925 if (HasAMXMOVRS)
926 Builder.defineMacro("__AMX_MOVRS__");
927 if (HasAMXTRANSPOSE)
928 Builder.defineMacro("__AMX_TRANSPOSE__");
929 if (HasAMXAVX512)
930 Builder.defineMacro("__AMX_AVX512__");
931 if (HasAMXTF32)
932 Builder.defineMacro("__AMX_TF32__");
933 if (HasCMPCCXADD)
934 Builder.defineMacro("__CMPCCXADD__");
935 if (HasRAOINT)
936 Builder.defineMacro("__RAOINT__");
937 if (HasAVXIFMA)
938 Builder.defineMacro("__AVXIFMA__");
939 if (HasAVXNECONVERT)
940 Builder.defineMacro("__AVXNECONVERT__");
941 if (HasAVXVNNI)
942 Builder.defineMacro("__AVXVNNI__");
943 if (HasAVXVNNIINT16)
944 Builder.defineMacro("__AVXVNNIINT16__");
945 if (HasAVXVNNIINT8)
946 Builder.defineMacro("__AVXVNNIINT8__");
947 if (HasSERIALIZE)
948 Builder.defineMacro("__SERIALIZE__");
949 if (HasTSXLDTRK)
950 Builder.defineMacro("__TSXLDTRK__");
951 if (HasUINTR)
952 Builder.defineMacro("__UINTR__");
953 if (HasUSERMSR)
954 Builder.defineMacro("__USERMSR__");
955 if (HasCRC32)
956 Builder.defineMacro("__CRC32__");
957 if (HasEGPR)
958 Builder.defineMacro("__EGPR__");
959 if (HasPush2Pop2)
960 Builder.defineMacro("__PUSH2POP2__");
961 if (HasPPX)
962 Builder.defineMacro("__PPX__");
963 if (HasNDD)
964 Builder.defineMacro("__NDD__");
965 if (HasCCMP)
966 Builder.defineMacro("__CCMP__");
967 if (HasNF)
968 Builder.defineMacro("__NF__");
969 if (HasCF)
970 Builder.defineMacro("__CF__");
971 if (HasZU)
972 Builder.defineMacro("__ZU__");
973 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF && HasZU)
974 Builder.defineMacro("__APX_F__");
975 if (HasEGPR && HasInlineAsmUseGPR32)
976 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
977
978 // Each case falls through to the previous one here.
979 switch (SSELevel) {
980 case AVX512F:
981 Builder.defineMacro("__AVX512F__");
982 [[fallthrough]];
983 case AVX2:
984 Builder.defineMacro("__AVX2__");
985 [[fallthrough]];
986 case AVX:
987 Builder.defineMacro("__AVX__");
988 [[fallthrough]];
989 case SSE42:
990 Builder.defineMacro("__SSE4_2__");
991 [[fallthrough]];
992 case SSE41:
993 Builder.defineMacro("__SSE4_1__");
994 [[fallthrough]];
995 case SSSE3:
996 Builder.defineMacro("__SSSE3__");
997 [[fallthrough]];
998 case SSE3:
999 Builder.defineMacro("__SSE3__");
1000 [[fallthrough]];
1001 case SSE2:
1002 Builder.defineMacro("__SSE2__");
1003 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1004 [[fallthrough]];
1005 case SSE1:
1006 Builder.defineMacro("__SSE__");
1007 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1008 [[fallthrough]];
1009 case NoSSE:
1010 break;
1011 }
1012
1013 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1014 switch (SSELevel) {
1015 case AVX512F:
1016 case AVX2:
1017 case AVX:
1018 case SSE42:
1019 case SSE41:
1020 case SSSE3:
1021 case SSE3:
1022 case SSE2:
1023 Builder.defineMacro("_M_IX86_FP", Twine(2));
1024 break;
1025 case SSE1:
1026 Builder.defineMacro("_M_IX86_FP", Twine(1));
1027 break;
1028 default:
1029 Builder.defineMacro("_M_IX86_FP", Twine(0));
1030 break;
1031 }
1032 }
1033
1034 // Each case falls through to the previous one here.
1035 if (HasMMX) {
1036 Builder.defineMacro("__MMX__");
1037 }
1038
1039 if (CPU >= CK_i486 || CPU == CK_None) {
1040 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1041 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1042 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1043 }
1044 if (HasCX8)
1045 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1046 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1047 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1048
1049 if (HasFloat128)
1050 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1051
1052 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1053 Builder.defineMacro("__CET__", Twine{(Opts.CFProtectionReturn << 1) |
1054 Opts.CFProtectionBranch});
1055}
1056
1057bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1058 return llvm::StringSwitch<bool>(Name)
1059 .Case("adx", true)
1060 .Case("aes", true)
1061 .Case("amx-avx512", true)
1062 .Case("amx-bf16", true)
1063 .Case("amx-complex", true)
1064 .Case("amx-fp16", true)
1065 .Case("amx-fp8", true)
1066 .Case("amx-int8", true)
1067 .Case("amx-movrs", true)
1068 .Case("amx-tf32", true)
1069 .Case("amx-tile", true)
1070 .Case("amx-transpose", true)
1071 .Case("avx", true)
1072 .Case("avx10.1", true)
1073 .Case("avx10.2", true)
1074 .Case("avx2", true)
1075 .Case("avx512f", true)
1076 .Case("avx512cd", true)
1077 .Case("avx512vpopcntdq", true)
1078 .Case("avx512vnni", true)
1079 .Case("avx512bf16", true)
1080 .Case("avx512fp16", true)
1081 .Case("avx512dq", true)
1082 .Case("avx512bitalg", true)
1083 .Case("avx512bw", true)
1084 .Case("avx512vl", true)
1085 .Case("avx512vbmi", true)
1086 .Case("avx512vbmi2", true)
1087 .Case("avx512ifma", true)
1088 .Case("avx512vp2intersect", true)
1089 .Case("avxifma", true)
1090 .Case("avxneconvert", true)
1091 .Case("avxvnni", true)
1092 .Case("avxvnniint16", true)
1093 .Case("avxvnniint8", true)
1094 .Case("bmi", true)
1095 .Case("bmi2", true)
1096 .Case("cldemote", true)
1097 .Case("clflushopt", true)
1098 .Case("clwb", true)
1099 .Case("clzero", true)
1100 .Case("cmpccxadd", true)
1101 .Case("crc32", true)
1102 .Case("cx16", true)
1103 .Case("enqcmd", true)
1104 .Case("f16c", true)
1105 .Case("fma", true)
1106 .Case("fma4", true)
1107 .Case("fsgsbase", true)
1108 .Case("fxsr", true)
1109 .Case("general-regs-only", true)
1110 .Case("gfni", true)
1111 .Case("hreset", true)
1112 .Case("invpcid", true)
1113 .Case("kl", true)
1114 .Case("widekl", true)
1115 .Case("lwp", true)
1116 .Case("lzcnt", true)
1117 .Case("mmx", true)
1118 .Case("movbe", true)
1119 .Case("movrs", true)
1120 .Case("movdiri", true)
1121 .Case("movdir64b", true)
1122 .Case("mwaitx", true)
1123 .Case("pclmul", true)
1124 .Case("pconfig", true)
1125 .Case("pku", true)
1126 .Case("popcnt", true)
1127 .Case("prefer-256-bit", true)
1128 .Case("prefetchi", true)
1129 .Case("prfchw", true)
1130 .Case("ptwrite", true)
1131 .Case("raoint", true)
1132 .Case("rdpid", true)
1133 .Case("rdpru", true)
1134 .Case("rdrnd", true)
1135 .Case("rdseed", true)
1136 .Case("rtm", true)
1137 .Case("sahf", true)
1138 .Case("serialize", true)
1139 .Case("sgx", true)
1140 .Case("sha", true)
1141 .Case("sha512", true)
1142 .Case("shstk", true)
1143 .Case("sm3", true)
1144 .Case("sm4", true)
1145 .Case("sse", true)
1146 .Case("sse2", true)
1147 .Case("sse3", true)
1148 .Case("ssse3", true)
1149 .Case("sse4", true)
1150 .Case("sse4.1", true)
1151 .Case("sse4.2", true)
1152 .Case("sse4a", true)
1153 .Case("tbm", true)
1154 .Case("tsxldtrk", true)
1155 .Case("uintr", true)
1156 .Case("usermsr", true)
1157 .Case("vaes", true)
1158 .Case("vpclmulqdq", true)
1159 .Case("wbnoinvd", true)
1160 .Case("waitpkg", true)
1161 .Case("x87", true)
1162 .Case("xop", true)
1163 .Case("xsave", true)
1164 .Case("xsavec", true)
1165 .Case("xsaves", true)
1166 .Case("xsaveopt", true)
1167 .Case("egpr", true)
1168 .Case("push2pop2", true)
1169 .Case("ppx", true)
1170 .Case("ndd", true)
1171 .Case("ccmp", true)
1172 .Case("nf", true)
1173 .Case("cf", true)
1174 .Case("zu", true)
1175 .Default(false);
1176}
1177
1178bool X86TargetInfo::hasFeature(StringRef Feature) const {
1179 return llvm::StringSwitch<bool>(Feature)
1180 .Case("adx", HasADX)
1181 .Case("aes", HasAES)
1182 .Case("amx-avx512", HasAMXAVX512)
1183 .Case("amx-bf16", HasAMXBF16)
1184 .Case("amx-complex", HasAMXCOMPLEX)
1185 .Case("amx-fp16", HasAMXFP16)
1186 .Case("amx-fp8", HasAMXFP8)
1187 .Case("amx-int8", HasAMXINT8)
1188 .Case("amx-movrs", HasAMXMOVRS)
1189 .Case("amx-tf32", HasAMXTF32)
1190 .Case("amx-tile", HasAMXTILE)
1191 .Case("amx-transpose", HasAMXTRANSPOSE)
1192 .Case("avx", SSELevel >= AVX)
1193 .Case("avx10.1", HasAVX10_1)
1194 .Case("avx10.2", HasAVX10_2)
1195 .Case("avx2", SSELevel >= AVX2)
1196 .Case("avx512f", SSELevel >= AVX512F)
1197 .Case("avx512cd", HasAVX512CD)
1198 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1199 .Case("avx512vnni", HasAVX512VNNI)
1200 .Case("avx512bf16", HasAVX512BF16)
1201 .Case("avx512fp16", HasAVX512FP16)
1202 .Case("avx512dq", HasAVX512DQ)
1203 .Case("avx512bitalg", HasAVX512BITALG)
1204 .Case("avx512bw", HasAVX512BW)
1205 .Case("avx512vl", HasAVX512VL)
1206 .Case("avx512vbmi", HasAVX512VBMI)
1207 .Case("avx512vbmi2", HasAVX512VBMI2)
1208 .Case("avx512ifma", HasAVX512IFMA)
1209 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1210 .Case("avxifma", HasAVXIFMA)
1211 .Case("avxneconvert", HasAVXNECONVERT)
1212 .Case("avxvnni", HasAVXVNNI)
1213 .Case("avxvnniint16", HasAVXVNNIINT16)
1214 .Case("avxvnniint8", HasAVXVNNIINT8)
1215 .Case("bmi", HasBMI)
1216 .Case("bmi2", HasBMI2)
1217 .Case("cldemote", HasCLDEMOTE)
1218 .Case("clflushopt", HasCLFLUSHOPT)
1219 .Case("clwb", HasCLWB)
1220 .Case("clzero", HasCLZERO)
1221 .Case("cmpccxadd", HasCMPCCXADD)
1222 .Case("crc32", HasCRC32)
1223 .Case("cx8", HasCX8)
1224 .Case("cx16", HasCX16)
1225 .Case("enqcmd", HasENQCMD)
1226 .Case("f16c", HasF16C)
1227 .Case("fma", HasFMA)
1228 .Case("fma4", XOPLevel >= FMA4)
1229 .Case("fsgsbase", HasFSGSBASE)
1230 .Case("fxsr", HasFXSR)
1231 .Case("gfni", HasGFNI)
1232 .Case("hreset", HasHRESET)
1233 .Case("invpcid", HasINVPCID)
1234 .Case("kl", HasKL)
1235 .Case("widekl", HasWIDEKL)
1236 .Case("lwp", HasLWP)
1237 .Case("lzcnt", HasLZCNT)
1238 .Case("mmx", HasMMX)
1239 .Case("movbe", HasMOVBE)
1240 .Case("movrs", HasMOVRS)
1241 .Case("movdiri", HasMOVDIRI)
1242 .Case("movdir64b", HasMOVDIR64B)
1243 .Case("mwaitx", HasMWAITX)
1244 .Case("pclmul", HasPCLMUL)
1245 .Case("pconfig", HasPCONFIG)
1246 .Case("pku", HasPKU)
1247 .Case("popcnt", HasPOPCNT)
1248 .Case("prefetchi", HasPREFETCHI)
1249 .Case("prfchw", HasPRFCHW)
1250 .Case("ptwrite", HasPTWRITE)
1251 .Case("raoint", HasRAOINT)
1252 .Case("rdpid", HasRDPID)
1253 .Case("rdpru", HasRDPRU)
1254 .Case("rdrnd", HasRDRND)
1255 .Case("rdseed", HasRDSEED)
1256 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1257 .Case("rtm", HasRTM)
1258 .Case("sahf", HasLAHFSAHF)
1259 .Case("serialize", HasSERIALIZE)
1260 .Case("sgx", HasSGX)
1261 .Case("sha", HasSHA)
1262 .Case("sha512", HasSHA512)
1263 .Case("shstk", HasSHSTK)
1264 .Case("sm3", HasSM3)
1265 .Case("sm4", HasSM4)
1266 .Case("sse", SSELevel >= SSE1)
1267 .Case("sse2", SSELevel >= SSE2)
1268 .Case("sse3", SSELevel >= SSE3)
1269 .Case("ssse3", SSELevel >= SSSE3)
1270 .Case("sse4.1", SSELevel >= SSE41)
1271 .Case("sse4.2", SSELevel >= SSE42)
1272 .Case("sse4a", XOPLevel >= SSE4A)
1273 .Case("tbm", HasTBM)
1274 .Case("tsxldtrk", HasTSXLDTRK)
1275 .Case("uintr", HasUINTR)
1276 .Case("usermsr", HasUSERMSR)
1277 .Case("vaes", HasVAES)
1278 .Case("vpclmulqdq", HasVPCLMULQDQ)
1279 .Case("wbnoinvd", HasWBNOINVD)
1280 .Case("waitpkg", HasWAITPKG)
1281 .Case("x86", true)
1282 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1283 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1284 .Case("x87", HasX87)
1285 .Case("xop", XOPLevel >= XOP)
1286 .Case("xsave", HasXSAVE)
1287 .Case("xsavec", HasXSAVEC)
1288 .Case("xsaves", HasXSAVES)
1289 .Case("xsaveopt", HasXSAVEOPT)
1290 .Case("fullbf16", HasFullBFloat16)
1291 .Case("egpr", HasEGPR)
1292 .Case("push2pop2", HasPush2Pop2)
1293 .Case("ppx", HasPPX)
1294 .Case("ndd", HasNDD)
1295 .Case("ccmp", HasCCMP)
1296 .Case("nf", HasNF)
1297 .Case("cf", HasCF)
1298 .Case("zu", HasZU)
1299 .Case("branch-hint", HasBranchHint)
1300 .Default(false);
1301}
1302
1303// We can't use a generic validation scheme for the features accepted here
1304// versus subtarget features accepted in the target attribute because the
1305// bitfield structure that's initialized in the runtime only supports the
1306// below currently rather than the full range of subtarget features. (See
1307// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1308bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1309 return llvm::StringSwitch<bool>(FeatureStr)
1310#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1311#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true)
1312#include "llvm/TargetParser/X86TargetParser.def"
1313 .Default(false);
1314}
1315
1316static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1317 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1318#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1319 .Case(STR, llvm::X86::FEATURE_##ENUM)
1320
1321#include "llvm/TargetParser/X86TargetParser.def"
1322 ;
1323 // Note, this function should only be used after ensuring the value is
1324 // correct, so it asserts if the value is out of range.
1325}
1326
1327llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1328 auto getPriority = [](StringRef Feature) -> unsigned {
1329 // Valid CPUs have a 'key feature' that compares just better than its key
1330 // feature.
1331 using namespace llvm::X86;
1332 CPUKind Kind = parseArchX86(Feature);
1333 if (Kind != CK_None) {
1334 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1335 return (getFeaturePriority(KeyFeature) << 1) + 1;
1336 }
1337 // Now we know we have a feature, so get its priority and shift it a few so
1338 // that we have sufficient room for the CPUs (above).
1339 return getFeaturePriority(getFeature(Feature)) << 1;
1340 };
1341
1342 unsigned Priority = 0;
1343 for (StringRef Feature : Features)
1344 if (!Feature.empty())
1345 Priority = std::max(Priority, getPriority(Feature));
1346 return llvm::APInt(32, Priority);
1347}
1348
1349bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1350 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1351}
1352
1353char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1354 return llvm::X86::getCPUDispatchMangling(Name);
1355}
1356
1357void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1358 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1359 SmallVector<StringRef, 32> TargetCPUFeatures;
1360 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1361 for (auto &F : TargetCPUFeatures)
1362 Features.push_back(F);
1363}
1364
1365// We can't use a generic validation scheme for the cpus accepted here
1366// versus subtarget cpus accepted in the target attribute because the
1367// variables intitialized by the runtime only support the below currently
1368// rather than the full range of cpus.
1369bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1370 return llvm::StringSwitch<bool>(FeatureStr)
1371#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1372#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1373#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1374#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1375#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1376#include "llvm/TargetParser/X86TargetParser.def"
1377 .Default(false);
1378}
1379
1380static unsigned matchAsmCCConstraint(const char *Name) {
1381 auto RV = llvm::StringSwitch<unsigned>(Name)
1382 .Case("@cca", 4)
1383 .Case("@ccae", 5)
1384 .Case("@ccb", 4)
1385 .Case("@ccbe", 5)
1386 .Case("@ccc", 4)
1387 .Case("@cce", 4)
1388 .Case("@ccz", 4)
1389 .Case("@ccg", 4)
1390 .Case("@ccge", 5)
1391 .Case("@ccl", 4)
1392 .Case("@ccle", 5)
1393 .Case("@ccna", 5)
1394 .Case("@ccnae", 6)
1395 .Case("@ccnb", 5)
1396 .Case("@ccnbe", 6)
1397 .Case("@ccnc", 5)
1398 .Case("@ccne", 5)
1399 .Case("@ccnz", 5)
1400 .Case("@ccng", 5)
1401 .Case("@ccnge", 6)
1402 .Case("@ccnl", 5)
1403 .Case("@ccnle", 6)
1404 .Case("@ccno", 5)
1405 .Case("@ccnp", 5)
1406 .Case("@ccns", 5)
1407 .Case("@cco", 4)
1408 .Case("@ccp", 4)
1409 .Case("@ccs", 4)
1410 .Default(0);
1411 return RV;
1412}
1413
1414bool X86TargetInfo::validateAsmConstraint(
1415 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1416 switch (*Name) {
1417 default:
1418 return false;
1419 // Constant constraints.
1420 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1421 // instructions.
1422 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1423 // x86_64 instructions.
1424 case 's':
1425 Info.setRequiresImmediate();
1426 return true;
1427 case 'I':
1428 Info.setRequiresImmediate(0, 31);
1429 return true;
1430 case 'J':
1431 Info.setRequiresImmediate(0, 63);
1432 return true;
1433 case 'K':
1434 Info.setRequiresImmediate(-128, 127);
1435 return true;
1436 case 'L':
1437 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1438 return true;
1439 case 'M':
1440 Info.setRequiresImmediate(0, 3);
1441 return true;
1442 case 'N':
1443 Info.setRequiresImmediate(0, 255);
1444 return true;
1445 case 'O':
1446 Info.setRequiresImmediate(0, 127);
1447 return true;
1448 case 'W':
1449 switch (*++Name) {
1450 default:
1451 return false;
1452 case 's':
1453 Info.setAllowsRegister();
1454 return true;
1455 }
1456 // Register constraints.
1457 case 'Y': // 'Y' is the first character for several 2-character constraints.
1458 // Shift the pointer to the second character of the constraint.
1459 Name++;
1460 switch (*Name) {
1461 default:
1462 return false;
1463 case 'z': // First SSE register.
1464 case '2':
1465 case 't': // Any SSE register, when SSE2 is enabled.
1466 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1467 case 'm': // Any MMX register, when inter-unit moves enabled.
1468 case 'k': // AVX512 arch mask registers: k1-k7.
1469 Info.setAllowsRegister();
1470 return true;
1471 }
1472 case 'f': // Any x87 floating point stack register.
1473 // Constraint 'f' cannot be used for output operands.
1474 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1475 return false;
1476 Info.setAllowsRegister();
1477 return true;
1478 case 'a': // eax.
1479 case 'b': // ebx.
1480 case 'c': // ecx.
1481 case 'd': // edx.
1482 case 'S': // esi.
1483 case 'D': // edi.
1484 case 'A': // edx:eax.
1485 case 't': // Top of floating point stack.
1486 case 'u': // Second from top of floating point stack.
1487 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1488 case 'y': // Any MMX register.
1489 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1490 case 'x': // Any SSE register.
1491 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1492 // for intermideate k reg operations).
1493 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1494 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1495 case 'l': // "Index" registers: any general register that can be used as an
1496 // index in a base+index memory access.
1497 Info.setAllowsRegister();
1498 return true;
1499 // Floating point constant constraints.
1500 case 'C': // SSE floating point constant.
1501 case 'G': // x87 floating point constant.
1502 return true;
1503 case 'j':
1504 Name++;
1505 switch (*Name) {
1506 default:
1507 return false;
1508 case 'r':
1509 Info.setAllowsRegister();
1510 return true;
1511 case 'R':
1512 Info.setAllowsRegister();
1513 return true;
1514 }
1515 case '@':
1516 // CC condition changes.
1517 if (auto Len = matchAsmCCConstraint(Name)) {
1518 Name += Len - 1;
1519 Info.setAllowsRegister();
1520 Info.setOutputOperandBounds(0, 2);
1521 return true;
1522 }
1523 return false;
1524 }
1525}
1526
1527// Below is based on the following information:
1528// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1529// | Processor Name | Cache Line Size (Bytes) | Source |
1530// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1531// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1532// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1533// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1534// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1535// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1536// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1537// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1538// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1539// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1540// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1541// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1542// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1543// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1544// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1545// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1546// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1547// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1548// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1549std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1550 using namespace llvm::X86;
1551 switch (CPU) {
1552 // i386
1553 case CK_i386:
1554 // i486
1555 case CK_i486:
1556 case CK_WinChipC6:
1557 case CK_WinChip2:
1558 case CK_C3:
1559 // Lakemont
1560 case CK_Lakemont:
1561 return 16;
1562
1563 // i586
1564 case CK_i586:
1565 case CK_Pentium:
1566 case CK_PentiumMMX:
1567 // i686
1568 case CK_PentiumPro:
1569 case CK_i686:
1570 case CK_Pentium2:
1571 case CK_Pentium3:
1572 case CK_PentiumM:
1573 case CK_C3_2:
1574 // K6
1575 case CK_K6:
1576 case CK_K6_2:
1577 case CK_K6_3:
1578 // Geode
1579 case CK_Geode:
1580 return 32;
1581
1582 // Netburst
1583 case CK_Pentium4:
1584 case CK_Prescott:
1585 case CK_Nocona:
1586 // Atom
1587 case CK_Bonnell:
1588 case CK_Silvermont:
1589 case CK_Goldmont:
1590 case CK_GoldmontPlus:
1591 case CK_Tremont:
1592 case CK_Gracemont:
1593
1594 case CK_Westmere:
1595 case CK_SandyBridge:
1596 case CK_IvyBridge:
1597 case CK_Haswell:
1598 case CK_Broadwell:
1599 case CK_SkylakeClient:
1600 case CK_SkylakeServer:
1601 case CK_Cascadelake:
1602 case CK_Nehalem:
1603 case CK_Cooperlake:
1604 case CK_Cannonlake:
1605 case CK_Tigerlake:
1606 case CK_SapphireRapids:
1607 case CK_IcelakeClient:
1608 case CK_Rocketlake:
1609 case CK_IcelakeServer:
1610 case CK_Alderlake:
1611 case CK_Raptorlake:
1612 case CK_Meteorlake:
1613 case CK_Arrowlake:
1614 case CK_ArrowlakeS:
1615 case CK_Lunarlake:
1616 case CK_Pantherlake:
1617 case CK_Wildcatlake:
1618 case CK_Sierraforest:
1619 case CK_Grandridge:
1620 case CK_Graniterapids:
1621 case CK_GraniterapidsD:
1622 case CK_Emeraldrapids:
1623 case CK_Clearwaterforest:
1624 case CK_Diamondrapids:
1625 case CK_KNL:
1626 case CK_KNM:
1627 // K7
1628 case CK_Athlon:
1629 case CK_AthlonXP:
1630 // K8
1631 case CK_K8:
1632 case CK_K8SSE3:
1633 case CK_AMDFAM10:
1634 // Bobcat
1635 case CK_BTVER1:
1636 case CK_BTVER2:
1637 // Bulldozer
1638 case CK_BDVER1:
1639 case CK_BDVER2:
1640 case CK_BDVER3:
1641 case CK_BDVER4:
1642 // Zen
1643 case CK_ZNVER1:
1644 case CK_ZNVER2:
1645 case CK_ZNVER3:
1646 case CK_ZNVER4:
1647 case CK_ZNVER5:
1648 // Deprecated
1649 case CK_x86_64:
1650 case CK_x86_64_v2:
1651 case CK_x86_64_v3:
1652 case CK_x86_64_v4:
1653 case CK_Yonah:
1654 case CK_Penryn:
1655 case CK_Core2:
1656 return 64;
1657
1658 // The following currently have unknown cache line sizes (but they are probably all 64):
1659 // Core
1660 case CK_None:
1661 return std::nullopt;
1662 }
1663 llvm_unreachable("Unknown CPU kind");
1664}
1665
1666bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1667 StringRef Constraint,
1668 unsigned Size) const {
1669 // Strip off constraint modifiers.
1670 Constraint = Constraint.ltrim("=+&");
1671
1672 return validateOperandSize(FeatureMap, Constraint, Size);
1673}
1674
1675bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1676 StringRef Constraint,
1677 unsigned Size) const {
1678 return validateOperandSize(FeatureMap, Constraint, Size);
1679}
1680
1681bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1682 StringRef Constraint,
1683 unsigned Size) const {
1684 switch (Constraint[0]) {
1685 default:
1686 break;
1687 case 'k':
1688 // Registers k0-k7 (AVX512) size limit is 64 bit.
1689 case 'y':
1690 return Size <= 64;
1691 case 'f':
1692 case 't':
1693 case 'u':
1694 return Size <= 128;
1695 case 'Y':
1696 // 'Y' is the first character for several 2-character constraints.
1697 switch (Constraint[1]) {
1698 default:
1699 return false;
1700 case 'm':
1701 // 'Ym' is synonymous with 'y'.
1702 case 'k':
1703 return Size <= 64;
1704 case 'z':
1705 // XMM0/YMM/ZMM0
1706 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1707 // ZMM0 can be used if target supports AVX512F.
1708 return Size <= 512U;
1709 else if (hasFeatureEnabled(FeatureMap, "avx"))
1710 // YMM0 can be used if target supports AVX.
1711 return Size <= 256U;
1712 else if (hasFeatureEnabled(FeatureMap, "sse"))
1713 return Size <= 128U;
1714 return false;
1715 case 'i':
1716 case 't':
1717 case '2':
1718 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1719 if (SSELevel < SSE2)
1720 return false;
1721 break;
1722 }
1723 break;
1724 case 'v':
1725 case 'x':
1726 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1727 // 512-bit zmm registers can be used if target supports AVX512F.
1728 return Size <= 512U;
1729 else if (hasFeatureEnabled(FeatureMap, "avx"))
1730 // 256-bit ymm registers can be used if target supports AVX.
1731 return Size <= 256U;
1732 return Size <= 128U;
1733
1734 }
1735
1736 return true;
1737}
1738
1739std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1740 switch (*Constraint) {
1741 case '@':
1742 if (auto Len = matchAsmCCConstraint(Constraint)) {
1743 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1744 Constraint += Len - 1;
1745 return Converted;
1746 }
1747 return std::string(1, *Constraint);
1748 case 'a':
1749 return std::string("{ax}");
1750 case 'b':
1751 return std::string("{bx}");
1752 case 'c':
1753 return std::string("{cx}");
1754 case 'd':
1755 return std::string("{dx}");
1756 case 'S':
1757 return std::string("{si}");
1758 case 'D':
1759 return std::string("{di}");
1760 case 'p': // Keep 'p' constraint (address).
1761 return std::string("p");
1762 case 't': // top of floating point stack.
1763 return std::string("{st}");
1764 case 'u': // second from top of floating point stack.
1765 return std::string("{st(1)}"); // second from top of floating point stack.
1766 case 'W':
1767 assert(Constraint[1] == 's');
1768 return '^' + std::string(Constraint++, 2);
1769 case 'Y':
1770 switch (Constraint[1]) {
1771 default:
1772 // Break from inner switch and fall through (copy single char),
1773 // continue parsing after copying the current constraint into
1774 // the return string.
1775 break;
1776 case 'k':
1777 case 'm':
1778 case 'i':
1779 case 't':
1780 case 'z':
1781 case '2':
1782 // "^" hints llvm that this is a 2 letter constraint.
1783 // "Constraint++" is used to promote the string iterator
1784 // to the next constraint.
1785 return std::string("^") + std::string(Constraint++, 2);
1786 }
1787 [[fallthrough]];
1788 case 'j':
1789 switch (Constraint[1]) {
1790 default:
1791 // Break from inner switch and fall through (copy single char),
1792 // continue parsing after copying the current constraint into
1793 // the return string.
1794 break;
1795 case 'r':
1796 case 'R':
1797 // "^" hints llvm that this is a 2 letter constraint.
1798 // "Constraint++" is used to promote the string iterator
1799 // to the next constraint.
1800 return std::string("^") + std::string(Constraint++, 2);
1801 }
1802 [[fallthrough]];
1803 default:
1804 return std::string(1, *Constraint);
1805 }
1806}
1807
1808void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1809 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1810 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1811}
1812
1813void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1814 llvm::X86::fillValidTuneCPUList(Values);
1815}
1816
1820
1824
1825llvm::SmallVector<Builtin::InfosShard>
1826X86_32TargetInfo::getTargetBuiltins() const {
1827 return {
1828 {&X86::BuiltinStrings, X86::BuiltinInfos},
1829 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1830 };
1831}
1832
1833llvm::SmallVector<Builtin::InfosShard>
1834X86_64TargetInfo::getTargetBuiltins() const {
1835 return {
1836 {&X86::BuiltinStrings, X86::BuiltinInfos},
1837 {&X86::BuiltinStrings, X86::PrefixedBuiltinInfos, "__builtin_ia32_"},
1838 {&X86_64::BuiltinStrings, X86_64::BuiltinInfos},
1839 {&X86_64::BuiltinStrings, X86_64::PrefixedBuiltinInfos,
1840 "__builtin_ia32_"},
1841 };
1842}
Diagnostic.h
Defines the Diagnostic-related interfaces.
matchAsmCCConstraint
static unsigned matchAsmCCConstraint(const char *Name)
Definition AArch64.cpp:1467
PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition Hexagon.cpp:219
getFeature
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition X86.cpp:1316
BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition Builtins.cpp:38
Builtins.h
Defines enum values for all the target-independent builtin functions.
TargetBuiltins.h
Enumerates target-specific builtins in their own namespaces within namespace clang.
int
__device__ int
Definition __clang_hip_libdevice_declares.h:68
clang::DiagnosticsEngine
Concrete class used by the front-end to report problems and issues.
Definition Diagnostic.h:232
clang::DiagnosticsEngine::Report
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition Diagnostic.h:1546
clang::LangOptions
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition LangOptions.h:434
clang::TargetInfo::getTargetOpts
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition TargetInfo.h:323
clang::TargetInfo::getTriple
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition TargetInfo.h:1311
clang::TargetInfo::hasFeatureEnabled
virtual bool hasFeatureEnabled(const llvm::StringMap< bool > &Features, StringRef Name) const
Check if target has a given feature enabled.
Definition TargetInfo.h:1440
clang::TargetInfo::initFeatureMap
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition TargetInfo.cpp:563
clang::targets::X86TargetInfo::FPMath
enum clang::targets::X86TargetInfo::FPMathKind FPMath
clang::targets::X86TargetInfo::handleTargetFeatures
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features.
Definition X86.cpp:233
clang::targets::X86TargetInfo::getCPUCacheLineSize
std::optional< unsigned > getCPUCacheLineSize() const override
Definition X86.cpp:1549
clang::targets::X86TargetInfo::validateAsmConstraint
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition X86.cpp:1414
clang::targets::X86TargetInfo::getFMVPriority
llvm::APInt getFMVPriority(ArrayRef< StringRef > Features) const override
Definition X86.cpp:1327
clang::targets::X86TargetInfo::setFPMath
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition X86.cpp:140
clang::targets::X86TargetInfo::getGCCRegNames
ArrayRef< const char * > getGCCRegNames() const override
Definition X86.cpp:1817
clang::targets::X86TargetInfo::CPUSpecificManglingCharacter
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition X86.cpp:1353
clang::targets::X86TargetInfo::convertConstraint
std::string convertConstraint(const char *&Constraint) const override
Definition X86.cpp:1739
clang::targets::X86TargetInfo::getTargetDefines
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition X86.cpp:508
clang::targets::X86TargetInfo::initFeatureMap
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition X86.cpp:152
clang::targets::X86TargetInfo::getCPUSpecificCPUDispatchFeatures
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition X86.cpp:1357
clang::targets::X86TargetInfo::validateCpuIs
bool validateCpuIs(StringRef FeatureStr) const override
Definition X86.cpp:1369
clang::targets::X86TargetInfo::validateOutputSize
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1666
clang::targets::X86TargetInfo::validateOperandSize
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition X86.cpp:1681
clang::targets::X86TargetInfo::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values for tuning CPU.
Definition X86.cpp:1813
clang::targets::X86TargetInfo::validateCPUSpecificCPUDispatch
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition X86.cpp:1349
clang::targets::X86TargetInfo::validateCpuSupports
bool validateCpuSupports(StringRef FeatureStr) const override
Definition X86.cpp:1308
clang::targets::X86TargetInfo::isValidFeatureName
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition X86.cpp:1057
clang::targets::X86TargetInfo::hasFeature
bool hasFeature(StringRef Feature) const final
Determine whether the given target has the given feature.
Definition X86.cpp:1178
clang::targets::X86TargetInfo::setFeatureEnabled
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const final
Enable or disable a specific target feature; the feature name must be valid.
Definition X86.cpp:214
clang::targets::X86TargetInfo::CPU
llvm::X86::CPUKind CPU
Definition X86.h:184
clang::targets::X86TargetInfo::fillValidCPUList
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition X86.cpp:1808
clang::targets::X86TargetInfo::getGCCAddlRegNames
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition X86.cpp:1821
clang::targets::X86TargetInfo::validateInputSize
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition X86.cpp:1675
clang::targets::X86_32TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1826
clang::targets::X86_64TargetInfo::getTargetBuiltins
llvm::SmallVector< Builtin::InfosShard > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition X86.cpp:1834
clang::targets::X86_64
Definition X86.cpp:53
clang::targets::X86_64::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:58
clang::targets::X86_64::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:64
clang::targets::X86::BuiltinInfos
static constexpr Builtin::Info BuiltinInfos[]
Definition X86.cpp:38
clang::targets::X86::PrefixedBuiltinInfos
static constexpr Builtin::Info PrefixedBuiltinInfos[]
Definition X86.cpp:44
clang::targets::NumX86Builtins
static constexpr int NumX86Builtins
Definition X86.cpp:26
clang::targets::defineCPUMacros
LLVM_LIBRARY_VISIBILITY void defineCPUMacros(clang::MacroBuilder &Builder, llvm::StringRef CPUName, bool Tuning=true)
clang::targets::NumBuiltins
static constexpr int NumBuiltins
Definition X86.cpp:30
clang::targets::AddlRegNames
const TargetInfo::AddlRegName AddlRegNames[]
Definition X86.cpp:100
clang::targets::GCCRegNames
static const char *const GCCRegNames[]
Definition X86.cpp:73
clang::targets::NumX86_64Builtins
static constexpr int NumX86_64Builtins
Definition X86.cpp:28
clang::targets::DefineStd
LLVM_LIBRARY_VISIBILITY void DefineStd(clang::MacroBuilder &Builder, llvm::StringRef MacroName, const clang::LangOptions &Opts)
Define a macro name and standard variants.
clang
The JSON file list parser is used to communicate input to InstallAPI.
Definition CalledOnceCheck.h:17
clang::Builtin::Info
The info used to represent each builtin.
Definition Builtins.h:78
clang::TargetInfo::ConstraintInfo::setOutputOperandBounds
void setOutputOperandBounds(unsigned Min, unsigned Max)
Definition TargetInfo.h:1222
clang::TargetInfo::ConstraintInfo::setRequiresImmediate
void setRequiresImmediate(int Min, int Max)
Definition TargetInfo.h:1186
clang::TransferrableTargetInfo::LongDoubleFormat
const llvm::fltSemantics * LongDoubleFormat
Definition TargetInfo.h:143
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