clang  8.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements X86 TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 namespace clang {
24 namespace targets {
25 
27 #define BUILTIN(ID, TYPE, ATTRS) \
28  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
33 #include "clang/Basic/BuiltinsX86.def"
34 
35 #define BUILTIN(ID, TYPE, ATTRS) \
36  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
41 #include "clang/Basic/BuiltinsX86_64.def"
42 };
43 
44 static const char *const GCCRegNames[] = {
45  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62  "k2", "k3", "k4", "k5", "k6", "k7",
63  "cr0", "cr2", "cr3", "cr4", "cr8",
64  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65  "bnd0", "bnd1", "bnd2", "bnd3",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107  const std::vector<std::string> &FeaturesVec) const {
108  // FIXME: This *really* should not be here.
109  // X86_64 always has SSE2.
110  if (getTriple().getArch() == llvm::Triple::x86_64)
111  setFeatureEnabledImpl(Features, "sse2", true);
112 
113  const CPUKind Kind = getCPUKind(CPU);
114 
115  // Enable X87 for all X86 processors but Lakemont.
116  if (Kind != CK_Lakemont)
117  setFeatureEnabledImpl(Features, "x87", true);
118 
119  switch (Kind) {
120  case CK_Generic:
121  case CK_i386:
122  case CK_i486:
123  case CK_i586:
124  case CK_Pentium:
125  case CK_PentiumPro:
126  case CK_Lakemont:
127  break;
128 
129  case CK_PentiumMMX:
130  case CK_Pentium2:
131  case CK_K6:
132  case CK_WinChipC6:
133  setFeatureEnabledImpl(Features, "mmx", true);
134  break;
135 
136  case CK_IcelakeServer:
137  setFeatureEnabledImpl(Features, "pconfig", true);
138  setFeatureEnabledImpl(Features, "wbnoinvd", true);
139  LLVM_FALLTHROUGH;
140  case CK_IcelakeClient:
141  setFeatureEnabledImpl(Features, "vaes", true);
142  setFeatureEnabledImpl(Features, "gfni", true);
143  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
144  setFeatureEnabledImpl(Features, "avx512bitalg", true);
145  setFeatureEnabledImpl(Features, "avx512vnni", true);
146  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
147  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
148  setFeatureEnabledImpl(Features, "rdpid", true);
149  LLVM_FALLTHROUGH;
150  case CK_Cannonlake:
151  setFeatureEnabledImpl(Features, "avx512ifma", true);
152  setFeatureEnabledImpl(Features, "avx512vbmi", true);
153  setFeatureEnabledImpl(Features, "sha", true);
154  LLVM_FALLTHROUGH;
155  case CK_SkylakeServer:
156  setFeatureEnabledImpl(Features, "avx512f", true);
157  setFeatureEnabledImpl(Features, "avx512cd", true);
158  setFeatureEnabledImpl(Features, "avx512dq", true);
159  setFeatureEnabledImpl(Features, "avx512bw", true);
160  setFeatureEnabledImpl(Features, "avx512vl", true);
161  setFeatureEnabledImpl(Features, "pku", true);
162  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
163  setFeatureEnabledImpl(Features, "clwb", true);
164  LLVM_FALLTHROUGH;
165  case CK_SkylakeClient:
166  setFeatureEnabledImpl(Features, "xsavec", true);
167  setFeatureEnabledImpl(Features, "xsaves", true);
168  setFeatureEnabledImpl(Features, "mpx", true);
169  if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX
170  setFeatureEnabledImpl(Features, "sgx", true);
171  setFeatureEnabledImpl(Features, "clflushopt", true);
172  setFeatureEnabledImpl(Features, "rtm", true);
173  setFeatureEnabledImpl(Features, "aes", true);
174  LLVM_FALLTHROUGH;
175  case CK_Broadwell:
176  setFeatureEnabledImpl(Features, "rdseed", true);
177  setFeatureEnabledImpl(Features, "adx", true);
178  setFeatureEnabledImpl(Features, "prfchw", true);
179  LLVM_FALLTHROUGH;
180  case CK_Haswell:
181  setFeatureEnabledImpl(Features, "avx2", true);
182  setFeatureEnabledImpl(Features, "lzcnt", true);
183  setFeatureEnabledImpl(Features, "bmi", true);
184  setFeatureEnabledImpl(Features, "bmi2", true);
185  setFeatureEnabledImpl(Features, "fma", true);
186  setFeatureEnabledImpl(Features, "invpcid", true);
187  setFeatureEnabledImpl(Features, "movbe", true);
188  LLVM_FALLTHROUGH;
189  case CK_IvyBridge:
190  setFeatureEnabledImpl(Features, "rdrnd", true);
191  setFeatureEnabledImpl(Features, "f16c", true);
192  setFeatureEnabledImpl(Features, "fsgsbase", true);
193  LLVM_FALLTHROUGH;
194  case CK_SandyBridge:
195  setFeatureEnabledImpl(Features, "avx", true);
196  setFeatureEnabledImpl(Features, "xsave", true);
197  setFeatureEnabledImpl(Features, "xsaveopt", true);
198  LLVM_FALLTHROUGH;
199  case CK_Westmere:
200  setFeatureEnabledImpl(Features, "pclmul", true);
201  LLVM_FALLTHROUGH;
202  case CK_Nehalem:
203  setFeatureEnabledImpl(Features, "sse4.2", true);
204  LLVM_FALLTHROUGH;
205  case CK_Penryn:
206  setFeatureEnabledImpl(Features, "sse4.1", true);
207  LLVM_FALLTHROUGH;
208  case CK_Core2:
209  setFeatureEnabledImpl(Features, "ssse3", true);
210  setFeatureEnabledImpl(Features, "sahf", true);
211  LLVM_FALLTHROUGH;
212  case CK_Yonah:
213  case CK_Prescott:
214  case CK_Nocona:
215  setFeatureEnabledImpl(Features, "sse3", true);
216  setFeatureEnabledImpl(Features, "cx16", true);
217  LLVM_FALLTHROUGH;
218  case CK_PentiumM:
219  case CK_Pentium4:
220  case CK_x86_64:
221  setFeatureEnabledImpl(Features, "sse2", true);
222  LLVM_FALLTHROUGH;
223  case CK_Pentium3:
224  case CK_C3_2:
225  setFeatureEnabledImpl(Features, "sse", true);
226  setFeatureEnabledImpl(Features, "fxsr", true);
227  break;
228 
229  case CK_Tremont:
230  setFeatureEnabledImpl(Features, "cldemote", true);
231  setFeatureEnabledImpl(Features, "movdiri", true);
232  setFeatureEnabledImpl(Features, "movdir64b", true);
233  setFeatureEnabledImpl(Features, "gfni", true);
234  setFeatureEnabledImpl(Features, "waitpkg", true);
235  LLVM_FALLTHROUGH;
236  case CK_GoldmontPlus:
237  setFeatureEnabledImpl(Features, "ptwrite", true);
238  setFeatureEnabledImpl(Features, "rdpid", true);
239  setFeatureEnabledImpl(Features, "sgx", true);
240  LLVM_FALLTHROUGH;
241  case CK_Goldmont:
242  setFeatureEnabledImpl(Features, "sha", true);
243  setFeatureEnabledImpl(Features, "rdseed", true);
244  setFeatureEnabledImpl(Features, "xsave", true);
245  setFeatureEnabledImpl(Features, "xsaveopt", true);
246  setFeatureEnabledImpl(Features, "xsavec", true);
247  setFeatureEnabledImpl(Features, "xsaves", true);
248  setFeatureEnabledImpl(Features, "clflushopt", true);
249  setFeatureEnabledImpl(Features, "mpx", true);
250  setFeatureEnabledImpl(Features, "fsgsbase", true);
251  setFeatureEnabledImpl(Features, "aes", true);
252  LLVM_FALLTHROUGH;
253  case CK_Silvermont:
254  setFeatureEnabledImpl(Features, "rdrnd", true);
255  setFeatureEnabledImpl(Features, "pclmul", true);
256  setFeatureEnabledImpl(Features, "sse4.2", true);
257  setFeatureEnabledImpl(Features, "prfchw", true);
258  LLVM_FALLTHROUGH;
259  case CK_Bonnell:
260  setFeatureEnabledImpl(Features, "movbe", true);
261  setFeatureEnabledImpl(Features, "ssse3", true);
262  setFeatureEnabledImpl(Features, "fxsr", true);
263  setFeatureEnabledImpl(Features, "cx16", true);
264  setFeatureEnabledImpl(Features, "sahf", true);
265  break;
266 
267  case CK_KNM:
268  // TODO: Add avx5124fmaps/avx5124vnniw.
269  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
270  LLVM_FALLTHROUGH;
271  case CK_KNL:
272  setFeatureEnabledImpl(Features, "avx512f", true);
273  setFeatureEnabledImpl(Features, "avx512cd", true);
274  setFeatureEnabledImpl(Features, "avx512er", true);
275  setFeatureEnabledImpl(Features, "avx512pf", true);
276  setFeatureEnabledImpl(Features, "prfchw", true);
277  setFeatureEnabledImpl(Features, "prefetchwt1", true);
278  setFeatureEnabledImpl(Features, "fxsr", true);
279  setFeatureEnabledImpl(Features, "rdseed", true);
280  setFeatureEnabledImpl(Features, "adx", true);
281  setFeatureEnabledImpl(Features, "lzcnt", true);
282  setFeatureEnabledImpl(Features, "bmi", true);
283  setFeatureEnabledImpl(Features, "bmi2", true);
284  setFeatureEnabledImpl(Features, "rtm", true);
285  setFeatureEnabledImpl(Features, "fma", true);
286  setFeatureEnabledImpl(Features, "rdrnd", true);
287  setFeatureEnabledImpl(Features, "f16c", true);
288  setFeatureEnabledImpl(Features, "fsgsbase", true);
289  setFeatureEnabledImpl(Features, "aes", true);
290  setFeatureEnabledImpl(Features, "pclmul", true);
291  setFeatureEnabledImpl(Features, "cx16", true);
292  setFeatureEnabledImpl(Features, "xsaveopt", true);
293  setFeatureEnabledImpl(Features, "xsave", true);
294  setFeatureEnabledImpl(Features, "movbe", true);
295  setFeatureEnabledImpl(Features, "sahf", true);
296  break;
297 
298  case CK_K6_2:
299  case CK_K6_3:
300  case CK_WinChip2:
301  case CK_C3:
302  setFeatureEnabledImpl(Features, "3dnow", true);
303  break;
304 
305  case CK_AMDFAM10:
306  setFeatureEnabledImpl(Features, "sse4a", true);
307  setFeatureEnabledImpl(Features, "lzcnt", true);
308  setFeatureEnabledImpl(Features, "popcnt", true);
309  setFeatureEnabledImpl(Features, "sahf", true);
310  LLVM_FALLTHROUGH;
311  case CK_K8SSE3:
312  setFeatureEnabledImpl(Features, "sse3", true);
313  LLVM_FALLTHROUGH;
314  case CK_K8:
315  setFeatureEnabledImpl(Features, "sse2", true);
316  LLVM_FALLTHROUGH;
317  case CK_AthlonXP:
318  setFeatureEnabledImpl(Features, "sse", true);
319  setFeatureEnabledImpl(Features, "fxsr", true);
320  LLVM_FALLTHROUGH;
321  case CK_Athlon:
322  case CK_Geode:
323  setFeatureEnabledImpl(Features, "3dnowa", true);
324  break;
325 
326  case CK_BTVER2:
327  setFeatureEnabledImpl(Features, "avx", true);
328  setFeatureEnabledImpl(Features, "aes", true);
329  setFeatureEnabledImpl(Features, "pclmul", true);
330  setFeatureEnabledImpl(Features, "bmi", true);
331  setFeatureEnabledImpl(Features, "f16c", true);
332  setFeatureEnabledImpl(Features, "xsaveopt", true);
333  setFeatureEnabledImpl(Features, "movbe", true);
334  LLVM_FALLTHROUGH;
335  case CK_BTVER1:
336  setFeatureEnabledImpl(Features, "ssse3", true);
337  setFeatureEnabledImpl(Features, "sse4a", true);
338  setFeatureEnabledImpl(Features, "lzcnt", true);
339  setFeatureEnabledImpl(Features, "popcnt", true);
340  setFeatureEnabledImpl(Features, "prfchw", true);
341  setFeatureEnabledImpl(Features, "cx16", true);
342  setFeatureEnabledImpl(Features, "fxsr", true);
343  setFeatureEnabledImpl(Features, "sahf", true);
344  break;
345 
346  case CK_ZNVER1:
347  setFeatureEnabledImpl(Features, "adx", true);
348  setFeatureEnabledImpl(Features, "aes", true);
349  setFeatureEnabledImpl(Features, "avx2", true);
350  setFeatureEnabledImpl(Features, "bmi", true);
351  setFeatureEnabledImpl(Features, "bmi2", true);
352  setFeatureEnabledImpl(Features, "clflushopt", true);
353  setFeatureEnabledImpl(Features, "clzero", true);
354  setFeatureEnabledImpl(Features, "cx16", true);
355  setFeatureEnabledImpl(Features, "f16c", true);
356  setFeatureEnabledImpl(Features, "fma", true);
357  setFeatureEnabledImpl(Features, "fsgsbase", true);
358  setFeatureEnabledImpl(Features, "fxsr", true);
359  setFeatureEnabledImpl(Features, "lzcnt", true);
360  setFeatureEnabledImpl(Features, "mwaitx", true);
361  setFeatureEnabledImpl(Features, "movbe", true);
362  setFeatureEnabledImpl(Features, "pclmul", true);
363  setFeatureEnabledImpl(Features, "popcnt", true);
364  setFeatureEnabledImpl(Features, "prfchw", true);
365  setFeatureEnabledImpl(Features, "rdrnd", true);
366  setFeatureEnabledImpl(Features, "rdseed", true);
367  setFeatureEnabledImpl(Features, "sahf", true);
368  setFeatureEnabledImpl(Features, "sha", true);
369  setFeatureEnabledImpl(Features, "sse4a", true);
370  setFeatureEnabledImpl(Features, "xsave", true);
371  setFeatureEnabledImpl(Features, "xsavec", true);
372  setFeatureEnabledImpl(Features, "xsaveopt", true);
373  setFeatureEnabledImpl(Features, "xsaves", true);
374  break;
375 
376  case CK_BDVER4:
377  setFeatureEnabledImpl(Features, "avx2", true);
378  setFeatureEnabledImpl(Features, "bmi2", true);
379  setFeatureEnabledImpl(Features, "mwaitx", true);
380  LLVM_FALLTHROUGH;
381  case CK_BDVER3:
382  setFeatureEnabledImpl(Features, "fsgsbase", true);
383  setFeatureEnabledImpl(Features, "xsaveopt", true);
384  LLVM_FALLTHROUGH;
385  case CK_BDVER2:
386  setFeatureEnabledImpl(Features, "bmi", true);
387  setFeatureEnabledImpl(Features, "fma", true);
388  setFeatureEnabledImpl(Features, "f16c", true);
389  setFeatureEnabledImpl(Features, "tbm", true);
390  LLVM_FALLTHROUGH;
391  case CK_BDVER1:
392  // xop implies avx, sse4a and fma4.
393  setFeatureEnabledImpl(Features, "xop", true);
394  setFeatureEnabledImpl(Features, "lwp", true);
395  setFeatureEnabledImpl(Features, "lzcnt", true);
396  setFeatureEnabledImpl(Features, "aes", true);
397  setFeatureEnabledImpl(Features, "pclmul", true);
398  setFeatureEnabledImpl(Features, "prfchw", true);
399  setFeatureEnabledImpl(Features, "cx16", true);
400  setFeatureEnabledImpl(Features, "fxsr", true);
401  setFeatureEnabledImpl(Features, "xsave", true);
402  setFeatureEnabledImpl(Features, "sahf", true);
403  break;
404  }
405  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
406  return false;
407 
408  // Can't do this earlier because we need to be able to explicitly enable
409  // or disable these features and the things that they depend upon.
410 
411  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
412  auto I = Features.find("sse4.2");
413  if (I != Features.end() && I->getValue() &&
414  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
415  FeaturesVec.end())
416  Features["popcnt"] = true;
417 
418  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
419  I = Features.find("3dnow");
420  if (I != Features.end() && I->getValue() &&
421  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
422  FeaturesVec.end())
423  Features["prfchw"] = true;
424 
425  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
426  // then enable MMX.
427  I = Features.find("sse");
428  if (I != Features.end() && I->getValue() &&
429  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
430  FeaturesVec.end())
431  Features["mmx"] = true;
432 
433  return true;
434 }
435 
436 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
437  X86SSEEnum Level, bool Enabled) {
438  if (Enabled) {
439  switch (Level) {
440  case AVX512F:
441  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
442  LLVM_FALLTHROUGH;
443  case AVX2:
444  Features["avx2"] = true;
445  LLVM_FALLTHROUGH;
446  case AVX:
447  Features["avx"] = true;
448  Features["xsave"] = true;
449  LLVM_FALLTHROUGH;
450  case SSE42:
451  Features["sse4.2"] = true;
452  LLVM_FALLTHROUGH;
453  case SSE41:
454  Features["sse4.1"] = true;
455  LLVM_FALLTHROUGH;
456  case SSSE3:
457  Features["ssse3"] = true;
458  LLVM_FALLTHROUGH;
459  case SSE3:
460  Features["sse3"] = true;
461  LLVM_FALLTHROUGH;
462  case SSE2:
463  Features["sse2"] = true;
464  LLVM_FALLTHROUGH;
465  case SSE1:
466  Features["sse"] = true;
467  LLVM_FALLTHROUGH;
468  case NoSSE:
469  break;
470  }
471  return;
472  }
473 
474  switch (Level) {
475  case NoSSE:
476  case SSE1:
477  Features["sse"] = false;
478  LLVM_FALLTHROUGH;
479  case SSE2:
480  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
481  Features["gfni"] = false;
482  LLVM_FALLTHROUGH;
483  case SSE3:
484  Features["sse3"] = false;
485  setXOPLevel(Features, NoXOP, false);
486  LLVM_FALLTHROUGH;
487  case SSSE3:
488  Features["ssse3"] = false;
489  LLVM_FALLTHROUGH;
490  case SSE41:
491  Features["sse4.1"] = false;
492  LLVM_FALLTHROUGH;
493  case SSE42:
494  Features["sse4.2"] = false;
495  LLVM_FALLTHROUGH;
496  case AVX:
497  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
498  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
499  setXOPLevel(Features, FMA4, false);
500  LLVM_FALLTHROUGH;
501  case AVX2:
502  Features["avx2"] = false;
503  LLVM_FALLTHROUGH;
504  case AVX512F:
505  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
506  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
507  Features["avx512vl"] = Features["avx512vbmi"] =
508  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
509  Features["avx512bitalg"] = Features["avx512vnni"] =
510  Features["avx512vbmi2"] = false;
511  break;
512  }
513 }
514 
515 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
516  MMX3DNowEnum Level, bool Enabled) {
517  if (Enabled) {
518  switch (Level) {
519  case AMD3DNowAthlon:
520  Features["3dnowa"] = true;
521  LLVM_FALLTHROUGH;
522  case AMD3DNow:
523  Features["3dnow"] = true;
524  LLVM_FALLTHROUGH;
525  case MMX:
526  Features["mmx"] = true;
527  LLVM_FALLTHROUGH;
528  case NoMMX3DNow:
529  break;
530  }
531  return;
532  }
533 
534  switch (Level) {
535  case NoMMX3DNow:
536  case MMX:
537  Features["mmx"] = false;
538  LLVM_FALLTHROUGH;
539  case AMD3DNow:
540  Features["3dnow"] = false;
541  LLVM_FALLTHROUGH;
542  case AMD3DNowAthlon:
543  Features["3dnowa"] = false;
544  break;
545  }
546 }
547 
548 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
549  bool Enabled) {
550  if (Enabled) {
551  switch (Level) {
552  case XOP:
553  Features["xop"] = true;
554  LLVM_FALLTHROUGH;
555  case FMA4:
556  Features["fma4"] = true;
557  setSSELevel(Features, AVX, true);
558  LLVM_FALLTHROUGH;
559  case SSE4A:
560  Features["sse4a"] = true;
561  setSSELevel(Features, SSE3, true);
562  LLVM_FALLTHROUGH;
563  case NoXOP:
564  break;
565  }
566  return;
567  }
568 
569  switch (Level) {
570  case NoXOP:
571  case SSE4A:
572  Features["sse4a"] = false;
573  LLVM_FALLTHROUGH;
574  case FMA4:
575  Features["fma4"] = false;
576  LLVM_FALLTHROUGH;
577  case XOP:
578  Features["xop"] = false;
579  break;
580  }
581 }
582 
583 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
584  StringRef Name, bool Enabled) {
585  // This is a bit of a hack to deal with the sse4 target feature when used
586  // as part of the target attribute. We handle sse4 correctly everywhere
587  // else. See below for more information on how we handle the sse4 options.
588  if (Name != "sse4")
589  Features[Name] = Enabled;
590 
591  if (Name == "mmx") {
592  setMMXLevel(Features, MMX, Enabled);
593  } else if (Name == "sse") {
594  setSSELevel(Features, SSE1, Enabled);
595  } else if (Name == "sse2") {
596  setSSELevel(Features, SSE2, Enabled);
597  } else if (Name == "sse3") {
598  setSSELevel(Features, SSE3, Enabled);
599  } else if (Name == "ssse3") {
600  setSSELevel(Features, SSSE3, Enabled);
601  } else if (Name == "sse4.2") {
602  setSSELevel(Features, SSE42, Enabled);
603  } else if (Name == "sse4.1") {
604  setSSELevel(Features, SSE41, Enabled);
605  } else if (Name == "3dnow") {
606  setMMXLevel(Features, AMD3DNow, Enabled);
607  } else if (Name == "3dnowa") {
608  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
609  } else if (Name == "aes") {
610  if (Enabled)
611  setSSELevel(Features, SSE2, Enabled);
612  else
613  Features["vaes"] = false;
614  } else if (Name == "vaes") {
615  if (Enabled) {
616  setSSELevel(Features, AVX, Enabled);
617  Features["aes"] = true;
618  }
619  } else if (Name == "pclmul") {
620  if (Enabled)
621  setSSELevel(Features, SSE2, Enabled);
622  else
623  Features["vpclmulqdq"] = false;
624  } else if (Name == "vpclmulqdq") {
625  if (Enabled) {
626  setSSELevel(Features, AVX, Enabled);
627  Features["pclmul"] = true;
628  }
629  } else if (Name == "gfni") {
630  if (Enabled)
631  setSSELevel(Features, SSE2, Enabled);
632  } else if (Name == "avx") {
633  setSSELevel(Features, AVX, Enabled);
634  } else if (Name == "avx2") {
635  setSSELevel(Features, AVX2, Enabled);
636  } else if (Name == "avx512f") {
637  setSSELevel(Features, AVX512F, Enabled);
638  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
639  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
640  Name == "avx512vbmi" || Name == "avx512ifma" ||
641  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
642  Name == "avx512vnni" || Name == "avx512vbmi2") {
643  if (Enabled)
644  setSSELevel(Features, AVX512F, Enabled);
645  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
646  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
647  Features["avx512bw"] = true;
648  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
649  if (Name == "avx512bw" && !Enabled)
650  Features["avx512vbmi"] = Features["avx512vbmi2"] =
651  Features["avx512bitalg"] = false;
652  } else if (Name == "fma") {
653  if (Enabled)
654  setSSELevel(Features, AVX, Enabled);
655  else
656  setSSELevel(Features, AVX512F, Enabled);
657  } else if (Name == "fma4") {
658  setXOPLevel(Features, FMA4, Enabled);
659  } else if (Name == "xop") {
660  setXOPLevel(Features, XOP, Enabled);
661  } else if (Name == "sse4a") {
662  setXOPLevel(Features, SSE4A, Enabled);
663  } else if (Name == "f16c") {
664  if (Enabled)
665  setSSELevel(Features, AVX, Enabled);
666  else
667  setSSELevel(Features, AVX512F, Enabled);
668  } else if (Name == "sha") {
669  if (Enabled)
670  setSSELevel(Features, SSE2, Enabled);
671  } else if (Name == "sse4") {
672  // We can get here via the __target__ attribute since that's not controlled
673  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
674  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
675  // disabled.
676  if (Enabled)
677  setSSELevel(Features, SSE42, Enabled);
678  else
679  setSSELevel(Features, SSE41, Enabled);
680  } else if (Name == "xsave") {
681  if (!Enabled)
682  Features["xsaveopt"] = false;
683  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
684  if (Enabled)
685  Features["xsave"] = true;
686  }
687 }
688 
689 /// handleTargetFeatures - Perform initialization based on the user
690 /// configured set of features.
691 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
692  DiagnosticsEngine &Diags) {
693  for (const auto &Feature : Features) {
694  if (Feature[0] != '+')
695  continue;
696 
697  if (Feature == "+aes") {
698  HasAES = true;
699  } else if (Feature == "+vaes") {
700  HasVAES = true;
701  } else if (Feature == "+pclmul") {
702  HasPCLMUL = true;
703  } else if (Feature == "+vpclmulqdq") {
704  HasVPCLMULQDQ = true;
705  } else if (Feature == "+lzcnt") {
706  HasLZCNT = true;
707  } else if (Feature == "+rdrnd") {
708  HasRDRND = true;
709  } else if (Feature == "+fsgsbase") {
710  HasFSGSBASE = true;
711  } else if (Feature == "+bmi") {
712  HasBMI = true;
713  } else if (Feature == "+bmi2") {
714  HasBMI2 = true;
715  } else if (Feature == "+popcnt") {
716  HasPOPCNT = true;
717  } else if (Feature == "+rtm") {
718  HasRTM = true;
719  } else if (Feature == "+prfchw") {
720  HasPRFCHW = true;
721  } else if (Feature == "+rdseed") {
722  HasRDSEED = true;
723  } else if (Feature == "+adx") {
724  HasADX = true;
725  } else if (Feature == "+tbm") {
726  HasTBM = true;
727  } else if (Feature == "+lwp") {
728  HasLWP = true;
729  } else if (Feature == "+fma") {
730  HasFMA = true;
731  } else if (Feature == "+f16c") {
732  HasF16C = true;
733  } else if (Feature == "+gfni") {
734  HasGFNI = true;
735  } else if (Feature == "+avx512cd") {
736  HasAVX512CD = true;
737  } else if (Feature == "+avx512vpopcntdq") {
738  HasAVX512VPOPCNTDQ = true;
739  } else if (Feature == "+avx512vnni") {
740  HasAVX512VNNI = true;
741  } else if (Feature == "+avx512er") {
742  HasAVX512ER = true;
743  } else if (Feature == "+avx512pf") {
744  HasAVX512PF = true;
745  } else if (Feature == "+avx512dq") {
746  HasAVX512DQ = true;
747  } else if (Feature == "+avx512bitalg") {
748  HasAVX512BITALG = true;
749  } else if (Feature == "+avx512bw") {
750  HasAVX512BW = true;
751  } else if (Feature == "+avx512vl") {
752  HasAVX512VL = true;
753  } else if (Feature == "+avx512vbmi") {
754  HasAVX512VBMI = true;
755  } else if (Feature == "+avx512vbmi2") {
756  HasAVX512VBMI2 = true;
757  } else if (Feature == "+avx512ifma") {
758  HasAVX512IFMA = true;
759  } else if (Feature == "+sha") {
760  HasSHA = true;
761  } else if (Feature == "+mpx") {
762  HasMPX = true;
763  } else if (Feature == "+shstk") {
764  HasSHSTK = true;
765  } else if (Feature == "+movbe") {
766  HasMOVBE = true;
767  } else if (Feature == "+sgx") {
768  HasSGX = true;
769  } else if (Feature == "+cx16") {
770  HasCX16 = true;
771  } else if (Feature == "+fxsr") {
772  HasFXSR = true;
773  } else if (Feature == "+xsave") {
774  HasXSAVE = true;
775  } else if (Feature == "+xsaveopt") {
776  HasXSAVEOPT = true;
777  } else if (Feature == "+xsavec") {
778  HasXSAVEC = true;
779  } else if (Feature == "+xsaves") {
780  HasXSAVES = true;
781  } else if (Feature == "+mwaitx") {
782  HasMWAITX = true;
783  } else if (Feature == "+pku") {
784  HasPKU = true;
785  } else if (Feature == "+clflushopt") {
786  HasCLFLUSHOPT = true;
787  } else if (Feature == "+clwb") {
788  HasCLWB = true;
789  } else if (Feature == "+wbnoinvd") {
790  HasWBNOINVD = true;
791  } else if (Feature == "+prefetchwt1") {
792  HasPREFETCHWT1 = true;
793  } else if (Feature == "+clzero") {
794  HasCLZERO = true;
795  } else if (Feature == "+cldemote") {
796  HasCLDEMOTE = true;
797  } else if (Feature == "+rdpid") {
798  HasRDPID = true;
799  } else if (Feature == "+retpoline-external-thunk") {
800  HasRetpolineExternalThunk = true;
801  } else if (Feature == "+sahf") {
802  HasLAHFSAHF = true;
803  } else if (Feature == "+waitpkg") {
804  HasWAITPKG = true;
805  } else if (Feature == "+movdiri") {
806  HasMOVDIRI = true;
807  } else if (Feature == "+movdir64b") {
808  HasMOVDIR64B = true;
809  } else if (Feature == "+pconfig") {
810  HasPCONFIG = true;
811  } else if (Feature == "+ptwrite") {
812  HasPTWRITE = true;
813  } else if (Feature == "+invpcid") {
814  HasINVPCID = true;
815  }
816 
817  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
818  .Case("+avx512f", AVX512F)
819  .Case("+avx2", AVX2)
820  .Case("+avx", AVX)
821  .Case("+sse4.2", SSE42)
822  .Case("+sse4.1", SSE41)
823  .Case("+ssse3", SSSE3)
824  .Case("+sse3", SSE3)
825  .Case("+sse2", SSE2)
826  .Case("+sse", SSE1)
827  .Default(NoSSE);
828  SSELevel = std::max(SSELevel, Level);
829 
830  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
831  .Case("+3dnowa", AMD3DNowAthlon)
832  .Case("+3dnow", AMD3DNow)
833  .Case("+mmx", MMX)
834  .Default(NoMMX3DNow);
835  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
836 
837  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
838  .Case("+xop", XOP)
839  .Case("+fma4", FMA4)
840  .Case("+sse4a", SSE4A)
841  .Default(NoXOP);
842  XOPLevel = std::max(XOPLevel, XLevel);
843  }
844 
845  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
846  // matches the selected sse level.
847  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
848  (FPMath == FP_387 && SSELevel >= SSE1)) {
849  Diags.Report(diag::err_target_unsupported_fpmath)
850  << (FPMath == FP_SSE ? "sse" : "387");
851  return false;
852  }
853 
854  SimdDefaultAlign =
855  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
856  return true;
857 }
858 
859 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
860 /// definitions for this particular subtarget.
862  MacroBuilder &Builder) const {
863  // Target identification.
864  if (getTriple().getArch() == llvm::Triple::x86_64) {
865  Builder.defineMacro("__amd64__");
866  Builder.defineMacro("__amd64");
867  Builder.defineMacro("__x86_64");
868  Builder.defineMacro("__x86_64__");
869  if (getTriple().getArchName() == "x86_64h") {
870  Builder.defineMacro("__x86_64h");
871  Builder.defineMacro("__x86_64h__");
872  }
873  } else {
874  DefineStd(Builder, "i386", Opts);
875  }
876 
877  // Subtarget options.
878  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
879  // truly should be based on -mtune options.
880  switch (CPU) {
881  case CK_Generic:
882  break;
883  case CK_i386:
884  // The rest are coming from the i386 define above.
885  Builder.defineMacro("__tune_i386__");
886  break;
887  case CK_i486:
888  case CK_WinChipC6:
889  case CK_WinChip2:
890  case CK_C3:
891  defineCPUMacros(Builder, "i486");
892  break;
893  case CK_PentiumMMX:
894  Builder.defineMacro("__pentium_mmx__");
895  Builder.defineMacro("__tune_pentium_mmx__");
896  LLVM_FALLTHROUGH;
897  case CK_i586:
898  case CK_Pentium:
899  defineCPUMacros(Builder, "i586");
900  defineCPUMacros(Builder, "pentium");
901  break;
902  case CK_Pentium3:
903  case CK_PentiumM:
904  Builder.defineMacro("__tune_pentium3__");
905  LLVM_FALLTHROUGH;
906  case CK_Pentium2:
907  case CK_C3_2:
908  Builder.defineMacro("__tune_pentium2__");
909  LLVM_FALLTHROUGH;
910  case CK_PentiumPro:
911  defineCPUMacros(Builder, "i686");
912  defineCPUMacros(Builder, "pentiumpro");
913  break;
914  case CK_Pentium4:
915  defineCPUMacros(Builder, "pentium4");
916  break;
917  case CK_Yonah:
918  case CK_Prescott:
919  case CK_Nocona:
920  defineCPUMacros(Builder, "nocona");
921  break;
922  case CK_Core2:
923  case CK_Penryn:
924  defineCPUMacros(Builder, "core2");
925  break;
926  case CK_Bonnell:
927  defineCPUMacros(Builder, "atom");
928  break;
929  case CK_Silvermont:
930  defineCPUMacros(Builder, "slm");
931  break;
932  case CK_Goldmont:
933  defineCPUMacros(Builder, "goldmont");
934  break;
935  case CK_GoldmontPlus:
936  defineCPUMacros(Builder, "goldmont_plus");
937  break;
938  case CK_Tremont:
939  defineCPUMacros(Builder, "tremont");
940  break;
941  case CK_Nehalem:
942  case CK_Westmere:
943  case CK_SandyBridge:
944  case CK_IvyBridge:
945  case CK_Haswell:
946  case CK_Broadwell:
947  case CK_SkylakeClient:
948  case CK_SkylakeServer:
949  case CK_Cannonlake:
950  case CK_IcelakeClient:
951  case CK_IcelakeServer:
952  // FIXME: Historically, we defined this legacy name, it would be nice to
953  // remove it at some point. We've never exposed fine-grained names for
954  // recent primary x86 CPUs, and we should keep it that way.
955  defineCPUMacros(Builder, "corei7");
956  break;
957  case CK_KNL:
958  defineCPUMacros(Builder, "knl");
959  break;
960  case CK_KNM:
961  break;
962  case CK_Lakemont:
963  defineCPUMacros(Builder, "i586", /*Tuning*/false);
964  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
965  Builder.defineMacro("__tune_lakemont__");
966  break;
967  case CK_K6_2:
968  Builder.defineMacro("__k6_2__");
969  Builder.defineMacro("__tune_k6_2__");
970  LLVM_FALLTHROUGH;
971  case CK_K6_3:
972  if (CPU != CK_K6_2) { // In case of fallthrough
973  // FIXME: GCC may be enabling these in cases where some other k6
974  // architecture is specified but -m3dnow is explicitly provided. The
975  // exact semantics need to be determined and emulated here.
976  Builder.defineMacro("__k6_3__");
977  Builder.defineMacro("__tune_k6_3__");
978  }
979  LLVM_FALLTHROUGH;
980  case CK_K6:
981  defineCPUMacros(Builder, "k6");
982  break;
983  case CK_Athlon:
984  case CK_AthlonXP:
985  defineCPUMacros(Builder, "athlon");
986  if (SSELevel != NoSSE) {
987  Builder.defineMacro("__athlon_sse__");
988  Builder.defineMacro("__tune_athlon_sse__");
989  }
990  break;
991  case CK_K8:
992  case CK_K8SSE3:
993  case CK_x86_64:
994  defineCPUMacros(Builder, "k8");
995  break;
996  case CK_AMDFAM10:
997  defineCPUMacros(Builder, "amdfam10");
998  break;
999  case CK_BTVER1:
1000  defineCPUMacros(Builder, "btver1");
1001  break;
1002  case CK_BTVER2:
1003  defineCPUMacros(Builder, "btver2");
1004  break;
1005  case CK_BDVER1:
1006  defineCPUMacros(Builder, "bdver1");
1007  break;
1008  case CK_BDVER2:
1009  defineCPUMacros(Builder, "bdver2");
1010  break;
1011  case CK_BDVER3:
1012  defineCPUMacros(Builder, "bdver3");
1013  break;
1014  case CK_BDVER4:
1015  defineCPUMacros(Builder, "bdver4");
1016  break;
1017  case CK_ZNVER1:
1018  defineCPUMacros(Builder, "znver1");
1019  break;
1020  case CK_Geode:
1021  defineCPUMacros(Builder, "geode");
1022  break;
1023  }
1024 
1025  // Target properties.
1026  Builder.defineMacro("__REGISTER_PREFIX__", "");
1027 
1028  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1029  // functions in glibc header files that use FP Stack inline asm which the
1030  // backend can't deal with (PR879).
1031  Builder.defineMacro("__NO_MATH_INLINES");
1032 
1033  if (HasAES)
1034  Builder.defineMacro("__AES__");
1035 
1036  if (HasVAES)
1037  Builder.defineMacro("__VAES__");
1038 
1039  if (HasPCLMUL)
1040  Builder.defineMacro("__PCLMUL__");
1041 
1042  if (HasVPCLMULQDQ)
1043  Builder.defineMacro("__VPCLMULQDQ__");
1044 
1045  if (HasLZCNT)
1046  Builder.defineMacro("__LZCNT__");
1047 
1048  if (HasRDRND)
1049  Builder.defineMacro("__RDRND__");
1050 
1051  if (HasFSGSBASE)
1052  Builder.defineMacro("__FSGSBASE__");
1053 
1054  if (HasBMI)
1055  Builder.defineMacro("__BMI__");
1056 
1057  if (HasBMI2)
1058  Builder.defineMacro("__BMI2__");
1059 
1060  if (HasPOPCNT)
1061  Builder.defineMacro("__POPCNT__");
1062 
1063  if (HasRTM)
1064  Builder.defineMacro("__RTM__");
1065 
1066  if (HasPRFCHW)
1067  Builder.defineMacro("__PRFCHW__");
1068 
1069  if (HasRDSEED)
1070  Builder.defineMacro("__RDSEED__");
1071 
1072  if (HasADX)
1073  Builder.defineMacro("__ADX__");
1074 
1075  if (HasTBM)
1076  Builder.defineMacro("__TBM__");
1077 
1078  if (HasLWP)
1079  Builder.defineMacro("__LWP__");
1080 
1081  if (HasMWAITX)
1082  Builder.defineMacro("__MWAITX__");
1083 
1084  switch (XOPLevel) {
1085  case XOP:
1086  Builder.defineMacro("__XOP__");
1087  LLVM_FALLTHROUGH;
1088  case FMA4:
1089  Builder.defineMacro("__FMA4__");
1090  LLVM_FALLTHROUGH;
1091  case SSE4A:
1092  Builder.defineMacro("__SSE4A__");
1093  LLVM_FALLTHROUGH;
1094  case NoXOP:
1095  break;
1096  }
1097 
1098  if (HasFMA)
1099  Builder.defineMacro("__FMA__");
1100 
1101  if (HasF16C)
1102  Builder.defineMacro("__F16C__");
1103 
1104  if (HasGFNI)
1105  Builder.defineMacro("__GFNI__");
1106 
1107  if (HasAVX512CD)
1108  Builder.defineMacro("__AVX512CD__");
1109  if (HasAVX512VPOPCNTDQ)
1110  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1111  if (HasAVX512VNNI)
1112  Builder.defineMacro("__AVX512VNNI__");
1113  if (HasAVX512ER)
1114  Builder.defineMacro("__AVX512ER__");
1115  if (HasAVX512PF)
1116  Builder.defineMacro("__AVX512PF__");
1117  if (HasAVX512DQ)
1118  Builder.defineMacro("__AVX512DQ__");
1119  if (HasAVX512BITALG)
1120  Builder.defineMacro("__AVX512BITALG__");
1121  if (HasAVX512BW)
1122  Builder.defineMacro("__AVX512BW__");
1123  if (HasAVX512VL)
1124  Builder.defineMacro("__AVX512VL__");
1125  if (HasAVX512VBMI)
1126  Builder.defineMacro("__AVX512VBMI__");
1127  if (HasAVX512VBMI2)
1128  Builder.defineMacro("__AVX512VBMI2__");
1129  if (HasAVX512IFMA)
1130  Builder.defineMacro("__AVX512IFMA__");
1131 
1132  if (HasSHA)
1133  Builder.defineMacro("__SHA__");
1134 
1135  if (HasFXSR)
1136  Builder.defineMacro("__FXSR__");
1137  if (HasXSAVE)
1138  Builder.defineMacro("__XSAVE__");
1139  if (HasXSAVEOPT)
1140  Builder.defineMacro("__XSAVEOPT__");
1141  if (HasXSAVEC)
1142  Builder.defineMacro("__XSAVEC__");
1143  if (HasXSAVES)
1144  Builder.defineMacro("__XSAVES__");
1145  if (HasPKU)
1146  Builder.defineMacro("__PKU__");
1147  if (HasCLFLUSHOPT)
1148  Builder.defineMacro("__CLFLUSHOPT__");
1149  if (HasCLWB)
1150  Builder.defineMacro("__CLWB__");
1151  if (HasWBNOINVD)
1152  Builder.defineMacro("__WBNOINVD__");
1153  if (HasMPX)
1154  Builder.defineMacro("__MPX__");
1155  if (HasSHSTK)
1156  Builder.defineMacro("__SHSTK__");
1157  if (HasSGX)
1158  Builder.defineMacro("__SGX__");
1159  if (HasPREFETCHWT1)
1160  Builder.defineMacro("__PREFETCHWT1__");
1161  if (HasCLZERO)
1162  Builder.defineMacro("__CLZERO__");
1163  if (HasRDPID)
1164  Builder.defineMacro("__RDPID__");
1165  if (HasCLDEMOTE)
1166  Builder.defineMacro("__CLDEMOTE__");
1167  if (HasWAITPKG)
1168  Builder.defineMacro("__WAITPKG__");
1169  if (HasMOVDIRI)
1170  Builder.defineMacro("__MOVDIRI__");
1171  if (HasMOVDIR64B)
1172  Builder.defineMacro("__MOVDIR64B__");
1173  if (HasPCONFIG)
1174  Builder.defineMacro("__PCONFIG__");
1175  if (HasPTWRITE)
1176  Builder.defineMacro("__PTWRITE__");
1177  if (HasINVPCID)
1178  Builder.defineMacro("__INVPCID__");
1179 
1180  // Each case falls through to the previous one here.
1181  switch (SSELevel) {
1182  case AVX512F:
1183  Builder.defineMacro("__AVX512F__");
1184  LLVM_FALLTHROUGH;
1185  case AVX2:
1186  Builder.defineMacro("__AVX2__");
1187  LLVM_FALLTHROUGH;
1188  case AVX:
1189  Builder.defineMacro("__AVX__");
1190  LLVM_FALLTHROUGH;
1191  case SSE42:
1192  Builder.defineMacro("__SSE4_2__");
1193  LLVM_FALLTHROUGH;
1194  case SSE41:
1195  Builder.defineMacro("__SSE4_1__");
1196  LLVM_FALLTHROUGH;
1197  case SSSE3:
1198  Builder.defineMacro("__SSSE3__");
1199  LLVM_FALLTHROUGH;
1200  case SSE3:
1201  Builder.defineMacro("__SSE3__");
1202  LLVM_FALLTHROUGH;
1203  case SSE2:
1204  Builder.defineMacro("__SSE2__");
1205  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1206  LLVM_FALLTHROUGH;
1207  case SSE1:
1208  Builder.defineMacro("__SSE__");
1209  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1210  LLVM_FALLTHROUGH;
1211  case NoSSE:
1212  break;
1213  }
1214 
1215  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1216  switch (SSELevel) {
1217  case AVX512F:
1218  case AVX2:
1219  case AVX:
1220  case SSE42:
1221  case SSE41:
1222  case SSSE3:
1223  case SSE3:
1224  case SSE2:
1225  Builder.defineMacro("_M_IX86_FP", Twine(2));
1226  break;
1227  case SSE1:
1228  Builder.defineMacro("_M_IX86_FP", Twine(1));
1229  break;
1230  default:
1231  Builder.defineMacro("_M_IX86_FP", Twine(0));
1232  break;
1233  }
1234  }
1235 
1236  // Each case falls through to the previous one here.
1237  switch (MMX3DNowLevel) {
1238  case AMD3DNowAthlon:
1239  Builder.defineMacro("__3dNOW_A__");
1240  LLVM_FALLTHROUGH;
1241  case AMD3DNow:
1242  Builder.defineMacro("__3dNOW__");
1243  LLVM_FALLTHROUGH;
1244  case MMX:
1245  Builder.defineMacro("__MMX__");
1246  LLVM_FALLTHROUGH;
1247  case NoMMX3DNow:
1248  break;
1249  }
1250 
1251  if (CPU >= CK_i486) {
1252  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1253  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1254  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1255  }
1256  if (CPU >= CK_i586)
1257  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1258  if (HasCX16)
1259  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1260 
1261  if (HasFloat128)
1262  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1263 }
1264 
1265 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1266  return llvm::StringSwitch<bool>(Name)
1267  .Case("3dnow", true)
1268  .Case("3dnowa", true)
1269  .Case("adx", true)
1270  .Case("aes", true)
1271  .Case("avx", true)
1272  .Case("avx2", true)
1273  .Case("avx512f", true)
1274  .Case("avx512cd", true)
1275  .Case("avx512vpopcntdq", true)
1276  .Case("avx512vnni", true)
1277  .Case("avx512er", true)
1278  .Case("avx512pf", true)
1279  .Case("avx512dq", true)
1280  .Case("avx512bitalg", true)
1281  .Case("avx512bw", true)
1282  .Case("avx512vl", true)
1283  .Case("avx512vbmi", true)
1284  .Case("avx512vbmi2", true)
1285  .Case("avx512ifma", true)
1286  .Case("bmi", true)
1287  .Case("bmi2", true)
1288  .Case("cldemote", true)
1289  .Case("clflushopt", true)
1290  .Case("clwb", true)
1291  .Case("clzero", true)
1292  .Case("cx16", true)
1293  .Case("f16c", true)
1294  .Case("fma", true)
1295  .Case("fma4", true)
1296  .Case("fsgsbase", true)
1297  .Case("fxsr", true)
1298  .Case("gfni", true)
1299  .Case("invpcid", true)
1300  .Case("lwp", true)
1301  .Case("lzcnt", true)
1302  .Case("mmx", true)
1303  .Case("movbe", true)
1304  .Case("movdiri", true)
1305  .Case("movdir64b", true)
1306  .Case("mpx", true)
1307  .Case("mwaitx", true)
1308  .Case("pclmul", true)
1309  .Case("pconfig", true)
1310  .Case("pku", true)
1311  .Case("popcnt", true)
1312  .Case("prefetchwt1", true)
1313  .Case("prfchw", true)
1314  .Case("ptwrite", true)
1315  .Case("rdpid", true)
1316  .Case("rdrnd", true)
1317  .Case("rdseed", true)
1318  .Case("rtm", true)
1319  .Case("sahf", true)
1320  .Case("sgx", true)
1321  .Case("sha", true)
1322  .Case("shstk", true)
1323  .Case("sse", true)
1324  .Case("sse2", true)
1325  .Case("sse3", true)
1326  .Case("ssse3", true)
1327  .Case("sse4", true)
1328  .Case("sse4.1", true)
1329  .Case("sse4.2", true)
1330  .Case("sse4a", true)
1331  .Case("tbm", true)
1332  .Case("vaes", true)
1333  .Case("vpclmulqdq", true)
1334  .Case("wbnoinvd", true)
1335  .Case("waitpkg", true)
1336  .Case("x87", true)
1337  .Case("xop", true)
1338  .Case("xsave", true)
1339  .Case("xsavec", true)
1340  .Case("xsaves", true)
1341  .Case("xsaveopt", true)
1342  .Default(false);
1343 }
1344 
1345 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1346  return llvm::StringSwitch<bool>(Feature)
1347  .Case("adx", HasADX)
1348  .Case("aes", HasAES)
1349  .Case("avx", SSELevel >= AVX)
1350  .Case("avx2", SSELevel >= AVX2)
1351  .Case("avx512f", SSELevel >= AVX512F)
1352  .Case("avx512cd", HasAVX512CD)
1353  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1354  .Case("avx512vnni", HasAVX512VNNI)
1355  .Case("avx512er", HasAVX512ER)
1356  .Case("avx512pf", HasAVX512PF)
1357  .Case("avx512dq", HasAVX512DQ)
1358  .Case("avx512bitalg", HasAVX512BITALG)
1359  .Case("avx512bw", HasAVX512BW)
1360  .Case("avx512vl", HasAVX512VL)
1361  .Case("avx512vbmi", HasAVX512VBMI)
1362  .Case("avx512vbmi2", HasAVX512VBMI2)
1363  .Case("avx512ifma", HasAVX512IFMA)
1364  .Case("bmi", HasBMI)
1365  .Case("bmi2", HasBMI2)
1366  .Case("cldemote", HasCLDEMOTE)
1367  .Case("clflushopt", HasCLFLUSHOPT)
1368  .Case("clwb", HasCLWB)
1369  .Case("clzero", HasCLZERO)
1370  .Case("cx16", HasCX16)
1371  .Case("f16c", HasF16C)
1372  .Case("fma", HasFMA)
1373  .Case("fma4", XOPLevel >= FMA4)
1374  .Case("fsgsbase", HasFSGSBASE)
1375  .Case("fxsr", HasFXSR)
1376  .Case("gfni", HasGFNI)
1377  .Case("invpcid", HasINVPCID)
1378  .Case("lwp", HasLWP)
1379  .Case("lzcnt", HasLZCNT)
1380  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1381  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1382  .Case("mmx", MMX3DNowLevel >= MMX)
1383  .Case("movbe", HasMOVBE)
1384  .Case("movdiri", HasMOVDIRI)
1385  .Case("movdir64b", HasMOVDIR64B)
1386  .Case("mpx", HasMPX)
1387  .Case("mwaitx", HasMWAITX)
1388  .Case("pclmul", HasPCLMUL)
1389  .Case("pconfig", HasPCONFIG)
1390  .Case("pku", HasPKU)
1391  .Case("popcnt", HasPOPCNT)
1392  .Case("prefetchwt1", HasPREFETCHWT1)
1393  .Case("prfchw", HasPRFCHW)
1394  .Case("ptwrite", HasPTWRITE)
1395  .Case("rdpid", HasRDPID)
1396  .Case("rdrnd", HasRDRND)
1397  .Case("rdseed", HasRDSEED)
1398  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1399  .Case("rtm", HasRTM)
1400  .Case("sahf", HasLAHFSAHF)
1401  .Case("sgx", HasSGX)
1402  .Case("sha", HasSHA)
1403  .Case("shstk", HasSHSTK)
1404  .Case("sse", SSELevel >= SSE1)
1405  .Case("sse2", SSELevel >= SSE2)
1406  .Case("sse3", SSELevel >= SSE3)
1407  .Case("ssse3", SSELevel >= SSSE3)
1408  .Case("sse4.1", SSELevel >= SSE41)
1409  .Case("sse4.2", SSELevel >= SSE42)
1410  .Case("sse4a", XOPLevel >= SSE4A)
1411  .Case("tbm", HasTBM)
1412  .Case("vaes", HasVAES)
1413  .Case("vpclmulqdq", HasVPCLMULQDQ)
1414  .Case("wbnoinvd", HasWBNOINVD)
1415  .Case("waitpkg", HasWAITPKG)
1416  .Case("x86", true)
1417  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1418  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1419  .Case("xop", XOPLevel >= XOP)
1420  .Case("xsave", HasXSAVE)
1421  .Case("xsavec", HasXSAVEC)
1422  .Case("xsaves", HasXSAVES)
1423  .Case("xsaveopt", HasXSAVEOPT)
1424  .Default(false);
1425 }
1426 
1427 // We can't use a generic validation scheme for the features accepted here
1428 // versus subtarget features accepted in the target attribute because the
1429 // bitfield structure that's initialized in the runtime only supports the
1430 // below currently rather than the full range of subtarget features. (See
1431 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1432 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1433  return llvm::StringSwitch<bool>(FeatureStr)
1434 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1435 #include "llvm/Support/X86TargetParser.def"
1436  .Default(false);
1437 }
1438 
1439 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1440  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1441 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1442 #include "llvm/Support/X86TargetParser.def"
1443  ;
1444  // Note, this function should only be used after ensuring the value is
1445  // correct, so it asserts if the value is out of range.
1446 }
1447 
1448 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1449  enum class FeatPriority {
1450 #define FEATURE(FEAT) FEAT,
1451 #include "clang/Basic/X86Target.def"
1452  };
1453  switch (Feat) {
1454 #define FEATURE(FEAT) \
1455  case llvm::X86::FEAT: \
1456  return static_cast<unsigned>(FeatPriority::FEAT);
1457 #include "clang/Basic/X86Target.def"
1458  default:
1459  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1460  }
1461 }
1462 
1463 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1464  // Valid CPUs have a 'key feature' that compares just better than its key
1465  // feature.
1466  CPUKind Kind = getCPUKind(Name);
1467  if (Kind != CK_Generic) {
1468  switch (Kind) {
1469  default:
1470  llvm_unreachable(
1471  "CPU Type without a key feature used in 'target' attribute");
1472 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1473  case CK_##ENUM: \
1474  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1475 #include "clang/Basic/X86Target.def"
1476  }
1477  }
1478 
1479  // Now we know we have a feature, so get its priority and shift it a few so
1480  // that we have sufficient room for the CPUs (above).
1481  return getFeaturePriority(getFeature(Name)) << 1;
1482 }
1483 
1485  return llvm::StringSwitch<bool>(Name)
1486 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1487 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1488 #include "clang/Basic/X86Target.def"
1489  .Default(false);
1490 }
1491 
1492 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1493  return llvm::StringSwitch<StringRef>(Name)
1494 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1495 #include "clang/Basic/X86Target.def"
1496  .Default(Name);
1497 }
1498 
1500  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1501 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1502 #include "clang/Basic/X86Target.def"
1503  .Default(0);
1504 }
1505 
1507  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1508  StringRef WholeList =
1509  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1510 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1511 #include "clang/Basic/X86Target.def"
1512  .Default("");
1513  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1514 }
1515 
1517  switch (Kind) {
1518  case CK_Generic:
1519  return "";
1520 #define PROC(ENUM, STRING, IS64BIT) \
1521  case CK_##ENUM: \
1522  return STRING;
1523 #include "clang/Basic/X86Target.def"
1524  }
1525  llvm_unreachable("Invalid CPUKind");
1526 }
1527 
1528 // We can't use a generic validation scheme for the cpus accepted here
1529 // versus subtarget cpus accepted in the target attribute because the
1530 // variables intitialized by the runtime only support the below currently
1531 // rather than the full range of cpus.
1532 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1533  return llvm::StringSwitch<bool>(FeatureStr)
1534 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1535 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1536  .Cases(STR, ALIAS, true)
1537 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1538 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1539 #include "llvm/Support/X86TargetParser.def"
1540  .Default(false);
1541 }
1542 
1544  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1545  switch (*Name) {
1546  default:
1547  return false;
1548  // Constant constraints.
1549  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1550  // instructions.
1551  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1552  // x86_64 instructions.
1553  case 's':
1554  Info.setRequiresImmediate();
1555  return true;
1556  case 'I':
1557  Info.setRequiresImmediate(0, 31);
1558  return true;
1559  case 'J':
1560  Info.setRequiresImmediate(0, 63);
1561  return true;
1562  case 'K':
1563  Info.setRequiresImmediate(-128, 127);
1564  return true;
1565  case 'L':
1566  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1567  return true;
1568  case 'M':
1569  Info.setRequiresImmediate(0, 3);
1570  return true;
1571  case 'N':
1572  Info.setRequiresImmediate(0, 255);
1573  return true;
1574  case 'O':
1575  Info.setRequiresImmediate(0, 127);
1576  return true;
1577  // Register constraints.
1578  case 'Y': // 'Y' is the first character for several 2-character constraints.
1579  // Shift the pointer to the second character of the constraint.
1580  Name++;
1581  switch (*Name) {
1582  default:
1583  return false;
1584  case 'z':
1585  case '0': // First SSE register.
1586  case '2':
1587  case 't': // Any SSE register, when SSE2 is enabled.
1588  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1589  case 'm': // Any MMX register, when inter-unit moves enabled.
1590  case 'k': // AVX512 arch mask registers: k1-k7.
1591  Info.setAllowsRegister();
1592  return true;
1593  }
1594  case 'f': // Any x87 floating point stack register.
1595  // Constraint 'f' cannot be used for output operands.
1596  if (Info.ConstraintStr[0] == '=')
1597  return false;
1598  Info.setAllowsRegister();
1599  return true;
1600  case 'a': // eax.
1601  case 'b': // ebx.
1602  case 'c': // ecx.
1603  case 'd': // edx.
1604  case 'S': // esi.
1605  case 'D': // edi.
1606  case 'A': // edx:eax.
1607  case 't': // Top of floating point stack.
1608  case 'u': // Second from top of floating point stack.
1609  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1610  case 'y': // Any MMX register.
1611  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1612  case 'x': // Any SSE register.
1613  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1614  // for intermideate k reg operations).
1615  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1616  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1617  case 'l': // "Index" registers: any general register that can be used as an
1618  // index in a base+index memory access.
1619  Info.setAllowsRegister();
1620  return true;
1621  // Floating point constant constraints.
1622  case 'C': // SSE floating point constant.
1623  case 'G': // x87 floating point constant.
1624  return true;
1625  }
1626 }
1627 
1628 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1629  unsigned Size) const {
1630  // Strip off constraint modifiers.
1631  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1632  Constraint = Constraint.substr(1);
1633 
1634  return validateOperandSize(Constraint, Size);
1635 }
1636 
1637 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1638  unsigned Size) const {
1639  return validateOperandSize(Constraint, Size);
1640 }
1641 
1642 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1643  unsigned Size) const {
1644  switch (Constraint[0]) {
1645  default:
1646  break;
1647  case 'k':
1648  // Registers k0-k7 (AVX512) size limit is 64 bit.
1649  case 'y':
1650  return Size <= 64;
1651  case 'f':
1652  case 't':
1653  case 'u':
1654  return Size <= 128;
1655  case 'Y':
1656  // 'Y' is the first character for several 2-character constraints.
1657  switch (Constraint[1]) {
1658  default:
1659  return false;
1660  case 'm':
1661  // 'Ym' is synonymous with 'y'.
1662  case 'k':
1663  return Size <= 64;
1664  case 'z':
1665  case '0':
1666  // XMM0
1667  if (SSELevel >= SSE1)
1668  return Size <= 128U;
1669  return false;
1670  case 'i':
1671  case 't':
1672  case '2':
1673  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1674  if (SSELevel < SSE2)
1675  return false;
1676  break;
1677  }
1678  case 'v':
1679  case 'x':
1680  if (SSELevel >= AVX512F)
1681  // 512-bit zmm registers can be used if target supports AVX512F.
1682  return Size <= 512U;
1683  else if (SSELevel >= AVX)
1684  // 256-bit ymm registers can be used if target supports AVX.
1685  return Size <= 256U;
1686  return Size <= 128U;
1687 
1688  }
1689 
1690  return true;
1691 }
1692 
1693 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1694  switch (*Constraint) {
1695  case 'a':
1696  return std::string("{ax}");
1697  case 'b':
1698  return std::string("{bx}");
1699  case 'c':
1700  return std::string("{cx}");
1701  case 'd':
1702  return std::string("{dx}");
1703  case 'S':
1704  return std::string("{si}");
1705  case 'D':
1706  return std::string("{di}");
1707  case 'p': // address
1708  return std::string("im");
1709  case 't': // top of floating point stack.
1710  return std::string("{st}");
1711  case 'u': // second from top of floating point stack.
1712  return std::string("{st(1)}"); // second from top of floating point stack.
1713  case 'Y':
1714  switch (Constraint[1]) {
1715  default:
1716  // Break from inner switch and fall through (copy single char),
1717  // continue parsing after copying the current constraint into
1718  // the return string.
1719  break;
1720  case 'k':
1721  case 'm':
1722  case 'i':
1723  case 't':
1724  case 'z':
1725  case '0':
1726  case '2':
1727  // "^" hints llvm that this is a 2 letter constraint.
1728  // "Constraint++" is used to promote the string iterator
1729  // to the next constraint.
1730  return std::string("^") + std::string(Constraint++, 2);
1731  }
1732  LLVM_FALLTHROUGH;
1733  default:
1734  return std::string(1, *Constraint);
1735  }
1736 }
1737 
1739  // Perform any per-CPU checks necessary to determine if this CPU is
1740  // acceptable.
1741  switch (Kind) {
1742  case CK_Generic:
1743  // No processor selected!
1744  return false;
1745 #define PROC(ENUM, STRING, IS64BIT) \
1746  case CK_##ENUM: \
1747  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1748 #include "clang/Basic/X86Target.def"
1749  }
1750  llvm_unreachable("Unhandled CPU kind");
1751 }
1752 
1754 #define PROC(ENUM, STRING, IS64BIT) \
1755  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1756  Values.emplace_back(STRING);
1757  // Go through CPUKind checking to ensure that the alias is de-aliased and
1758  // 64 bit-ness is checked.
1759 #define PROC_ALIAS(ENUM, ALIAS) \
1760  if (checkCPUKind(getCPUKind(ALIAS))) \
1761  Values.emplace_back(ALIAS);
1762 #include "clang/Basic/X86Target.def"
1763 }
1764 
1766  return llvm::StringSwitch<CPUKind>(CPU)
1767 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1768 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1769 #include "clang/Basic/X86Target.def"
1770  .Default(CK_Generic);
1771 }
1772 
1774  return llvm::makeArrayRef(GCCRegNames);
1775 }
1776 
1778  return llvm::makeArrayRef(AddlRegNames);
1779 }
1780 
1782  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1784 }
1785 
1787  return llvm::makeArrayRef(BuiltinInfoX86,
1789 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:55
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:107
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:26
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:515
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1294
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1628
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1777
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:853
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1642
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1753
std::string getCPUKindCanonicalName(CPUKind Kind) const
Definition: X86.cpp:1516
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:548
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:50
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1432
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1506
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
Defines the Diagnostic-related interfaces.
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1439
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1543
static const char *const GCCRegNames[]
Definition: X86.cpp:44
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1484
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1265
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:385
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1492
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1765
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1345
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:436
Enumerates target-specific builtins in their own namespaces within namespace clang.
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:115
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1786
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1448
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1693
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1781
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1499
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1463
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:691
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1637
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:861
#define PROC(ENUM, STRING, IS64BIT)
__DEVICE__ int max(int __a, int __b)
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1738
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:71
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:583
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1532
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1773
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:105