clang  7.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements X86 TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 namespace clang {
24 namespace targets {
25 
27 #define BUILTIN(ID, TYPE, ATTRS) \
28  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
33 #include "clang/Basic/BuiltinsX86.def"
34 
35 #define BUILTIN(ID, TYPE, ATTRS) \
36  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
41 #include "clang/Basic/BuiltinsX86_64.def"
42 };
43 
44 static const char *const GCCRegNames[] = {
45  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62  "k2", "k3", "k4", "k5", "k6", "k7",
63  "cr0", "cr2", "cr3", "cr4", "cr8",
64  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65  "bnd0", "bnd1", "bnd2", "bnd3",
66 };
67 
69  {{"al", "ah", "eax", "rax"}, 0},
70  {{"bl", "bh", "ebx", "rbx"}, 3},
71  {{"cl", "ch", "ecx", "rcx"}, 2},
72  {{"dl", "dh", "edx", "rdx"}, 1},
73  {{"esi", "rsi"}, 4},
74  {{"edi", "rdi"}, 5},
75  {{"esp", "rsp"}, 7},
76  {{"ebp", "rbp"}, 6},
77  {{"r8d", "r8w", "r8b"}, 38},
78  {{"r9d", "r9w", "r9b"}, 39},
79  {{"r10d", "r10w", "r10b"}, 40},
80  {{"r11d", "r11w", "r11b"}, 41},
81  {{"r12d", "r12w", "r12b"}, 42},
82  {{"r13d", "r13w", "r13b"}, 43},
83  {{"r14d", "r14w", "r14b"}, 44},
84  {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
93 bool X86TargetInfo::setFPMath(StringRef Name) {
94  if (Name == "387") {
95  FPMath = FP_387;
96  return true;
97  }
98  if (Name == "sse") {
99  FPMath = FP_SSE;
100  return true;
101  }
102  return false;
103 }
104 
106  DiagnosticsEngine &Diags) const {
107  if (HasSHSTK)
108  return true;
109 
110  Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return"
111  << "-mshstk";
112  return false;
113 }
114 
116  DiagnosticsEngine &Diags) const {
117  if (HasIBT)
118  return true;
119 
120  Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch"
121  << "-mibt";
122  return false;
123 }
124 
126  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
127  const std::vector<std::string> &FeaturesVec) const {
128  // FIXME: This *really* should not be here.
129  // X86_64 always has SSE2.
130  if (getTriple().getArch() == llvm::Triple::x86_64)
131  setFeatureEnabledImpl(Features, "sse2", true);
132 
133  const CPUKind Kind = getCPUKind(CPU);
134 
135  // Enable X87 for all X86 processors but Lakemont.
136  if (Kind != CK_Lakemont)
137  setFeatureEnabledImpl(Features, "x87", true);
138 
139  switch (Kind) {
140  case CK_Generic:
141  case CK_i386:
142  case CK_i486:
143  case CK_i586:
144  case CK_Pentium:
145  case CK_PentiumPro:
146  case CK_Lakemont:
147  break;
148 
149  case CK_PentiumMMX:
150  case CK_Pentium2:
151  case CK_K6:
152  case CK_WinChipC6:
153  setFeatureEnabledImpl(Features, "mmx", true);
154  break;
155 
156  case CK_Icelake:
157  setFeatureEnabledImpl(Features, "vaes", true);
158  setFeatureEnabledImpl(Features, "gfni", true);
159  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
160  setFeatureEnabledImpl(Features, "avx512bitalg", true);
161  setFeatureEnabledImpl(Features, "avx512vnni", true);
162  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
163  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
164  setFeatureEnabledImpl(Features, "rdpid", true);
165  LLVM_FALLTHROUGH;
166  case CK_Cannonlake:
167  setFeatureEnabledImpl(Features, "avx512ifma", true);
168  setFeatureEnabledImpl(Features, "avx512vbmi", true);
169  setFeatureEnabledImpl(Features, "sha", true);
170  LLVM_FALLTHROUGH;
171  case CK_SkylakeServer:
172  setFeatureEnabledImpl(Features, "avx512f", true);
173  setFeatureEnabledImpl(Features, "avx512cd", true);
174  setFeatureEnabledImpl(Features, "avx512dq", true);
175  setFeatureEnabledImpl(Features, "avx512bw", true);
176  setFeatureEnabledImpl(Features, "avx512vl", true);
177  setFeatureEnabledImpl(Features, "pku", true);
178  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
179  setFeatureEnabledImpl(Features, "clwb", true);
180  LLVM_FALLTHROUGH;
181  case CK_SkylakeClient:
182  setFeatureEnabledImpl(Features, "xsavec", true);
183  setFeatureEnabledImpl(Features, "xsaves", true);
184  setFeatureEnabledImpl(Features, "mpx", true);
185  setFeatureEnabledImpl(Features, "sgx", true);
186  setFeatureEnabledImpl(Features, "clflushopt", true);
187  setFeatureEnabledImpl(Features, "rtm", true);
188  LLVM_FALLTHROUGH;
189  case CK_Broadwell:
190  setFeatureEnabledImpl(Features, "rdseed", true);
191  setFeatureEnabledImpl(Features, "adx", true);
192  setFeatureEnabledImpl(Features, "prfchw", true);
193  LLVM_FALLTHROUGH;
194  case CK_Haswell:
195  setFeatureEnabledImpl(Features, "avx2", true);
196  setFeatureEnabledImpl(Features, "lzcnt", true);
197  setFeatureEnabledImpl(Features, "bmi", true);
198  setFeatureEnabledImpl(Features, "bmi2", true);
199  setFeatureEnabledImpl(Features, "fma", true);
200  setFeatureEnabledImpl(Features, "movbe", true);
201  LLVM_FALLTHROUGH;
202  case CK_IvyBridge:
203  setFeatureEnabledImpl(Features, "rdrnd", true);
204  setFeatureEnabledImpl(Features, "f16c", true);
205  setFeatureEnabledImpl(Features, "fsgsbase", true);
206  LLVM_FALLTHROUGH;
207  case CK_SandyBridge:
208  setFeatureEnabledImpl(Features, "avx", true);
209  setFeatureEnabledImpl(Features, "xsave", true);
210  setFeatureEnabledImpl(Features, "xsaveopt", true);
211  LLVM_FALLTHROUGH;
212  case CK_Westmere:
213  setFeatureEnabledImpl(Features, "aes", true);
214  setFeatureEnabledImpl(Features, "pclmul", true);
215  LLVM_FALLTHROUGH;
216  case CK_Nehalem:
217  setFeatureEnabledImpl(Features, "sse4.2", true);
218  LLVM_FALLTHROUGH;
219  case CK_Penryn:
220  setFeatureEnabledImpl(Features, "sse4.1", true);
221  LLVM_FALLTHROUGH;
222  case CK_Core2:
223  setFeatureEnabledImpl(Features, "ssse3", true);
224  setFeatureEnabledImpl(Features, "sahf", true);
225  LLVM_FALLTHROUGH;
226  case CK_Yonah:
227  case CK_Prescott:
228  case CK_Nocona:
229  setFeatureEnabledImpl(Features, "sse3", true);
230  setFeatureEnabledImpl(Features, "cx16", true);
231  LLVM_FALLTHROUGH;
232  case CK_PentiumM:
233  case CK_Pentium4:
234  case CK_x86_64:
235  setFeatureEnabledImpl(Features, "sse2", true);
236  LLVM_FALLTHROUGH;
237  case CK_Pentium3:
238  case CK_C3_2:
239  setFeatureEnabledImpl(Features, "sse", true);
240  setFeatureEnabledImpl(Features, "fxsr", true);
241  break;
242 
243  case CK_Goldmont:
244  setFeatureEnabledImpl(Features, "sha", true);
245  setFeatureEnabledImpl(Features, "rdseed", true);
246  setFeatureEnabledImpl(Features, "xsave", true);
247  setFeatureEnabledImpl(Features, "xsaveopt", true);
248  setFeatureEnabledImpl(Features, "xsavec", true);
249  setFeatureEnabledImpl(Features, "xsaves", true);
250  setFeatureEnabledImpl(Features, "clflushopt", true);
251  setFeatureEnabledImpl(Features, "mpx", true);
252  setFeatureEnabledImpl(Features, "fsgsbase", true);
253  LLVM_FALLTHROUGH;
254  case CK_Silvermont:
255  setFeatureEnabledImpl(Features, "rdrnd", true);
256  setFeatureEnabledImpl(Features, "aes", true);
257  setFeatureEnabledImpl(Features, "pclmul", true);
258  setFeatureEnabledImpl(Features, "sse4.2", true);
259  setFeatureEnabledImpl(Features, "prfchw", true);
260  LLVM_FALLTHROUGH;
261  case CK_Bonnell:
262  setFeatureEnabledImpl(Features, "movbe", true);
263  setFeatureEnabledImpl(Features, "ssse3", true);
264  setFeatureEnabledImpl(Features, "fxsr", true);
265  setFeatureEnabledImpl(Features, "cx16", true);
266  setFeatureEnabledImpl(Features, "sahf", true);
267  break;
268 
269  case CK_KNM:
270  // TODO: Add avx5124fmaps/avx5124vnniw.
271  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
272  LLVM_FALLTHROUGH;
273  case CK_KNL:
274  setFeatureEnabledImpl(Features, "avx512f", true);
275  setFeatureEnabledImpl(Features, "avx512cd", true);
276  setFeatureEnabledImpl(Features, "avx512er", true);
277  setFeatureEnabledImpl(Features, "avx512pf", true);
278  setFeatureEnabledImpl(Features, "prfchw", true);
279  setFeatureEnabledImpl(Features, "prefetchwt1", true);
280  setFeatureEnabledImpl(Features, "fxsr", true);
281  setFeatureEnabledImpl(Features, "rdseed", true);
282  setFeatureEnabledImpl(Features, "adx", true);
283  setFeatureEnabledImpl(Features, "lzcnt", true);
284  setFeatureEnabledImpl(Features, "bmi", true);
285  setFeatureEnabledImpl(Features, "bmi2", true);
286  setFeatureEnabledImpl(Features, "rtm", true);
287  setFeatureEnabledImpl(Features, "fma", true);
288  setFeatureEnabledImpl(Features, "rdrnd", true);
289  setFeatureEnabledImpl(Features, "f16c", true);
290  setFeatureEnabledImpl(Features, "fsgsbase", true);
291  setFeatureEnabledImpl(Features, "aes", true);
292  setFeatureEnabledImpl(Features, "pclmul", true);
293  setFeatureEnabledImpl(Features, "cx16", true);
294  setFeatureEnabledImpl(Features, "xsaveopt", true);
295  setFeatureEnabledImpl(Features, "xsave", true);
296  setFeatureEnabledImpl(Features, "movbe", true);
297  setFeatureEnabledImpl(Features, "sahf", true);
298  break;
299 
300  case CK_K6_2:
301  case CK_K6_3:
302  case CK_WinChip2:
303  case CK_C3:
304  setFeatureEnabledImpl(Features, "3dnow", true);
305  break;
306 
307  case CK_AMDFAM10:
308  setFeatureEnabledImpl(Features, "sse4a", true);
309  setFeatureEnabledImpl(Features, "lzcnt", true);
310  setFeatureEnabledImpl(Features, "popcnt", true);
311  setFeatureEnabledImpl(Features, "sahf", true);
312  LLVM_FALLTHROUGH;
313  case CK_K8SSE3:
314  setFeatureEnabledImpl(Features, "sse3", true);
315  LLVM_FALLTHROUGH;
316  case CK_K8:
317  setFeatureEnabledImpl(Features, "sse2", true);
318  LLVM_FALLTHROUGH;
319  case CK_AthlonXP:
320  setFeatureEnabledImpl(Features, "sse", true);
321  setFeatureEnabledImpl(Features, "fxsr", true);
322  LLVM_FALLTHROUGH;
323  case CK_Athlon:
324  case CK_Geode:
325  setFeatureEnabledImpl(Features, "3dnowa", true);
326  break;
327 
328  case CK_BTVER2:
329  setFeatureEnabledImpl(Features, "avx", true);
330  setFeatureEnabledImpl(Features, "aes", true);
331  setFeatureEnabledImpl(Features, "pclmul", true);
332  setFeatureEnabledImpl(Features, "bmi", true);
333  setFeatureEnabledImpl(Features, "f16c", true);
334  setFeatureEnabledImpl(Features, "xsaveopt", true);
335  setFeatureEnabledImpl(Features, "movbe", true);
336  LLVM_FALLTHROUGH;
337  case CK_BTVER1:
338  setFeatureEnabledImpl(Features, "ssse3", true);
339  setFeatureEnabledImpl(Features, "sse4a", true);
340  setFeatureEnabledImpl(Features, "lzcnt", true);
341  setFeatureEnabledImpl(Features, "popcnt", true);
342  setFeatureEnabledImpl(Features, "prfchw", true);
343  setFeatureEnabledImpl(Features, "cx16", true);
344  setFeatureEnabledImpl(Features, "fxsr", true);
345  setFeatureEnabledImpl(Features, "sahf", true);
346  break;
347 
348  case CK_ZNVER1:
349  setFeatureEnabledImpl(Features, "adx", true);
350  setFeatureEnabledImpl(Features, "aes", true);
351  setFeatureEnabledImpl(Features, "avx2", true);
352  setFeatureEnabledImpl(Features, "bmi", true);
353  setFeatureEnabledImpl(Features, "bmi2", true);
354  setFeatureEnabledImpl(Features, "clflushopt", true);
355  setFeatureEnabledImpl(Features, "clzero", true);
356  setFeatureEnabledImpl(Features, "cx16", true);
357  setFeatureEnabledImpl(Features, "f16c", true);
358  setFeatureEnabledImpl(Features, "fma", true);
359  setFeatureEnabledImpl(Features, "fsgsbase", true);
360  setFeatureEnabledImpl(Features, "fxsr", true);
361  setFeatureEnabledImpl(Features, "lzcnt", true);
362  setFeatureEnabledImpl(Features, "mwaitx", true);
363  setFeatureEnabledImpl(Features, "movbe", true);
364  setFeatureEnabledImpl(Features, "pclmul", true);
365  setFeatureEnabledImpl(Features, "popcnt", true);
366  setFeatureEnabledImpl(Features, "prfchw", true);
367  setFeatureEnabledImpl(Features, "rdrnd", true);
368  setFeatureEnabledImpl(Features, "rdseed", true);
369  setFeatureEnabledImpl(Features, "sahf", true);
370  setFeatureEnabledImpl(Features, "sha", true);
371  setFeatureEnabledImpl(Features, "sse4a", true);
372  setFeatureEnabledImpl(Features, "xsave", true);
373  setFeatureEnabledImpl(Features, "xsavec", true);
374  setFeatureEnabledImpl(Features, "xsaveopt", true);
375  setFeatureEnabledImpl(Features, "xsaves", true);
376  break;
377 
378  case CK_BDVER4:
379  setFeatureEnabledImpl(Features, "avx2", true);
380  setFeatureEnabledImpl(Features, "bmi2", true);
381  setFeatureEnabledImpl(Features, "mwaitx", true);
382  LLVM_FALLTHROUGH;
383  case CK_BDVER3:
384  setFeatureEnabledImpl(Features, "fsgsbase", true);
385  setFeatureEnabledImpl(Features, "xsaveopt", true);
386  LLVM_FALLTHROUGH;
387  case CK_BDVER2:
388  setFeatureEnabledImpl(Features, "bmi", true);
389  setFeatureEnabledImpl(Features, "fma", true);
390  setFeatureEnabledImpl(Features, "f16c", true);
391  setFeatureEnabledImpl(Features, "tbm", true);
392  LLVM_FALLTHROUGH;
393  case CK_BDVER1:
394  // xop implies avx, sse4a and fma4.
395  setFeatureEnabledImpl(Features, "xop", true);
396  setFeatureEnabledImpl(Features, "lwp", true);
397  setFeatureEnabledImpl(Features, "lzcnt", true);
398  setFeatureEnabledImpl(Features, "aes", true);
399  setFeatureEnabledImpl(Features, "pclmul", true);
400  setFeatureEnabledImpl(Features, "prfchw", true);
401  setFeatureEnabledImpl(Features, "cx16", true);
402  setFeatureEnabledImpl(Features, "fxsr", true);
403  setFeatureEnabledImpl(Features, "xsave", true);
404  setFeatureEnabledImpl(Features, "sahf", true);
405  break;
406  }
407  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
408  return false;
409 
410  // Can't do this earlier because we need to be able to explicitly enable
411  // or disable these features and the things that they depend upon.
412 
413  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
414  auto I = Features.find("sse4.2");
415  if (I != Features.end() && I->getValue() &&
416  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
417  FeaturesVec.end())
418  Features["popcnt"] = true;
419 
420  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
421  I = Features.find("3dnow");
422  if (I != Features.end() && I->getValue() &&
423  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
424  FeaturesVec.end())
425  Features["prfchw"] = true;
426 
427  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
428  // then enable MMX.
429  I = Features.find("sse");
430  if (I != Features.end() && I->getValue() &&
431  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
432  FeaturesVec.end())
433  Features["mmx"] = true;
434 
435  return true;
436 }
437 
438 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
439  X86SSEEnum Level, bool Enabled) {
440  if (Enabled) {
441  switch (Level) {
442  case AVX512F:
443  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
444  LLVM_FALLTHROUGH;
445  case AVX2:
446  Features["avx2"] = true;
447  LLVM_FALLTHROUGH;
448  case AVX:
449  Features["avx"] = true;
450  Features["xsave"] = true;
451  LLVM_FALLTHROUGH;
452  case SSE42:
453  Features["sse4.2"] = true;
454  LLVM_FALLTHROUGH;
455  case SSE41:
456  Features["sse4.1"] = true;
457  LLVM_FALLTHROUGH;
458  case SSSE3:
459  Features["ssse3"] = true;
460  LLVM_FALLTHROUGH;
461  case SSE3:
462  Features["sse3"] = true;
463  LLVM_FALLTHROUGH;
464  case SSE2:
465  Features["sse2"] = true;
466  LLVM_FALLTHROUGH;
467  case SSE1:
468  Features["sse"] = true;
469  LLVM_FALLTHROUGH;
470  case NoSSE:
471  break;
472  }
473  return;
474  }
475 
476  switch (Level) {
477  case NoSSE:
478  case SSE1:
479  Features["sse"] = false;
480  LLVM_FALLTHROUGH;
481  case SSE2:
482  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
483  Features["gfni"] = false;
484  LLVM_FALLTHROUGH;
485  case SSE3:
486  Features["sse3"] = false;
487  setXOPLevel(Features, NoXOP, false);
488  LLVM_FALLTHROUGH;
489  case SSSE3:
490  Features["ssse3"] = false;
491  LLVM_FALLTHROUGH;
492  case SSE41:
493  Features["sse4.1"] = false;
494  LLVM_FALLTHROUGH;
495  case SSE42:
496  Features["sse4.2"] = false;
497  LLVM_FALLTHROUGH;
498  case AVX:
499  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
500  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
501  setXOPLevel(Features, FMA4, false);
502  LLVM_FALLTHROUGH;
503  case AVX2:
504  Features["avx2"] = false;
505  LLVM_FALLTHROUGH;
506  case AVX512F:
507  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
508  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
509  Features["avx512vl"] = Features["avx512vbmi"] =
510  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
511  Features["avx512bitalg"] = Features["avx512vnni"] =
512  Features["avx512vbmi2"] = false;
513  break;
514  }
515 }
516 
517 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
518  MMX3DNowEnum Level, bool Enabled) {
519  if (Enabled) {
520  switch (Level) {
521  case AMD3DNowAthlon:
522  Features["3dnowa"] = true;
523  LLVM_FALLTHROUGH;
524  case AMD3DNow:
525  Features["3dnow"] = true;
526  LLVM_FALLTHROUGH;
527  case MMX:
528  Features["mmx"] = true;
529  LLVM_FALLTHROUGH;
530  case NoMMX3DNow:
531  break;
532  }
533  return;
534  }
535 
536  switch (Level) {
537  case NoMMX3DNow:
538  case MMX:
539  Features["mmx"] = false;
540  LLVM_FALLTHROUGH;
541  case AMD3DNow:
542  Features["3dnow"] = false;
543  LLVM_FALLTHROUGH;
544  case AMD3DNowAthlon:
545  Features["3dnowa"] = false;
546  break;
547  }
548 }
549 
550 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
551  bool Enabled) {
552  if (Enabled) {
553  switch (Level) {
554  case XOP:
555  Features["xop"] = true;
556  LLVM_FALLTHROUGH;
557  case FMA4:
558  Features["fma4"] = true;
559  setSSELevel(Features, AVX, true);
560  LLVM_FALLTHROUGH;
561  case SSE4A:
562  Features["sse4a"] = true;
563  setSSELevel(Features, SSE3, true);
564  LLVM_FALLTHROUGH;
565  case NoXOP:
566  break;
567  }
568  return;
569  }
570 
571  switch (Level) {
572  case NoXOP:
573  case SSE4A:
574  Features["sse4a"] = false;
575  LLVM_FALLTHROUGH;
576  case FMA4:
577  Features["fma4"] = false;
578  LLVM_FALLTHROUGH;
579  case XOP:
580  Features["xop"] = false;
581  break;
582  }
583 }
584 
585 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
586  StringRef Name, bool Enabled) {
587  // This is a bit of a hack to deal with the sse4 target feature when used
588  // as part of the target attribute. We handle sse4 correctly everywhere
589  // else. See below for more information on how we handle the sse4 options.
590  if (Name != "sse4")
591  Features[Name] = Enabled;
592 
593  if (Name == "mmx") {
594  setMMXLevel(Features, MMX, Enabled);
595  } else if (Name == "sse") {
596  setSSELevel(Features, SSE1, Enabled);
597  } else if (Name == "sse2") {
598  setSSELevel(Features, SSE2, Enabled);
599  } else if (Name == "sse3") {
600  setSSELevel(Features, SSE3, Enabled);
601  } else if (Name == "ssse3") {
602  setSSELevel(Features, SSSE3, Enabled);
603  } else if (Name == "sse4.2") {
604  setSSELevel(Features, SSE42, Enabled);
605  } else if (Name == "sse4.1") {
606  setSSELevel(Features, SSE41, Enabled);
607  } else if (Name == "3dnow") {
608  setMMXLevel(Features, AMD3DNow, Enabled);
609  } else if (Name == "3dnowa") {
610  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
611  } else if (Name == "aes") {
612  if (Enabled)
613  setSSELevel(Features, SSE2, Enabled);
614  else
615  Features["vaes"] = false;
616  } else if (Name == "vaes") {
617  if (Enabled) {
618  setSSELevel(Features, AVX, Enabled);
619  Features["aes"] = true;
620  }
621  } else if (Name == "pclmul") {
622  if (Enabled)
623  setSSELevel(Features, SSE2, Enabled);
624  else
625  Features["vpclmulqdq"] = false;
626  } else if (Name == "vpclmulqdq") {
627  if (Enabled) {
628  setSSELevel(Features, AVX, Enabled);
629  Features["pclmul"] = true;
630  }
631  } else if (Name == "gfni") {
632  if (Enabled)
633  setSSELevel(Features, SSE2, Enabled);
634  } else if (Name == "avx") {
635  setSSELevel(Features, AVX, Enabled);
636  } else if (Name == "avx2") {
637  setSSELevel(Features, AVX2, Enabled);
638  } else if (Name == "avx512f") {
639  setSSELevel(Features, AVX512F, Enabled);
640  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
641  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
642  Name == "avx512vbmi" || Name == "avx512ifma" ||
643  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
644  Name == "avx512vnni" || Name == "avx512vbmi2") {
645  if (Enabled)
646  setSSELevel(Features, AVX512F, Enabled);
647  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
648  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
649  Features["avx512bw"] = true;
650  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
651  if (Name == "avx512bw" && !Enabled)
652  Features["avx512vbmi"] = Features["avx512vbmi2"] =
653  Features["avx512bitalg"] = false;
654  } else if (Name == "fma") {
655  if (Enabled)
656  setSSELevel(Features, AVX, Enabled);
657  else
658  setSSELevel(Features, AVX512F, Enabled);
659  } else if (Name == "fma4") {
660  setXOPLevel(Features, FMA4, Enabled);
661  } else if (Name == "xop") {
662  setXOPLevel(Features, XOP, Enabled);
663  } else if (Name == "sse4a") {
664  setXOPLevel(Features, SSE4A, Enabled);
665  } else if (Name == "f16c") {
666  if (Enabled)
667  setSSELevel(Features, AVX, Enabled);
668  else
669  setSSELevel(Features, AVX512F, Enabled);
670  } else if (Name == "sha") {
671  if (Enabled)
672  setSSELevel(Features, SSE2, Enabled);
673  } else if (Name == "sse4") {
674  // We can get here via the __target__ attribute since that's not controlled
675  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
676  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
677  // disabled.
678  if (Enabled)
679  setSSELevel(Features, SSE42, Enabled);
680  else
681  setSSELevel(Features, SSE41, Enabled);
682  } else if (Name == "xsave") {
683  if (!Enabled)
684  Features["xsaveopt"] = false;
685  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
686  if (Enabled)
687  Features["xsave"] = true;
688  }
689 }
690 
691 /// handleTargetFeatures - Perform initialization based on the user
692 /// configured set of features.
693 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
694  DiagnosticsEngine &Diags) {
695  for (const auto &Feature : Features) {
696  if (Feature[0] != '+')
697  continue;
698 
699  if (Feature == "+aes") {
700  HasAES = true;
701  } else if (Feature == "+vaes") {
702  HasVAES = true;
703  } else if (Feature == "+pclmul") {
704  HasPCLMUL = true;
705  } else if (Feature == "+vpclmulqdq") {
706  HasVPCLMULQDQ = true;
707  } else if (Feature == "+lzcnt") {
708  HasLZCNT = true;
709  } else if (Feature == "+rdrnd") {
710  HasRDRND = true;
711  } else if (Feature == "+fsgsbase") {
712  HasFSGSBASE = true;
713  } else if (Feature == "+bmi") {
714  HasBMI = true;
715  } else if (Feature == "+bmi2") {
716  HasBMI2 = true;
717  } else if (Feature == "+popcnt") {
718  HasPOPCNT = true;
719  } else if (Feature == "+rtm") {
720  HasRTM = true;
721  } else if (Feature == "+prfchw") {
722  HasPRFCHW = true;
723  } else if (Feature == "+rdseed") {
724  HasRDSEED = true;
725  } else if (Feature == "+adx") {
726  HasADX = true;
727  } else if (Feature == "+tbm") {
728  HasTBM = true;
729  } else if (Feature == "+lwp") {
730  HasLWP = true;
731  } else if (Feature == "+fma") {
732  HasFMA = true;
733  } else if (Feature == "+f16c") {
734  HasF16C = true;
735  } else if (Feature == "+gfni") {
736  HasGFNI = true;
737  } else if (Feature == "+avx512cd") {
738  HasAVX512CD = true;
739  } else if (Feature == "+avx512vpopcntdq") {
740  HasAVX512VPOPCNTDQ = true;
741  } else if (Feature == "+avx512vnni") {
742  HasAVX512VNNI = true;
743  } else if (Feature == "+avx512er") {
744  HasAVX512ER = true;
745  } else if (Feature == "+avx512pf") {
746  HasAVX512PF = true;
747  } else if (Feature == "+avx512dq") {
748  HasAVX512DQ = true;
749  } else if (Feature == "+avx512bitalg") {
750  HasAVX512BITALG = true;
751  } else if (Feature == "+avx512bw") {
752  HasAVX512BW = true;
753  } else if (Feature == "+avx512vl") {
754  HasAVX512VL = true;
755  } else if (Feature == "+avx512vbmi") {
756  HasAVX512VBMI = true;
757  } else if (Feature == "+avx512vbmi2") {
758  HasAVX512VBMI2 = true;
759  } else if (Feature == "+avx512ifma") {
760  HasAVX512IFMA = true;
761  } else if (Feature == "+sha") {
762  HasSHA = true;
763  } else if (Feature == "+mpx") {
764  HasMPX = true;
765  } else if (Feature == "+shstk") {
766  HasSHSTK = true;
767  } else if (Feature == "+ibt") {
768  HasIBT = true;
769  } else if (Feature == "+movbe") {
770  HasMOVBE = true;
771  } else if (Feature == "+sgx") {
772  HasSGX = true;
773  } else if (Feature == "+cx16") {
774  HasCX16 = true;
775  } else if (Feature == "+fxsr") {
776  HasFXSR = true;
777  } else if (Feature == "+xsave") {
778  HasXSAVE = true;
779  } else if (Feature == "+xsaveopt") {
780  HasXSAVEOPT = true;
781  } else if (Feature == "+xsavec") {
782  HasXSAVEC = true;
783  } else if (Feature == "+xsaves") {
784  HasXSAVES = true;
785  } else if (Feature == "+mwaitx") {
786  HasMWAITX = true;
787  } else if (Feature == "+pku") {
788  HasPKU = true;
789  } else if (Feature == "+clflushopt") {
790  HasCLFLUSHOPT = true;
791  } else if (Feature == "+clwb") {
792  HasCLWB = true;
793  } else if (Feature == "+prefetchwt1") {
794  HasPREFETCHWT1 = true;
795  } else if (Feature == "+clzero") {
796  HasCLZERO = true;
797  } else if (Feature == "+rdpid") {
798  HasRDPID = true;
799  } else if (Feature == "+retpoline") {
800  HasRetpoline = true;
801  } else if (Feature == "+retpoline-external-thunk") {
802  HasRetpolineExternalThunk = true;
803  } else if (Feature == "+sahf") {
804  HasLAHFSAHF = true;
805  }
806 
807  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
808  .Case("+avx512f", AVX512F)
809  .Case("+avx2", AVX2)
810  .Case("+avx", AVX)
811  .Case("+sse4.2", SSE42)
812  .Case("+sse4.1", SSE41)
813  .Case("+ssse3", SSSE3)
814  .Case("+sse3", SSE3)
815  .Case("+sse2", SSE2)
816  .Case("+sse", SSE1)
817  .Default(NoSSE);
818  SSELevel = std::max(SSELevel, Level);
819 
820  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
821  .Case("+3dnowa", AMD3DNowAthlon)
822  .Case("+3dnow", AMD3DNow)
823  .Case("+mmx", MMX)
824  .Default(NoMMX3DNow);
825  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
826 
827  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
828  .Case("+xop", XOP)
829  .Case("+fma4", FMA4)
830  .Case("+sse4a", SSE4A)
831  .Default(NoXOP);
832  XOPLevel = std::max(XOPLevel, XLevel);
833  }
834 
835  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
836  // matches the selected sse level.
837  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
838  (FPMath == FP_387 && SSELevel >= SSE1)) {
839  Diags.Report(diag::err_target_unsupported_fpmath)
840  << (FPMath == FP_SSE ? "sse" : "387");
841  return false;
842  }
843 
844  SimdDefaultAlign =
845  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
846  return true;
847 }
848 
849 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
850 /// definitions for this particular subtarget.
852  MacroBuilder &Builder) const {
853  // Target identification.
854  if (getTriple().getArch() == llvm::Triple::x86_64) {
855  Builder.defineMacro("__amd64__");
856  Builder.defineMacro("__amd64");
857  Builder.defineMacro("__x86_64");
858  Builder.defineMacro("__x86_64__");
859  if (getTriple().getArchName() == "x86_64h") {
860  Builder.defineMacro("__x86_64h");
861  Builder.defineMacro("__x86_64h__");
862  }
863  } else {
864  DefineStd(Builder, "i386", Opts);
865  }
866 
867  // Subtarget options.
868  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
869  // truly should be based on -mtune options.
870  switch (CPU) {
871  case CK_Generic:
872  break;
873  case CK_i386:
874  // The rest are coming from the i386 define above.
875  Builder.defineMacro("__tune_i386__");
876  break;
877  case CK_i486:
878  case CK_WinChipC6:
879  case CK_WinChip2:
880  case CK_C3:
881  defineCPUMacros(Builder, "i486");
882  break;
883  case CK_PentiumMMX:
884  Builder.defineMacro("__pentium_mmx__");
885  Builder.defineMacro("__tune_pentium_mmx__");
886  LLVM_FALLTHROUGH;
887  case CK_i586:
888  case CK_Pentium:
889  defineCPUMacros(Builder, "i586");
890  defineCPUMacros(Builder, "pentium");
891  break;
892  case CK_Pentium3:
893  case CK_PentiumM:
894  Builder.defineMacro("__tune_pentium3__");
895  LLVM_FALLTHROUGH;
896  case CK_Pentium2:
897  case CK_C3_2:
898  Builder.defineMacro("__tune_pentium2__");
899  LLVM_FALLTHROUGH;
900  case CK_PentiumPro:
901  defineCPUMacros(Builder, "i686");
902  defineCPUMacros(Builder, "pentiumpro");
903  break;
904  case CK_Pentium4:
905  defineCPUMacros(Builder, "pentium4");
906  break;
907  case CK_Yonah:
908  case CK_Prescott:
909  case CK_Nocona:
910  defineCPUMacros(Builder, "nocona");
911  break;
912  case CK_Core2:
913  case CK_Penryn:
914  defineCPUMacros(Builder, "core2");
915  break;
916  case CK_Bonnell:
917  defineCPUMacros(Builder, "atom");
918  break;
919  case CK_Silvermont:
920  defineCPUMacros(Builder, "slm");
921  break;
922  case CK_Goldmont:
923  defineCPUMacros(Builder, "goldmont");
924  break;
925  case CK_Nehalem:
926  case CK_Westmere:
927  case CK_SandyBridge:
928  case CK_IvyBridge:
929  case CK_Haswell:
930  case CK_Broadwell:
931  case CK_SkylakeClient:
932  case CK_SkylakeServer:
933  case CK_Cannonlake:
934  case CK_Icelake:
935  // FIXME: Historically, we defined this legacy name, it would be nice to
936  // remove it at some point. We've never exposed fine-grained names for
937  // recent primary x86 CPUs, and we should keep it that way.
938  defineCPUMacros(Builder, "corei7");
939  break;
940  case CK_KNL:
941  defineCPUMacros(Builder, "knl");
942  break;
943  case CK_KNM:
944  break;
945  case CK_Lakemont:
946  defineCPUMacros(Builder, "i586", /*Tuning*/false);
947  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
948  Builder.defineMacro("__tune_lakemont__");
949  break;
950  case CK_K6_2:
951  Builder.defineMacro("__k6_2__");
952  Builder.defineMacro("__tune_k6_2__");
953  LLVM_FALLTHROUGH;
954  case CK_K6_3:
955  if (CPU != CK_K6_2) { // In case of fallthrough
956  // FIXME: GCC may be enabling these in cases where some other k6
957  // architecture is specified but -m3dnow is explicitly provided. The
958  // exact semantics need to be determined and emulated here.
959  Builder.defineMacro("__k6_3__");
960  Builder.defineMacro("__tune_k6_3__");
961  }
962  LLVM_FALLTHROUGH;
963  case CK_K6:
964  defineCPUMacros(Builder, "k6");
965  break;
966  case CK_Athlon:
967  case CK_AthlonXP:
968  defineCPUMacros(Builder, "athlon");
969  if (SSELevel != NoSSE) {
970  Builder.defineMacro("__athlon_sse__");
971  Builder.defineMacro("__tune_athlon_sse__");
972  }
973  break;
974  case CK_K8:
975  case CK_K8SSE3:
976  case CK_x86_64:
977  defineCPUMacros(Builder, "k8");
978  break;
979  case CK_AMDFAM10:
980  defineCPUMacros(Builder, "amdfam10");
981  break;
982  case CK_BTVER1:
983  defineCPUMacros(Builder, "btver1");
984  break;
985  case CK_BTVER2:
986  defineCPUMacros(Builder, "btver2");
987  break;
988  case CK_BDVER1:
989  defineCPUMacros(Builder, "bdver1");
990  break;
991  case CK_BDVER2:
992  defineCPUMacros(Builder, "bdver2");
993  break;
994  case CK_BDVER3:
995  defineCPUMacros(Builder, "bdver3");
996  break;
997  case CK_BDVER4:
998  defineCPUMacros(Builder, "bdver4");
999  break;
1000  case CK_ZNVER1:
1001  defineCPUMacros(Builder, "znver1");
1002  break;
1003  case CK_Geode:
1004  defineCPUMacros(Builder, "geode");
1005  break;
1006  }
1007 
1008  // Target properties.
1009  Builder.defineMacro("__REGISTER_PREFIX__", "");
1010 
1011  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1012  // functions in glibc header files that use FP Stack inline asm which the
1013  // backend can't deal with (PR879).
1014  Builder.defineMacro("__NO_MATH_INLINES");
1015 
1016  if (HasAES)
1017  Builder.defineMacro("__AES__");
1018 
1019  if (HasVAES)
1020  Builder.defineMacro("__VAES__");
1021 
1022  if (HasPCLMUL)
1023  Builder.defineMacro("__PCLMUL__");
1024 
1025  if (HasVPCLMULQDQ)
1026  Builder.defineMacro("__VPCLMULQDQ__");
1027 
1028  if (HasLZCNT)
1029  Builder.defineMacro("__LZCNT__");
1030 
1031  if (HasRDRND)
1032  Builder.defineMacro("__RDRND__");
1033 
1034  if (HasFSGSBASE)
1035  Builder.defineMacro("__FSGSBASE__");
1036 
1037  if (HasBMI)
1038  Builder.defineMacro("__BMI__");
1039 
1040  if (HasBMI2)
1041  Builder.defineMacro("__BMI2__");
1042 
1043  if (HasPOPCNT)
1044  Builder.defineMacro("__POPCNT__");
1045 
1046  if (HasRTM)
1047  Builder.defineMacro("__RTM__");
1048 
1049  if (HasPRFCHW)
1050  Builder.defineMacro("__PRFCHW__");
1051 
1052  if (HasRDSEED)
1053  Builder.defineMacro("__RDSEED__");
1054 
1055  if (HasADX)
1056  Builder.defineMacro("__ADX__");
1057 
1058  if (HasTBM)
1059  Builder.defineMacro("__TBM__");
1060 
1061  if (HasLWP)
1062  Builder.defineMacro("__LWP__");
1063 
1064  if (HasMWAITX)
1065  Builder.defineMacro("__MWAITX__");
1066 
1067  switch (XOPLevel) {
1068  case XOP:
1069  Builder.defineMacro("__XOP__");
1070  LLVM_FALLTHROUGH;
1071  case FMA4:
1072  Builder.defineMacro("__FMA4__");
1073  LLVM_FALLTHROUGH;
1074  case SSE4A:
1075  Builder.defineMacro("__SSE4A__");
1076  LLVM_FALLTHROUGH;
1077  case NoXOP:
1078  break;
1079  }
1080 
1081  if (HasFMA)
1082  Builder.defineMacro("__FMA__");
1083 
1084  if (HasF16C)
1085  Builder.defineMacro("__F16C__");
1086 
1087  if (HasGFNI)
1088  Builder.defineMacro("__GFNI__");
1089 
1090  if (HasAVX512CD)
1091  Builder.defineMacro("__AVX512CD__");
1092  if (HasAVX512VPOPCNTDQ)
1093  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1094  if (HasAVX512VNNI)
1095  Builder.defineMacro("__AVX512VNNI__");
1096  if (HasAVX512ER)
1097  Builder.defineMacro("__AVX512ER__");
1098  if (HasAVX512PF)
1099  Builder.defineMacro("__AVX512PF__");
1100  if (HasAVX512DQ)
1101  Builder.defineMacro("__AVX512DQ__");
1102  if (HasAVX512BITALG)
1103  Builder.defineMacro("__AVX512BITALG__");
1104  if (HasAVX512BW)
1105  Builder.defineMacro("__AVX512BW__");
1106  if (HasAVX512VL)
1107  Builder.defineMacro("__AVX512VL__");
1108  if (HasAVX512VBMI)
1109  Builder.defineMacro("__AVX512VBMI__");
1110  if (HasAVX512VBMI2)
1111  Builder.defineMacro("__AVX512VBMI2__");
1112  if (HasAVX512IFMA)
1113  Builder.defineMacro("__AVX512IFMA__");
1114 
1115  if (HasSHA)
1116  Builder.defineMacro("__SHA__");
1117 
1118  if (HasFXSR)
1119  Builder.defineMacro("__FXSR__");
1120  if (HasXSAVE)
1121  Builder.defineMacro("__XSAVE__");
1122  if (HasXSAVEOPT)
1123  Builder.defineMacro("__XSAVEOPT__");
1124  if (HasXSAVEC)
1125  Builder.defineMacro("__XSAVEC__");
1126  if (HasXSAVES)
1127  Builder.defineMacro("__XSAVES__");
1128  if (HasPKU)
1129  Builder.defineMacro("__PKU__");
1130  if (HasCLFLUSHOPT)
1131  Builder.defineMacro("__CLFLUSHOPT__");
1132  if (HasCLWB)
1133  Builder.defineMacro("__CLWB__");
1134  if (HasMPX)
1135  Builder.defineMacro("__MPX__");
1136  if (HasSHSTK)
1137  Builder.defineMacro("__SHSTK__");
1138  if (HasIBT)
1139  Builder.defineMacro("__IBT__");
1140  if (HasSGX)
1141  Builder.defineMacro("__SGX__");
1142  if (HasPREFETCHWT1)
1143  Builder.defineMacro("__PREFETCHWT1__");
1144  if (HasCLZERO)
1145  Builder.defineMacro("__CLZERO__");
1146  if (HasRDPID)
1147  Builder.defineMacro("__RDPID__");
1148 
1149  // Each case falls through to the previous one here.
1150  switch (SSELevel) {
1151  case AVX512F:
1152  Builder.defineMacro("__AVX512F__");
1153  LLVM_FALLTHROUGH;
1154  case AVX2:
1155  Builder.defineMacro("__AVX2__");
1156  LLVM_FALLTHROUGH;
1157  case AVX:
1158  Builder.defineMacro("__AVX__");
1159  LLVM_FALLTHROUGH;
1160  case SSE42:
1161  Builder.defineMacro("__SSE4_2__");
1162  LLVM_FALLTHROUGH;
1163  case SSE41:
1164  Builder.defineMacro("__SSE4_1__");
1165  LLVM_FALLTHROUGH;
1166  case SSSE3:
1167  Builder.defineMacro("__SSSE3__");
1168  LLVM_FALLTHROUGH;
1169  case SSE3:
1170  Builder.defineMacro("__SSE3__");
1171  LLVM_FALLTHROUGH;
1172  case SSE2:
1173  Builder.defineMacro("__SSE2__");
1174  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1175  LLVM_FALLTHROUGH;
1176  case SSE1:
1177  Builder.defineMacro("__SSE__");
1178  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1179  LLVM_FALLTHROUGH;
1180  case NoSSE:
1181  break;
1182  }
1183 
1184  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1185  switch (SSELevel) {
1186  case AVX512F:
1187  case AVX2:
1188  case AVX:
1189  case SSE42:
1190  case SSE41:
1191  case SSSE3:
1192  case SSE3:
1193  case SSE2:
1194  Builder.defineMacro("_M_IX86_FP", Twine(2));
1195  break;
1196  case SSE1:
1197  Builder.defineMacro("_M_IX86_FP", Twine(1));
1198  break;
1199  default:
1200  Builder.defineMacro("_M_IX86_FP", Twine(0));
1201  break;
1202  }
1203  }
1204 
1205  // Each case falls through to the previous one here.
1206  switch (MMX3DNowLevel) {
1207  case AMD3DNowAthlon:
1208  Builder.defineMacro("__3dNOW_A__");
1209  LLVM_FALLTHROUGH;
1210  case AMD3DNow:
1211  Builder.defineMacro("__3dNOW__");
1212  LLVM_FALLTHROUGH;
1213  case MMX:
1214  Builder.defineMacro("__MMX__");
1215  LLVM_FALLTHROUGH;
1216  case NoMMX3DNow:
1217  break;
1218  }
1219 
1220  if (CPU >= CK_i486) {
1221  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1222  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1223  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1224  }
1225  if (CPU >= CK_i586)
1226  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1227  if (HasCX16)
1228  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1229 
1230  if (HasFloat128)
1231  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1232 }
1233 
1234 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1235  return llvm::StringSwitch<bool>(Name)
1236  .Case("3dnow", true)
1237  .Case("3dnowa", true)
1238  .Case("adx", true)
1239  .Case("aes", true)
1240  .Case("avx", true)
1241  .Case("avx2", true)
1242  .Case("avx512f", true)
1243  .Case("avx512cd", true)
1244  .Case("avx512vpopcntdq", true)
1245  .Case("avx512vnni", true)
1246  .Case("avx512er", true)
1247  .Case("avx512pf", true)
1248  .Case("avx512dq", true)
1249  .Case("avx512bitalg", true)
1250  .Case("avx512bw", true)
1251  .Case("avx512vl", true)
1252  .Case("avx512vbmi", true)
1253  .Case("avx512vbmi2", true)
1254  .Case("avx512ifma", true)
1255  .Case("bmi", true)
1256  .Case("bmi2", true)
1257  .Case("clflushopt", true)
1258  .Case("clwb", true)
1259  .Case("clzero", true)
1260  .Case("cx16", true)
1261  .Case("f16c", true)
1262  .Case("fma", true)
1263  .Case("fma4", true)
1264  .Case("fsgsbase", true)
1265  .Case("fxsr", true)
1266  .Case("gfni", true)
1267  .Case("lwp", true)
1268  .Case("lzcnt", true)
1269  .Case("mmx", true)
1270  .Case("movbe", true)
1271  .Case("mpx", true)
1272  .Case("mwaitx", true)
1273  .Case("pclmul", true)
1274  .Case("pku", true)
1275  .Case("popcnt", true)
1276  .Case("prefetchwt1", true)
1277  .Case("prfchw", true)
1278  .Case("rdpid", true)
1279  .Case("rdrnd", true)
1280  .Case("rdseed", true)
1281  .Case("rtm", true)
1282  .Case("sahf", true)
1283  .Case("sgx", true)
1284  .Case("sha", true)
1285  .Case("shstk", true)
1286  .Case("sse", true)
1287  .Case("sse2", true)
1288  .Case("sse3", true)
1289  .Case("ssse3", true)
1290  .Case("sse4", true)
1291  .Case("sse4.1", true)
1292  .Case("sse4.2", true)
1293  .Case("sse4a", true)
1294  .Case("tbm", true)
1295  .Case("vaes", true)
1296  .Case("vpclmulqdq", true)
1297  .Case("x87", true)
1298  .Case("xop", true)
1299  .Case("xsave", true)
1300  .Case("xsavec", true)
1301  .Case("xsaves", true)
1302  .Case("xsaveopt", true)
1303  .Default(false);
1304 }
1305 
1306 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1307  return llvm::StringSwitch<bool>(Feature)
1308  .Case("adx", HasADX)
1309  .Case("aes", HasAES)
1310  .Case("avx", SSELevel >= AVX)
1311  .Case("avx2", SSELevel >= AVX2)
1312  .Case("avx512f", SSELevel >= AVX512F)
1313  .Case("avx512cd", HasAVX512CD)
1314  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1315  .Case("avx512vnni", HasAVX512VNNI)
1316  .Case("avx512er", HasAVX512ER)
1317  .Case("avx512pf", HasAVX512PF)
1318  .Case("avx512dq", HasAVX512DQ)
1319  .Case("avx512bitalg", HasAVX512BITALG)
1320  .Case("avx512bw", HasAVX512BW)
1321  .Case("avx512vl", HasAVX512VL)
1322  .Case("avx512vbmi", HasAVX512VBMI)
1323  .Case("avx512vbmi2", HasAVX512VBMI2)
1324  .Case("avx512ifma", HasAVX512IFMA)
1325  .Case("bmi", HasBMI)
1326  .Case("bmi2", HasBMI2)
1327  .Case("clflushopt", HasCLFLUSHOPT)
1328  .Case("clwb", HasCLWB)
1329  .Case("clzero", HasCLZERO)
1330  .Case("cx16", HasCX16)
1331  .Case("f16c", HasF16C)
1332  .Case("fma", HasFMA)
1333  .Case("fma4", XOPLevel >= FMA4)
1334  .Case("fsgsbase", HasFSGSBASE)
1335  .Case("fxsr", HasFXSR)
1336  .Case("gfni", HasGFNI)
1337  .Case("ibt", HasIBT)
1338  .Case("lwp", HasLWP)
1339  .Case("lzcnt", HasLZCNT)
1340  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1341  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1342  .Case("mmx", MMX3DNowLevel >= MMX)
1343  .Case("movbe", HasMOVBE)
1344  .Case("mpx", HasMPX)
1345  .Case("mwaitx", HasMWAITX)
1346  .Case("pclmul", HasPCLMUL)
1347  .Case("pku", HasPKU)
1348  .Case("popcnt", HasPOPCNT)
1349  .Case("prefetchwt1", HasPREFETCHWT1)
1350  .Case("prfchw", HasPRFCHW)
1351  .Case("rdpid", HasRDPID)
1352  .Case("rdrnd", HasRDRND)
1353  .Case("rdseed", HasRDSEED)
1354  .Case("retpoline", HasRetpoline)
1355  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1356  .Case("rtm", HasRTM)
1357  .Case("sahf", HasLAHFSAHF)
1358  .Case("sgx", HasSGX)
1359  .Case("sha", HasSHA)
1360  .Case("shstk", HasSHSTK)
1361  .Case("sse", SSELevel >= SSE1)
1362  .Case("sse2", SSELevel >= SSE2)
1363  .Case("sse3", SSELevel >= SSE3)
1364  .Case("ssse3", SSELevel >= SSSE3)
1365  .Case("sse4.1", SSELevel >= SSE41)
1366  .Case("sse4.2", SSELevel >= SSE42)
1367  .Case("sse4a", XOPLevel >= SSE4A)
1368  .Case("tbm", HasTBM)
1369  .Case("vaes", HasVAES)
1370  .Case("vpclmulqdq", HasVPCLMULQDQ)
1371  .Case("x86", true)
1372  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1373  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1374  .Case("xop", XOPLevel >= XOP)
1375  .Case("xsave", HasXSAVE)
1376  .Case("xsavec", HasXSAVEC)
1377  .Case("xsaves", HasXSAVES)
1378  .Case("xsaveopt", HasXSAVEOPT)
1379  .Default(false);
1380 }
1381 
1382 // We can't use a generic validation scheme for the features accepted here
1383 // versus subtarget features accepted in the target attribute because the
1384 // bitfield structure that's initialized in the runtime only supports the
1385 // below currently rather than the full range of subtarget features. (See
1386 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1387 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1388  return llvm::StringSwitch<bool>(FeatureStr)
1389 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1390 #include "llvm/Support/X86TargetParser.def"
1391  .Default(false);
1392 }
1393 
1394 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1395  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1396 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1397 #include "llvm/Support/X86TargetParser.def"
1398  ;
1399  // Note, this function should only be used after ensuring the value is
1400  // correct, so it asserts if the value is out of range.
1401 }
1402 
1403 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1404  enum class FeatPriority {
1405 #define FEATURE(FEAT) FEAT,
1406 #include "clang/Basic/X86Target.def"
1407  };
1408  switch (Feat) {
1409 #define FEATURE(FEAT) \
1410  case llvm::X86::FEAT: \
1411  return static_cast<unsigned>(FeatPriority::FEAT);
1412 #include "clang/Basic/X86Target.def"
1413  default:
1414  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1415  }
1416 }
1417 
1418 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1419  // Valid CPUs have a 'key feature' that compares just better than its key
1420  // feature.
1421  CPUKind Kind = getCPUKind(Name);
1422  if (Kind != CK_Generic) {
1423  switch (Kind) {
1424  default:
1425  llvm_unreachable(
1426  "CPU Type without a key feature used in 'target' attribute");
1427 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1428  case CK_##ENUM: \
1429  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1430 #include "clang/Basic/X86Target.def"
1431  }
1432  }
1433 
1434  // Now we know we have a feature, so get its priority and shift it a few so
1435  // that we have sufficient room for the CPUs (above).
1436  return getFeaturePriority(getFeature(Name)) << 1;
1437 }
1438 
1440  switch (Kind) {
1441  case CK_Generic:
1442  return "";
1443 #define PROC(ENUM, STRING, IS64BIT) \
1444  case CK_##ENUM: \
1445  return STRING;
1446 #include "clang/Basic/X86Target.def"
1447  }
1448  llvm_unreachable("Invalid CPUKind");
1449 }
1450 
1451 // We can't use a generic validation scheme for the cpus accepted here
1452 // versus subtarget cpus accepted in the target attribute because the
1453 // variables intitialized by the runtime only support the below currently
1454 // rather than the full range of cpus.
1455 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1456  return llvm::StringSwitch<bool>(FeatureStr)
1457 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1458 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1459  .Cases(STR, ALIAS, true)
1460 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1461 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1462 #include "llvm/Support/X86TargetParser.def"
1463  .Default(false);
1464 }
1465 
1467  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1468  switch (*Name) {
1469  default:
1470  return false;
1471  // Constant constraints.
1472  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1473  // instructions.
1474  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1475  // x86_64 instructions.
1476  case 's':
1477  Info.setRequiresImmediate();
1478  return true;
1479  case 'I':
1480  Info.setRequiresImmediate(0, 31);
1481  return true;
1482  case 'J':
1483  Info.setRequiresImmediate(0, 63);
1484  return true;
1485  case 'K':
1486  Info.setRequiresImmediate(-128, 127);
1487  return true;
1488  case 'L':
1489  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1490  return true;
1491  case 'M':
1492  Info.setRequiresImmediate(0, 3);
1493  return true;
1494  case 'N':
1495  Info.setRequiresImmediate(0, 255);
1496  return true;
1497  case 'O':
1498  Info.setRequiresImmediate(0, 127);
1499  return true;
1500  // Register constraints.
1501  case 'Y': // 'Y' is the first character for several 2-character constraints.
1502  // Shift the pointer to the second character of the constraint.
1503  Name++;
1504  switch (*Name) {
1505  default:
1506  return false;
1507  case 'z':
1508  case '0': // First SSE register.
1509  case '2':
1510  case 't': // Any SSE register, when SSE2 is enabled.
1511  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1512  case 'm': // Any MMX register, when inter-unit moves enabled.
1513  case 'k': // AVX512 arch mask registers: k1-k7.
1514  Info.setAllowsRegister();
1515  return true;
1516  }
1517  case 'f': // Any x87 floating point stack register.
1518  // Constraint 'f' cannot be used for output operands.
1519  if (Info.ConstraintStr[0] == '=')
1520  return false;
1521  Info.setAllowsRegister();
1522  return true;
1523  case 'a': // eax.
1524  case 'b': // ebx.
1525  case 'c': // ecx.
1526  case 'd': // edx.
1527  case 'S': // esi.
1528  case 'D': // edi.
1529  case 'A': // edx:eax.
1530  case 't': // Top of floating point stack.
1531  case 'u': // Second from top of floating point stack.
1532  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1533  case 'y': // Any MMX register.
1534  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1535  case 'x': // Any SSE register.
1536  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
1537  // for intermideate k reg operations).
1538  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1539  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1540  case 'l': // "Index" registers: any general register that can be used as an
1541  // index in a base+index memory access.
1542  Info.setAllowsRegister();
1543  return true;
1544  // Floating point constant constraints.
1545  case 'C': // SSE floating point constant.
1546  case 'G': // x87 floating point constant.
1547  return true;
1548  }
1549 }
1550 
1551 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1552  unsigned Size) const {
1553  // Strip off constraint modifiers.
1554  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1555  Constraint = Constraint.substr(1);
1556 
1557  return validateOperandSize(Constraint, Size);
1558 }
1559 
1560 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1561  unsigned Size) const {
1562  return validateOperandSize(Constraint, Size);
1563 }
1564 
1565 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1566  unsigned Size) const {
1567  switch (Constraint[0]) {
1568  default:
1569  break;
1570  case 'k':
1571  // Registers k0-k7 (AVX512) size limit is 64 bit.
1572  case 'y':
1573  return Size <= 64;
1574  case 'f':
1575  case 't':
1576  case 'u':
1577  return Size <= 128;
1578  case 'Y':
1579  // 'Y' is the first character for several 2-character constraints.
1580  switch (Constraint[1]) {
1581  default:
1582  return false;
1583  case 'm':
1584  // 'Ym' is synonymous with 'y'.
1585  case 'k':
1586  return Size <= 64;
1587  case 'z':
1588  case '0':
1589  // XMM0
1590  if (SSELevel >= SSE1)
1591  return Size <= 128U;
1592  return false;
1593  case 'i':
1594  case 't':
1595  case '2':
1596  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1597  if (SSELevel < SSE2)
1598  return false;
1599  break;
1600  }
1601  case 'v':
1602  case 'x':
1603  if (SSELevel >= AVX512F)
1604  // 512-bit zmm registers can be used if target supports AVX512F.
1605  return Size <= 512U;
1606  else if (SSELevel >= AVX)
1607  // 256-bit ymm registers can be used if target supports AVX.
1608  return Size <= 256U;
1609  return Size <= 128U;
1610 
1611  }
1612 
1613  return true;
1614 }
1615 
1616 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1617  switch (*Constraint) {
1618  case 'a':
1619  return std::string("{ax}");
1620  case 'b':
1621  return std::string("{bx}");
1622  case 'c':
1623  return std::string("{cx}");
1624  case 'd':
1625  return std::string("{dx}");
1626  case 'S':
1627  return std::string("{si}");
1628  case 'D':
1629  return std::string("{di}");
1630  case 'p': // address
1631  return std::string("im");
1632  case 't': // top of floating point stack.
1633  return std::string("{st}");
1634  case 'u': // second from top of floating point stack.
1635  return std::string("{st(1)}"); // second from top of floating point stack.
1636  case 'Y':
1637  switch (Constraint[1]) {
1638  default:
1639  // Break from inner switch and fall through (copy single char),
1640  // continue parsing after copying the current constraint into
1641  // the return string.
1642  break;
1643  case 'k':
1644  case 'm':
1645  case 'i':
1646  case 't':
1647  case 'z':
1648  case '0':
1649  case '2':
1650  // "^" hints llvm that this is a 2 letter constraint.
1651  // "Constraint++" is used to promote the string iterator
1652  // to the next constraint.
1653  return std::string("^") + std::string(Constraint++, 2);
1654  }
1655  LLVM_FALLTHROUGH;
1656  default:
1657  return std::string(1, *Constraint);
1658  }
1659 }
1660 
1662  // Perform any per-CPU checks necessary to determine if this CPU is
1663  // acceptable.
1664  switch (Kind) {
1665  case CK_Generic:
1666  // No processor selected!
1667  return false;
1668 #define PROC(ENUM, STRING, IS64BIT) \
1669  case CK_##ENUM: \
1670  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1671 #include "clang/Basic/X86Target.def"
1672  }
1673  llvm_unreachable("Unhandled CPU kind");
1674 }
1675 
1677 #define PROC(ENUM, STRING, IS64BIT) \
1678  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1679  Values.emplace_back(STRING);
1680  // Go through CPUKind checking to ensure that the alias is de-aliased and
1681  // 64 bit-ness is checked.
1682 #define PROC_ALIAS(ENUM, ALIAS) \
1683  if (checkCPUKind(getCPUKind(ALIAS))) \
1684  Values.emplace_back(ALIAS);
1685 #include "clang/Basic/X86Target.def"
1686 }
1687 
1689  return llvm::StringSwitch<CPUKind>(CPU)
1690 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1691 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1692 #include "clang/Basic/X86Target.def"
1693  .Default(CK_Generic);
1694 }
1695 
1697  return llvm::makeArrayRef(GCCRegNames);
1698 }
1699 
1701  return llvm::makeArrayRef(AddlRegNames);
1702 }
1703 
1705  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1707 }
1708 
1710  return llvm::makeArrayRef(BuiltinInfoX86,
1712 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:55
virtual bool checkCFProtectionBranchSupported(DiagnosticsEngine &Diags) const override
Check if the target supports CFProtection branch.
Definition: X86.cpp:115
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:73
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:93
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:26
virtual bool checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override
Check if the target supports CFProtection branch.
Definition: X86.cpp:105
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:517
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1294
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1551
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1700
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:694
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1565
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1676
std::string getCPUKindCanonicalName(CPUKind Kind) const
Definition: X86.cpp:1439
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:550
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:68
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:50
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1387
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
Defines the Diagnostic-related interfaces.
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1394
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1466
static const char *const GCCRegNames[]
Definition: X86.cpp:44
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1234
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:347
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1688
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1306
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:438
Enumerates target-specific builtins in their own namespaces within namespace clang.
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:109
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1709
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1403
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1616
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1704
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1418
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:693
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1560
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:851
#define PROC(ENUM, STRING, IS64BIT)
__DEVICE__ int max(int __a, int __b)
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1661
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:71
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:585
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1455
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1696
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:125