clang  6.0.0svn
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements X86 TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 
21 namespace clang {
22 namespace targets {
23 
25 #define BUILTIN(ID, TYPE, ATTRS) \
26  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
28  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
30  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
31 #include "clang/Basic/BuiltinsX86.def"
32 
33 #define BUILTIN(ID, TYPE, ATTRS) \
34  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
36  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
38  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
39 #include "clang/Basic/BuiltinsX86_64.def"
40 };
41 
42 static const char *const GCCRegNames[] = {
43  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
44  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
45  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
46  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
47  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
48  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
49  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
50  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
51  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
52  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
53  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
54  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
55  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
56  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
57  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
58  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
59  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
60  "k2", "k3", "k4", "k5", "k6", "k7",
61  "cr0", "cr2", "cr3", "cr4", "cr8",
62  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
63  "bnd0", "bnd1", "bnd2", "bnd3",
64 };
65 
67  {{"al", "ah", "eax", "rax"}, 0},
68  {{"bl", "bh", "ebx", "rbx"}, 3},
69  {{"cl", "ch", "ecx", "rcx"}, 2},
70  {{"dl", "dh", "edx", "rdx"}, 1},
71  {{"esi", "rsi"}, 4},
72  {{"edi", "rdi"}, 5},
73  {{"esp", "rsp"}, 7},
74  {{"ebp", "rbp"}, 6},
75  {{"r8d", "r8w", "r8b"}, 38},
76  {{"r9d", "r9w", "r9b"}, 39},
77  {{"r10d", "r10w", "r10b"}, 40},
78  {{"r11d", "r11w", "r11b"}, 41},
79  {{"r12d", "r12w", "r12b"}, 42},
80  {{"r13d", "r13w", "r13b"}, 43},
81  {{"r14d", "r14w", "r14b"}, 44},
82  {{"r15d", "r15w", "r15b"}, 45},
83 };
84 
85 } // namespace targets
86 } // namespace clang
87 
88 using namespace clang;
89 using namespace clang::targets;
90 
91 bool X86TargetInfo::setFPMath(StringRef Name) {
92  if (Name == "387") {
93  FPMath = FP_387;
94  return true;
95  }
96  if (Name == "sse") {
97  FPMath = FP_SSE;
98  return true;
99  }
100  return false;
101 }
102 
104  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
105  const std::vector<std::string> &FeaturesVec) const {
106  // FIXME: This *really* should not be here.
107  // X86_64 always has SSE2.
108  if (getTriple().getArch() == llvm::Triple::x86_64)
109  setFeatureEnabledImpl(Features, "sse2", true);
110 
111  const CPUKind Kind = getCPUKind(CPU);
112 
113  // Enable X87 for all X86 processors but Lakemont.
114  if (Kind != CK_Lakemont)
115  setFeatureEnabledImpl(Features, "x87", true);
116 
117  switch (Kind) {
118  case CK_Generic:
119  case CK_i386:
120  case CK_i486:
121  case CK_i586:
122  case CK_Pentium:
123  case CK_PentiumPro:
124  case CK_Lakemont:
125  break;
126 
127  case CK_PentiumMMX:
128  case CK_Pentium2:
129  case CK_K6:
130  case CK_WinChipC6:
131  setFeatureEnabledImpl(Features, "mmx", true);
132  break;
133 
134  case CK_Icelake:
135  // TODO: Add icelake features here.
136  LLVM_FALLTHROUGH;
137  case CK_Cannonlake:
138  setFeatureEnabledImpl(Features, "avx512ifma", true);
139  setFeatureEnabledImpl(Features, "avx512vbmi", true);
140  setFeatureEnabledImpl(Features, "sha", true);
141  LLVM_FALLTHROUGH;
142  case CK_SkylakeServer:
143  setFeatureEnabledImpl(Features, "avx512f", true);
144  setFeatureEnabledImpl(Features, "avx512cd", true);
145  setFeatureEnabledImpl(Features, "avx512dq", true);
146  setFeatureEnabledImpl(Features, "avx512bw", true);
147  setFeatureEnabledImpl(Features, "avx512vl", true);
148  setFeatureEnabledImpl(Features, "pku", true);
149  setFeatureEnabledImpl(Features, "clwb", true);
150  LLVM_FALLTHROUGH;
151  case CK_SkylakeClient:
152  setFeatureEnabledImpl(Features, "xsavec", true);
153  setFeatureEnabledImpl(Features, "xsaves", true);
154  setFeatureEnabledImpl(Features, "mpx", true);
155  setFeatureEnabledImpl(Features, "sgx", true);
156  setFeatureEnabledImpl(Features, "clflushopt", true);
157  setFeatureEnabledImpl(Features, "rtm", true);
158  LLVM_FALLTHROUGH;
159  case CK_Broadwell:
160  setFeatureEnabledImpl(Features, "rdseed", true);
161  setFeatureEnabledImpl(Features, "adx", true);
162  LLVM_FALLTHROUGH;
163  case CK_Haswell:
164  setFeatureEnabledImpl(Features, "avx2", true);
165  setFeatureEnabledImpl(Features, "lzcnt", true);
166  setFeatureEnabledImpl(Features, "bmi", true);
167  setFeatureEnabledImpl(Features, "bmi2", true);
168  setFeatureEnabledImpl(Features, "fma", true);
169  setFeatureEnabledImpl(Features, "movbe", true);
170  LLVM_FALLTHROUGH;
171  case CK_IvyBridge:
172  setFeatureEnabledImpl(Features, "rdrnd", true);
173  setFeatureEnabledImpl(Features, "f16c", true);
174  setFeatureEnabledImpl(Features, "fsgsbase", true);
175  LLVM_FALLTHROUGH;
176  case CK_SandyBridge:
177  setFeatureEnabledImpl(Features, "avx", true);
178  setFeatureEnabledImpl(Features, "xsave", true);
179  setFeatureEnabledImpl(Features, "xsaveopt", true);
180  LLVM_FALLTHROUGH;
181  case CK_Westmere:
182  setFeatureEnabledImpl(Features, "aes", true);
183  setFeatureEnabledImpl(Features, "pclmul", true);
184  LLVM_FALLTHROUGH;
185  case CK_Nehalem:
186  setFeatureEnabledImpl(Features, "sse4.2", true);
187  LLVM_FALLTHROUGH;
188  case CK_Penryn:
189  setFeatureEnabledImpl(Features, "sse4.1", true);
190  LLVM_FALLTHROUGH;
191  case CK_Core2:
192  setFeatureEnabledImpl(Features, "ssse3", true);
193  LLVM_FALLTHROUGH;
194  case CK_Yonah:
195  case CK_Prescott:
196  case CK_Nocona:
197  setFeatureEnabledImpl(Features, "sse3", true);
198  setFeatureEnabledImpl(Features, "cx16", true);
199  LLVM_FALLTHROUGH;
200  case CK_PentiumM:
201  case CK_Pentium4:
202  case CK_x86_64:
203  setFeatureEnabledImpl(Features, "sse2", true);
204  LLVM_FALLTHROUGH;
205  case CK_Pentium3:
206  case CK_C3_2:
207  setFeatureEnabledImpl(Features, "sse", true);
208  setFeatureEnabledImpl(Features, "fxsr", true);
209  break;
210 
211  case CK_Goldmont:
212  setFeatureEnabledImpl(Features, "sha", true);
213  setFeatureEnabledImpl(Features, "rdrnd", true);
214  setFeatureEnabledImpl(Features, "rdseed", true);
215  setFeatureEnabledImpl(Features, "xsave", true);
216  setFeatureEnabledImpl(Features, "xsaveopt", true);
217  setFeatureEnabledImpl(Features, "xsavec", true);
218  setFeatureEnabledImpl(Features, "xsaves", true);
219  setFeatureEnabledImpl(Features, "clflushopt", true);
220  setFeatureEnabledImpl(Features, "mpx", true);
221  setFeatureEnabledImpl(Features, "fsgsbase", true);
222  LLVM_FALLTHROUGH;
223  case CK_Silvermont:
224  setFeatureEnabledImpl(Features, "aes", true);
225  setFeatureEnabledImpl(Features, "pclmul", true);
226  setFeatureEnabledImpl(Features, "sse4.2", true);
227  LLVM_FALLTHROUGH;
228  case CK_Bonnell:
229  setFeatureEnabledImpl(Features, "movbe", true);
230  setFeatureEnabledImpl(Features, "ssse3", true);
231  setFeatureEnabledImpl(Features, "fxsr", true);
232  setFeatureEnabledImpl(Features, "cx16", true);
233  break;
234 
235  case CK_KNM:
236  // TODO: Add avx5124fmaps/avx5124vnniw.
237  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
238  LLVM_FALLTHROUGH;
239  case CK_KNL:
240  setFeatureEnabledImpl(Features, "avx512f", true);
241  setFeatureEnabledImpl(Features, "avx512cd", true);
242  setFeatureEnabledImpl(Features, "avx512er", true);
243  setFeatureEnabledImpl(Features, "avx512pf", true);
244  setFeatureEnabledImpl(Features, "prefetchwt1", true);
245  setFeatureEnabledImpl(Features, "fxsr", true);
246  setFeatureEnabledImpl(Features, "rdseed", true);
247  setFeatureEnabledImpl(Features, "adx", true);
248  setFeatureEnabledImpl(Features, "lzcnt", true);
249  setFeatureEnabledImpl(Features, "bmi", true);
250  setFeatureEnabledImpl(Features, "bmi2", true);
251  setFeatureEnabledImpl(Features, "rtm", true);
252  setFeatureEnabledImpl(Features, "fma", true);
253  setFeatureEnabledImpl(Features, "rdrnd", true);
254  setFeatureEnabledImpl(Features, "f16c", true);
255  setFeatureEnabledImpl(Features, "fsgsbase", true);
256  setFeatureEnabledImpl(Features, "aes", true);
257  setFeatureEnabledImpl(Features, "pclmul", true);
258  setFeatureEnabledImpl(Features, "cx16", true);
259  setFeatureEnabledImpl(Features, "xsaveopt", true);
260  setFeatureEnabledImpl(Features, "xsave", true);
261  setFeatureEnabledImpl(Features, "movbe", true);
262  break;
263 
264  case CK_K6_2:
265  case CK_K6_3:
266  case CK_WinChip2:
267  case CK_C3:
268  setFeatureEnabledImpl(Features, "3dnow", true);
269  break;
270 
271  case CK_AMDFAM10:
272  setFeatureEnabledImpl(Features, "sse4a", true);
273  setFeatureEnabledImpl(Features, "lzcnt", true);
274  setFeatureEnabledImpl(Features, "popcnt", true);
275  LLVM_FALLTHROUGH;
276  case CK_K8SSE3:
277  setFeatureEnabledImpl(Features, "sse3", true);
278  LLVM_FALLTHROUGH;
279  case CK_K8:
280  setFeatureEnabledImpl(Features, "sse2", true);
281  LLVM_FALLTHROUGH;
282  case CK_AthlonXP:
283  setFeatureEnabledImpl(Features, "sse", true);
284  setFeatureEnabledImpl(Features, "fxsr", true);
285  LLVM_FALLTHROUGH;
286  case CK_Athlon:
287  case CK_Geode:
288  setFeatureEnabledImpl(Features, "3dnowa", true);
289  break;
290 
291  case CK_BTVER2:
292  setFeatureEnabledImpl(Features, "avx", true);
293  setFeatureEnabledImpl(Features, "aes", true);
294  setFeatureEnabledImpl(Features, "pclmul", true);
295  setFeatureEnabledImpl(Features, "bmi", true);
296  setFeatureEnabledImpl(Features, "f16c", true);
297  setFeatureEnabledImpl(Features, "xsaveopt", true);
298  setFeatureEnabledImpl(Features, "movbe", true);
299  LLVM_FALLTHROUGH;
300  case CK_BTVER1:
301  setFeatureEnabledImpl(Features, "ssse3", true);
302  setFeatureEnabledImpl(Features, "sse4a", true);
303  setFeatureEnabledImpl(Features, "lzcnt", true);
304  setFeatureEnabledImpl(Features, "popcnt", true);
305  setFeatureEnabledImpl(Features, "prfchw", true);
306  setFeatureEnabledImpl(Features, "cx16", true);
307  setFeatureEnabledImpl(Features, "fxsr", true);
308  break;
309 
310  case CK_ZNVER1:
311  setFeatureEnabledImpl(Features, "adx", true);
312  setFeatureEnabledImpl(Features, "aes", true);
313  setFeatureEnabledImpl(Features, "avx2", true);
314  setFeatureEnabledImpl(Features, "bmi", true);
315  setFeatureEnabledImpl(Features, "bmi2", true);
316  setFeatureEnabledImpl(Features, "clflushopt", true);
317  setFeatureEnabledImpl(Features, "clzero", true);
318  setFeatureEnabledImpl(Features, "cx16", true);
319  setFeatureEnabledImpl(Features, "f16c", true);
320  setFeatureEnabledImpl(Features, "fma", true);
321  setFeatureEnabledImpl(Features, "fsgsbase", true);
322  setFeatureEnabledImpl(Features, "fxsr", true);
323  setFeatureEnabledImpl(Features, "lzcnt", true);
324  setFeatureEnabledImpl(Features, "mwaitx", true);
325  setFeatureEnabledImpl(Features, "movbe", true);
326  setFeatureEnabledImpl(Features, "pclmul", true);
327  setFeatureEnabledImpl(Features, "popcnt", true);
328  setFeatureEnabledImpl(Features, "prfchw", true);
329  setFeatureEnabledImpl(Features, "rdrnd", true);
330  setFeatureEnabledImpl(Features, "rdseed", true);
331  setFeatureEnabledImpl(Features, "sha", true);
332  setFeatureEnabledImpl(Features, "sse4a", true);
333  setFeatureEnabledImpl(Features, "xsave", true);
334  setFeatureEnabledImpl(Features, "xsavec", true);
335  setFeatureEnabledImpl(Features, "xsaveopt", true);
336  setFeatureEnabledImpl(Features, "xsaves", true);
337  break;
338 
339  case CK_BDVER4:
340  setFeatureEnabledImpl(Features, "avx2", true);
341  setFeatureEnabledImpl(Features, "bmi2", true);
342  setFeatureEnabledImpl(Features, "mwaitx", true);
343  LLVM_FALLTHROUGH;
344  case CK_BDVER3:
345  setFeatureEnabledImpl(Features, "fsgsbase", true);
346  setFeatureEnabledImpl(Features, "xsaveopt", true);
347  LLVM_FALLTHROUGH;
348  case CK_BDVER2:
349  setFeatureEnabledImpl(Features, "bmi", true);
350  setFeatureEnabledImpl(Features, "fma", true);
351  setFeatureEnabledImpl(Features, "f16c", true);
352  setFeatureEnabledImpl(Features, "tbm", true);
353  LLVM_FALLTHROUGH;
354  case CK_BDVER1:
355  // xop implies avx, sse4a and fma4.
356  setFeatureEnabledImpl(Features, "xop", true);
357  setFeatureEnabledImpl(Features, "lwp", true);
358  setFeatureEnabledImpl(Features, "lzcnt", true);
359  setFeatureEnabledImpl(Features, "aes", true);
360  setFeatureEnabledImpl(Features, "pclmul", true);
361  setFeatureEnabledImpl(Features, "prfchw", true);
362  setFeatureEnabledImpl(Features, "cx16", true);
363  setFeatureEnabledImpl(Features, "fxsr", true);
364  setFeatureEnabledImpl(Features, "xsave", true);
365  break;
366  }
367  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
368  return false;
369 
370  // Can't do this earlier because we need to be able to explicitly enable
371  // or disable these features and the things that they depend upon.
372 
373  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
374  auto I = Features.find("sse4.2");
375  if (I != Features.end() && I->getValue() &&
376  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
377  FeaturesVec.end())
378  Features["popcnt"] = true;
379 
380  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
381  I = Features.find("3dnow");
382  if (I != Features.end() && I->getValue() &&
383  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
384  FeaturesVec.end())
385  Features["prfchw"] = true;
386 
387  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
388  // then enable MMX.
389  I = Features.find("sse");
390  if (I != Features.end() && I->getValue() &&
391  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
392  FeaturesVec.end())
393  Features["mmx"] = true;
394 
395  return true;
396 }
397 
398 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
399  X86SSEEnum Level, bool Enabled) {
400  if (Enabled) {
401  switch (Level) {
402  case AVX512F:
403  Features["avx512f"] = true;
404  LLVM_FALLTHROUGH;
405  case AVX2:
406  Features["avx2"] = true;
407  LLVM_FALLTHROUGH;
408  case AVX:
409  Features["avx"] = true;
410  Features["xsave"] = true;
411  LLVM_FALLTHROUGH;
412  case SSE42:
413  Features["sse4.2"] = true;
414  LLVM_FALLTHROUGH;
415  case SSE41:
416  Features["sse4.1"] = true;
417  LLVM_FALLTHROUGH;
418  case SSSE3:
419  Features["ssse3"] = true;
420  LLVM_FALLTHROUGH;
421  case SSE3:
422  Features["sse3"] = true;
423  LLVM_FALLTHROUGH;
424  case SSE2:
425  Features["sse2"] = true;
426  LLVM_FALLTHROUGH;
427  case SSE1:
428  Features["sse"] = true;
429  LLVM_FALLTHROUGH;
430  case NoSSE:
431  break;
432  }
433  return;
434  }
435 
436  switch (Level) {
437  case NoSSE:
438  case SSE1:
439  Features["sse"] = false;
440  LLVM_FALLTHROUGH;
441  case SSE2:
442  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
443  false;
444  LLVM_FALLTHROUGH;
445  case SSE3:
446  Features["sse3"] = false;
447  setXOPLevel(Features, NoXOP, false);
448  LLVM_FALLTHROUGH;
449  case SSSE3:
450  Features["ssse3"] = false;
451  LLVM_FALLTHROUGH;
452  case SSE41:
453  Features["sse4.1"] = false;
454  LLVM_FALLTHROUGH;
455  case SSE42:
456  Features["sse4.2"] = false;
457  LLVM_FALLTHROUGH;
458  case AVX:
459  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
460  Features["xsaveopt"] = false;
461  setXOPLevel(Features, FMA4, false);
462  LLVM_FALLTHROUGH;
463  case AVX2:
464  Features["avx2"] = false;
465  LLVM_FALLTHROUGH;
466  case AVX512F:
467  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
468  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
469  Features["avx512vl"] = Features["avx512vbmi"] =
470  Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
471  break;
472  }
473 }
474 
475 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
476  MMX3DNowEnum Level, bool Enabled) {
477  if (Enabled) {
478  switch (Level) {
479  case AMD3DNowAthlon:
480  Features["3dnowa"] = true;
481  LLVM_FALLTHROUGH;
482  case AMD3DNow:
483  Features["3dnow"] = true;
484  LLVM_FALLTHROUGH;
485  case MMX:
486  Features["mmx"] = true;
487  LLVM_FALLTHROUGH;
488  case NoMMX3DNow:
489  break;
490  }
491  return;
492  }
493 
494  switch (Level) {
495  case NoMMX3DNow:
496  case MMX:
497  Features["mmx"] = false;
498  LLVM_FALLTHROUGH;
499  case AMD3DNow:
500  Features["3dnow"] = false;
501  LLVM_FALLTHROUGH;
502  case AMD3DNowAthlon:
503  Features["3dnowa"] = false;
504  break;
505  }
506 }
507 
508 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
509  bool Enabled) {
510  if (Enabled) {
511  switch (Level) {
512  case XOP:
513  Features["xop"] = true;
514  LLVM_FALLTHROUGH;
515  case FMA4:
516  Features["fma4"] = true;
517  setSSELevel(Features, AVX, true);
518  LLVM_FALLTHROUGH;
519  case SSE4A:
520  Features["sse4a"] = true;
521  setSSELevel(Features, SSE3, true);
522  LLVM_FALLTHROUGH;
523  case NoXOP:
524  break;
525  }
526  return;
527  }
528 
529  switch (Level) {
530  case NoXOP:
531  case SSE4A:
532  Features["sse4a"] = false;
533  LLVM_FALLTHROUGH;
534  case FMA4:
535  Features["fma4"] = false;
536  LLVM_FALLTHROUGH;
537  case XOP:
538  Features["xop"] = false;
539  break;
540  }
541 }
542 
543 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
544  StringRef Name, bool Enabled) {
545  // This is a bit of a hack to deal with the sse4 target feature when used
546  // as part of the target attribute. We handle sse4 correctly everywhere
547  // else. See below for more information on how we handle the sse4 options.
548  if (Name != "sse4")
549  Features[Name] = Enabled;
550 
551  if (Name == "mmx") {
552  setMMXLevel(Features, MMX, Enabled);
553  } else if (Name == "sse") {
554  setSSELevel(Features, SSE1, Enabled);
555  } else if (Name == "sse2") {
556  setSSELevel(Features, SSE2, Enabled);
557  } else if (Name == "sse3") {
558  setSSELevel(Features, SSE3, Enabled);
559  } else if (Name == "ssse3") {
560  setSSELevel(Features, SSSE3, Enabled);
561  } else if (Name == "sse4.2") {
562  setSSELevel(Features, SSE42, Enabled);
563  } else if (Name == "sse4.1") {
564  setSSELevel(Features, SSE41, Enabled);
565  } else if (Name == "3dnow") {
566  setMMXLevel(Features, AMD3DNow, Enabled);
567  } else if (Name == "3dnowa") {
568  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
569  } else if (Name == "aes") {
570  if (Enabled)
571  setSSELevel(Features, SSE2, Enabled);
572  } else if (Name == "pclmul") {
573  if (Enabled)
574  setSSELevel(Features, SSE2, Enabled);
575  } else if (Name == "avx") {
576  setSSELevel(Features, AVX, Enabled);
577  } else if (Name == "avx2") {
578  setSSELevel(Features, AVX2, Enabled);
579  } else if (Name == "avx512f") {
580  setSSELevel(Features, AVX512F, Enabled);
581  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
582  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
583  Name == "avx512vbmi" || Name == "avx512ifma" ||
584  Name == "avx512vpopcntdq") {
585  if (Enabled)
586  setSSELevel(Features, AVX512F, Enabled);
587  // Enable BWI instruction if VBMI is being enabled.
588  if (Name == "avx512vbmi" && Enabled)
589  Features["avx512bw"] = true;
590  // Also disable VBMI if BWI is being disabled.
591  if (Name == "avx512bw" && !Enabled)
592  Features["avx512vbmi"] = false;
593  } else if (Name == "fma") {
594  if (Enabled)
595  setSSELevel(Features, AVX, Enabled);
596  } else if (Name == "fma4") {
597  setXOPLevel(Features, FMA4, Enabled);
598  } else if (Name == "xop") {
599  setXOPLevel(Features, XOP, Enabled);
600  } else if (Name == "sse4a") {
601  setXOPLevel(Features, SSE4A, Enabled);
602  } else if (Name == "f16c") {
603  if (Enabled)
604  setSSELevel(Features, AVX, Enabled);
605  } else if (Name == "sha") {
606  if (Enabled)
607  setSSELevel(Features, SSE2, Enabled);
608  } else if (Name == "sse4") {
609  // We can get here via the __target__ attribute since that's not controlled
610  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
611  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
612  // disabled.
613  if (Enabled)
614  setSSELevel(Features, SSE42, Enabled);
615  else
616  setSSELevel(Features, SSE41, Enabled);
617  } else if (Name == "xsave") {
618  if (!Enabled)
619  Features["xsaveopt"] = false;
620  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
621  if (Enabled)
622  Features["xsave"] = true;
623  }
624 }
625 
626 /// handleTargetFeatures - Perform initialization based on the user
627 /// configured set of features.
628 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
629  DiagnosticsEngine &Diags) {
630  for (const auto &Feature : Features) {
631  if (Feature[0] != '+')
632  continue;
633 
634  if (Feature == "+aes") {
635  HasAES = true;
636  } else if (Feature == "+pclmul") {
637  HasPCLMUL = true;
638  } else if (Feature == "+lzcnt") {
639  HasLZCNT = true;
640  } else if (Feature == "+rdrnd") {
641  HasRDRND = true;
642  } else if (Feature == "+fsgsbase") {
643  HasFSGSBASE = true;
644  } else if (Feature == "+bmi") {
645  HasBMI = true;
646  } else if (Feature == "+bmi2") {
647  HasBMI2 = true;
648  } else if (Feature == "+popcnt") {
649  HasPOPCNT = true;
650  } else if (Feature == "+rtm") {
651  HasRTM = true;
652  } else if (Feature == "+prfchw") {
653  HasPRFCHW = true;
654  } else if (Feature == "+rdseed") {
655  HasRDSEED = true;
656  } else if (Feature == "+adx") {
657  HasADX = true;
658  } else if (Feature == "+tbm") {
659  HasTBM = true;
660  } else if (Feature == "+lwp") {
661  HasLWP = true;
662  } else if (Feature == "+fma") {
663  HasFMA = true;
664  } else if (Feature == "+f16c") {
665  HasF16C = true;
666  } else if (Feature == "+avx512cd") {
667  HasAVX512CD = true;
668  } else if (Feature == "+avx512vpopcntdq") {
669  HasAVX512VPOPCNTDQ = true;
670  } else if (Feature == "+avx512er") {
671  HasAVX512ER = true;
672  } else if (Feature == "+avx512pf") {
673  HasAVX512PF = true;
674  } else if (Feature == "+avx512dq") {
675  HasAVX512DQ = true;
676  } else if (Feature == "+avx512bw") {
677  HasAVX512BW = true;
678  } else if (Feature == "+avx512vl") {
679  HasAVX512VL = true;
680  } else if (Feature == "+avx512vbmi") {
681  HasAVX512VBMI = true;
682  } else if (Feature == "+avx512ifma") {
683  HasAVX512IFMA = true;
684  } else if (Feature == "+sha") {
685  HasSHA = true;
686  } else if (Feature == "+mpx") {
687  HasMPX = true;
688  } else if (Feature == "+shstk") {
689  HasSHSTK = true;
690  } else if (Feature == "+ibt") {
691  HasIBT = true;
692  } else if (Feature == "+movbe") {
693  HasMOVBE = true;
694  } else if (Feature == "+sgx") {
695  HasSGX = true;
696  } else if (Feature == "+cx16") {
697  HasCX16 = true;
698  } else if (Feature == "+fxsr") {
699  HasFXSR = true;
700  } else if (Feature == "+xsave") {
701  HasXSAVE = true;
702  } else if (Feature == "+xsaveopt") {
703  HasXSAVEOPT = true;
704  } else if (Feature == "+xsavec") {
705  HasXSAVEC = true;
706  } else if (Feature == "+xsaves") {
707  HasXSAVES = true;
708  } else if (Feature == "+mwaitx") {
709  HasMWAITX = true;
710  } else if (Feature == "+pku") {
711  HasPKU = true;
712  } else if (Feature == "+clflushopt") {
713  HasCLFLUSHOPT = true;
714  } else if (Feature == "+clwb") {
715  HasCLWB = true;
716  } else if (Feature == "+prefetchwt1") {
717  HasPREFETCHWT1 = true;
718  } else if (Feature == "+clzero") {
719  HasCLZERO = true;
720  }
721 
722  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
723  .Case("+avx512f", AVX512F)
724  .Case("+avx2", AVX2)
725  .Case("+avx", AVX)
726  .Case("+sse4.2", SSE42)
727  .Case("+sse4.1", SSE41)
728  .Case("+ssse3", SSSE3)
729  .Case("+sse3", SSE3)
730  .Case("+sse2", SSE2)
731  .Case("+sse", SSE1)
732  .Default(NoSSE);
733  SSELevel = std::max(SSELevel, Level);
734 
735  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
736  .Case("+3dnowa", AMD3DNowAthlon)
737  .Case("+3dnow", AMD3DNow)
738  .Case("+mmx", MMX)
739  .Default(NoMMX3DNow);
740  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
741 
742  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
743  .Case("+xop", XOP)
744  .Case("+fma4", FMA4)
745  .Case("+sse4a", SSE4A)
746  .Default(NoXOP);
747  XOPLevel = std::max(XOPLevel, XLevel);
748  }
749 
750  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
751  // matches the selected sse level.
752  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
753  (FPMath == FP_387 && SSELevel >= SSE1)) {
754  Diags.Report(diag::err_target_unsupported_fpmath)
755  << (FPMath == FP_SSE ? "sse" : "387");
756  return false;
757  }
758 
759  SimdDefaultAlign =
760  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
761  return true;
762 }
763 
764 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
765 /// definitions for this particular subtarget.
767  MacroBuilder &Builder) const {
768  // Target identification.
769  if (getTriple().getArch() == llvm::Triple::x86_64) {
770  Builder.defineMacro("__amd64__");
771  Builder.defineMacro("__amd64");
772  Builder.defineMacro("__x86_64");
773  Builder.defineMacro("__x86_64__");
774  if (getTriple().getArchName() == "x86_64h") {
775  Builder.defineMacro("__x86_64h");
776  Builder.defineMacro("__x86_64h__");
777  }
778  } else {
779  DefineStd(Builder, "i386", Opts);
780  }
781 
782  // Subtarget options.
783  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
784  // truly should be based on -mtune options.
785  switch (CPU) {
786  case CK_Generic:
787  break;
788  case CK_i386:
789  // The rest are coming from the i386 define above.
790  Builder.defineMacro("__tune_i386__");
791  break;
792  case CK_i486:
793  case CK_WinChipC6:
794  case CK_WinChip2:
795  case CK_C3:
796  defineCPUMacros(Builder, "i486");
797  break;
798  case CK_PentiumMMX:
799  Builder.defineMacro("__pentium_mmx__");
800  Builder.defineMacro("__tune_pentium_mmx__");
801  LLVM_FALLTHROUGH;
802  case CK_i586:
803  case CK_Pentium:
804  defineCPUMacros(Builder, "i586");
805  defineCPUMacros(Builder, "pentium");
806  break;
807  case CK_Pentium3:
808  case CK_PentiumM:
809  Builder.defineMacro("__tune_pentium3__");
810  LLVM_FALLTHROUGH;
811  case CK_Pentium2:
812  case CK_C3_2:
813  Builder.defineMacro("__tune_pentium2__");
814  LLVM_FALLTHROUGH;
815  case CK_PentiumPro:
816  defineCPUMacros(Builder, "i686");
817  defineCPUMacros(Builder, "pentiumpro");
818  break;
819  case CK_Pentium4:
820  defineCPUMacros(Builder, "pentium4");
821  break;
822  case CK_Yonah:
823  case CK_Prescott:
824  case CK_Nocona:
825  defineCPUMacros(Builder, "nocona");
826  break;
827  case CK_Core2:
828  case CK_Penryn:
829  defineCPUMacros(Builder, "core2");
830  break;
831  case CK_Bonnell:
832  defineCPUMacros(Builder, "atom");
833  break;
834  case CK_Silvermont:
835  defineCPUMacros(Builder, "slm");
836  break;
837  case CK_Goldmont:
838  defineCPUMacros(Builder, "goldmont");
839  break;
840  case CK_Nehalem:
841  case CK_Westmere:
842  case CK_SandyBridge:
843  case CK_IvyBridge:
844  case CK_Haswell:
845  case CK_Broadwell:
846  case CK_SkylakeClient:
847  case CK_SkylakeServer:
848  case CK_Cannonlake:
849  case CK_Icelake:
850  // FIXME: Historically, we defined this legacy name, it would be nice to
851  // remove it at some point. We've never exposed fine-grained names for
852  // recent primary x86 CPUs, and we should keep it that way.
853  defineCPUMacros(Builder, "corei7");
854  break;
855  case CK_KNL:
856  defineCPUMacros(Builder, "knl");
857  break;
858  case CK_KNM:
859  break;
860  case CK_Lakemont:
861  defineCPUMacros(Builder, "i586", /*Tuning*/false);
862  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
863  Builder.defineMacro("__tune_lakemont__");
864  break;
865  case CK_K6_2:
866  Builder.defineMacro("__k6_2__");
867  Builder.defineMacro("__tune_k6_2__");
868  LLVM_FALLTHROUGH;
869  case CK_K6_3:
870  if (CPU != CK_K6_2) { // In case of fallthrough
871  // FIXME: GCC may be enabling these in cases where some other k6
872  // architecture is specified but -m3dnow is explicitly provided. The
873  // exact semantics need to be determined and emulated here.
874  Builder.defineMacro("__k6_3__");
875  Builder.defineMacro("__tune_k6_3__");
876  }
877  LLVM_FALLTHROUGH;
878  case CK_K6:
879  defineCPUMacros(Builder, "k6");
880  break;
881  case CK_Athlon:
882  case CK_AthlonXP:
883  defineCPUMacros(Builder, "athlon");
884  if (SSELevel != NoSSE) {
885  Builder.defineMacro("__athlon_sse__");
886  Builder.defineMacro("__tune_athlon_sse__");
887  }
888  break;
889  case CK_K8:
890  case CK_K8SSE3:
891  case CK_x86_64:
892  defineCPUMacros(Builder, "k8");
893  break;
894  case CK_AMDFAM10:
895  defineCPUMacros(Builder, "amdfam10");
896  break;
897  case CK_BTVER1:
898  defineCPUMacros(Builder, "btver1");
899  break;
900  case CK_BTVER2:
901  defineCPUMacros(Builder, "btver2");
902  break;
903  case CK_BDVER1:
904  defineCPUMacros(Builder, "bdver1");
905  break;
906  case CK_BDVER2:
907  defineCPUMacros(Builder, "bdver2");
908  break;
909  case CK_BDVER3:
910  defineCPUMacros(Builder, "bdver3");
911  break;
912  case CK_BDVER4:
913  defineCPUMacros(Builder, "bdver4");
914  break;
915  case CK_ZNVER1:
916  defineCPUMacros(Builder, "znver1");
917  break;
918  case CK_Geode:
919  defineCPUMacros(Builder, "geode");
920  break;
921  }
922 
923  // Target properties.
924  Builder.defineMacro("__REGISTER_PREFIX__", "");
925 
926  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
927  // functions in glibc header files that use FP Stack inline asm which the
928  // backend can't deal with (PR879).
929  Builder.defineMacro("__NO_MATH_INLINES");
930 
931  if (HasAES)
932  Builder.defineMacro("__AES__");
933 
934  if (HasPCLMUL)
935  Builder.defineMacro("__PCLMUL__");
936 
937  if (HasLZCNT)
938  Builder.defineMacro("__LZCNT__");
939 
940  if (HasRDRND)
941  Builder.defineMacro("__RDRND__");
942 
943  if (HasFSGSBASE)
944  Builder.defineMacro("__FSGSBASE__");
945 
946  if (HasBMI)
947  Builder.defineMacro("__BMI__");
948 
949  if (HasBMI2)
950  Builder.defineMacro("__BMI2__");
951 
952  if (HasPOPCNT)
953  Builder.defineMacro("__POPCNT__");
954 
955  if (HasRTM)
956  Builder.defineMacro("__RTM__");
957 
958  if (HasPRFCHW)
959  Builder.defineMacro("__PRFCHW__");
960 
961  if (HasRDSEED)
962  Builder.defineMacro("__RDSEED__");
963 
964  if (HasADX)
965  Builder.defineMacro("__ADX__");
966 
967  if (HasTBM)
968  Builder.defineMacro("__TBM__");
969 
970  if (HasLWP)
971  Builder.defineMacro("__LWP__");
972 
973  if (HasMWAITX)
974  Builder.defineMacro("__MWAITX__");
975 
976  switch (XOPLevel) {
977  case XOP:
978  Builder.defineMacro("__XOP__");
979  LLVM_FALLTHROUGH;
980  case FMA4:
981  Builder.defineMacro("__FMA4__");
982  LLVM_FALLTHROUGH;
983  case SSE4A:
984  Builder.defineMacro("__SSE4A__");
985  LLVM_FALLTHROUGH;
986  case NoXOP:
987  break;
988  }
989 
990  if (HasFMA)
991  Builder.defineMacro("__FMA__");
992 
993  if (HasF16C)
994  Builder.defineMacro("__F16C__");
995 
996  if (HasAVX512CD)
997  Builder.defineMacro("__AVX512CD__");
998  if (HasAVX512VPOPCNTDQ)
999  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1000  if (HasAVX512ER)
1001  Builder.defineMacro("__AVX512ER__");
1002  if (HasAVX512PF)
1003  Builder.defineMacro("__AVX512PF__");
1004  if (HasAVX512DQ)
1005  Builder.defineMacro("__AVX512DQ__");
1006  if (HasAVX512BW)
1007  Builder.defineMacro("__AVX512BW__");
1008  if (HasAVX512VL)
1009  Builder.defineMacro("__AVX512VL__");
1010  if (HasAVX512VBMI)
1011  Builder.defineMacro("__AVX512VBMI__");
1012  if (HasAVX512IFMA)
1013  Builder.defineMacro("__AVX512IFMA__");
1014 
1015  if (HasSHA)
1016  Builder.defineMacro("__SHA__");
1017 
1018  if (HasFXSR)
1019  Builder.defineMacro("__FXSR__");
1020  if (HasXSAVE)
1021  Builder.defineMacro("__XSAVE__");
1022  if (HasXSAVEOPT)
1023  Builder.defineMacro("__XSAVEOPT__");
1024  if (HasXSAVEC)
1025  Builder.defineMacro("__XSAVEC__");
1026  if (HasXSAVES)
1027  Builder.defineMacro("__XSAVES__");
1028  if (HasPKU)
1029  Builder.defineMacro("__PKU__");
1030  if (HasCX16)
1031  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1032  if (HasCLFLUSHOPT)
1033  Builder.defineMacro("__CLFLUSHOPT__");
1034  if (HasCLWB)
1035  Builder.defineMacro("__CLWB__");
1036  if (HasMPX)
1037  Builder.defineMacro("__MPX__");
1038  if (HasSHSTK)
1039  Builder.defineMacro("__SHSTK__");
1040  if (HasSGX)
1041  Builder.defineMacro("__SGX__");
1042  if (HasPREFETCHWT1)
1043  Builder.defineMacro("__PREFETCHWT1__");
1044  if (HasCLZERO)
1045  Builder.defineMacro("__CLZERO__");
1046 
1047  // Each case falls through to the previous one here.
1048  switch (SSELevel) {
1049  case AVX512F:
1050  Builder.defineMacro("__AVX512F__");
1051  LLVM_FALLTHROUGH;
1052  case AVX2:
1053  Builder.defineMacro("__AVX2__");
1054  LLVM_FALLTHROUGH;
1055  case AVX:
1056  Builder.defineMacro("__AVX__");
1057  LLVM_FALLTHROUGH;
1058  case SSE42:
1059  Builder.defineMacro("__SSE4_2__");
1060  LLVM_FALLTHROUGH;
1061  case SSE41:
1062  Builder.defineMacro("__SSE4_1__");
1063  LLVM_FALLTHROUGH;
1064  case SSSE3:
1065  Builder.defineMacro("__SSSE3__");
1066  LLVM_FALLTHROUGH;
1067  case SSE3:
1068  Builder.defineMacro("__SSE3__");
1069  LLVM_FALLTHROUGH;
1070  case SSE2:
1071  Builder.defineMacro("__SSE2__");
1072  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1073  LLVM_FALLTHROUGH;
1074  case SSE1:
1075  Builder.defineMacro("__SSE__");
1076  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1077  LLVM_FALLTHROUGH;
1078  case NoSSE:
1079  break;
1080  }
1081 
1082  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1083  switch (SSELevel) {
1084  case AVX512F:
1085  case AVX2:
1086  case AVX:
1087  case SSE42:
1088  case SSE41:
1089  case SSSE3:
1090  case SSE3:
1091  case SSE2:
1092  Builder.defineMacro("_M_IX86_FP", Twine(2));
1093  break;
1094  case SSE1:
1095  Builder.defineMacro("_M_IX86_FP", Twine(1));
1096  break;
1097  default:
1098  Builder.defineMacro("_M_IX86_FP", Twine(0));
1099  break;
1100  }
1101  }
1102 
1103  // Each case falls through to the previous one here.
1104  switch (MMX3DNowLevel) {
1105  case AMD3DNowAthlon:
1106  Builder.defineMacro("__3dNOW_A__");
1107  LLVM_FALLTHROUGH;
1108  case AMD3DNow:
1109  Builder.defineMacro("__3dNOW__");
1110  LLVM_FALLTHROUGH;
1111  case MMX:
1112  Builder.defineMacro("__MMX__");
1113  LLVM_FALLTHROUGH;
1114  case NoMMX3DNow:
1115  break;
1116  }
1117 
1118  if (CPU >= CK_i486) {
1119  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1120  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1121  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1122  }
1123  if (CPU >= CK_i586)
1124  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1125 
1126  if (HasFloat128)
1127  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1128 }
1129 
1130 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1131  return llvm::StringSwitch<bool>(Name)
1132  .Case("3dnow", true)
1133  .Case("3dnowa", true)
1134  .Case("aes", true)
1135  .Case("avx", true)
1136  .Case("avx2", true)
1137  .Case("avx512f", true)
1138  .Case("avx512cd", true)
1139  .Case("avx512vpopcntdq", true)
1140  .Case("avx512er", true)
1141  .Case("avx512pf", true)
1142  .Case("avx512dq", true)
1143  .Case("avx512bw", true)
1144  .Case("avx512vl", true)
1145  .Case("avx512vbmi", true)
1146  .Case("avx512ifma", true)
1147  .Case("bmi", true)
1148  .Case("bmi2", true)
1149  .Case("clflushopt", true)
1150  .Case("clwb", true)
1151  .Case("clzero", true)
1152  .Case("cx16", true)
1153  .Case("f16c", true)
1154  .Case("fma", true)
1155  .Case("fma4", true)
1156  .Case("fsgsbase", true)
1157  .Case("fxsr", true)
1158  .Case("lwp", true)
1159  .Case("lzcnt", true)
1160  .Case("mmx", true)
1161  .Case("movbe", true)
1162  .Case("mpx", true)
1163  .Case("pclmul", true)
1164  .Case("pku", true)
1165  .Case("popcnt", true)
1166  .Case("prefetchwt1", true)
1167  .Case("prfchw", true)
1168  .Case("rdrnd", true)
1169  .Case("rdseed", true)
1170  .Case("rtm", true)
1171  .Case("sgx", true)
1172  .Case("sha", true)
1173  .Case("sse", true)
1174  .Case("sse2", true)
1175  .Case("sse3", true)
1176  .Case("ssse3", true)
1177  .Case("sse4", true)
1178  .Case("sse4.1", true)
1179  .Case("sse4.2", true)
1180  .Case("sse4a", true)
1181  .Case("tbm", true)
1182  .Case("x87", true)
1183  .Case("xop", true)
1184  .Case("xsave", true)
1185  .Case("xsavec", true)
1186  .Case("xsaves", true)
1187  .Case("xsaveopt", true)
1188  .Default(false);
1189 }
1190 
1191 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1192  return llvm::StringSwitch<bool>(Feature)
1193  .Case("aes", HasAES)
1194  .Case("avx", SSELevel >= AVX)
1195  .Case("avx2", SSELevel >= AVX2)
1196  .Case("avx512f", SSELevel >= AVX512F)
1197  .Case("avx512cd", HasAVX512CD)
1198  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1199  .Case("avx512er", HasAVX512ER)
1200  .Case("avx512pf", HasAVX512PF)
1201  .Case("avx512dq", HasAVX512DQ)
1202  .Case("avx512bw", HasAVX512BW)
1203  .Case("avx512vl", HasAVX512VL)
1204  .Case("avx512vbmi", HasAVX512VBMI)
1205  .Case("avx512ifma", HasAVX512IFMA)
1206  .Case("bmi", HasBMI)
1207  .Case("bmi2", HasBMI2)
1208  .Case("clflushopt", HasCLFLUSHOPT)
1209  .Case("clwb", HasCLWB)
1210  .Case("clzero", HasCLZERO)
1211  .Case("cx16", HasCX16)
1212  .Case("f16c", HasF16C)
1213  .Case("fma", HasFMA)
1214  .Case("fma4", XOPLevel >= FMA4)
1215  .Case("fsgsbase", HasFSGSBASE)
1216  .Case("fxsr", HasFXSR)
1217  .Case("lwp", HasLWP)
1218  .Case("lzcnt", HasLZCNT)
1219  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1220  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1221  .Case("mmx", MMX3DNowLevel >= MMX)
1222  .Case("movbe", HasMOVBE)
1223  .Case("mpx", HasMPX)
1224  .Case("shstk", HasSHSTK)
1225  .Case("ibt", HasIBT)
1226  .Case("pclmul", HasPCLMUL)
1227  .Case("pku", HasPKU)
1228  .Case("popcnt", HasPOPCNT)
1229  .Case("prefetchwt1", HasPREFETCHWT1)
1230  .Case("prfchw", HasPRFCHW)
1231  .Case("rdrnd", HasRDRND)
1232  .Case("rdseed", HasRDSEED)
1233  .Case("rtm", HasRTM)
1234  .Case("sgx", HasSGX)
1235  .Case("sha", HasSHA)
1236  .Case("sse", SSELevel >= SSE1)
1237  .Case("sse2", SSELevel >= SSE2)
1238  .Case("sse3", SSELevel >= SSE3)
1239  .Case("ssse3", SSELevel >= SSSE3)
1240  .Case("sse4.1", SSELevel >= SSE41)
1241  .Case("sse4.2", SSELevel >= SSE42)
1242  .Case("sse4a", XOPLevel >= SSE4A)
1243  .Case("tbm", HasTBM)
1244  .Case("x86", true)
1245  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1246  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1247  .Case("xop", XOPLevel >= XOP)
1248  .Case("xsave", HasXSAVE)
1249  .Case("xsavec", HasXSAVEC)
1250  .Case("xsaves", HasXSAVES)
1251  .Case("xsaveopt", HasXSAVEOPT)
1252  .Default(false);
1253 }
1254 
1255 // We can't use a generic validation scheme for the features accepted here
1256 // versus subtarget features accepted in the target attribute because the
1257 // bitfield structure that's initialized in the runtime only supports the
1258 // below currently rather than the full range of subtarget features. (See
1259 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1260 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1261  return llvm::StringSwitch<bool>(FeatureStr)
1262 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1263 #include "llvm/Support/X86TargetParser.def"
1264  .Default(false);
1265 }
1266 
1267 // We can't use a generic validation scheme for the cpus accepted here
1268 // versus subtarget cpus accepted in the target attribute because the
1269 // variables intitialized by the runtime only support the below currently
1270 // rather than the full range of cpus.
1271 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1272  return llvm::StringSwitch<bool>(FeatureStr)
1273 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1274 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1275  .Cases(STR, ALIAS, true)
1276 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1277 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1278 #include "llvm/Support/X86TargetParser.def"
1279  .Default(false);
1280 }
1281 
1283  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1284  switch (*Name) {
1285  default:
1286  return false;
1287  // Constant constraints.
1288  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1289  // instructions.
1290  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1291  // x86_64 instructions.
1292  case 's':
1293  Info.setRequiresImmediate();
1294  return true;
1295  case 'I':
1296  Info.setRequiresImmediate(0, 31);
1297  return true;
1298  case 'J':
1299  Info.setRequiresImmediate(0, 63);
1300  return true;
1301  case 'K':
1302  Info.setRequiresImmediate(-128, 127);
1303  return true;
1304  case 'L':
1305  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1306  return true;
1307  case 'M':
1308  Info.setRequiresImmediate(0, 3);
1309  return true;
1310  case 'N':
1311  Info.setRequiresImmediate(0, 255);
1312  return true;
1313  case 'O':
1314  Info.setRequiresImmediate(0, 127);
1315  return true;
1316  // Register constraints.
1317  case 'Y': // 'Y' is the first character for several 2-character constraints.
1318  // Shift the pointer to the second character of the constraint.
1319  Name++;
1320  switch (*Name) {
1321  default:
1322  return false;
1323  case 'z':
1324  case '0': // First SSE register.
1325  case '2':
1326  case 't': // Any SSE register, when SSE2 is enabled.
1327  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1328  case 'm': // Any MMX register, when inter-unit moves enabled.
1329  case 'k': // AVX512 arch mask registers: k1-k7.
1330  Info.setAllowsRegister();
1331  return true;
1332  }
1333  case 'f': // Any x87 floating point stack register.
1334  // Constraint 'f' cannot be used for output operands.
1335  if (Info.ConstraintStr[0] == '=')
1336  return false;
1337  Info.setAllowsRegister();
1338  return true;
1339  case 'a': // eax.
1340  case 'b': // ebx.
1341  case 'c': // ecx.
1342  case 'd': // edx.
1343  case 'S': // esi.
1344  case 'D': // edi.
1345  case 'A': // edx:eax.
1346  case 't': // Top of floating point stack.
1347  case 'u': // Second from top of floating point stack.
1348  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1349  case 'y': // Any MMX register.
1350  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1351  case 'x': // Any SSE register.
1352  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
1353  // for intermideate k reg operations).
1354  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1355  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1356  case 'l': // "Index" registers: any general register that can be used as an
1357  // index in a base+index memory access.
1358  Info.setAllowsRegister();
1359  return true;
1360  // Floating point constant constraints.
1361  case 'C': // SSE floating point constant.
1362  case 'G': // x87 floating point constant.
1363  return true;
1364  }
1365 }
1366 
1367 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1368  unsigned Size) const {
1369  // Strip off constraint modifiers.
1370  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1371  Constraint = Constraint.substr(1);
1372 
1373  return validateOperandSize(Constraint, Size);
1374 }
1375 
1376 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1377  unsigned Size) const {
1378  return validateOperandSize(Constraint, Size);
1379 }
1380 
1381 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1382  unsigned Size) const {
1383  switch (Constraint[0]) {
1384  default:
1385  break;
1386  case 'k':
1387  // Registers k0-k7 (AVX512) size limit is 64 bit.
1388  case 'y':
1389  return Size <= 64;
1390  case 'f':
1391  case 't':
1392  case 'u':
1393  return Size <= 128;
1394  case 'Y':
1395  // 'Y' is the first character for several 2-character constraints.
1396  switch (Constraint[1]) {
1397  default:
1398  return false;
1399  case 'm':
1400  // 'Ym' is synonymous with 'y'.
1401  case 'k':
1402  return Size <= 64;
1403  case 'z':
1404  case '0':
1405  // XMM0
1406  if (SSELevel >= SSE1)
1407  return Size <= 128U;
1408  return false;
1409  case 'i':
1410  case 't':
1411  case '2':
1412  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1413  if (SSELevel < SSE2)
1414  return false;
1415  break;
1416  }
1417  case 'v':
1418  case 'x':
1419  if (SSELevel >= AVX512F)
1420  // 512-bit zmm registers can be used if target supports AVX512F.
1421  return Size <= 512U;
1422  else if (SSELevel >= AVX)
1423  // 256-bit ymm registers can be used if target supports AVX.
1424  return Size <= 256U;
1425  return Size <= 128U;
1426 
1427  }
1428 
1429  return true;
1430 }
1431 
1432 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1433  switch (*Constraint) {
1434  case 'a':
1435  return std::string("{ax}");
1436  case 'b':
1437  return std::string("{bx}");
1438  case 'c':
1439  return std::string("{cx}");
1440  case 'd':
1441  return std::string("{dx}");
1442  case 'S':
1443  return std::string("{si}");
1444  case 'D':
1445  return std::string("{di}");
1446  case 'p': // address
1447  return std::string("im");
1448  case 't': // top of floating point stack.
1449  return std::string("{st}");
1450  case 'u': // second from top of floating point stack.
1451  return std::string("{st(1)}"); // second from top of floating point stack.
1452  case 'Y':
1453  switch (Constraint[1]) {
1454  default:
1455  // Break from inner switch and fall through (copy single char),
1456  // continue parsing after copying the current constraint into
1457  // the return string.
1458  break;
1459  case 'k':
1460  case 'm':
1461  case 'i':
1462  case 't':
1463  case 'z':
1464  case '0':
1465  case '2':
1466  // "^" hints llvm that this is a 2 letter constraint.
1467  // "Constraint++" is used to promote the string iterator
1468  // to the next constraint.
1469  return std::string("^") + std::string(Constraint++, 2);
1470  }
1471  LLVM_FALLTHROUGH;
1472  default:
1473  return std::string(1, *Constraint);
1474  }
1475 }
1476 
1477 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1478  // Perform any per-CPU checks necessary to determine if this CPU is
1479  // acceptable.
1480  // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1481  // invalid without explaining *why*.
1482  switch (Kind) {
1483  case CK_Generic:
1484  // No processor selected!
1485  return false;
1486 #define PROC(ENUM, STRING, IS64BIT) \
1487  case CK_##ENUM: \
1488  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1489 #include "clang/Basic/X86Target.def"
1490  }
1491  llvm_unreachable("Unhandled CPU kind");
1492 }
1493 
1494 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1495  return llvm::StringSwitch<CPUKind>(CPU)
1496 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1497 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1498 #include "clang/Basic/X86Target.def"
1499  .Default(CK_Generic);
1500 }
1501 
1503  return llvm::makeArrayRef(GCCRegNames);
1504 }
1505 
1507  return llvm::makeArrayRef(AddlRegNames);
1508 }
1509 
1511  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1513 }
1514 
1516  return llvm::makeArrayRef(BuiltinInfoX86,
1518 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:53
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:73
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:91
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:24
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:475
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1207
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1367
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1506
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:694
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1381
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:508
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:66
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:48
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1260
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:147
Defines the Diagnostic-related interfaces.
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1282
static const char *const GCCRegNames[]
Definition: X86.cpp:42
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1130
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:347
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1191
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:398
Enumerates target-specific builtins in their own namespaces within namespace clang.
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1515
Kind
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1432
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1510
Dataflow Directional Tag Classes.
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:628
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1376
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:766
#define PROC(ENUM, STRING, IS64BIT)
char __ovld __cnfn max(char x, char y)
Returns y if x < y, otherwise it returns x.
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:69
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:543
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1271
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1502
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:103