clang 19.0.0git
AArch64.cpp
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1//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements AArch64 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64.h"
17#include "llvm/ADT/APSInt.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/StringExtras.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/TargetParser/AArch64TargetParser.h"
22#include "llvm/TargetParser/ARMTargetParserCommon.h"
23#include <optional>
24
25using namespace clang;
26using namespace clang::targets;
27
28static constexpr Builtin::Info BuiltinInfo[] = {
29#define BUILTIN(ID, TYPE, ATTRS) \
30 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
31#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
33#include "clang/Basic/BuiltinsNEON.def"
34
35#define BUILTIN(ID, TYPE, ATTRS) \
36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
37#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
39#include "clang/Basic/BuiltinsSVE.def"
40
41#define BUILTIN(ID, TYPE, ATTRS) \
42 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
43#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
44 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
45#include "clang/Basic/BuiltinsSME.def"
46
47#define BUILTIN(ID, TYPE, ATTRS) \
48 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
49#define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
50 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, LANG},
51#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
52 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
53#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
54 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
55#include "clang/Basic/BuiltinsAArch64.def"
56};
57
59 if (*ArchInfo == llvm::AArch64::ARMV8R) {
60 HasDotProd = true;
61 HasDIT = true;
62 HasFlagM = true;
63 HasRCPC = true;
64 FPU |= NeonMode;
65 HasCCPP = true;
66 HasCRC = true;
67 HasLSE = true;
68 HasRDM = true;
69 } else if (ArchInfo->Version.getMajor() == 8) {
70 if (ArchInfo->Version.getMinor() >= 7u) {
71 HasWFxT = true;
72 }
73 if (ArchInfo->Version.getMinor() >= 6u) {
74 HasBFloat16 = true;
75 HasMatMul = true;
76 }
77 if (ArchInfo->Version.getMinor() >= 5u) {
78 HasAlternativeNZCV = true;
79 HasFRInt3264 = true;
80 HasSSBS = true;
81 HasSB = true;
82 HasPredRes = true;
83 HasBTI = true;
84 }
85 if (ArchInfo->Version.getMinor() >= 4u) {
86 HasDotProd = true;
87 HasDIT = true;
88 HasFlagM = true;
89 }
90 if (ArchInfo->Version.getMinor() >= 3u) {
91 HasRCPC = true;
92 FPU |= NeonMode;
93 }
94 if (ArchInfo->Version.getMinor() >= 2u) {
95 HasCCPP = true;
96 }
97 if (ArchInfo->Version.getMinor() >= 1u) {
98 HasCRC = true;
99 HasLSE = true;
100 HasRDM = true;
101 }
102 } else if (ArchInfo->Version.getMajor() == 9) {
103 if (ArchInfo->Version.getMinor() >= 2u) {
104 HasWFxT = true;
105 }
106 if (ArchInfo->Version.getMinor() >= 1u) {
107 HasBFloat16 = true;
108 HasMatMul = true;
109 }
110 FPU |= SveMode;
111 HasSVE2 = true;
112 HasFullFP16 = true;
113 HasAlternativeNZCV = true;
114 HasFRInt3264 = true;
115 HasSSBS = true;
116 HasSB = true;
117 HasPredRes = true;
118 HasBTI = true;
119 HasDotProd = true;
120 HasDIT = true;
121 HasFlagM = true;
122 HasRCPC = true;
123 FPU |= NeonMode;
124 HasCCPP = true;
125 HasCRC = true;
126 HasLSE = true;
127 HasRDM = true;
128 }
129}
130
131AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
132 const TargetOptions &Opts)
133 : TargetInfo(Triple), ABI("aapcs") {
134 if (getTriple().isOSOpenBSD()) {
137 } else {
138 if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD())
140
143 }
144
145 // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
146 HasLegalHalfType = true;
147 HalfArgsAndReturns = true;
148 HasFloat16 = true;
149 HasStrictFP = true;
150
151 if (Triple.isArch64Bit())
153 else
155
156 MaxVectorAlign = 128;
159
161 LongDoubleFormat = &llvm::APFloat::IEEEquad();
162
164 BFloat16Format = &llvm::APFloat::BFloat();
165
166 // Make __builtin_ms_va_list available.
167 HasBuiltinMSVaList = true;
168
169 // Make the SVE types available. Note that this deliberately doesn't
170 // depend on SveMode, since in principle it should be possible to turn
171 // SVE on and off within a translation unit. It should also be possible
172 // to compile the global declaration:
173 //
174 // __SVInt8_t *ptr;
175 //
176 // even without SVE.
177 HasAArch64SVETypes = true;
178
179 // {} in inline assembly are neon specifiers, not assembly variant
180 // specifiers.
181 NoAsmVariants = true;
182
183 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
184 // contributes to the alignment of the containing aggregate in the same way
185 // a plain (non bit-field) member of that type would, without exception for
186 // zero-sized or anonymous bit-fields."
187 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
189
190 // AArch64 targets default to using the ARM C++ ABI.
191 TheCXXABI.set(TargetCXXABI::GenericAArch64);
192
193 if (Triple.getOS() == llvm::Triple::Linux)
194 this->MCountName = "\01_mcount";
195 else if (Triple.getOS() == llvm::Triple::UnknownOS)
196 this->MCountName =
197 Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
198}
199
200StringRef AArch64TargetInfo::getABI() const { return ABI; }
201
202bool AArch64TargetInfo::setABI(const std::string &Name) {
203 if (Name != "aapcs" && Name != "darwinpcs")
204 return false;
205
206 ABI = Name;
207 return true;
208}
209
210bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
212 StringRef &Err) const {
213 llvm::ARM::ParsedBranchProtection PBP;
214 if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
215 return false;
216
217 BPI.SignReturnAddr =
218 llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
222
223 if (PBP.Key == "a_key")
225 else
227
228 BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
229 BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
230 BPI.GuardedControlStack = PBP.GuardedControlStack;
231 return true;
232}
233
234bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
235 return Name == "generic" || llvm::AArch64::parseCpu(Name);
236}
237
238bool AArch64TargetInfo::setCPU(const std::string &Name) {
239 return isValidCPUName(Name);
240}
241
243 SmallVectorImpl<StringRef> &Values) const {
244 llvm::AArch64::fillValidCPUArchList(Values);
245}
246
248 MacroBuilder &Builder) const {
249 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
250}
251
253 MacroBuilder &Builder) const {
254 // Also include the ARMv8.1 defines
255 getTargetDefinesARMV81A(Opts, Builder);
256}
257
259 MacroBuilder &Builder) const {
260 Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
261 Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
262 // Also include the Armv8.2 defines
263 getTargetDefinesARMV82A(Opts, Builder);
264}
265
267 MacroBuilder &Builder) const {
268 // Also include the Armv8.3 defines
269 getTargetDefinesARMV83A(Opts, Builder);
270}
271
273 MacroBuilder &Builder) const {
274 Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
275 Builder.defineMacro("__ARM_FEATURE_BTI", "1");
276 // Also include the Armv8.4 defines
277 getTargetDefinesARMV84A(Opts, Builder);
278}
279
281 MacroBuilder &Builder) const {
282 // Also include the Armv8.5 defines
283 // FIXME: Armv8.6 makes the following extensions mandatory:
284 // - __ARM_FEATURE_BF16
285 // - __ARM_FEATURE_MATMUL_INT8
286 // Handle them here.
287 getTargetDefinesARMV85A(Opts, Builder);
288}
289
291 MacroBuilder &Builder) const {
292 // Also include the Armv8.6 defines
293 getTargetDefinesARMV86A(Opts, Builder);
294}
295
297 MacroBuilder &Builder) const {
298 // Also include the Armv8.7 defines
299 getTargetDefinesARMV87A(Opts, Builder);
300}
301
303 MacroBuilder &Builder) const {
304 // Also include the Armv8.8 defines
305 getTargetDefinesARMV88A(Opts, Builder);
306}
307
309 MacroBuilder &Builder) const {
310 // Armv9-A maps to Armv8.5-A
311 getTargetDefinesARMV85A(Opts, Builder);
312}
313
315 MacroBuilder &Builder) const {
316 // Armv9.1-A maps to Armv8.6-A
317 getTargetDefinesARMV86A(Opts, Builder);
318}
319
321 MacroBuilder &Builder) const {
322 // Armv9.2-A maps to Armv8.7-A
323 getTargetDefinesARMV87A(Opts, Builder);
324}
325
327 MacroBuilder &Builder) const {
328 // Armv9.3-A maps to Armv8.8-A
329 getTargetDefinesARMV88A(Opts, Builder);
330}
331
333 MacroBuilder &Builder) const {
334 // Armv9.4-A maps to Armv8.9-A
335 getTargetDefinesARMV89A(Opts, Builder);
336}
337
339 MacroBuilder &Builder) const {
340 // Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A.
341 getTargetDefinesARMV94A(Opts, Builder);
342}
343
345 MacroBuilder &Builder) const {
346 // Target identification.
347 if (getTriple().isWindowsArm64EC()) {
348 // Define the same set of macros as would be defined on x86_64 to ensure that
349 // ARM64EC datatype layouts match those of x86_64 compiled code
350 Builder.defineMacro("__amd64__");
351 Builder.defineMacro("__amd64");
352 Builder.defineMacro("__x86_64");
353 Builder.defineMacro("__x86_64__");
354 Builder.defineMacro("__arm64ec__");
355 } else {
356 Builder.defineMacro("__aarch64__");
357 }
358
359 // Inline assembly supports AArch64 flag outputs.
360 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
361
362 std::string CodeModel = getTargetOpts().CodeModel;
363 if (CodeModel == "default")
364 CodeModel = "small";
365 for (char &c : CodeModel)
366 c = toupper(c);
367 Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
368
369 // ACLE predefines. Many can only have one possible value on v8 AArch64.
370 Builder.defineMacro("__ARM_ACLE", "200");
371 Builder.defineMacro("__ARM_ARCH",
372 std::to_string(ArchInfo->Version.getMajor()));
373 Builder.defineMacro("__ARM_ARCH_PROFILE",
374 std::string("'") + (char)ArchInfo->Profile + "'");
375
376 Builder.defineMacro("__ARM_64BIT_STATE", "1");
377 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
378 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
379
380 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
381 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
382 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
383 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
384 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
385 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
386 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
387
388 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
389
390 // These macros are set when Clang can parse declarations with these
391 // attributes.
392 Builder.defineMacro("__ARM_STATE_ZA", "1");
393 Builder.defineMacro("__ARM_STATE_ZT0", "1");
394
395 // 0xe implies support for half, single and double precision operations.
396 if (FPU & FPUMode)
397 Builder.defineMacro("__ARM_FP", "0xE");
398
399 // PCS specifies this for SysV variants, which is all we support. Other ABIs
400 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
401 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
402 Builder.defineMacro("__ARM_FP16_ARGS", "1");
403
404 if (Opts.UnsafeFPMath)
405 Builder.defineMacro("__ARM_FP_FAST", "1");
406
407 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
408 Twine(Opts.WCharSize ? Opts.WCharSize : 4));
409
410 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
411
412 if (FPU & NeonMode) {
413 Builder.defineMacro("__ARM_NEON", "1");
414 // 64-bit NEON supports half, single and double precision operations.
415 Builder.defineMacro("__ARM_NEON_FP", "0xE");
416 }
417
418 if (FPU & SveMode)
419 Builder.defineMacro("__ARM_FEATURE_SVE", "1");
420
421 if ((FPU & NeonMode) && (FPU & SveMode))
422 Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
423
424 if (HasSVE2)
425 Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
426
427 if (HasSVE2 && HasSVE2AES)
428 Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
429
430 if (HasSVE2 && HasSVE2BitPerm)
431 Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
432
433 if (HasSVE2 && HasSVE2SHA3)
434 Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
435
436 if (HasSVE2 && HasSVE2SM4)
437 Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
438
439 if (HasSME) {
440 Builder.defineMacro("__ARM_FEATURE_SME");
441 Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1");
442 }
443
444 if (HasSME2) {
445 Builder.defineMacro("__ARM_FEATURE_SME");
446 Builder.defineMacro("__ARM_FEATURE_SME2");
447 Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1");
448 }
449
450 if (HasCRC)
451 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
452
453 if (HasRCPC3)
454 Builder.defineMacro("__ARM_FEATURE_RCPC", "3");
455 else if (HasRCPC)
456 Builder.defineMacro("__ARM_FEATURE_RCPC", "1");
457
458 if (HasFMV)
459 Builder.defineMacro("__HAVE_FUNCTION_MULTI_VERSIONING", "1");
460
461 // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
462 // macros for AES, SHA2, SHA3 and SM4
463 if (HasAES && HasSHA2)
464 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
465
466 if (HasAES)
467 Builder.defineMacro("__ARM_FEATURE_AES", "1");
468
469 if (HasSHA2)
470 Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
471
472 if (HasSHA3) {
473 Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
474 Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
475 }
476
477 if (HasSM4) {
478 Builder.defineMacro("__ARM_FEATURE_SM3", "1");
479 Builder.defineMacro("__ARM_FEATURE_SM4", "1");
480 }
481
482 if (HasPAuth)
483 Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
484
485 if (HasPAuthLR)
486 Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1");
487
488 if (HasUnaligned)
489 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
490
491 if ((FPU & NeonMode) && HasFullFP16)
492 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
493 if (HasFullFP16)
494 Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
495
496 if (HasDotProd)
497 Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
498
499 if (HasMTE)
500 Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
501
502 if (HasTME)
503 Builder.defineMacro("__ARM_FEATURE_TME", "1");
504
505 if (HasMatMul)
506 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
507
508 if (HasLSE)
509 Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
510
511 if (HasBFloat16) {
512 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
513 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
514 Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
515 Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
516 }
517
518 if ((FPU & SveMode) && HasBFloat16) {
519 Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
520 }
521
522 if ((FPU & SveMode) && HasMatmulFP64)
523 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
524
525 if ((FPU & SveMode) && HasMatmulFP32)
526 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
527
528 if ((FPU & SveMode) && HasMatMul)
529 Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
530
531 if ((FPU & NeonMode) && HasFP16FML)
532 Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
533
534 if (Opts.hasSignReturnAddress()) {
535 // Bitmask:
536 // 0: Protection using the A key
537 // 1: Protection using the B key
538 // 2: Protection including leaf functions
539 // 3: Protection using PC as a diversifier
540 unsigned Value = 0;
541
543 Value |= (1 << 0);
544 else
545 Value |= (1 << 1);
546
548 Value |= (1 << 2);
549
550 if (Opts.BranchProtectionPAuthLR)
551 Value |= (1 << 3);
552
553 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
554 }
555
556 if (Opts.BranchTargetEnforcement)
557 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
558
559 if (Opts.GuardedControlStack)
560 Builder.defineMacro("__ARM_FEATURE_GCS_DEFAULT", "1");
561
562 if (HasLS64)
563 Builder.defineMacro("__ARM_FEATURE_LS64", "1");
564
565 if (HasRandGen)
566 Builder.defineMacro("__ARM_FEATURE_RNG", "1");
567
568 if (HasMOPS)
569 Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
570
571 if (HasD128)
572 Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
573
574 if (HasGCS)
575 Builder.defineMacro("__ARM_FEATURE_GCS", "1");
576
577 if (*ArchInfo == llvm::AArch64::ARMV8_1A)
578 getTargetDefinesARMV81A(Opts, Builder);
579 else if (*ArchInfo == llvm::AArch64::ARMV8_2A)
580 getTargetDefinesARMV82A(Opts, Builder);
581 else if (*ArchInfo == llvm::AArch64::ARMV8_3A)
582 getTargetDefinesARMV83A(Opts, Builder);
583 else if (*ArchInfo == llvm::AArch64::ARMV8_4A)
584 getTargetDefinesARMV84A(Opts, Builder);
585 else if (*ArchInfo == llvm::AArch64::ARMV8_5A)
586 getTargetDefinesARMV85A(Opts, Builder);
587 else if (*ArchInfo == llvm::AArch64::ARMV8_6A)
588 getTargetDefinesARMV86A(Opts, Builder);
589 else if (*ArchInfo == llvm::AArch64::ARMV8_7A)
590 getTargetDefinesARMV87A(Opts, Builder);
591 else if (*ArchInfo == llvm::AArch64::ARMV8_8A)
592 getTargetDefinesARMV88A(Opts, Builder);
593 else if (*ArchInfo == llvm::AArch64::ARMV8_9A)
594 getTargetDefinesARMV89A(Opts, Builder);
595 else if (*ArchInfo == llvm::AArch64::ARMV9A)
596 getTargetDefinesARMV9A(Opts, Builder);
597 else if (*ArchInfo == llvm::AArch64::ARMV9_1A)
598 getTargetDefinesARMV91A(Opts, Builder);
599 else if (*ArchInfo == llvm::AArch64::ARMV9_2A)
600 getTargetDefinesARMV92A(Opts, Builder);
601 else if (*ArchInfo == llvm::AArch64::ARMV9_3A)
602 getTargetDefinesARMV93A(Opts, Builder);
603 else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
604 getTargetDefinesARMV94A(Opts, Builder);
605 else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
606 getTargetDefinesARMV95A(Opts, Builder);
607
608 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8|16) builtins work.
609 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
610 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
611 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
612 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
613 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
614
615 // Allow detection of fast FMA support.
616 Builder.defineMacro("__FP_FAST_FMA", "1");
617 Builder.defineMacro("__FP_FAST_FMAF", "1");
618
619 // C/C++ operators work on both VLS and VLA SVE types
620 if (FPU & SveMode)
621 Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS", "2");
622
623 if (Opts.VScaleMin && Opts.VScaleMin == Opts.VScaleMax) {
624 Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
625 }
626}
627
631}
632
633std::optional<std::pair<unsigned, unsigned>>
635 if (LangOpts.VScaleMin || LangOpts.VScaleMax)
636 return std::pair<unsigned, unsigned>(
637 LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
638
639 if (hasFeature("sve"))
640 return std::pair<unsigned, unsigned>(1, 16);
641
642 return std::nullopt;
643}
644
645unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
646 if (Name == "default")
647 return 0;
648 if (auto Ext = llvm::AArch64::parseArchExtension(Name))
649 return Ext->FmvPriority;
650 return 0;
651}
652
654 // Take the maximum priority as per feature cost, so more features win.
655 return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
656}
657
659 if (auto Ext = llvm::AArch64::parseArchExtension(Name))
660 return !Ext->DependentFeatures.empty();
661 return false;
662}
663
664StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
665 if (auto Ext = llvm::AArch64::parseArchExtension(Name))
666 return Ext->DependentFeatures;
667 return StringRef();
668}
669
670bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
671 // CPU features might be separated by '+', extract them and check
673 FeatureStr.split(Features, "+");
674 for (auto &Feature : Features)
675 if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
676 return false;
677 return true;
678}
679
680bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
681 return llvm::StringSwitch<bool>(Feature)
682 .Cases("aarch64", "arm64", "arm", true)
683 .Case("fmv", HasFMV)
684 .Cases("neon", "fp", "simd", FPU & NeonMode)
685 .Case("jscvt", HasJSCVT)
686 .Case("fcma", HasFCMA)
687 .Case("rng", HasRandGen)
688 .Case("flagm", HasFlagM)
689 .Case("flagm2", HasAlternativeNZCV)
690 .Case("fp16fml", HasFP16FML)
691 .Case("dotprod", HasDotProd)
692 .Case("sm4", HasSM4)
693 .Case("rdm", HasRDM)
694 .Case("lse", HasLSE)
695 .Case("crc", HasCRC)
696 .Case("sha2", HasSHA2)
697 .Case("sha3", HasSHA3)
698 .Cases("aes", "pmull", HasAES)
699 .Cases("fp16", "fullfp16", HasFullFP16)
700 .Case("dit", HasDIT)
701 .Case("dpb", HasCCPP)
702 .Case("dpb2", HasCCDP)
703 .Case("rcpc", HasRCPC)
704 .Case("frintts", HasFRInt3264)
705 .Case("i8mm", HasMatMul)
706 .Case("bf16", HasBFloat16)
707 .Case("sve", FPU & SveMode)
708 .Case("sve-bf16", FPU & SveMode && HasBFloat16)
709 .Case("sve-i8mm", FPU & SveMode && HasMatMul)
710 .Case("f32mm", FPU & SveMode && HasMatmulFP32)
711 .Case("f64mm", FPU & SveMode && HasMatmulFP64)
712 .Case("sve2", FPU & SveMode && HasSVE2)
713 .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
714 .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
715 .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
716 .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
717 .Case("sme", HasSME)
718 .Case("sme2", HasSME2)
719 .Case("sme-f64f64", HasSMEF64F64)
720 .Case("sme-i16i64", HasSMEI16I64)
721 .Case("sme-fa64", HasSMEFA64)
722 .Cases("memtag", "memtag2", HasMTE)
723 .Case("sb", HasSB)
724 .Case("predres", HasPredRes)
725 .Cases("ssbs", "ssbs2", HasSSBS)
726 .Case("bti", HasBTI)
727 .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
728 .Case("wfxt", HasWFxT)
729 .Case("rcpc3", HasRCPC3)
730 .Default(false);
731}
732
733void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
734 StringRef Name, bool Enabled) const {
735 Features[Name] = Enabled;
736 // If the feature is an architecture feature (like v8.2a), add all previous
737 // architecture versions and any dependant target features.
738 const std::optional<llvm::AArch64::ArchInfo> ArchInfo =
739 llvm::AArch64::ArchInfo::findBySubArch(Name);
740
741 if (!ArchInfo)
742 return; // Not an architecture, nothing more to do.
743
744 // Disabling an architecture feature does not affect dependent features
745 if (!Enabled)
746 return;
747
748 for (const auto *OtherArch : llvm::AArch64::ArchInfos)
749 if (ArchInfo->implies(*OtherArch))
750 Features[OtherArch->getSubArch()] = true;
751
752 // Set any features implied by the architecture
753 std::vector<StringRef> CPUFeats;
754 if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) {
755 for (auto F : CPUFeats) {
756 assert(F[0] == '+' && "Expected + in target feature!");
757 Features[F.drop_front(1)] = true;
758 }
759 }
760}
761
762bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
763 DiagnosticsEngine &Diags) {
764 for (const auto &Feature : Features) {
765 if (Feature == "-fp-armv8")
766 HasNoFP = true;
767 if (Feature == "-neon")
768 HasNoNeon = true;
769 if (Feature == "-sve")
770 HasNoSVE = true;
771
772 if (Feature == "+neon" || Feature == "+fp-armv8")
773 FPU |= NeonMode;
774 if (Feature == "+jscvt") {
775 HasJSCVT = true;
776 FPU |= NeonMode;
777 }
778 if (Feature == "+fcma") {
779 HasFCMA = true;
780 FPU |= NeonMode;
781 }
782
783 if (Feature == "+sve") {
784 FPU |= NeonMode;
785 FPU |= SveMode;
786 HasFullFP16 = true;
787 }
788 if (Feature == "+sve2") {
789 FPU |= NeonMode;
790 FPU |= SveMode;
791 HasFullFP16 = true;
792 HasSVE2 = true;
793 }
794 if (Feature == "+sve2-aes") {
795 FPU |= NeonMode;
796 FPU |= SveMode;
797 HasFullFP16 = true;
798 HasSVE2 = true;
799 HasSVE2AES = true;
800 }
801 if (Feature == "+sve2-sha3") {
802 FPU |= NeonMode;
803 FPU |= SveMode;
804 HasFullFP16 = true;
805 HasSVE2 = true;
806 HasSVE2SHA3 = true;
807 }
808 if (Feature == "+sve2-sm4") {
809 FPU |= NeonMode;
810 FPU |= SveMode;
811 HasFullFP16 = true;
812 HasSVE2 = true;
813 HasSVE2SM4 = true;
814 }
815 if (Feature == "+sve2-bitperm") {
816 FPU |= NeonMode;
817 FPU |= SveMode;
818 HasFullFP16 = true;
819 HasSVE2 = true;
820 HasSVE2BitPerm = true;
821 }
822 if (Feature == "+f32mm") {
823 FPU |= NeonMode;
824 FPU |= SveMode;
825 HasFullFP16 = true;
826 HasMatmulFP32 = true;
827 }
828 if (Feature == "+f64mm") {
829 FPU |= NeonMode;
830 FPU |= SveMode;
831 HasFullFP16 = true;
832 HasMatmulFP64 = true;
833 }
834 if (Feature == "+sme") {
835 HasSME = true;
836 HasBFloat16 = true;
837 HasFullFP16 = true;
838 }
839 if (Feature == "+sme2") {
840 HasSME = true;
841 HasSME2 = true;
842 HasBFloat16 = true;
843 HasFullFP16 = true;
844 }
845 if (Feature == "+sme-f64f64") {
846 HasSME = true;
847 HasSMEF64F64 = true;
848 HasBFloat16 = true;
849 HasFullFP16 = true;
850 }
851 if (Feature == "+sme-i16i64") {
852 HasSME = true;
853 HasSMEI16I64 = true;
854 HasBFloat16 = true;
855 HasFullFP16 = true;
856 }
857 if (Feature == "+sme-fa64") {
858 FPU |= NeonMode;
859 FPU |= SveMode;
860 HasSME = true;
861 HasSVE2 = true;
862 HasSMEFA64 = true;
863 }
864 if (Feature == "+sb")
865 HasSB = true;
866 if (Feature == "+predres")
867 HasPredRes = true;
868 if (Feature == "+ssbs")
869 HasSSBS = true;
870 if (Feature == "+bti")
871 HasBTI = true;
872 if (Feature == "+wfxt")
873 HasWFxT = true;
874 if (Feature == "-fmv")
875 HasFMV = false;
876 if (Feature == "+crc")
877 HasCRC = true;
878 if (Feature == "+rcpc")
879 HasRCPC = true;
880 if (Feature == "+aes") {
881 FPU |= NeonMode;
882 HasAES = true;
883 }
884 if (Feature == "+sha2") {
885 FPU |= NeonMode;
886 HasSHA2 = true;
887 }
888 if (Feature == "+sha3") {
889 FPU |= NeonMode;
890 HasSHA2 = true;
891 HasSHA3 = true;
892 }
893 if (Feature == "+rdm") {
894 FPU |= NeonMode;
895 HasRDM = true;
896 }
897 if (Feature == "+dit")
898 HasDIT = true;
899 if (Feature == "+cccp")
900 HasCCPP = true;
901 if (Feature == "+ccdp") {
902 HasCCPP = true;
903 HasCCDP = true;
904 }
905 if (Feature == "+fptoint")
906 HasFRInt3264 = true;
907 if (Feature == "+sm4") {
908 FPU |= NeonMode;
909 HasSM4 = true;
910 }
911 if (Feature == "+strict-align")
912 HasUnaligned = false;
913 // All predecessor archs are added but select the latest one for ArchKind.
914 if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version)
915 ArchInfo = &llvm::AArch64::ARMV8A;
916 if (Feature == "+v8.1a" &&
917 ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version)
918 ArchInfo = &llvm::AArch64::ARMV8_1A;
919 if (Feature == "+v8.2a" &&
920 ArchInfo->Version < llvm::AArch64::ARMV8_2A.Version)
921 ArchInfo = &llvm::AArch64::ARMV8_2A;
922 if (Feature == "+v8.3a" &&
923 ArchInfo->Version < llvm::AArch64::ARMV8_3A.Version)
924 ArchInfo = &llvm::AArch64::ARMV8_3A;
925 if (Feature == "+v8.4a" &&
926 ArchInfo->Version < llvm::AArch64::ARMV8_4A.Version)
927 ArchInfo = &llvm::AArch64::ARMV8_4A;
928 if (Feature == "+v8.5a" &&
929 ArchInfo->Version < llvm::AArch64::ARMV8_5A.Version)
930 ArchInfo = &llvm::AArch64::ARMV8_5A;
931 if (Feature == "+v8.6a" &&
932 ArchInfo->Version < llvm::AArch64::ARMV8_6A.Version)
933 ArchInfo = &llvm::AArch64::ARMV8_6A;
934 if (Feature == "+v8.7a" &&
935 ArchInfo->Version < llvm::AArch64::ARMV8_7A.Version)
936 ArchInfo = &llvm::AArch64::ARMV8_7A;
937 if (Feature == "+v8.8a" &&
938 ArchInfo->Version < llvm::AArch64::ARMV8_8A.Version)
939 ArchInfo = &llvm::AArch64::ARMV8_8A;
940 if (Feature == "+v8.9a" &&
941 ArchInfo->Version < llvm::AArch64::ARMV8_9A.Version)
942 ArchInfo = &llvm::AArch64::ARMV8_9A;
943 if (Feature == "+v9a" && ArchInfo->Version < llvm::AArch64::ARMV9A.Version)
944 ArchInfo = &llvm::AArch64::ARMV9A;
945 if (Feature == "+v9.1a" &&
946 ArchInfo->Version < llvm::AArch64::ARMV9_1A.Version)
947 ArchInfo = &llvm::AArch64::ARMV9_1A;
948 if (Feature == "+v9.2a" &&
949 ArchInfo->Version < llvm::AArch64::ARMV9_2A.Version)
950 ArchInfo = &llvm::AArch64::ARMV9_2A;
951 if (Feature == "+v9.3a" &&
952 ArchInfo->Version < llvm::AArch64::ARMV9_3A.Version)
953 ArchInfo = &llvm::AArch64::ARMV9_3A;
954 if (Feature == "+v9.4a" &&
955 ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
956 ArchInfo = &llvm::AArch64::ARMV9_4A;
957 if (Feature == "+v9.5a" &&
958 ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
959 ArchInfo = &llvm::AArch64::ARMV9_5A;
960 if (Feature == "+v8r")
961 ArchInfo = &llvm::AArch64::ARMV8R;
962 if (Feature == "+fullfp16") {
963 FPU |= NeonMode;
964 HasFullFP16 = true;
965 }
966 if (Feature == "+dotprod") {
967 FPU |= NeonMode;
968 HasDotProd = true;
969 }
970 if (Feature == "+fp16fml") {
971 FPU |= NeonMode;
972 HasFullFP16 = true;
973 HasFP16FML = true;
974 }
975 if (Feature == "+mte")
976 HasMTE = true;
977 if (Feature == "+tme")
978 HasTME = true;
979 if (Feature == "+pauth")
980 HasPAuth = true;
981 if (Feature == "+i8mm")
982 HasMatMul = true;
983 if (Feature == "+bf16")
984 HasBFloat16 = true;
985 if (Feature == "+lse")
986 HasLSE = true;
987 if (Feature == "+ls64")
988 HasLS64 = true;
989 if (Feature == "+rand")
990 HasRandGen = true;
991 if (Feature == "+flagm")
992 HasFlagM = true;
993 if (Feature == "+altnzcv") {
994 HasFlagM = true;
995 HasAlternativeNZCV = true;
996 }
997 if (Feature == "+mops")
998 HasMOPS = true;
999 if (Feature == "+d128")
1000 HasD128 = true;
1001 if (Feature == "+gcs")
1002 HasGCS = true;
1003 if (Feature == "+rcpc3")
1004 HasRCPC3 = true;
1005 if (Feature == "+pauth-lr") {
1006 HasPAuthLR = true;
1007 HasPAuth = true;
1008 }
1009 }
1010
1011 // Check features that are manually disabled by command line options.
1012 // This needs to be checked after architecture-related features are handled,
1013 // making sure they are properly disabled when required.
1014 for (const auto &Feature : Features) {
1015 if (Feature == "-d128")
1016 HasD128 = false;
1017 }
1018
1019 setDataLayout();
1021
1022 if (HasNoFP) {
1023 FPU &= ~FPUMode;
1024 FPU &= ~NeonMode;
1025 FPU &= ~SveMode;
1026 }
1027 if (HasNoNeon) {
1028 FPU &= ~NeonMode;
1029 FPU &= ~SveMode;
1030 }
1031 if (HasNoSVE)
1032 FPU &= ~SveMode;
1033
1034 return true;
1035}
1036
1038 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1039 const std::vector<std::string> &FeaturesVec) const {
1040 std::vector<std::string> UpdatedFeaturesVec;
1041 // Parse the CPU and add any implied features.
1042 std::optional<llvm::AArch64::CpuInfo> CpuInfo = llvm::AArch64::parseCpu(CPU);
1043 if (CpuInfo) {
1044 auto Exts = CpuInfo->getImpliedExtensions();
1045 std::vector<StringRef> CPUFeats;
1046 llvm::AArch64::getExtensionFeatures(Exts, CPUFeats);
1047 for (auto F : CPUFeats) {
1048 assert((F[0] == '+' || F[0] == '-') && "Expected +/- in target feature!");
1049 UpdatedFeaturesVec.push_back(F.str());
1050 }
1051 }
1052
1053 // Process target and dependent features. This is done in two loops collecting
1054 // them into UpdatedFeaturesVec: first to add dependent '+'features, second to
1055 // add target '+/-'features that can later disable some of features added on
1056 // the first loop. Function Multi Versioning features begin with '?'.
1057 for (const auto &Feature : FeaturesVec)
1058 if (((Feature[0] == '?' || Feature[0] == '+')) &&
1060 StringRef DepFeatures =
1062 SmallVector<StringRef, 1> AttrFeatures;
1063 DepFeatures.split(AttrFeatures, ",");
1064 for (auto F : AttrFeatures)
1065 UpdatedFeaturesVec.push_back(F.str());
1066 }
1067 for (const auto &Feature : FeaturesVec)
1068 if (Feature[0] != '?') {
1069 std::string UpdatedFeature = Feature;
1070 if (Feature[0] == '+') {
1071 std::optional<llvm::AArch64::ExtensionInfo> Extension =
1072 llvm::AArch64::parseArchExtension(Feature.substr(1));
1073 if (Extension)
1074 UpdatedFeature = Extension->Feature.str();
1075 }
1076 UpdatedFeaturesVec.push_back(UpdatedFeature);
1077 }
1078
1079 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
1080}
1081
1082// Parse AArch64 Target attributes, which are a comma separated list of:
1083// "arch=<arch>" - parsed to features as per -march=..
1084// "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
1085// "tune=<cpu>" - TuneCPU set to <cpu>
1086// "feature", "no-feature" - Add (or remove) feature.
1087// "+feature", "+nofeature" - Add (or remove) feature.
1089 ParsedTargetAttr Ret;
1090 if (Features == "default")
1091 return Ret;
1092 SmallVector<StringRef, 1> AttrFeatures;
1093 Features.split(AttrFeatures, ",");
1094 bool FoundArch = false;
1095
1096 auto SplitAndAddFeatures = [](StringRef FeatString,
1097 std::vector<std::string> &Features) {
1098 SmallVector<StringRef, 8> SplitFeatures;
1099 FeatString.split(SplitFeatures, StringRef("+"), -1, false);
1100 for (StringRef Feature : SplitFeatures) {
1101 StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
1102 if (!FeatureName.empty())
1103 Features.push_back(FeatureName.str());
1104 else
1105 // Pushing the original feature string to give a sema error later on
1106 // when they get checked.
1107 if (Feature.starts_with("no"))
1108 Features.push_back("-" + Feature.drop_front(2).str());
1109 else
1110 Features.push_back("+" + Feature.str());
1111 }
1112 };
1113
1114 for (auto &Feature : AttrFeatures) {
1115 Feature = Feature.trim();
1116 if (Feature.starts_with("fpmath="))
1117 continue;
1118
1119 if (Feature.starts_with("branch-protection=")) {
1120 Ret.BranchProtection = Feature.split('=').second.trim();
1121 continue;
1122 }
1123
1124 if (Feature.starts_with("arch=")) {
1125 if (FoundArch)
1126 Ret.Duplicate = "arch=";
1127 FoundArch = true;
1128 std::pair<StringRef, StringRef> Split =
1129 Feature.split("=").second.trim().split("+");
1130 const llvm::AArch64::ArchInfo *AI = llvm::AArch64::parseArch(Split.first);
1131
1132 // Parse the architecture version, adding the required features to
1133 // Ret.Features.
1134 if (!AI)
1135 continue;
1136 Ret.Features.push_back(AI->ArchFeature.str());
1137 // Add any extra features, after the +
1138 SplitAndAddFeatures(Split.second, Ret.Features);
1139 } else if (Feature.starts_with("cpu=")) {
1140 if (!Ret.CPU.empty())
1141 Ret.Duplicate = "cpu=";
1142 else {
1143 // Split the cpu string into "cpu=", "cortex-a710" and any remaining
1144 // "+feat" features.
1145 std::pair<StringRef, StringRef> Split =
1146 Feature.split("=").second.trim().split("+");
1147 Ret.CPU = Split.first;
1148 SplitAndAddFeatures(Split.second, Ret.Features);
1149 }
1150 } else if (Feature.starts_with("tune=")) {
1151 if (!Ret.Tune.empty())
1152 Ret.Duplicate = "tune=";
1153 else
1154 Ret.Tune = Feature.split("=").second.trim();
1155 } else if (Feature.starts_with("+")) {
1156 SplitAndAddFeatures(Feature, Ret.Features);
1157 } else if (Feature.starts_with("no-")) {
1158 StringRef FeatureName =
1159 llvm::AArch64::getArchExtFeature(Feature.split("-").second);
1160 if (!FeatureName.empty())
1161 Ret.Features.push_back("-" + FeatureName.drop_front(1).str());
1162 else
1163 Ret.Features.push_back("-" + Feature.split("-").second.str());
1164 } else {
1165 // Try parsing the string to the internal target feature name. If it is
1166 // invalid, add the original string (which could already be an internal
1167 // name). These should be checked later by isValidFeatureName.
1168 StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature);
1169 if (!FeatureName.empty())
1170 Ret.Features.push_back(FeatureName.str());
1171 else
1172 Ret.Features.push_back("+" + Feature.str());
1173 }
1174 }
1175 return Ret;
1176}
1177
1179 return true;
1180}
1181
1184 switch (CC) {
1185 case CC_C:
1186 case CC_Swift:
1187 case CC_SwiftAsync:
1188 case CC_PreserveMost:
1189 case CC_PreserveAll:
1190 case CC_OpenCLKernel:
1192 case CC_AArch64SVEPCS:
1193 case CC_Win64:
1194 return CCCR_OK;
1195 default:
1196 return CCCR_Warning;
1197 }
1198}
1199
1200bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
1201
1204}
1205
1206const char *const AArch64TargetInfo::GCCRegNames[] = {
1207 // clang-format off
1208
1209 // 32-bit Integer registers
1210 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
1211 "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
1212 "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
1213
1214 // 64-bit Integer registers
1215 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
1216 "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
1217 "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
1218
1219 // 32-bit floating point regsisters
1220 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
1221 "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
1222 "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1223
1224 // 64-bit floating point regsisters
1225 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
1226 "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
1227 "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
1228
1229 // Neon vector registers
1230 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
1231 "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
1232 "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1233
1234 // SVE vector registers
1235 "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10",
1236 "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
1237 "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
1238
1239 // SVE predicate registers
1240 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10",
1241 "p11", "p12", "p13", "p14", "p15",
1242
1243 // SVE predicate-as-counter registers
1244 "pn0", "pn1", "pn2", "pn3", "pn4", "pn5", "pn6", "pn7", "pn8",
1245 "pn9", "pn10", "pn11", "pn12", "pn13", "pn14", "pn15",
1246
1247 // SME registers
1248 "za", "zt0",
1249
1250 // clang-format on
1251};
1252
1254 return llvm::ArrayRef(GCCRegNames);
1255}
1256
1257const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
1258 {{"w31"}, "wsp"},
1259 {{"x31"}, "sp"},
1260 // GCC rN registers are aliases of xN registers.
1261 {{"r0"}, "x0"},
1262 {{"r1"}, "x1"},
1263 {{"r2"}, "x2"},
1264 {{"r3"}, "x3"},
1265 {{"r4"}, "x4"},
1266 {{"r5"}, "x5"},
1267 {{"r6"}, "x6"},
1268 {{"r7"}, "x7"},
1269 {{"r8"}, "x8"},
1270 {{"r9"}, "x9"},
1271 {{"r10"}, "x10"},
1272 {{"r11"}, "x11"},
1273 {{"r12"}, "x12"},
1274 {{"r13"}, "x13"},
1275 {{"r14"}, "x14"},
1276 {{"r15"}, "x15"},
1277 {{"r16"}, "x16"},
1278 {{"r17"}, "x17"},
1279 {{"r18"}, "x18"},
1280 {{"r19"}, "x19"},
1281 {{"r20"}, "x20"},
1282 {{"r21"}, "x21"},
1283 {{"r22"}, "x22"},
1284 {{"r23"}, "x23"},
1285 {{"r24"}, "x24"},
1286 {{"r25"}, "x25"},
1287 {{"r26"}, "x26"},
1288 {{"r27"}, "x27"},
1289 {{"r28"}, "x28"},
1290 {{"r29", "x29"}, "fp"},
1291 {{"r30", "x30"}, "lr"},
1292 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
1293 // don't want to substitute one of these for a different-sized one.
1294};
1295
1297 return llvm::ArrayRef(GCCRegAliases);
1298}
1299
1300// Returns the length of cc constraint.
1301static unsigned matchAsmCCConstraint(const char *Name) {
1302 constexpr unsigned len = 5;
1303 auto RV = llvm::StringSwitch<unsigned>(Name)
1304 .Case("@cceq", len)
1305 .Case("@ccne", len)
1306 .Case("@cchs", len)
1307 .Case("@cccs", len)
1308 .Case("@cccc", len)
1309 .Case("@cclo", len)
1310 .Case("@ccmi", len)
1311 .Case("@ccpl", len)
1312 .Case("@ccvs", len)
1313 .Case("@ccvc", len)
1314 .Case("@cchi", len)
1315 .Case("@ccls", len)
1316 .Case("@ccge", len)
1317 .Case("@cclt", len)
1318 .Case("@ccgt", len)
1319 .Case("@ccle", len)
1320 .Default(0);
1321 return RV;
1322}
1323
1324std::string
1325AArch64TargetInfo::convertConstraint(const char *&Constraint) const {
1326 std::string R;
1327 switch (*Constraint) {
1328 case 'U': // Three-character constraint; add "@3" hint for later parsing.
1329 R = std::string("@3") + std::string(Constraint, 3);
1330 Constraint += 2;
1331 break;
1332 case '@':
1333 if (const unsigned Len = matchAsmCCConstraint(Constraint)) {
1334 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1335 Constraint += Len - 1;
1336 return Converted;
1337 }
1338 return std::string(1, *Constraint);
1339 default:
1340 R = TargetInfo::convertConstraint(Constraint);
1341 break;
1342 }
1343 return R;
1344}
1345
1347 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1348 switch (*Name) {
1349 default:
1350 return false;
1351 case 'w': // Floating point and SIMD registers (V0-V31)
1352 Info.setAllowsRegister();
1353 return true;
1354 case 'I': // Constant that can be used with an ADD instruction
1355 case 'J': // Constant that can be used with a SUB instruction
1356 case 'K': // Constant that can be used with a 32-bit logical instruction
1357 case 'L': // Constant that can be used with a 64-bit logical instruction
1358 case 'M': // Constant that can be used as a 32-bit MOV immediate
1359 case 'N': // Constant that can be used as a 64-bit MOV immediate
1360 case 'Y': // Floating point constant zero
1361 case 'Z': // Integer constant zero
1362 return true;
1363 case 'Q': // A memory reference with base register and no offset
1364 Info.setAllowsMemory();
1365 return true;
1366 case 'S': // A symbolic address
1367 Info.setAllowsRegister();
1368 return true;
1369 case 'U':
1370 if (Name[1] == 'p' &&
1371 (Name[2] == 'l' || Name[2] == 'a' || Name[2] == 'h')) {
1372 // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7, "Uph"=P8-P15)
1373 Info.setAllowsRegister();
1374 Name += 2;
1375 return true;
1376 }
1377 if (Name[1] == 'c' && (Name[2] == 'i' || Name[2] == 'j')) {
1378 // Gpr registers ("Uci"=w8-11, "Ucj"=w12-15)
1379 Info.setAllowsRegister();
1380 Name += 2;
1381 return true;
1382 }
1383 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
1384 // Utf: A memory address suitable for ldp/stp in TF mode.
1385 // Usa: An absolute symbolic address.
1386 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
1387
1388 // Better to return an error saying that it's an unrecognised constraint
1389 // even if this is a valid constraint in gcc.
1390 return false;
1391 case 'z': // Zero register, wzr or xzr
1392 Info.setAllowsRegister();
1393 return true;
1394 case 'x': // Floating point and SIMD registers (V0-V15)
1395 Info.setAllowsRegister();
1396 return true;
1397 case 'y': // SVE registers (V0-V7)
1398 Info.setAllowsRegister();
1399 return true;
1400 case '@':
1401 // CC condition
1402 if (const unsigned Len = matchAsmCCConstraint(Name)) {
1403 Name += Len - 1;
1404 Info.setAllowsRegister();
1405 return true;
1406 }
1407 }
1408 return false;
1409}
1410
1412 StringRef Constraint, char Modifier, unsigned Size,
1413 std::string &SuggestedModifier) const {
1414 // Strip off constraint modifiers.
1415 Constraint = Constraint.ltrim("=+&");
1416
1417 switch (Constraint[0]) {
1418 default:
1419 return true;
1420 case 'z':
1421 case 'r': {
1422 switch (Modifier) {
1423 case 'x':
1424 case 'w':
1425 // For now assume that the person knows what they're
1426 // doing with the modifier.
1427 return true;
1428 default:
1429 // By default an 'r' constraint will be in the 'x'
1430 // registers.
1431 if (Size == 64)
1432 return true;
1433
1434 if (Size == 512)
1435 return HasLS64;
1436
1437 SuggestedModifier = "w";
1438 return false;
1439 }
1440 }
1441 }
1442}
1443
1444std::string_view AArch64TargetInfo::getClobbers() const { return ""; }
1445
1447 if (RegNo == 0)
1448 return 0;
1449 if (RegNo == 1)
1450 return 1;
1451 return -1;
1452}
1453
1455 const llvm::APSInt &value) const {
1456 return 0 <= value && value <= 3;
1457}
1458
1459bool AArch64TargetInfo::hasInt128Type() const { return true; }
1460
1462 const TargetOptions &Opts)
1463 : AArch64TargetInfo(Triple, Opts) {}
1464
1465void AArch64leTargetInfo::setDataLayout() {
1466 if (getTriple().isOSBinFormatMachO()) {
1467 if(getTriple().isArch32Bit())
1468 resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
1469 else
1470 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
1471 } else
1472 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
1473}
1474
1476 MacroBuilder &Builder) const {
1477 Builder.defineMacro("__AARCH64EL__");
1479}
1480
1482 const TargetOptions &Opts)
1483 : AArch64TargetInfo(Triple, Opts) {}
1484
1486 MacroBuilder &Builder) const {
1487 Builder.defineMacro("__AARCH64EB__");
1488 Builder.defineMacro("__AARCH_BIG_ENDIAN");
1489 Builder.defineMacro("__ARM_BIG_ENDIAN");
1491}
1492
1493void AArch64beTargetInfo::setDataLayout() {
1494 assert(!getTriple().isOSBinFormatMachO());
1495 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
1496}
1497
1499 const TargetOptions &Opts)
1500 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
1501
1502 // This is an LLP64 platform.
1503 // int:4, long:4, long long:8, long double:8.
1504 IntWidth = IntAlign = 32;
1505 LongWidth = LongAlign = 32;
1506 DoubleAlign = LongLongAlign = 64;
1507 LongDoubleWidth = LongDoubleAlign = 64;
1508 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1509 IntMaxType = SignedLongLong;
1510 Int64Type = SignedLongLong;
1511 SizeType = UnsignedLongLong;
1512 PtrDiffType = SignedLongLong;
1513 IntPtrType = SignedLongLong;
1514}
1515
1517 resetDataLayout(Triple.isOSBinFormatMachO()
1518 ? "e-m:o-i64:64-i128:128-n32:64-S128"
1519 : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128",
1520 Triple.isOSBinFormatMachO() ? "_" : "");
1521}
1522
1526}
1527
1530 switch (CC) {
1531 case CC_X86StdCall:
1532 case CC_X86ThisCall:
1533 case CC_X86FastCall:
1534 case CC_X86VectorCall:
1535 return CCCR_Ignore;
1536 case CC_C:
1537 case CC_OpenCLKernel:
1538 case CC_PreserveMost:
1539 case CC_PreserveAll:
1540 case CC_Swift:
1541 case CC_SwiftAsync:
1542 case CC_Win64:
1543 return CCCR_OK;
1544 default:
1545 return CCCR_Warning;
1546 }
1547}
1548
1550 const TargetOptions &Opts)
1551 : WindowsARM64TargetInfo(Triple, Opts) {
1552 TheCXXABI.set(TargetCXXABI::Microsoft);
1553}
1554
1556 MacroBuilder &Builder) const {
1558 if (getTriple().isWindowsArm64EC()) {
1559 Builder.defineMacro("_M_X64", "100");
1560 Builder.defineMacro("_M_AMD64", "100");
1561 Builder.defineMacro("_M_ARM64EC", "1");
1562 } else {
1563 Builder.defineMacro("_M_ARM64", "1");
1564 }
1565}
1566
1569 return CCK_MicrosoftWin64;
1570}
1571
1573 bool HasNonWeakDef) const {
1574 unsigned Align =
1575 WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef);
1576
1577 // MSVC does size based alignment for arm64 based on alignment section in
1578 // below document, replicate that to keep alignment consistent with object
1579 // files compiled by MSVC.
1580 // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
1581 if (TypeSize >= 512) { // TypeSize >= 64 bytes
1582 Align = std::max(Align, 128u); // align type at least 16 bytes
1583 } else if (TypeSize >= 64) { // TypeSize >= 8 bytes
1584 Align = std::max(Align, 64u); // align type at least 8 butes
1585 } else if (TypeSize >= 16) { // TypeSize >= 2 bytes
1586 Align = std::max(Align, 32u); // align type at least 4 bytes
1587 }
1588 return Align;
1589}
1590
1592 const TargetOptions &Opts)
1593 : WindowsARM64TargetInfo(Triple, Opts) {
1594 TheCXXABI.set(TargetCXXABI::GenericAArch64);
1595}
1596
1598 const TargetOptions &Opts)
1599 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1600 Int64Type = SignedLongLong;
1601 if (getTriple().isArch32Bit())
1602 IntMaxType = SignedLongLong;
1603
1604 WCharType = SignedInt;
1605 UseSignedCharForObjCBool = false;
1606
1607 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
1608 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1609
1610 UseZeroLengthBitfieldAlignment = false;
1611
1612 if (getTriple().isArch32Bit()) {
1613 UseBitFieldTypeAlignment = false;
1614 ZeroLengthBitfieldBoundary = 32;
1615 UseZeroLengthBitfieldAlignment = true;
1616 TheCXXABI.set(TargetCXXABI::WatchOS);
1617 } else
1618 TheCXXABI.set(TargetCXXABI::AppleARM64);
1619}
1620
1622 const llvm::Triple &Triple,
1623 MacroBuilder &Builder) const {
1624 Builder.defineMacro("__AARCH64_SIMD__");
1625 if (Triple.isArch32Bit())
1626 Builder.defineMacro("__ARM64_ARCH_8_32__");
1627 else
1628 Builder.defineMacro("__ARM64_ARCH_8__");
1629 Builder.defineMacro("__ARM_NEON__");
1630 Builder.defineMacro("__REGISTER_PREFIX__", "");
1631 Builder.defineMacro("__arm64", "1");
1632 Builder.defineMacro("__arm64__", "1");
1633
1634 if (Triple.isArm64e())
1635 Builder.defineMacro("__arm64e__", "1");
1636
1637 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1638}
1639
1643}
1644
1645// 64-bit RenderScript is aarch64
1647 const TargetOptions &Opts)
1648 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
1649 Triple.getOSName(),
1650 Triple.getEnvironmentName()),
1651 Opts) {
1652 IsRenderScriptTarget = true;
1653}
1654
1656 MacroBuilder &Builder) const {
1657 Builder.defineMacro("__RENDERSCRIPT__");
1659}
static unsigned matchAsmCCConstraint(const char *Name)
Definition: AArch64.cpp:1301
static constexpr Builtin::Info BuiltinInfo[]
Definition: AArch64.cpp:28
static constexpr Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:32
Defines the clang::LangOptions interface.
Enumerates target-specific builtins in their own namespaces within namespace clang.
__device__ __2f16 float c
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:192
@ NonLeaf
Sign the return address of functions that spill LR.
@ All
Sign the return address of all functions,.
@ BKey
Return address signing uses APIB key.
@ AKey
Return address signing uses APIA key.
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:418
bool isSignReturnAddressWithAKey() const
Check if return address signing uses AKey.
Definition: LangOptions.h:640
bool hasSignReturnAddress() const
Check if return address signing is enabled.
Definition: LangOptions.h:635
bool isSignReturnAddressScopeAll() const
Check if leaf functions are also signed.
Definition: LangOptions.h:645
void set(Kind kind)
Definition: TargetCXXABI.h:76
Exposes information about the current target.
Definition: TargetInfo.h:213
TargetOptions & getTargetOpts() const
Retrieve the target options.
Definition: TargetInfo.h:304
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:1220
unsigned HasAArch64SVETypes
Definition: TargetInfo.h:262
void resetDataLayout(StringRef DL, const char *UserLabelPrefix="")
Definition: TargetInfo.cpp:189
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:311
@ AArch64ABIBuiltinVaList
__builtin_va_list as defined by the AArch64 ABI http://infocenter.arm.com/help/topic/com....
Definition: TargetInfo.h:320
@ CharPtrBuiltinVaList
typedef char* __builtin_va_list;
Definition: TargetInfo.h:313
const char * MCountName
Definition: TargetInfo.h:240
unsigned IsRenderScriptTarget
Definition: TargetInfo.h:259
unsigned char MaxAtomicPromoteWidth
Definition: TargetInfo.h:237
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:521
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:1197
unsigned char MaxAtomicInlineWidth
Definition: TargetInfo.h:237
TargetCXXABI TheCXXABI
Definition: TargetInfo.h:242
unsigned HasBuiltinMSVaList
Definition: TargetInfo.h:256
Options for controlling the target.
Definition: TargetOptions.h:26
llvm::EABI EABIVersion
The EABI version to use.
Definition: TargetOptions.h:48
void getTargetDefinesARMV95A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:338
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: AArch64.cpp:645
std::string_view getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: AArch64.cpp:1444
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: AArch64.cpp:680
std::string convertConstraint(const char *&Constraint) const override
Definition: AArch64.cpp:1325
ArrayRef< TargetInfo::GCCRegAlias > getGCCRegAliases() const override
Definition: AArch64.cpp:1296
bool hasBFloat16Type() const override
Determine whether the _BFloat16 type is supported on this target.
Definition: AArch64.cpp:1178
ParsedTargetAttr parseTargetAttr(StringRef Str) const override
Definition: AArch64.cpp:1088
AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:131
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: AArch64.cpp:1037
unsigned multiVersionFeatureCost() const override
Definition: AArch64.cpp:653
ArrayRef< const char * > getGCCRegNames() const override
Definition: AArch64.cpp:1253
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
Perform initialization based on the user configured set of features (e.g., +sse4).
Definition: AArch64.cpp:762
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:344
void setFeatureEnabled(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled) const override
Enable or disable a specific target feature; the feature name must be valid.
Definition: AArch64.cpp:733
void getTargetDefinesARMV89A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:302
void getTargetDefinesARMV92A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:320
StringRef getFeatureDependencies(StringRef Name) const override
For given feature return dependent ones.
Definition: AArch64.cpp:664
void getTargetDefinesARMV93A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:326
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: AArch64.cpp:202
void getTargetDefinesARMV84A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:266
bool isValidCPUName(StringRef Name) const override
Determine whether this TargetInfo supports the given CPU name.
Definition: AArch64.cpp:234
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: AArch64.cpp:242
StringRef getABI() const override
Get the ABI currently in use.
Definition: AArch64.cpp:200
bool hasInt128Type() const override
Determine whether the __int128 type is supported on this target.
Definition: AArch64.cpp:1459
void getTargetDefinesARMV88A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:296
bool validateBranchProtection(StringRef Spec, StringRef Arch, BranchProtectionInfo &BPI, StringRef &Err) const override
Determine if this TargetInfo supports the given branch protection specification.
Definition: AArch64.cpp:210
void getTargetDefinesARMV87A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:290
void getTargetDefinesARMV9A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:308
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: AArch64.cpp:1183
void getTargetDefinesARMV91A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:314
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: AArch64.cpp:1202
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument.
Definition: AArch64.cpp:1446
void getTargetDefinesARMV81A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:247
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: AArch64.cpp:628
void getTargetDefinesARMV86A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:280
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: AArch64.cpp:238
std::optional< std::pair< unsigned, unsigned > > getVScaleRange(const LangOptions &LangOpts) const override
Returns target-specific min and max values VScale_Range.
Definition: AArch64.cpp:634
void getTargetDefinesARMV94A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:332
bool validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, std::string &SuggestedModifier) const override
Definition: AArch64.cpp:1411
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: AArch64.cpp:1200
void getTargetDefinesARMV82A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:252
void getTargetDefinesARMV83A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:258
bool validateCpuSupports(StringRef FeatureStr) const override
Definition: AArch64.cpp:670
bool validatePointerAuthKey(const llvm::APSInt &value) const override
Determine whether the given pointer-authentication key is valid.
Definition: AArch64.cpp:1454
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: AArch64.cpp:1346
bool doesFeatureAffectCodeGen(StringRef Name) const override
Returns true if feature has an impact on target code generation.
Definition: AArch64.cpp:658
void getTargetDefinesARMV85A(const LangOptions &Opts, MacroBuilder &Builder) const
Definition: AArch64.cpp:272
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1485
AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1481
AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1461
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1475
DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1597
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override
Definition: AArch64.cpp:1621
BuiltinVaListKind getBuiltinVaListKind() const override
Definition: AArch64.cpp:1641
unsigned getMinGlobalAlign(uint64_t TypeSize, bool HasNonWeakDef) const override
Definition: AArch64.cpp:1572
MicrosoftARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1549
TargetInfo::CallingConvKind getCallingConvKind(bool ClangABICompat4) const override
Definition: AArch64.cpp:1568
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
Definition: AArch64.cpp:1555
MinGWARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1591
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
Definition: OSTargets.h:30
RenderScript64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1646
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
===-— Other target property query methods -----------------------—===//
Definition: AArch64.cpp:1655
BuiltinVaListKind getBuiltinVaListKind() const override
Definition: AArch64.cpp:1524
WindowsARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: AArch64.cpp:1498
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Definition: AArch64.cpp:1529
Defines the clang::TargetInfo interface.
void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, const llvm::Triple &Triple, StringRef &PlatformName, VersionTuple &PlatformMinVersion)
Definition: OSTargets.cpp:22
The JSON file list parser is used to communicate input to InstallAPI.
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:275
@ CC_Swift
Definition: Specifiers.h:290
@ CC_OpenCLKernel
Definition: Specifiers.h:289
@ CC_PreserveMost
Definition: Specifiers.h:292
@ CC_Win64
Definition: Specifiers.h:282
@ CC_X86ThisCall
Definition: Specifiers.h:279
@ CC_AArch64VectorCall
Definition: Specifiers.h:294
@ CC_C
Definition: Specifiers.h:276
@ CC_SwiftAsync
Definition: Specifiers.h:291
@ CC_X86VectorCall
Definition: Specifiers.h:280
@ CC_AArch64SVEPCS
Definition: Specifiers.h:295
@ CC_X86StdCall
Definition: Specifiers.h:277
@ CC_PreserveAll
Definition: Specifiers.h:293
@ CC_X86FastCall
Definition: Specifiers.h:278
YAML serialization mapping.
Definition: Dominators.h:30
Contains information gathered from parsing the contents of TargetAttr.
Definition: TargetInfo.h:56
LangOptions::SignReturnAddressScopeKind SignReturnAddr
Definition: TargetInfo.h:1373
LangOptions::SignReturnAddressKeyKind SignKey
Definition: TargetInfo.h:1374
unsigned UseZeroLengthBitfieldAlignment
Whether zero length bitfields (e.g., int : 0;) force alignment of the next bitfield.
Definition: TargetInfo.h:178
const llvm::fltSemantics * LongDoubleFormat
Definition: TargetInfo.h:134
unsigned UseBitFieldTypeAlignment
Control whether the alignment of bit-field types is respected when laying out structures.
Definition: TargetInfo.h:169
const llvm::fltSemantics * BFloat16Format
Definition: TargetInfo.h:133