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riscv_bitmanip.h
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1/*===---- riscv_bitmanip.h - RISC-V Zb* intrinsics --------------------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9
10#ifndef __RISCV_BITMANIP_H
11#define __RISCV_BITMANIP_H
12
13#include <stdint.h>
14
15#if defined(__cplusplus)
16extern "C" {
17#endif
18
19#define __riscv_intrinsic_b 1
20#define __riscv_intrinsic_zbb 1
21#define __riscv_intrinsic_zbc 1
22#define __riscv_intrinsic_zbkb 1
23#define __riscv_intrinsic_zbkc 1
24#define __riscv_intrinsic_zbkx 1
25
26#if defined(__riscv_zbb)
27static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
28__riscv_orc_b_32(uint32_t __x) {
29 return __builtin_riscv_orc_b_32(__x);
30}
31
32static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
33__riscv_clz_32(uint32_t __x) {
34 return __builtin_riscv_clz_32(__x);
35}
36
37static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
38__riscv_ctz_32(uint32_t __x) {
39 return __builtin_riscv_ctz_32(__x);
40}
41
42static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
43__riscv_cpop_32(uint32_t __x) {
44 return __builtin_popcount(__x);
45}
46
47#if __riscv_xlen == 64
48static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
49__riscv_orc_b_64(uint64_t __x) {
50 return __builtin_riscv_orc_b_64(__x);
51}
52
53static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
54__riscv_clz_64(uint64_t __x) {
55 return __builtin_riscv_clz_64(__x);
56}
57
58static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
59__riscv_ctz_64(uint64_t __x) {
60 return __builtin_riscv_ctz_64(__x);
61}
62
63static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
64__riscv_cpop_64(uint64_t __x) {
65 return __builtin_popcountll(__x);
66}
67#endif
68#endif // defined(__riscv_zbb)
69
70#if defined(__riscv_zbb) || defined(__riscv_zbkb)
71static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
72__riscv_rev8_32(uint32_t __x) {
73 return __builtin_bswap32(__x);
74}
75
76static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
77__riscv_rol_32(uint32_t __x, uint32_t __y) {
78 return __builtin_rotateleft32(__x, __y);
79}
80
81static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
82__riscv_ror_32(uint32_t __x, uint32_t __y) {
83 return __builtin_rotateright32(__x, __y);
84}
85
86#if __riscv_xlen == 64
87static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
88__riscv_rev8_64(uint64_t __x) {
89 return __builtin_bswap64(__x);
90}
91
92static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
93__riscv_rol_64(uint64_t __x, uint32_t __y) {
94 return __builtin_rotateleft64(__x, __y);
95}
96
97static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
98__riscv_ror_64(uint64_t __x, uint32_t __y) {
99 return __builtin_rotateright64(__x, __y);
100}
101#endif
102#endif // defined(__riscv_zbb) || defined(__riscv_zbkb)
103
104#if defined(__riscv_zbkb)
105static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
106__riscv_brev8_32(uint32_t __x) {
107 return __builtin_riscv_brev8_32(__x);
108}
109
110#if __riscv_xlen == 64
111static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
112__riscv_brev8_64(uint64_t __x) {
113 return __builtin_riscv_brev8_64(__x);
114}
115#endif
116
117#if __riscv_xlen == 32
118static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
119__riscv_unzip_32(uint32_t __x) {
120 return __builtin_riscv_unzip_32(__x);
121}
122
123static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
124__riscv_zip_32(uint32_t __x) {
125 return __builtin_riscv_zip_32(__x);
126}
127#endif
128#endif // defined(__riscv_zbkb)
129
130#if defined(__riscv_zbc)
131#if __riscv_xlen == 32
132static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
133__riscv_clmulr_32(uint32_t __x, uint32_t __y) {
134 return __builtin_riscv_clmulr_32(__x, __y);
135}
136#endif
137
138#if __riscv_xlen == 64
139static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
140__riscv_clmulr_64(uint64_t __x, uint64_t __y) {
141 return __builtin_riscv_clmulr_64(__x, __y);
142}
143#endif
144#endif // defined(__riscv_zbc)
145
146#if defined(__riscv_zbkc) || defined(__riscv_zbc)
147static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
148__riscv_clmul_32(uint32_t __x, uint32_t __y) {
149 return __builtin_riscv_clmul_32(__x, __y);
150}
151
152#if __riscv_xlen == 32
153static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
154__riscv_clmulh_32(uint32_t __x, uint32_t __y) {
155 return __builtin_riscv_clmulh_32(__x, __y);
156}
157#endif
158
159#if __riscv_xlen == 64
160static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
161__riscv_clmul_64(uint64_t __x, uint64_t __y) {
162 return __builtin_riscv_clmul_64(__x, __y);
163}
164
165static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
166__riscv_clmulh_64(uint64_t __x, uint64_t __y) {
167 return __builtin_riscv_clmulh_64(__x, __y);
168}
169#endif
170#endif // defined(__riscv_zbkc) || defined(__riscv_zbc)
171
172#if defined(__riscv_zbkx)
173#if __riscv_xlen == 32
174static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
175__riscv_xperm4_32(uint32_t __x, uint32_t __y) {
176 return __builtin_riscv_xperm4_32(__x, __y);
177}
178
179static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
180__riscv_xperm8_32(uint32_t __x, uint32_t __y) {
181 return __builtin_riscv_xperm8_32(__x, __y);
182}
183#endif
184
185#if __riscv_xlen == 64
186static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
187__riscv_xperm4_64(uint64_t __x, uint64_t __y) {
188 return __builtin_riscv_xperm4_64(__x, __y);
189}
190
191static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
192__riscv_xperm8_64(uint64_t __x, uint64_t __y) {
193 return __builtin_riscv_xperm8_64(__x, __y);
194}
195#endif
196#endif // defined(__riscv_zbkx)
197
198#if defined(__cplusplus)
199}
200#endif
201
202#endif
_Float16 __2f16 __attribute__((ext_vector_type(2)))
Zeroes the upper 128 bits (bits 255:128) of all YMM registers.
static __inline__ uint32_t uint32_t __y
Definition arm_acle.h:132