clang  7.0.0svn
PPC.h
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1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares PPC TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
16 
17 #include "OSTargets.h"
18 #include "clang/Basic/TargetInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28  static const Builtin::Info BuiltinInfo[];
29  static const char *const GCCRegNames[];
30  static const TargetInfo::GCCRegAlias GCCRegAliases[];
31  std::string CPU;
32 
33  // Target cpu features.
34  bool HasAltivec;
35  bool HasVSX;
36  bool HasP8Vector;
37  bool HasP8Crypto;
38  bool HasDirectMove;
39  bool HasQPX;
40  bool HasHTM;
41  bool HasBPERMD;
42  bool HasExtDiv;
43  bool HasP9Vector;
44 
45 protected:
46  std::string ABI;
47 
48 public:
49  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
50  : TargetInfo(Triple), HasAltivec(false), HasVSX(false),
51  HasP8Vector(false), HasP8Crypto(false), HasDirectMove(false),
52  HasQPX(false), HasHTM(false), HasBPERMD(false), HasExtDiv(false),
53  HasP9Vector(false) {
54  SuitableAlign = 128;
55  SimdDefaultAlign = 128;
56  LongDoubleWidth = LongDoubleAlign = 128;
57  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
58  }
59 
60  /// Flags for architecture specific defines.
61  typedef enum {
62  ArchDefineNone = 0,
63  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
64  ArchDefinePpcgr = 1 << 1,
65  ArchDefinePpcsq = 1 << 2,
66  ArchDefine440 = 1 << 3,
67  ArchDefine603 = 1 << 4,
68  ArchDefine604 = 1 << 5,
69  ArchDefinePwr4 = 1 << 6,
70  ArchDefinePwr5 = 1 << 7,
71  ArchDefinePwr5x = 1 << 8,
72  ArchDefinePwr6 = 1 << 9,
73  ArchDefinePwr6x = 1 << 10,
74  ArchDefinePwr7 = 1 << 11,
75  ArchDefinePwr8 = 1 << 12,
76  ArchDefinePwr9 = 1 << 13,
77  ArchDefineA2 = 1 << 14,
78  ArchDefineA2q = 1 << 15
80 
81  // Set the language option for altivec based on our value.
82  void adjust(LangOptions &Opts) override;
83 
84  // Note: GCC recognizes the following additional cpus:
85  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
86  // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
87  // titan, rs64.
88  bool isValidCPUName(StringRef Name) const override;
89  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
90 
91  bool setCPU(const std::string &Name) override {
92  bool CPUKnown = isValidCPUName(Name);
93  if (CPUKnown)
94  CPU = Name;
95  return CPUKnown;
96  }
97 
98  StringRef getABI() const override { return ABI; }
99 
100  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
101 
102  bool isCLZForZeroUndef() const override { return false; }
103 
104  void getTargetDefines(const LangOptions &Opts,
105  MacroBuilder &Builder) const override;
106 
107  bool
108  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
109  StringRef CPU,
110  const std::vector<std::string> &FeaturesVec) const override;
111 
112  bool handleTargetFeatures(std::vector<std::string> &Features,
113  DiagnosticsEngine &Diags) override;
114 
115  bool hasFeature(StringRef Feature) const override;
116 
117  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
118  bool Enabled) const override;
119 
120  ArrayRef<const char *> getGCCRegNames() const override;
121 
122  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
123 
124  bool validateAsmConstraint(const char *&Name,
125  TargetInfo::ConstraintInfo &Info) const override {
126  switch (*Name) {
127  default:
128  return false;
129  case 'O': // Zero
130  break;
131  case 'b': // Base register
132  case 'f': // Floating point register
133  Info.setAllowsRegister();
134  break;
135  // FIXME: The following are added to allow parsing.
136  // I just took a guess at what the actions should be.
137  // Also, is more specific checking needed? I.e. specific registers?
138  case 'd': // Floating point register (containing 64-bit value)
139  case 'v': // Altivec vector register
140  Info.setAllowsRegister();
141  break;
142  case 'w':
143  switch (Name[1]) {
144  case 'd': // VSX vector register to hold vector double data
145  case 'f': // VSX vector register to hold vector float data
146  case 's': // VSX vector register to hold scalar float data
147  case 'a': // Any VSX register
148  case 'c': // An individual CR bit
149  break;
150  default:
151  return false;
152  }
153  Info.setAllowsRegister();
154  Name++; // Skip over 'w'.
155  break;
156  case 'h': // `MQ', `CTR', or `LINK' register
157  case 'q': // `MQ' register
158  case 'c': // `CTR' register
159  case 'l': // `LINK' register
160  case 'x': // `CR' register (condition register) number 0
161  case 'y': // `CR' register (condition register)
162  case 'z': // `XER[CA]' carry bit (part of the XER register)
163  Info.setAllowsRegister();
164  break;
165  case 'I': // Signed 16-bit constant
166  case 'J': // Unsigned 16-bit constant shifted left 16 bits
167  // (use `L' instead for SImode constants)
168  case 'K': // Unsigned 16-bit constant
169  case 'L': // Signed 16-bit constant shifted left 16 bits
170  case 'M': // Constant larger than 31
171  case 'N': // Exact power of 2
172  case 'P': // Constant whose negation is a signed 16-bit constant
173  case 'G': // Floating point constant that can be loaded into a
174  // register with one instruction per word
175  case 'H': // Integer/Floating point constant that can be loaded
176  // into a register using three instructions
177  break;
178  case 'm': // Memory operand. Note that on PowerPC targets, m can
179  // include addresses that update the base register. It
180  // is therefore only safe to use `m' in an asm statement
181  // if that asm statement accesses the operand exactly once.
182  // The asm statement must also use `%U<opno>' as a
183  // placeholder for the "update" flag in the corresponding
184  // load or store instruction. For example:
185  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
186  // is correct but:
187  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
188  // is not. Use es rather than m if you don't want the base
189  // register to be updated.
190  case 'e':
191  if (Name[1] != 's')
192  return false;
193  // es: A "stable" memory operand; that is, one which does not
194  // include any automodification of the base register. Unlike
195  // `m', this constraint can be used in asm statements that
196  // might access the operand several times, or that might not
197  // access it at all.
198  Info.setAllowsMemory();
199  Name++; // Skip over 'e'.
200  break;
201  case 'Q': // Memory operand that is an offset from a register (it is
202  // usually better to use `m' or `es' in asm statements)
203  case 'Z': // Memory operand that is an indexed or indirect from a
204  // register (it is usually better to use `m' or `es' in
205  // asm statements)
206  Info.setAllowsMemory();
207  Info.setAllowsRegister();
208  break;
209  case 'R': // AIX TOC entry
210  case 'a': // Address operand that is an indexed or indirect from a
211  // register (`p' is preferable for asm statements)
212  case 'S': // Constant suitable as a 64-bit mask operand
213  case 'T': // Constant suitable as a 32-bit mask operand
214  case 'U': // System V Release 4 small data area reference
215  case 't': // AND masks that can be performed by two rldic{l, r}
216  // instructions
217  case 'W': // Vector constant that does not require memory
218  case 'j': // Vector constant that is all zeros.
219  break;
220  // End FIXME.
221  }
222  return true;
223  }
224 
225  std::string convertConstraint(const char *&Constraint) const override {
226  std::string R;
227  switch (*Constraint) {
228  case 'e':
229  case 'w':
230  // Two-character constraint; add "^" hint for later parsing.
231  R = std::string("^") + std::string(Constraint, 2);
232  Constraint++;
233  break;
234  default:
235  return TargetInfo::convertConstraint(Constraint);
236  }
237  return R;
238  }
239 
240  const char *getClobbers() const override { return ""; }
241  int getEHDataRegisterNumber(unsigned RegNo) const override {
242  if (RegNo == 0)
243  return 3;
244  if (RegNo == 1)
245  return 4;
246  return -1;
247  }
248 
249  bool hasSjLjLowering() const override { return true; }
250 
251  bool useFloat128ManglingForLongDouble() const override {
252  return LongDoubleWidth == 128 &&
253  LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
254  getTriple().isOSBinFormatELF();
255  }
256 };
257 
258 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
259 public:
260  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
261  : PPCTargetInfo(Triple, Opts) {
262  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
263 
264  switch (getTriple().getOS()) {
265  case llvm::Triple::Linux:
266  case llvm::Triple::FreeBSD:
267  case llvm::Triple::NetBSD:
268  SizeType = UnsignedInt;
269  PtrDiffType = SignedInt;
270  IntPtrType = SignedInt;
271  break;
272  default:
273  break;
274  }
275 
276  if (getTriple().getOS() == llvm::Triple::FreeBSD) {
277  LongDoubleWidth = LongDoubleAlign = 64;
278  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
279  }
280 
281  // PPC32 supports atomics up to 4 bytes.
282  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
283  }
284 
286  // This is the ELF definition, and is overridden by the Darwin sub-target
288  }
289 };
290 
291 // Note: ABI differences may eventually require us to have a separate
292 // TargetInfo for little endian.
293 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
294 public:
295  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
296  : PPCTargetInfo(Triple, Opts) {
297  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
298  IntMaxType = SignedLong;
299  Int64Type = SignedLong;
300 
301  if ((Triple.getArch() == llvm::Triple::ppc64le)) {
302  resetDataLayout("e-m:e-i64:64-n32:64");
303  ABI = "elfv2";
304  } else {
305  resetDataLayout("E-m:e-i64:64-n32:64");
306  ABI = "elfv1";
307  }
308 
309  switch (getTriple().getOS()) {
310  case llvm::Triple::FreeBSD:
311  LongDoubleWidth = LongDoubleAlign = 64;
312  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
313  break;
314  case llvm::Triple::NetBSD:
315  IntMaxType = SignedLongLong;
316  Int64Type = SignedLongLong;
317  break;
318  default:
319  break;
320  }
321 
322  // PPC64 supports atomics up to 8 bytes.
323  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
324  }
325 
328  }
329 
330  // PPC64 Linux-specific ABI options.
331  bool setABI(const std::string &Name) override {
332  if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
333  ABI = Name;
334  return true;
335  }
336  return false;
337  }
338 };
339 
340 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
341  : public DarwinTargetInfo<PPC32TargetInfo> {
342 public:
343  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
344  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
345  HasAlignMac68kSupport = true;
346  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
347  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
348  LongLongAlign = 32;
349  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
350  }
351 
354  }
355 };
356 
357 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
358  : public DarwinTargetInfo<PPC64TargetInfo> {
359 public:
360  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
361  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
362  HasAlignMac68kSupport = true;
363  resetDataLayout("E-m:o-i64:64-n32:64");
364  }
365 };
366 
367 } // namespace targets
368 } // namespace clang
369 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:260
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:360
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:21
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:76
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:285
Options for controlling the target.
Definition: TargetOptions.h:26
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:295
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:50
bool useFloat128ManglingForLongDouble() const override
Return true if the &#39;long double&#39; type should be mangled like __float128.
Definition: PPC.h:251
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:98
ArchDefineTypes
Flags for architecture specific defines.
Definition: PPC.h:61
static const char *const GCCRegNames[]
Definition: X86.cpp:44
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:343
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:326
Exposes information about the current target.
Definition: TargetInfo.h:54
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:331
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:91
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument...
Definition: PPC.h:241
#define false
Definition: stdbool.h:33
Defines the clang::TargetOptions class.
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:172
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:102
Dataflow Directional Tag Classes.
typedef char* __builtin_va_list;
Definition: TargetInfo.h:156
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:154
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm...
Definition: PPC.h:249
Defines the clang::TargetInfo interface.
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:352
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:49
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:225
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:124
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:240
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:784