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PPC.h
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1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares PPC TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
16 
17 #include "OSTargets.h"
18 #include "clang/Basic/TargetInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/Support/Compiler.h"
23 
24 namespace clang {
25 namespace targets {
26 
27 // PPC abstract base class
28 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
29 
30  /// Flags for architecture specific defines.
31  typedef enum {
32  ArchDefineNone = 0,
33  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
34  ArchDefinePpcgr = 1 << 1,
35  ArchDefinePpcsq = 1 << 2,
36  ArchDefine440 = 1 << 3,
37  ArchDefine603 = 1 << 4,
38  ArchDefine604 = 1 << 5,
39  ArchDefinePwr4 = 1 << 6,
40  ArchDefinePwr5 = 1 << 7,
41  ArchDefinePwr5x = 1 << 8,
42  ArchDefinePwr6 = 1 << 9,
43  ArchDefinePwr6x = 1 << 10,
44  ArchDefinePwr7 = 1 << 11,
45  ArchDefinePwr8 = 1 << 12,
46  ArchDefinePwr9 = 1 << 13,
47  ArchDefineA2 = 1 << 14,
48  ArchDefineA2q = 1 << 15
49  } ArchDefineTypes;
50 
51 
52  ArchDefineTypes ArchDefs = ArchDefineNone;
53  static const Builtin::Info BuiltinInfo[];
54  static const char *const GCCRegNames[];
55  static const TargetInfo::GCCRegAlias GCCRegAliases[];
56  std::string CPU;
57 
58  // Target cpu features.
59  bool HasAltivec = false;
60  bool HasVSX = false;
61  bool HasP8Vector = false;
62  bool HasP8Crypto = false;
63  bool HasDirectMove = false;
64  bool HasQPX = false;
65  bool HasHTM = false;
66  bool HasBPERMD = false;
67  bool HasExtDiv = false;
68  bool HasP9Vector = false;
69 
70 protected:
71  std::string ABI;
72 
73 public:
74  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
75  : TargetInfo(Triple) {
76  SuitableAlign = 128;
77  SimdDefaultAlign = 128;
78  LongDoubleWidth = LongDoubleAlign = 128;
79  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
80  }
81 
82  // Set the language option for altivec based on our value.
83  void adjust(LangOptions &Opts) override;
84 
85  // Note: GCC recognizes the following additional cpus:
86  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
87  // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
88  // titan, rs64.
89  bool isValidCPUName(StringRef Name) const override;
90  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
91 
92  bool setCPU(const std::string &Name) override {
93  bool CPUKnown = isValidCPUName(Name);
94  if (CPUKnown) {
95  CPU = Name;
96 
97  // CPU identification.
98  ArchDefs =
99  (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
100  .Case("440", ArchDefineName)
101  .Case("450", ArchDefineName | ArchDefine440)
102  .Case("601", ArchDefineName)
103  .Case("602", ArchDefineName | ArchDefinePpcgr)
104  .Case("603", ArchDefineName | ArchDefinePpcgr)
105  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
106  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
107  .Case("604", ArchDefineName | ArchDefinePpcgr)
108  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
109  .Case("620", ArchDefineName | ArchDefinePpcgr)
110  .Case("630", ArchDefineName | ArchDefinePpcgr)
111  .Case("7400", ArchDefineName | ArchDefinePpcgr)
112  .Case("7450", ArchDefineName | ArchDefinePpcgr)
113  .Case("750", ArchDefineName | ArchDefinePpcgr)
114  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
115  ArchDefinePpcsq)
116  .Case("a2", ArchDefineA2)
117  .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
118  .Cases("power3", "pwr3", ArchDefinePpcgr)
119  .Cases("power4", "pwr4",
120  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
121  .Cases("power5", "pwr5",
122  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
123  ArchDefinePpcsq)
124  .Cases("power5x", "pwr5x",
125  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
126  ArchDefinePpcgr | ArchDefinePpcsq)
127  .Cases("power6", "pwr6",
128  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
129  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
130  .Cases("power6x", "pwr6x",
131  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
132  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
133  ArchDefinePpcsq)
134  .Cases("power7", "pwr7",
135  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
136  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
137  ArchDefinePpcgr | ArchDefinePpcsq)
138  // powerpc64le automatically defaults to at least power8.
139  .Cases("power8", "pwr8", "ppc64le",
140  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
141  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
142  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
143  .Cases("power9", "pwr9",
144  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
145  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
146  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
147  ArchDefinePpcsq)
148  .Default(ArchDefineNone);
149  }
150  return CPUKnown;
151  }
152 
153  StringRef getABI() const override { return ABI; }
154 
155  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
156 
157  bool isCLZForZeroUndef() const override { return false; }
158 
159  void getTargetDefines(const LangOptions &Opts,
160  MacroBuilder &Builder) const override;
161 
162  bool
163  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
164  StringRef CPU,
165  const std::vector<std::string> &FeaturesVec) const override;
166 
167  bool handleTargetFeatures(std::vector<std::string> &Features,
168  DiagnosticsEngine &Diags) override;
169 
170  bool hasFeature(StringRef Feature) const override;
171 
172  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
173  bool Enabled) const override;
174 
175  ArrayRef<const char *> getGCCRegNames() const override;
176 
177  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
178 
179  bool validateAsmConstraint(const char *&Name,
180  TargetInfo::ConstraintInfo &Info) const override {
181  switch (*Name) {
182  default:
183  return false;
184  case 'O': // Zero
185  break;
186  case 'b': // Base register
187  case 'f': // Floating point register
188  Info.setAllowsRegister();
189  break;
190  // FIXME: The following are added to allow parsing.
191  // I just took a guess at what the actions should be.
192  // Also, is more specific checking needed? I.e. specific registers?
193  case 'd': // Floating point register (containing 64-bit value)
194  case 'v': // Altivec vector register
195  Info.setAllowsRegister();
196  break;
197  case 'w':
198  switch (Name[1]) {
199  case 'd': // VSX vector register to hold vector double data
200  case 'f': // VSX vector register to hold vector float data
201  case 's': // VSX vector register to hold scalar float data
202  case 'a': // Any VSX register
203  case 'c': // An individual CR bit
204  break;
205  default:
206  return false;
207  }
208  Info.setAllowsRegister();
209  Name++; // Skip over 'w'.
210  break;
211  case 'h': // `MQ', `CTR', or `LINK' register
212  case 'q': // `MQ' register
213  case 'c': // `CTR' register
214  case 'l': // `LINK' register
215  case 'x': // `CR' register (condition register) number 0
216  case 'y': // `CR' register (condition register)
217  case 'z': // `XER[CA]' carry bit (part of the XER register)
218  Info.setAllowsRegister();
219  break;
220  case 'I': // Signed 16-bit constant
221  case 'J': // Unsigned 16-bit constant shifted left 16 bits
222  // (use `L' instead for SImode constants)
223  case 'K': // Unsigned 16-bit constant
224  case 'L': // Signed 16-bit constant shifted left 16 bits
225  case 'M': // Constant larger than 31
226  case 'N': // Exact power of 2
227  case 'P': // Constant whose negation is a signed 16-bit constant
228  case 'G': // Floating point constant that can be loaded into a
229  // register with one instruction per word
230  case 'H': // Integer/Floating point constant that can be loaded
231  // into a register using three instructions
232  break;
233  case 'm': // Memory operand. Note that on PowerPC targets, m can
234  // include addresses that update the base register. It
235  // is therefore only safe to use `m' in an asm statement
236  // if that asm statement accesses the operand exactly once.
237  // The asm statement must also use `%U<opno>' as a
238  // placeholder for the "update" flag in the corresponding
239  // load or store instruction. For example:
240  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
241  // is correct but:
242  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
243  // is not. Use es rather than m if you don't want the base
244  // register to be updated.
245  case 'e':
246  if (Name[1] != 's')
247  return false;
248  // es: A "stable" memory operand; that is, one which does not
249  // include any automodification of the base register. Unlike
250  // `m', this constraint can be used in asm statements that
251  // might access the operand several times, or that might not
252  // access it at all.
253  Info.setAllowsMemory();
254  Name++; // Skip over 'e'.
255  break;
256  case 'Q': // Memory operand that is an offset from a register (it is
257  // usually better to use `m' or `es' in asm statements)
258  case 'Z': // Memory operand that is an indexed or indirect from a
259  // register (it is usually better to use `m' or `es' in
260  // asm statements)
261  Info.setAllowsMemory();
262  Info.setAllowsRegister();
263  break;
264  case 'R': // AIX TOC entry
265  case 'a': // Address operand that is an indexed or indirect from a
266  // register (`p' is preferable for asm statements)
267  case 'S': // Constant suitable as a 64-bit mask operand
268  case 'T': // Constant suitable as a 32-bit mask operand
269  case 'U': // System V Release 4 small data area reference
270  case 't': // AND masks that can be performed by two rldic{l, r}
271  // instructions
272  case 'W': // Vector constant that does not require memory
273  case 'j': // Vector constant that is all zeros.
274  break;
275  // End FIXME.
276  }
277  return true;
278  }
279 
280  std::string convertConstraint(const char *&Constraint) const override {
281  std::string R;
282  switch (*Constraint) {
283  case 'e':
284  case 'w':
285  // Two-character constraint; add "^" hint for later parsing.
286  R = std::string("^") + std::string(Constraint, 2);
287  Constraint++;
288  break;
289  default:
290  return TargetInfo::convertConstraint(Constraint);
291  }
292  return R;
293  }
294 
295  const char *getClobbers() const override { return ""; }
296  int getEHDataRegisterNumber(unsigned RegNo) const override {
297  if (RegNo == 0)
298  return 3;
299  if (RegNo == 1)
300  return 4;
301  return -1;
302  }
303 
304  bool hasSjLjLowering() const override { return true; }
305 
306  bool useFloat128ManglingForLongDouble() const override {
307  return LongDoubleWidth == 128 &&
308  LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
309  getTriple().isOSBinFormatELF();
310  }
311 };
312 
313 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
314 public:
315  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
316  : PPCTargetInfo(Triple, Opts) {
317  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
318 
319  switch (getTriple().getOS()) {
320  case llvm::Triple::Linux:
321  case llvm::Triple::FreeBSD:
322  case llvm::Triple::NetBSD:
323  SizeType = UnsignedInt;
324  PtrDiffType = SignedInt;
325  IntPtrType = SignedInt;
326  break;
327  default:
328  break;
329  }
330 
331  if (getTriple().getOS() == llvm::Triple::FreeBSD) {
332  LongDoubleWidth = LongDoubleAlign = 64;
333  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
334  }
335 
336  // PPC32 supports atomics up to 4 bytes.
337  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
338  }
339 
341  // This is the ELF definition, and is overridden by the Darwin sub-target
343  }
344 };
345 
346 // Note: ABI differences may eventually require us to have a separate
347 // TargetInfo for little endian.
348 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
349 public:
350  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
351  : PPCTargetInfo(Triple, Opts) {
352  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
353  IntMaxType = SignedLong;
354  Int64Type = SignedLong;
355 
356  if ((Triple.getArch() == llvm::Triple::ppc64le)) {
357  resetDataLayout("e-m:e-i64:64-n32:64");
358  ABI = "elfv2";
359  } else {
360  resetDataLayout("E-m:e-i64:64-n32:64");
361  ABI = "elfv1";
362  }
363 
364  switch (getTriple().getOS()) {
365  case llvm::Triple::FreeBSD:
366  LongDoubleWidth = LongDoubleAlign = 64;
367  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
368  break;
369  default:
370  break;
371  }
372 
373  // PPC64 supports atomics up to 8 bytes.
374  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
375  }
376 
379  }
380 
381  // PPC64 Linux-specific ABI options.
382  bool setABI(const std::string &Name) override {
383  if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
384  ABI = Name;
385  return true;
386  }
387  return false;
388  }
389 
391  switch (CC) {
392  case CC_Swift:
393  return CCCR_OK;
394  default:
395  return CCCR_Warning;
396  }
397  }
398 };
399 
400 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
401  : public DarwinTargetInfo<PPC32TargetInfo> {
402 public:
403  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
404  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
405  HasAlignMac68kSupport = true;
406  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
407  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
408  LongLongAlign = 32;
409  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
410  }
411 
414  }
415 };
416 
417 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
418  : public DarwinTargetInfo<PPC64TargetInfo> {
419 public:
420  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
421  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
422  HasAlignMac68kSupport = true;
423  resetDataLayout("E-m:o-i64:64-n32:64");
424  }
425 };
426 
427 } // namespace targets
428 } // namespace clang
429 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:315
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:390
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:420
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:21
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:76
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:340
Options for controlling the target.
Definition: TargetOptions.h:26
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:350
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:50
bool useFloat128ManglingForLongDouble() const override
Return true if the &#39;long double&#39; type should be mangled like __float128.
Definition: PPC.h:306
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:153
static const char *const GCCRegNames[]
Definition: X86.cpp:44
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:403
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:377
Exposes information about the current target.
Definition: TargetInfo.h:54
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:382
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:92
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:236
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument...
Definition: PPC.h:296
Defines the clang::TargetOptions class.
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:199
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:157
Dataflow Directional Tag Classes.
typedef char* __builtin_va_list;
Definition: TargetInfo.h:183
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:181
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm...
Definition: PPC.h:304
Defines the clang::TargetInfo interface.
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:412
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:74
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:280
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:179
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:295
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:932