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sifive_vector.h
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1//===----- sifive_vector.h - SiFive Vector definitions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef _SIFIVE_VECTOR_H_
10#define _SIFIVE_VECTOR_H_
11
12#include "riscv_vector.h"
13
14#pragma clang riscv intrinsic sifive_vector
15
16#define __riscv_intrinsic_xsfmm32a16f 1
17#define __riscv_intrinsic_xsfmm32a32f 1
18#define __riscv_intrinsic_xsfmm32a8f 1
19#define __riscv_intrinsic_xsfmm32a8i 1
20#define __riscv_intrinsic_xsfmm32a 1
21#define __riscv_intrinsic_xsfmm64a64f 1
22#define __riscv_intrinsic_xsfmmbase 1
23#define __riscv_intrinsic_xsfvcp 1
24#define __riscv_intrinsic_xsfvfbfexp16e 1
25#define __riscv_intrinsic_xsfvfexp16e 1
26#define __riscv_intrinsic_xsfvfexp32e 1
27#define __riscv_intrinsic_xsfvfexpa 1
28#define __riscv_intrinsic_xsfvfexpa64e 1
29#define __riscv_intrinsic_xsfvfnrclipxfqf 1
30#define __riscv_intrinsic_xsfvfwmaccqqq 1
31#define __riscv_intrinsic_xsfvqmaccdod 1
32#define __riscv_intrinsic_xsfvqmaccqoq 1
33
34#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \
35 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
36#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \
37 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 7, vl)
38#define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \
39 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 0, vl)
40#define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \
41 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 1, vl)
42#define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \
43 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 2, vl)
44#define __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl) \
45 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 3, vl)
46
47#define __riscv_sf_vc_x_se_u16mf2(p27_26, p24_20, p11_7, rs1, vl) \
48 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 7, vl)
49#define __riscv_sf_vc_x_se_u16m1(p27_26, p24_20, p11_7, rs1, vl) \
50 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 0, vl)
51#define __riscv_sf_vc_x_se_u16m2(p27_26, p24_20, p11_7, rs1, vl) \
52 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 1, vl)
53#define __riscv_sf_vc_x_se_u16m4(p27_26, p24_20, p11_7, rs1, vl) \
54 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 2, vl)
55#define __riscv_sf_vc_x_se_u16m8(p27_26, p24_20, p11_7, rs1, vl) \
56 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 3, vl)
57
58#define __riscv_sf_vc_x_se_u32m1(p27_26, p24_20, p11_7, rs1, vl) \
59 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 0, vl)
60#define __riscv_sf_vc_x_se_u32m2(p27_26, p24_20, p11_7, rs1, vl) \
61 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 1, vl)
62#define __riscv_sf_vc_x_se_u32m4(p27_26, p24_20, p11_7, rs1, vl) \
63 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 2, vl)
64#define __riscv_sf_vc_x_se_u32m8(p27_26, p24_20, p11_7, rs1, vl) \
65 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 3, vl)
66
67#define __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl) \
68 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 6, vl)
69#define __riscv_sf_vc_i_se_u8mf2(p27_26, p24_20, p11_7, simm5, vl) \
70 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 7, vl)
71#define __riscv_sf_vc_i_se_u8m1(p27_26, p24_20, p11_7, simm5, vl) \
72 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 0, vl)
73#define __riscv_sf_vc_i_se_u8m2(p27_26, p24_20, p11_7, simm5, vl) \
74 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 1, vl)
75#define __riscv_sf_vc_i_se_u8m4(p27_26, p24_20, p11_7, simm5, vl) \
76 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 2, vl)
77#define __riscv_sf_vc_i_se_u8m8(p27_26, p24_20, p11_7, simm5, vl) \
78 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 3, vl)
79
80#define __riscv_sf_vc_i_se_u16mf2(p27_26, p24_20, p11_7, simm5, vl) \
81 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 7, vl)
82#define __riscv_sf_vc_i_se_u16m1(p27_26, p24_20, p11_7, simm5, vl) \
83 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 0, vl)
84#define __riscv_sf_vc_i_se_u16m2(p27_26, p24_20, p11_7, simm5, vl) \
85 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 1, vl)
86#define __riscv_sf_vc_i_se_u16m4(p27_26, p24_20, p11_7, simm5, vl) \
87 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 2, vl)
88#define __riscv_sf_vc_i_se_u16m8(p27_26, p24_20, p11_7, simm5, vl) \
89 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 3, vl)
90
91#define __riscv_sf_vc_i_se_u32m1(p27_26, p24_20, p11_7, simm5, vl) \
92 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 0, vl)
93#define __riscv_sf_vc_i_se_u32m2(p27_26, p24_20, p11_7, simm5, vl) \
94 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 1, vl)
95#define __riscv_sf_vc_i_se_u32m4(p27_26, p24_20, p11_7, simm5, vl) \
96 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 2, vl)
97#define __riscv_sf_vc_i_se_u32m8(p27_26, p24_20, p11_7, simm5, vl) \
98 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 3, vl)
99
100#if __riscv_v_elen >= 64
101#define __riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7, rs1, vl) \
102 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 5, vl)
103#define __riscv_sf_vc_x_se_u16mf4(p27_26, p24_20, p11_7, rs1, vl) \
104 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 6, vl)
105#define __riscv_sf_vc_x_se_u32mf2(p27_26, p24_20, p11_7, rs1, vl) \
106 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 7, vl)
107
108#define __riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5, vl) \
109 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 5, vl)
110#define __riscv_sf_vc_i_se_u16mf4(p27_26, p24_20, p11_7, simm5, vl) \
111 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 6, vl)
112#define __riscv_sf_vc_i_se_u32mf2(p27_26, p24_20, p11_7, simm5, vl) \
113 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 7, vl)
114
115#define __riscv_sf_vc_i_se_u64m1(p27_26, p24_20, p11_7, simm5, vl) \
116 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 0, vl)
117#define __riscv_sf_vc_i_se_u64m2(p27_26, p24_20, p11_7, simm5, vl) \
118 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 1, vl)
119#define __riscv_sf_vc_i_se_u64m4(p27_26, p24_20, p11_7, simm5, vl) \
120 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 2, vl)
121#define __riscv_sf_vc_i_se_u64m8(p27_26, p24_20, p11_7, simm5, vl) \
122 __riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 3, vl)
123
124#if __riscv_xlen >= 64
125#define __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl) \
126 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 0, vl)
127#define __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl) \
128 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 1, vl)
129#define __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl) \
130 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 2, vl)
131#define __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl) \
132 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 3, vl)
133#endif
134#endif
135
136#define __riscv_sf_vsettnt_e8w1(atn) __riscv_sf_vsettnt(atn, 0, 1);
137#define __riscv_sf_vsettnt_e8w2(atn) __riscv_sf_vsettnt(atn, 0, 2);
138#define __riscv_sf_vsettnt_e8w4(atn) __riscv_sf_vsettnt(atn, 0, 3);
139#define __riscv_sf_vsettnt_e16w1(atn) __riscv_sf_vsettnt(atn, 1, 1);
140#define __riscv_sf_vsettnt_e16w2(atn) __riscv_sf_vsettnt(atn, 1, 2);
141#define __riscv_sf_vsettnt_e16w4(atn) __riscv_sf_vsettnt(atn, 1, 3);
142#define __riscv_sf_vsettnt_e32w1(atn) __riscv_sf_vsettnt(atn, 2, 1);
143#define __riscv_sf_vsettnt_e32w2(atn) __riscv_sf_vsettnt(atn, 2, 2);
144#define __riscv_sf_vsettm_e8w1(atm) __riscv_sf_vsettm(atm, 0, 1);
145#define __riscv_sf_vsettm_e8w2(atm) __riscv_sf_vsettm(atm, 0, 2);
146#define __riscv_sf_vsettm_e8w4(atm) __riscv_sf_vsettm(atm, 0, 3);
147#define __riscv_sf_vsettm_e16w1(atm) __riscv_sf_vsettm(atm, 1, 1);
148#define __riscv_sf_vsettm_e16w2(atm) __riscv_sf_vsettm(atm, 1, 2);
149#define __riscv_sf_vsettm_e16w4(atm) __riscv_sf_vsettm(atm, 1, 3);
150#define __riscv_sf_vsettm_e32w1(atm) __riscv_sf_vsettm(atm, 2, 1);
151#define __riscv_sf_vsettm_e32w2(atm) __riscv_sf_vsettm(atm, 2, 2);
152#define __riscv_sf_vsettn_e8w1(atn) __riscv_sf_vsettn(atn, 0, 1);
153#define __riscv_sf_vsettn_e8w2(atn) __riscv_sf_vsettn(atn, 0, 2);
154#define __riscv_sf_vsettn_e8w4(atn) __riscv_sf_vsettn(atn, 0, 3);
155#define __riscv_sf_vsettn_e16w1(atn) __riscv_sf_vsettn(atn, 1, 1);
156#define __riscv_sf_vsettn_e16w2(atn) __riscv_sf_vsettn(atn, 1, 2);
157#define __riscv_sf_vsettn_e16w4(atn) __riscv_sf_vsettn(atn, 1, 3);
158#define __riscv_sf_vsettn_e32w1(atn) __riscv_sf_vsettn(atn, 2, 1);
159#define __riscv_sf_vsettn_e32w2(atn) __riscv_sf_vsettn(atn, 2, 2);
160#define __riscv_sf_vsettk_e8w1(atk) __riscv_sf_vsettk(atk, 0, 1);
161#define __riscv_sf_vsettk_e8w2(atk) __riscv_sf_vsettk(atk, 0, 2);
162#define __riscv_sf_vsettk_e8w4(atk) __riscv_sf_vsettk(atk, 0, 3);
163#define __riscv_sf_vsettk_e16w1(atk) __riscv_sf_vsettk(atk, 1, 1);
164#define __riscv_sf_vsettk_e16w2(atk) __riscv_sf_vsettk(atk, 1, 2);
165#define __riscv_sf_vsettk_e16w4(atk) __riscv_sf_vsettk(atk, 1, 3);
166#define __riscv_sf_vsettk_e32w1(atk) __riscv_sf_vsettk(atk, 2, 1);
167#define __riscv_sf_vsettk_e32w2(atk) __riscv_sf_vsettk(atk, 2, 2);
168#define __riscv_sf_vtzero_t_e8w1(tile, atm, atn) \
169 __riscv_sf_vtzero_t(tile, atm, atn, 3, 1);
170#define __riscv_sf_vtzero_t_e8w2(tile, atm, atn) \
171 __riscv_sf_vtzero_t(tile, atm, atn, 3, 2);
172#define __riscv_sf_vtzero_t_e8w4(tile, atm, atn) \
173 __riscv_sf_vtzero_t(tile, atm, atn, 3, 4);
174#define __riscv_sf_vtzero_t_e16w1(tile, atm, atn) \
175 __riscv_sf_vtzero_t(tile, atm, atn, 4, 1);
176#define __riscv_sf_vtzero_t_e16w2(tile, atm, atn) \
177 __riscv_sf_vtzero_t(tile, atm, atn, 4, 2);
178#define __riscv_sf_vtzero_t_e16w4(tile, atm, atn) \
179 __riscv_sf_vtzero_t(tile, atm, atn, 4, 4);
180#define __riscv_sf_vtzero_t_e32w1(tile, atm, atn) \
181 __riscv_sf_vtzero_t(tile, atm, atn, 5, 1);
182#define __riscv_sf_vtzero_t_e32w2(tile, atm, atn) \
183 __riscv_sf_vtzero_t(tile, atm, atn, 5, 2);
184#if __riscv_v_elen >= 64
185#define __riscv_sf_vsettnt_e64w1(atn) __riscv_sf_vsettnt(atn, 3, 1);
186#define __riscv_sf_vsettm_e64w1(atm) __riscv_sf_vsettm(atm, 3, 1);
187#define __riscv_sf_vsettn_e64w1(atn) __riscv_sf_vsettn(atn, 3, 1);
188#define __riscv_sf_vsettk_e64w1(atk) __riscv_sf_vsettk(atk, 3, 1);
189#define __riscv_sf_vtzero_t_e64w1(tile, atm, atn) \
190 __riscv_sf_vtzero_t(tile, atm, atn, 6, 1);
191#endif
192#endif //_SIFIVE_VECTOR_H_
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