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avxifmaintrin.h
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1/*===----------------- avxifmaintrin.h - IFMA intrinsics -------------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9
10#ifndef __IMMINTRIN_H
11#error "Never use <avxifmaintrin.h> directly; include <immintrin.h> instead."
12#endif
13
14#ifndef __AVXIFMAINTRIN_H
15#define __AVXIFMAINTRIN_H
16
17/* Define the default attributes for the functions in this file. */
18#if defined(__cplusplus) && (__cplusplus >= 201103L)
19#define __DEFAULT_FN_ATTRS128 \
20 constexpr __attribute__((__always_inline__, __nodebug__, \
21 __target__("avxifma"), __min_vector_width__(128)))
22#define __DEFAULT_FN_ATTRS256 \
23 constexpr __attribute__((__always_inline__, __nodebug__, \
24 __target__("avxifma"), __min_vector_width__(256)))
25#else
26#define __DEFAULT_FN_ATTRS128 \
27 __attribute__((__always_inline__, __nodebug__, __target__("avxifma"), \
28 __min_vector_width__(128)))
29#define __DEFAULT_FN_ATTRS256 \
30 __attribute__((__always_inline__, __nodebug__, __target__("avxifma"), \
31 __min_vector_width__(256)))
32#endif
33
34// must vex-encoding
35
36/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
37/// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
38/// unsigned integer from the intermediate result with the corresponding
39/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
40///
41/// \headerfile <immintrin.h>
42///
43/// \code
44/// __m128i
45/// _mm_madd52hi_avx_epu64 (__m128i __X, __m128i __Y, __m128i __Z)
46/// \endcode
47///
48/// This intrinsic corresponds to the \c VPMADD52HUQ instruction.
49///
50/// \return
51/// return __m128i dst.
52/// \param __X
53/// A 128-bit vector of [2 x i64]
54/// \param __Y
55/// A 128-bit vector of [2 x i64]
56/// \param __Z
57/// A 128-bit vector of [2 x i64]
58///
59/// \code{.operation}
60/// FOR j := 0 to 1
61/// i := j*64
62/// tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
63/// dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
64/// ENDFOR
65/// dst[MAX:128] := 0
66/// \endcode
67static __inline__ __m128i __DEFAULT_FN_ATTRS128
68_mm_madd52hi_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z) {
69 return (__m128i)__builtin_ia32_vpmadd52huq128((__v2di)__X, (__v2di)__Y,
70 (__v2di)__Z);
71}
72
73/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
74/// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
75/// unsigned integer from the intermediate result with the corresponding
76/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
77///
78/// \headerfile <immintrin.h>
79///
80/// \code
81/// __m256i
82/// _mm256_madd52hi_avx_epu64 (__m256i __X, __m256i __Y, __m256i __Z)
83/// \endcode
84///
85/// This intrinsic corresponds to the \c VPMADD52HUQ instruction.
86///
87/// \return
88/// return __m256i dst.
89/// \param __X
90/// A 256-bit vector of [4 x i64]
91/// \param __Y
92/// A 256-bit vector of [4 x i64]
93/// \param __Z
94/// A 256-bit vector of [4 x i64]
95///
96/// \code{.operation}
97/// FOR j := 0 to 3
98/// i := j*64
99/// tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
100/// dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
101/// ENDFOR
102/// dst[MAX:256] := 0
103/// \endcode
104static __inline__ __m256i __DEFAULT_FN_ATTRS256
105_mm256_madd52hi_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z) {
106 return (__m256i)__builtin_ia32_vpmadd52huq256((__v4di)__X, (__v4di)__Y,
107 (__v4di)__Z);
108}
109
110/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
111/// and \a __Z to form a 104-bit intermediate result. Add the low 52-bit
112/// unsigned integer from the intermediate result with the corresponding
113/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
114///
115/// \headerfile <immintrin.h>
116///
117/// \code
118/// __m128i
119/// _mm_madd52lo_avx_epu64 (__m128i __X, __m128i __Y, __m128i __Z)
120/// \endcode
121///
122/// This intrinsic corresponds to the \c VPMADD52LUQ instruction.
123///
124/// \return
125/// return __m128i dst.
126/// \param __X
127/// A 128-bit vector of [2 x i64]
128/// \param __Y
129/// A 128-bit vector of [2 x i64]
130/// \param __Z
131/// A 128-bit vector of [2 x i64]
132///
133/// \code{.operation}
134/// FOR j := 0 to 1
135/// i := j*64
136/// tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
137/// dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
138/// ENDFOR
139/// dst[MAX:128] := 0
140/// \endcode
141static __inline__ __m128i __DEFAULT_FN_ATTRS128
142_mm_madd52lo_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z) {
143 return (__m128i)__builtin_ia32_vpmadd52luq128((__v2di)__X, (__v2di)__Y,
144 (__v2di)__Z);
145}
146
147/// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
148/// and \a __Z to form a 104-bit intermediate result. Add the low 52-bit
149/// unsigned integer from the intermediate result with the corresponding
150/// unsigned 64-bit integer in \a __X, and store the results in \a dst.
151///
152/// \headerfile <immintrin.h>
153///
154/// \code
155/// __m256i
156/// _mm256_madd52lo_avx_epu64 (__m256i __X, __m256i __Y, __m256i __Z)
157/// \endcode
158///
159/// This intrinsic corresponds to the \c VPMADD52LUQ instruction.
160///
161/// \return
162/// return __m256i dst.
163/// \param __X
164/// A 256-bit vector of [4 x i64]
165/// \param __Y
166/// A 256-bit vector of [4 x i64]
167/// \param __Z
168/// A 256-bit vector of [4 x i64]
169///
170/// \code{.operation}
171/// FOR j := 0 to 3
172/// i := j*64
173/// tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
174/// dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
175/// ENDFOR
176/// dst[MAX:256] := 0
177/// \endcode
178static __inline__ __m256i __DEFAULT_FN_ATTRS256
179_mm256_madd52lo_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z) {
180 return (__m256i)__builtin_ia32_vpmadd52luq256((__v4di)__X, (__v4di)__Y,
181 (__v4di)__Z);
182}
183#undef __DEFAULT_FN_ATTRS128
184#undef __DEFAULT_FN_ATTRS256
185
186#endif // __AVXIFMAINTRIN_H
#define __DEFAULT_FN_ATTRS128
#define __DEFAULT_FN_ATTRS256
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_madd52hi_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z)
Multiply packed unsigned 52-bit integers in each 64-bit element of __Y and __Z to form a 104-bit inte...
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_madd52lo_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z)
Multiply packed unsigned 52-bit integers in each 64-bit element of __Y and __Z to form a 104-bit inte...
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_madd52hi_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z)
Multiply packed unsigned 52-bit integers in each 64-bit element of __Y and __Z to form a 104-bit inte...
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_madd52lo_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z)
Multiply packed unsigned 52-bit integers in each 64-bit element of __Y and __Z to form a 104-bit inte...
__inline unsigned int unsigned int __Y
Definition bmi2intrin.h:19