10#error "Never use <avx10v2auxintrin.h> directly; include <immintrin.h> instead."
15#ifndef __AVX10V2AUXINTRIN_H
16#define __AVX10V2AUXINTRIN_H
19#define __DEFAULT_FN_ATTRS128 \
20 __attribute__((__always_inline__, __nodebug__, __target__("avx10v2aux"), \
21 __min_vector_width__(128)))
22#define __DEFAULT_FN_ATTRS256 \
23 __attribute__((__always_inline__, __nodebug__, __target__("avx10v2aux"), \
24 __min_vector_width__(256)))
40 return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
65 return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask((__v4sf)__A, (__v16qi)__W,
85_mm_maskz_cvtps_bf8(
__mmask8 __U, __m128 __A) {
86 return (__m128i)__builtin_ia32_vcvtps2bf8_128_mask(
104 return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
127_mm256_mask_cvtps_bf8(__m128i __W,
__mmask8 __U, __m256 __A) {
128 return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask((__v8sf)__A, (__v16qi)__W,
148_mm256_maskz_cvtps_bf8(
__mmask8 __U, __m256 __A) {
149 return (__m128i)__builtin_ia32_vcvtps2bf8_256_mask(
166 return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
189_mm_mask_cvts_ps_bf8(__m128i __W,
__mmask8 __U, __m128 __A) {
190 return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask((__v4sf)__A, (__v16qi)__W,
210_mm_maskz_cvts_ps_bf8(
__mmask8 __U, __m128 __A) {
211 return (__m128i)__builtin_ia32_vcvtps2bf8s_128_mask(
228 return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
251_mm256_mask_cvts_ps_bf8(__m128i __W,
__mmask8 __U, __m256 __A) {
252 return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask((__v8sf)__A, (__v16qi)__W,
272_mm256_maskz_cvts_ps_bf8(
__mmask8 __U, __m256 __A) {
273 return (__m128i)__builtin_ia32_vcvtps2bf8s_256_mask(
290 return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask(
315 return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask((__v4sf)__A, (__v16qi)__W,
335_mm_maskz_cvtps_hf8(
__mmask8 __U, __m128 __A) {
336 return (__m128i)__builtin_ia32_vcvtps2hf8_128_mask(
353 return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask(
376_mm256_mask_cvtps_hf8(__m128i __W,
__mmask8 __U, __m256 __A) {
377 return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask((__v8sf)__A, (__v16qi)__W,
397_mm256_maskz_cvtps_hf8(
__mmask8 __U, __m256 __A) {
398 return (__m128i)__builtin_ia32_vcvtps2hf8_256_mask(
415 return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask(
438_mm_mask_cvts_ps_hf8(__m128i __W,
__mmask8 __U, __m128 __A) {
439 return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask((__v4sf)__A, (__v16qi)__W,
459_mm_maskz_cvts_ps_hf8(
__mmask8 __U, __m128 __A) {
460 return (__m128i)__builtin_ia32_vcvtps2hf8s_128_mask(
477 return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask(
500_mm256_mask_cvts_ps_hf8(__m128i __W,
__mmask8 __U, __m256 __A) {
501 return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask((__v8sf)__A, (__v16qi)__W,
521_mm256_maskz_cvts_ps_hf8(
__mmask8 __U, __m256 __A) {
522 return (__m128i)__builtin_ia32_vcvtps2hf8s_256_mask(
539 return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
562_mm_mask_cvtrops_hf8(__m128i __W,
__mmask8 __U, __m128 __A) {
563 return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
564 (__v4sf)__A, (__v16qi)__W, (
__mmask8)__U);
583_mm_maskz_cvtrops_hf8(
__mmask8 __U, __m128 __A) {
584 return (__m128i)__builtin_ia32_vcvtrops2hf8_128_mask(
601 return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
624_mm256_mask_cvtrops_hf8(__m128i __W,
__mmask8 __U, __m256 __A) {
625 return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
626 (__v8sf)__A, (__v16qi)__W, (
__mmask8)__U);
645_mm256_maskz_cvtrops_hf8(
__mmask8 __U, __m256 __A) {
646 return (__m128i)__builtin_ia32_vcvtrops2hf8_256_mask(
663 return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
686_mm_mask_cvts_rops_hf8(__m128i __W,
__mmask8 __U, __m128 __A) {
687 return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
688 (__v4sf)__A, (__v16qi)__W, (
__mmask8)__U);
707_mm_maskz_cvts_rops_hf8(
__mmask8 __U, __m128 __A) {
708 return (__m128i)__builtin_ia32_vcvtrops2hf8s_128_mask(
725_mm256_cvts_rops_hf8(__m256 __A) {
726 return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
749_mm256_mask_cvts_rops_hf8(__m128i __W,
__mmask8 __U, __m256 __A) {
750 return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
751 (__v8sf)__A, (__v16qi)__W, (
__mmask8)__U);
770_mm256_maskz_cvts_rops_hf8(
__mmask8 __U, __m256 __A) {
771 return (__m128i)__builtin_ia32_vcvtrops2hf8s_256_mask(
791 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
816_mm_mask_cvtbiasps_bf8(__m128i __W,
__mmask8 __U, __m128i __A, __m128 __B) {
817 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
818 (__v4si)__A, (__v4sf)__B, (__v16qi)__W, (
__mmask8)__U);
839_mm_maskz_cvtbiasps_bf8(
__mmask8 __U, __m128i __A, __m128 __B) {
840 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_128_mask(
859_mm256_cvtbiasps_bf8(__m256i __A, __m256 __B) {
860 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
885_mm256_mask_cvtbiasps_bf8(__m128i __W,
__mmask8 __U, __m256i __A, __m256 __B) {
886 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
887 (__v8si)__A, (__v8sf)__B, (__v16qi)__W, (
__mmask8)__U);
908_mm256_maskz_cvtbiasps_bf8(
__mmask8 __U, __m256i __A, __m256 __B) {
909 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_256_mask(
928_mm_cvts_biasps_bf8(__m128i __A, __m128 __B) {
929 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
954_mm_mask_cvts_biasps_bf8(__m128i __W,
__mmask8 __U, __m128i __A, __m128 __B) {
955 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
956 (__v4si)__A, (__v4sf)__B, (__v16qi)__W, (
__mmask8)__U);
977_mm_maskz_cvts_biasps_bf8(
__mmask8 __U, __m128i __A, __m128 __B) {
978 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_128_mask(
997_mm256_cvts_biasps_bf8(__m256i __A, __m256 __B) {
998 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
1023 __m128i __W,
__mmask8 __U, __m256i __A, __m256 __B) {
1024 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
1025 (__v8si)__A, (__v8sf)__B, (__v16qi)__W, (
__mmask8)__U);
1046_mm256_maskz_cvts_biasps_bf8(
__mmask8 __U, __m256i __A, __m256 __B) {
1047 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_256_mask(
1067 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
1092_mm_mask_cvtbiasps_hf8(__m128i __W,
__mmask8 __U, __m128i __A, __m128 __B) {
1093 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
1094 (__v4si)__A, (__v4sf)__B, (__v16qi)__W, (
__mmask8)__U);
1115_mm_maskz_cvtbiasps_hf8(
__mmask8 __U, __m128i __A, __m128 __B) {
1116 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_128_mask(
1135_mm256_cvtbiasps_hf8(__m256i __A, __m256 __B) {
1136 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
1161_mm256_mask_cvtbiasps_hf8(__m128i __W,
__mmask8 __U, __m256i __A, __m256 __B) {
1162 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
1163 (__v8si)__A, (__v8sf)__B, (__v16qi)__W, (
__mmask8)__U);
1184_mm256_maskz_cvtbiasps_hf8(
__mmask8 __U, __m256i __A, __m256 __B) {
1185 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_256_mask(
1204_mm_cvts_biasps_hf8(__m128i __A, __m128 __B) {
1205 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
1230_mm_mask_cvts_biasps_hf8(__m128i __W,
__mmask8 __U, __m128i __A, __m128 __B) {
1231 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
1232 (__v4si)__A, (__v4sf)__B, (__v16qi)__W, (
__mmask8)__U);
1253_mm_maskz_cvts_biasps_hf8(
__mmask8 __U, __m128i __A, __m128 __B) {
1254 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_128_mask(
1273_mm256_cvts_biasps_hf8(__m256i __A, __m256 __B) {
1274 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
1299 __m128i __W,
__mmask8 __U, __m256i __A, __m256 __B) {
1300 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
1301 (__v8si)__A, (__v8sf)__B, (__v16qi)__W, (
__mmask8)__U);
1322_mm256_maskz_cvts_biasps_hf8(
__mmask8 __U, __m256i __A, __m256 __B) {
1323 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_256_mask(
1340 return (__m128)__builtin_ia32_vcvtbf82ps_128((__v16qi)__A);
1362 return (__m128)__builtin_ia32_selectps_128(
1363 (
__mmask8)__U, (__v4sf)_mm_cvtbf8_ps(__A), (__v4sf)__W);
1381_mm_maskz_cvtbf8_ps(
__mmask8 __U, __m128i __A) {
1382 return (__m128)__builtin_ia32_selectps_128(
1399 return (__m256)__builtin_ia32_vcvtbf82ps_256((__v16qi)__A);
1419_mm256_mask_cvtbf8_ps(__m256 __W,
__mmask8 __U, __m128i __A) {
1420 return (__m256)__builtin_ia32_selectps_256(
1421 (
__mmask8)__U, (__v8sf)_mm256_cvtbf8_ps(__A), (__v8sf)__W);
1439_mm256_maskz_cvtbf8_ps(
__mmask8 __U, __m128i __A) {
1440 return (__m256)__builtin_ia32_selectps_256((
__mmask8)__U,
1441 (__v8sf)_mm256_cvtbf8_ps(__A),
1458 return (__m128)__builtin_ia32_vcvthf82ps_128((__v16qi)__A);
1480 return (__m128)__builtin_ia32_selectps_128(
1481 (
__mmask8)__U, (__v4sf)_mm_cvthf8_ps(__A), (__v4sf)__W);
1499_mm_maskz_cvthf8_ps(
__mmask8 __U, __m128i __A) {
1500 return (__m128)__builtin_ia32_selectps_128(
1517 return (__m256)__builtin_ia32_vcvthf82ps_256((__v16qi)__A);
1537_mm256_mask_cvthf8_ps(__m256 __W,
__mmask8 __U, __m128i __A) {
1538 return (__m256)__builtin_ia32_selectps_256(
1539 (
__mmask8)__U, (__v8sf)_mm256_cvthf8_ps(__A), (__v8sf)__W);
1557_mm256_maskz_cvthf8_ps(
__mmask8 __U, __m128i __A) {
1558 return (__m256)__builtin_ia32_selectps_256((
__mmask8)__U,
1559 (__v8sf)_mm256_cvthf8_ps(__A),
1577 return (__m128i)__builtin_ia32_vcvtbf82bf6s_128((__v16qi)__A);
1594_mm256_cvts_bf8_bf6(__m256i __A) {
1595 return (__m256i)__builtin_ia32_vcvtbf82bf6s_256((__v32qi)__A);
1612 return (__m128i)__builtin_ia32_vcvthf82hf6s_128((__v16qi)__A);
1629_mm256_cvts_hf8_hf6(__m256i __A) {
1630 return (__m256i)__builtin_ia32_vcvthf82hf6s_256((__v32qi)__A);
1647 return (__m128i)__builtin_ia32_vcvtbf82bf4s_128((__v16qi)__A);
1663_mm256_cvts_bf8_bf4(__m256i __A) {
1664 return (__m128i)__builtin_ia32_vcvtbf82bf4s_256((__v32qi)__A);
1681 return (__m128i)__builtin_ia32_vcvthf82bf4s_128((__v16qi)__A);
1697_mm256_cvts_hf8_bf4(__m256i __A) {
1698 return (__m128i)__builtin_ia32_vcvthf82bf4s_256((__v32qi)__A);
1714 return (__m128i)__builtin_ia32_vcvtbf42hf8_128((__v16qi)__A);
1734_mm_mask_cvtbf4_hf8(__m128i __W,
__mmask16 __U, __m128i __A) {
1735 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvtbf4_hf8(__A),
1754_mm_maskz_cvtbf4_hf8(
__mmask16 __U, __m128i __A) {
1755 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvtbf4_hf8(__A),
1772 return (__m256i)__builtin_ia32_vcvtbf42hf8_256((__v16qi)__A);
1792_mm256_mask_cvtbf4_hf8(__m256i __W,
__mmask32 __U, __m128i __A) {
1793 return (__m256i)__builtin_ia32_selectb_256(
1794 __U, (__v32qi)_mm256_cvtbf4_hf8(__A), (__v32qi)__W);
1812_mm256_maskz_cvtbf4_hf8(
__mmask32 __U, __m128i __A) {
1813 return (__m256i)__builtin_ia32_selectb_256(
1830 return (__m128i)__builtin_ia32_vcvtbf62hf8_128((__v16qi)__A);
1850_mm_mask_cvtbf6_hf8(__m128i __W,
__mmask16 __U, __m128i __A) {
1851 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvtbf6_hf8(__A),
1870_mm_maskz_cvtbf6_hf8(
__mmask16 __U, __m128i __A) {
1871 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvtbf6_hf8(__A),
1888 return (__m256i)__builtin_ia32_vcvtbf62hf8_256((__v32qi)__A);
1908_mm256_mask_cvtbf6_hf8(__m256i __W,
__mmask32 __U, __m256i __A) {
1909 return (__m256i)__builtin_ia32_selectb_256(
1910 __U, (__v32qi)_mm256_cvtbf6_hf8(__A), (__v32qi)__W);
1928_mm256_maskz_cvtbf6_hf8(
__mmask32 __U, __m256i __A) {
1929 return (__m256i)__builtin_ia32_selectb_256(
1946 return (__m128i)__builtin_ia32_vcvthf62hf8_128((__v16qi)__A);
1966_mm_mask_cvthf6_hf8(__m128i __W,
__mmask16 __U, __m128i __A) {
1967 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvthf6_hf8(__A),
1986_mm_maskz_cvthf6_hf8(
__mmask16 __U, __m128i __A) {
1987 return (__m128i)__builtin_ia32_selectb_128(__U, (__v16qi)_mm_cvthf6_hf8(__A),
2004 return (__m256i)__builtin_ia32_vcvthf62hf8_256((__v32qi)__A);
2024_mm256_mask_cvthf6_hf8(__m256i __W,
__mmask32 __U, __m256i __A) {
2025 return (__m256i)__builtin_ia32_selectb_256(
2026 __U, (__v32qi)_mm256_cvthf6_hf8(__A), (__v32qi)__W);
2044_mm256_maskz_cvthf6_hf8(
__mmask32 __U, __m256i __A) {
2045 return (__m256i)__builtin_ia32_selectb_256(
2058#define _MM_UNPACKB_SIZE(n) (((n) & 0x7) << 2)
2070#define _MM_UNPACKB_START(s) (((s) & 0x3) << 0)
2077#define _MM_UNPACKB_SEXT (1 << 5)
2100#define _mm_unpack_epi8(A, imm) \
2101 ((__m128i)__builtin_ia32_vunpackb128((__v16qi)(__m128i)(A), (int)(imm)))
2128#define _mm_mask_unpack_epi8(W, U, A, imm) \
2129 ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
2130 (__v16qi)_mm_unpack_epi8((A), (imm)), \
2131 (__v16qi)(__m128i)(W)))
2156#define _mm_maskz_unpack_epi8(U, A, imm) \
2157 ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
2158 (__v16qi)_mm_unpack_epi8((A), (imm)), \
2159 (__v16qi)_mm_setzero_si128()))
2182#define _mm256_unpack_epi8(A, imm) \
2183 ((__m256i)__builtin_ia32_vunpackb256((__v32qi)(__m256i)(A), (int)(imm)))
2210#define _mm256_mask_unpack_epi8(W, U, A, imm) \
2211 ((__m256i)__builtin_ia32_selectb_256( \
2212 (__mmask32)(U), (__v32qi)_mm256_unpack_epi8((A), (imm)), \
2213 (__v32qi)(__m256i)(W)))
2238#define _mm256_maskz_unpack_epi8(U, A, imm) \
2239 ((__m256i)__builtin_ia32_selectb_256( \
2240 (__mmask32)(U), (__v32qi)_mm256_unpack_epi8((A), (imm)), \
2241 (__v32qi)_mm256_setzero_si256()))
2257_mm_cvtss_epi32_epi8(__m128i __A) {
2258 return (__m128i)__builtin_ia32_vpmovssdb128_mask(
2278_mm_mask_cvtss_epi32_epi8(__m128i __W,
__mmask8 __U, __m128i __A) {
2279 return (__m128i)__builtin_ia32_vpmovssdb128_mask((__v4si)__A, (__v16qi)__W,
2297_mm_maskz_cvtss_epi32_epi8(
__mmask8 __U, __m128i __A) {
2298 return (__m128i)__builtin_ia32_vpmovssdb128_mask(
2316_mm256_cvtss_epi32_epi8(__m256i __A) {
2317 return (__m128i)__builtin_ia32_vpmovssdb256_mask(
2337_mm256_mask_cvtss_epi32_epi8(__m128i __W,
__mmask8 __U, __m256i __A) {
2338 return (__m128i)__builtin_ia32_vpmovssdb256_mask((__v8si)__A, (__v16qi)__W,
2356_mm256_maskz_cvtss_epi32_epi8(
__mmask8 __U, __m256i __A) {
2357 return (__m128i)__builtin_ia32_vpmovssdb256_mask(
2376_mm_mask_cvtss_epi32_storeu_epi8(
void *
__P,
__mmask8 __M, __m128i __A) {
2377 __builtin_ia32_vpmovssdb128mem_mask((__v16qi *)
__P, (__v4si)__A, __M);
2395_mm256_mask_cvtss_epi32_storeu_epi8(
void *
__P,
__mmask8 __M, __m256i __A) {
2396 __builtin_ia32_vpmovssdb256mem_mask((__v16qi *)
__P, (__v8si)__A, __M);
2399#undef __DEFAULT_FN_ATTRS128
2400#undef __DEFAULT_FN_ATTRS256
#define __DEFAULT_FN_ATTRS128
#define __DEFAULT_FN_ATTRS256
static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_setzero_ps(void)
Constructs a 256-bit floating-point vector of [8 x float] with all vector elements initialized to zer...
static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_setzero_si256(void)
Constructs a 256-bit integer vector initialized to zero.
static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setzero_si128(void)
Creates a 128-bit integer vector initialized to zero.
static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_undefined_si128(void)
Generates a 128-bit vector of [4 x i32] with unspecified content.
__inline unsigned int unsigned int unsigned int * __P
static __inline__ __m128 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setzero_ps(void)
Constructs a 128-bit floating-point vector of [4 x float] initialized to zero.