11 "Never use <avx10v2aux_512intrin.h> directly; include <immintrin.h> instead."
16#ifndef __AVX10V2AUX_512INTRIN_H
17#define __AVX10V2AUX_512INTRIN_H
20#define __DEFAULT_FN_ATTRS512 \
21 __attribute__((__always_inline__, __nodebug__, __target__("avx10v2aux"), \
22 __min_vector_width__(512)))
37 return (__m128i)__builtin_ia32_vcvtps2bf8_512((__v16sf)__A);
57_mm512_mask_cvtps_bf8(__m128i __W,
__mmask16 __U, __m512 __A) {
58 return (__m128i)__builtin_ia32_selectb_128(
59 (
__mmask16)__U, (__v16qi)_mm512_cvtps_bf8(__A), (__v16qi)__W);
77_mm512_maskz_cvtps_bf8(
__mmask16 __U, __m512 __A) {
78 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
79 (__v16qi)_mm512_cvtps_bf8(__A),
96 return (__m128i)__builtin_ia32_vcvtps2bf8s_512((__v16sf)__A);
116_mm512_mask_cvts_ps_bf8(__m128i __W,
__mmask16 __U, __m512 __A) {
117 return (__m128i)__builtin_ia32_selectb_128(
118 (
__mmask16)__U, (__v16qi)_mm512_cvts_ps_bf8(__A), (__v16qi)__W);
136_mm512_maskz_cvts_ps_bf8(
__mmask16 __U, __m512 __A) {
137 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
138 (__v16qi)_mm512_cvts_ps_bf8(__A),
155 return (__m128i)__builtin_ia32_vcvtps2hf8_512((__v16sf)__A);
175_mm512_mask_cvtps_hf8(__m128i __W,
__mmask16 __U, __m512 __A) {
176 return (__m128i)__builtin_ia32_selectb_128(
177 (
__mmask16)__U, (__v16qi)_mm512_cvtps_hf8(__A), (__v16qi)__W);
195_mm512_maskz_cvtps_hf8(
__mmask16 __U, __m512 __A) {
196 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
197 (__v16qi)_mm512_cvtps_hf8(__A),
214 return (__m128i)__builtin_ia32_vcvtps2hf8s_512((__v16sf)__A);
234_mm512_mask_cvts_ps_hf8(__m128i __W,
__mmask16 __U, __m512 __A) {
235 return (__m128i)__builtin_ia32_selectb_128(
236 (
__mmask16)__U, (__v16qi)_mm512_cvts_ps_hf8(__A), (__v16qi)__W);
254_mm512_maskz_cvts_ps_hf8(
__mmask16 __U, __m512 __A) {
255 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
256 (__v16qi)_mm512_cvts_ps_hf8(__A),
273 return (__m128i)__builtin_ia32_vcvtrops2hf8_512((__v16sf)__A);
293_mm512_mask_cvtrops_hf8(__m128i __W,
__mmask16 __U, __m512 __A) {
294 return (__m128i)__builtin_ia32_selectb_128(
295 (
__mmask16)__U, (__v16qi)_mm512_cvtrops_hf8(__A), (__v16qi)__W);
313_mm512_maskz_cvtrops_hf8(
__mmask16 __U, __m512 __A) {
314 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
315 (__v16qi)_mm512_cvtrops_hf8(__A),
332_mm512_cvts_rops_hf8(__m512 __A) {
333 return (__m128i)__builtin_ia32_vcvtrops2hf8s_512((__v16sf)__A);
354_mm512_mask_cvts_rops_hf8(__m128i __W,
__mmask16 __U, __m512 __A) {
355 return (__m128i)__builtin_ia32_selectb_128(
356 (
__mmask16)__U, (__v16qi)_mm512_cvts_rops_hf8(__A), (__v16qi)__W);
375_mm512_maskz_cvts_rops_hf8(
__mmask16 __U, __m512 __A) {
376 return (__m128i)__builtin_ia32_selectb_128((
__mmask16)__U,
377 (__v16qi)_mm512_cvts_rops_hf8(__A),
396_mm512_cvtbiasps_bf8(__m512i __A, __m512 __B) {
397 return (__m128i)__builtin_ia32_vcvtbiasps2bf8_512((__v16si)__A, (__v16sf)__B);
419_mm512_mask_cvtbiasps_bf8(__m128i __W,
__mmask16 __U, __m512i __A, __m512 __B) {
420 return (__m128i)__builtin_ia32_selectb_128(
421 (
__mmask16)__U, (__v16qi)_mm512_cvtbiasps_bf8(__A, __B), (__v16qi)__W);
441_mm512_maskz_cvtbiasps_bf8(
__mmask16 __U, __m512i __A, __m512 __B) {
442 return (__m128i)__builtin_ia32_selectb_128(
443 (
__mmask16)__U, (__v16qi)_mm512_cvtbiasps_bf8(__A, __B),
462_mm512_cvts_biasps_bf8(__m512i __A, __m512 __B) {
463 return (__m128i)__builtin_ia32_vcvtbiasps2bf8s_512((__v16si)__A,
486 __m128i __W,
__mmask16 __U, __m512i __A, __m512 __B) {
487 return (__m128i)__builtin_ia32_selectb_128(
488 (
__mmask16)__U, (__v16qi)_mm512_cvts_biasps_bf8(__A, __B), (__v16qi)__W);
508_mm512_maskz_cvts_biasps_bf8(
__mmask16 __U, __m512i __A, __m512 __B) {
509 return (__m128i)__builtin_ia32_selectb_128(
510 (
__mmask16)__U, (__v16qi)_mm512_cvts_biasps_bf8(__A, __B),
529_mm512_cvtbiasps_hf8(__m512i __A, __m512 __B) {
530 return (__m128i)__builtin_ia32_vcvtbiasps2hf8_512((__v16si)__A, (__v16sf)__B);
552_mm512_mask_cvtbiasps_hf8(__m128i __W,
__mmask16 __U, __m512i __A, __m512 __B) {
553 return (__m128i)__builtin_ia32_selectb_128(
554 (
__mmask16)__U, (__v16qi)_mm512_cvtbiasps_hf8(__A, __B), (__v16qi)__W);
574_mm512_maskz_cvtbiasps_hf8(
__mmask16 __U, __m512i __A, __m512 __B) {
575 return (__m128i)__builtin_ia32_selectb_128(
576 (
__mmask16)__U, (__v16qi)_mm512_cvtbiasps_hf8(__A, __B),
595_mm512_cvts_biasps_hf8(__m512i __A, __m512 __B) {
596 return (__m128i)__builtin_ia32_vcvtbiasps2hf8s_512((__v16si)__A,
619 __m128i __W,
__mmask16 __U, __m512i __A, __m512 __B) {
620 return (__m128i)__builtin_ia32_selectb_128(
621 (
__mmask16)__U, (__v16qi)_mm512_cvts_biasps_hf8(__A, __B), (__v16qi)__W);
641_mm512_maskz_cvts_biasps_hf8(
__mmask16 __U, __m512i __A, __m512 __B) {
642 return (__m128i)__builtin_ia32_selectb_128(
643 (
__mmask16)__U, (__v16qi)_mm512_cvts_biasps_hf8(__A, __B),
660 return (__m512)__builtin_ia32_vcvtbf82ps_512((__v16qi)__A);
680_mm512_mask_cvtbf8_ps(__m512 __W,
__mmask16 __U, __m128i __A) {
681 return (__m512)__builtin_ia32_selectps_512(
682 (
__mmask16)__U, (__v16sf)_mm512_cvtbf8_ps(__A), (__v16sf)__W);
700_mm512_maskz_cvtbf8_ps(
__mmask16 __U, __m128i __A) {
701 return (__m512)__builtin_ia32_selectps_512((
__mmask16)__U,
702 (__v16sf)_mm512_cvtbf8_ps(__A),
719 return (__m512)__builtin_ia32_vcvthf82ps_512((__v16qi)__A);
739_mm512_mask_cvthf8_ps(__m512 __W,
__mmask16 __U, __m128i __A) {
740 return (__m512)__builtin_ia32_selectps_512(
741 (
__mmask16)__U, (__v16sf)_mm512_cvthf8_ps(__A), (__v16sf)__W);
759_mm512_maskz_cvthf8_ps(
__mmask16 __U, __m128i __A) {
760 return (__m512)__builtin_ia32_selectps_512((
__mmask16)__U,
761 (__v16sf)_mm512_cvthf8_ps(__A),
779_mm512_cvts_bf8_bf6(__m512i __A) {
780 return (__m512i)__builtin_ia32_vcvtbf82bf6s_512((__v64qi)__A);
797_mm512_cvts_hf8_hf6(__m512i __A) {
798 return (__m512i)__builtin_ia32_vcvthf82hf6s_512((__v64qi)__A);
814_mm512_cvts_bf8_bf4(__m512i __A) {
815 return (__m256i)__builtin_ia32_vcvtbf82bf4s_512((__v64qi)__A);
831_mm512_cvts_hf8_bf4(__m512i __A) {
832 return (__m256i)__builtin_ia32_vcvthf82bf4s_512((__v64qi)__A);
848 return (__m512i)__builtin_ia32_vcvtbf42hf8_512((__v32qi)__A);
868_mm512_mask_cvtbf4_hf8(__m512i __W,
__mmask64 __U, __m256i __A) {
869 return (__m512i)__builtin_ia32_selectb_512(
870 __U, (__v64qi)_mm512_cvtbf4_hf8(__A), (__v64qi)__W);
888_mm512_maskz_cvtbf4_hf8(
__mmask64 __U, __m256i __A) {
889 return (__m512i)__builtin_ia32_selectb_512(
906 return (__m512i)__builtin_ia32_vcvtbf62hf8_512((__v64qi)__A);
926_mm512_mask_cvtbf6_hf8(__m512i __W,
__mmask64 __U, __m512i __A) {
927 return (__m512i)__builtin_ia32_selectb_512(
928 __U, (__v64qi)_mm512_cvtbf6_hf8(__A), (__v64qi)__W);
946_mm512_maskz_cvtbf6_hf8(
__mmask64 __U, __m512i __A) {
947 return (__m512i)__builtin_ia32_selectb_512(
964 return (__m512i)__builtin_ia32_vcvthf62hf8_512((__v64qi)__A);
984_mm512_mask_cvthf6_hf8(__m512i __W,
__mmask64 __U, __m512i __A) {
985 return (__m512i)__builtin_ia32_selectb_512(
986 __U, (__v64qi)_mm512_cvthf6_hf8(__A), (__v64qi)__W);
1004_mm512_maskz_cvthf6_hf8(
__mmask64 __U, __m512i __A) {
1005 return (__m512i)__builtin_ia32_selectb_512(
1030#define _mm512_unpack_epi8(A, imm) \
1031 ((__m512i)__builtin_ia32_vunpackb512((__v64qi)(__m512i)(A), (int)(imm)))
1058#define _mm512_mask_unpack_epi8(W, U, A, imm) \
1059 ((__m512i)__builtin_ia32_selectb_512( \
1060 (__mmask64)(U), (__v64qi)_mm512_unpack_epi8((A), (imm)), \
1061 (__v64qi)(__m512i)(W)))
1086#define _mm512_maskz_unpack_epi8(U, A, imm) \
1087 ((__m512i)__builtin_ia32_selectb_512( \
1088 (__mmask64)(U), (__v64qi)_mm512_unpack_epi8((A), (imm)), \
1089 (__v64qi)_mm512_setzero_si512()))
1104_mm512_cvtss_epi32_epi8(__m512i __A) {
1105 return (__m128i)__builtin_ia32_vpmovssdb512_mask(
1125_mm512_mask_cvtss_epi32_epi8(__m128i __W,
__mmask16 __U, __m512i __A) {
1126 return (__m128i)__builtin_ia32_vpmovssdb512_mask((__v16si)__A, (__v16qi)__W,
1144_mm512_maskz_cvtss_epi32_epi8(
__mmask16 __U, __m512i __A) {
1145 return (__m128i)__builtin_ia32_vpmovssdb512_mask(
1164_mm512_mask_cvtss_epi32_storeu_epi8(
void *
__P,
__mmask16 __M, __m512i __A) {
1165 __builtin_ia32_vpmovssdb512mem_mask((__v16qi *)
__P, (__v16si)__A, __M);
1168#undef __DEFAULT_FN_ATTRS512
#define __DEFAULT_FN_ATTRS512
unsigned long long __mmask64
static __inline __m512 __DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_setzero_ps(void)
static __inline __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_setzero_si512(void)
static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setzero_si128(void)
Creates a 128-bit integer vector initialized to zero.
__inline unsigned int unsigned int unsigned int * __P