11 "Never use <avx10_2_512convertintrin.h> directly; include <immintrin.h> instead."
16#ifndef __AVX10_2_512CONVERTINTRIN_H
17#define __AVX10_2_512CONVERTINTRIN_H
20#define __DEFAULT_FN_ATTRS512 \
21 __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \
22 __min_vector_width__(512)))
26 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
27 (__v16sf)__A, (__v16sf)__B, (__v32hf)_mm512_setzero_ph(), (
__mmask32)(-1),
32_mm512_mask_cvtx2ps_ph(__m512h __W,
__mmask32 __U, __m512 __A, __m512 __B) {
33 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
34 (__v16sf)__A, (__v16sf)__B, (__v32hf)__W, (
__mmask32)__U,
39_mm512_maskz_cvtx2ps_ph(
__mmask32 __U, __m512 __A, __m512 __B) {
40 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
41 (__v16sf)__A, (__v16sf)__B, (__v32hf)_mm512_setzero_ph(), (
__mmask32)__U,
45#define _mm512_cvtx_round2ps_ph(A, B, R) \
46 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask( \
47 (__v16sf)(A), (__v16sf)(B), (__v32hf)_mm512_undefined_ph(), \
48 (__mmask32)(-1), (const int)(R)))
50#define _mm512_mask_cvtx_round2ps_ph(W, U, A, B, R) \
51 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask((__v16sf)(A), (__v16sf)(B), \
52 (__v32hf)(W), (__mmask32)(U), \
55#define _mm512_maskz_cvtx_round2ps_ph(U, A, B, R) \
56 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask( \
57 (__v16sf)(A), (__v16sf)(B), (__v32hf)_mm512_setzero_ph(), \
58 (__mmask32)(U), (const int)(R)))
61_mm512_cvtbiasph_bf8(__m512i __A, __m512h __B) {
62 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
68 __m256i __W,
__mmask32 __U, __m512i __A, __m512h __B) {
69 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
70 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (
__mmask32)__U);
74_mm512_maskz_cvtbiasph_bf8(
__mmask32 __U, __m512i __A, __m512h __B) {
75 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
81_mm512_cvtbiassph_bf8(__m512i __A, __m512h __B) {
82 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
88 __m256i __W,
__mmask32 __U, __m512i __A, __m512h __B) {
89 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
90 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (
__mmask32)__U);
94_mm512_maskz_cvtbiassph_bf8(
__mmask32 __U, __m512i __A, __m512h __B) {
95 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
101_mm512_cvtbiasph_hf8(__m512i __A, __m512h __B) {
102 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
108 __m256i __W,
__mmask32 __U, __m512i __A, __m512h __B) {
109 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
110 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (
__mmask32)__U);
114_mm512_maskz_cvtbiasph_hf8(
__mmask32 __U, __m512i __A, __m512h __B) {
115 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
121_mm512_cvtbiassph_hf8(__m512i __A, __m512h __B) {
122 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
128 __m256i __W,
__mmask32 __U, __m512i __A, __m512h __B) {
129 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
130 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (
__mmask32)__U);
134_mm512_maskz_cvtbiassph_hf8(
__mmask32 __U, __m512i __A, __m512h __B) {
135 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
142 return (__m512i)__builtin_ia32_vcvt2ph2bf8_512((__v32hf)(__A),
147_mm512_mask_cvt2ph_bf8(__m512i __W,
__mmask64 __U, __m512h __A, __m512h __B) {
148 return (__m512i)__builtin_ia32_selectb_512(
149 (
__mmask64)__U, (__v64qi)_mm512_cvt2ph_bf8(__A, __B), (__v64qi)__W);
153_mm512_maskz_cvt2ph_bf8(
__mmask64 __U, __m512h __A, __m512h __B) {
154 return (__m512i)__builtin_ia32_selectb_512(
155 (
__mmask64)__U, (__v64qi)_mm512_cvt2ph_bf8(__A, __B),
160_mm512_cvts2ph_bf8(__m512h __A, __m512h __B) {
161 return (__m512i)__builtin_ia32_vcvt2ph2bf8s_512((__v32hf)(__A),
166_mm512_mask_cvts2ph_bf8(__m512i __W,
__mmask64 __U, __m512h __A, __m512h __B) {
167 return (__m512i)__builtin_ia32_selectb_512(
168 (
__mmask64)__U, (__v64qi)_mm512_cvts2ph_bf8(__A, __B), (__v64qi)__W);
172_mm512_maskz_cvts2ph_bf8(
__mmask64 __U, __m512h __A, __m512h __B) {
173 return (__m512i)__builtin_ia32_selectb_512(
174 (
__mmask64)__U, (__v64qi)_mm512_cvts2ph_bf8(__A, __B),
180 return (__m512i)__builtin_ia32_vcvt2ph2hf8_512((__v32hf)(__A),
185_mm512_mask_cvt2ph_hf8(__m512i __W,
__mmask64 __U, __m512h __A, __m512h __B) {
186 return (__m512i)__builtin_ia32_selectb_512(
187 (
__mmask64)__U, (__v64qi)_mm512_cvt2ph_hf8(__A, __B), (__v64qi)__W);
191_mm512_maskz_cvt2ph_hf8(
__mmask64 __U, __m512h __A, __m512h __B) {
192 return (__m512i)__builtin_ia32_selectb_512(
193 (
__mmask64)__U, (__v64qi)_mm512_cvt2ph_hf8(__A, __B),
198_mm512_cvts2ph_hf8(__m512h __A, __m512h __B) {
199 return (__m512i)__builtin_ia32_vcvt2ph2hf8s_512((__v32hf)(__A),
204_mm512_mask_cvts2ph_hf8(__m512i __W,
__mmask64 __U, __m512h __A, __m512h __B) {
205 return (__m512i)__builtin_ia32_selectb_512(
206 (
__mmask64)__U, (__v64qi)_mm512_cvts2ph_hf8(__A, __B), (__v64qi)__W);
210_mm512_maskz_cvts2ph_hf8(
__mmask64 __U, __m512h __A, __m512h __B) {
211 return (__m512i)__builtin_ia32_selectb_512(
212 (
__mmask64)__U, (__v64qi)_mm512_cvts2ph_hf8(__A, __B),
217 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
218 (__v32qi)__A, (__v32hf)(__m512h)_mm512_undefined_ph(), (
__mmask32)-1);
222_mm512_mask_cvthf8(__m512h __W,
__mmask32 __U, __m256i __A) {
223 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
224 (__v32qi)__A, (__v32hf)(__m512h)__W, (
__mmask32)__U);
228_mm512_maskz_cvthf8(
__mmask32 __U, __m256i __A) {
229 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
230 (__v32qi)__A, (__v32hf)(__m512h)_mm512_setzero_ph(), (
__mmask32)__U);
234 return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
239_mm512_mask_cvtph_bf8(__m256i __W,
__mmask32 __U, __m512h __A) {
240 return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
241 (__v32hf)__A, (__v32qi)(__m256i)__W, (
__mmask32)__U);
245_mm512_maskz_cvtph_bf8(
__mmask32 __U, __m512h __A) {
246 return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
251 return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
256_mm512_mask_cvtsph_bf8(__m256i __W,
__mmask32 __U, __m512h __A) {
257 return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
258 (__v32hf)__A, (__v32qi)(__m256i)__W, (
__mmask32)__U);
262_mm512_maskz_cvtsph_bf8(
__mmask32 __U, __m512h __A) {
263 return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
268 return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
273_mm512_mask_cvtph_hf8(__m256i __W,
__mmask32 __U, __m512h __A) {
274 return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
275 (__v32hf)__A, (__v32qi)(__m256i)__W, (
__mmask32)__U);
279_mm512_maskz_cvtph_hf8(
__mmask32 __U, __m512h __A) {
280 return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
285 return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
290_mm512_mask_cvtsph_hf8(__m256i __W,
__mmask32 __U, __m512h __A) {
291 return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
292 (__v32hf)__A, (__v32qi)(__m256i)__W, (
__mmask32)__U);
296_mm512_maskz_cvtsph_hf8(
__mmask32 __U, __m512h __A) {
297 return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
306_mm512_mask_cvtbf8_ph(__m512h __S,
__mmask32 __U, __m256i __A) {
307 return _mm512_castsi512_ph(
312_mm512_maskz_cvtbf8_ph(
__mmask32 __U, __m256i __A) {
313 return _mm512_castsi512_ph(
317#undef __DEFAULT_FN_ATTRS512
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_cvtepi8_epi16(__m256i __A)
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_maskz_cvtepi8_epi16(__mmask32 __U, __m256i __A)
#define __DEFAULT_FN_ATTRS512
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_slli_epi16(__m512i __A, unsigned int __B)
unsigned long long __mmask64
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_slli_epi16(__m512i __W, __mmask32 __U, __m512i __A, unsigned int __B)
#define _MM_FROUND_CUR_DIRECTION
static __inline __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_setzero_si512(void)
static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_undefined_si256(void)
Create a 256-bit integer vector with undefined values.
static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_setzero_si256(void)
Constructs a 256-bit integer vector initialized to zero.